Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann:
"Here is another set of bugfixes for ARM SoCs, mostly harmless:
- a boot regression fix on ux500
- PCIe interrupts on NXP i.MX7 and on Marvell Armada 7K/8K were wired
up wrong, in different ways
- Armada XP support for large memory never worked
- the socfpga reset controller now builds on 64-bit
- minor device tree corrections on gemini, mvebu, r-pi 3, rockchip
and at91"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: ux500: Fix regression while init PM domains
ARM: dts: fix PCLK name on Gemini and MOXA ART
arm64: dts: rockchip: fix typo in iommu nodes
arm64: dts: rockchip: correct vqmmc voltage for rk3399 platforms
ARM: dts: imx7d: Invert legacy PCI irq mapping
bus: mbus: fix window size calculation for 4GB windows
ARM: dts: at91: sama5d2: add ADC hw trigger edge type
ARM: dts: at91: sama5d2_xplained: enable ADTRG pin
ARM: dts: at91: at91-sama5d27_som1: fix PHY ID
ARM: dts: bcm283x: Fix console path on RPi3
reset: socfpga: fix for 64-bit compilation
ARM: dts: Fix I2C repeated start issue on Armada-38x
arm64: dts: marvell: fix interrupt-map property for Armada CP110 PCIe controller
arm64: dts: salvator-common: add 12V regulator to backlight
ARM: dts: sun6i: Fix endpoint IDs in second display pipeline
arm64: allwinner: a64: pine64: Use dcdc1 regulator for mmc0
+92
-62
+2
-2
arch/arm/boot/dts/armada-38x.dtsi
+2
-2
arch/arm/boot/dts/armada-38x.dtsi
···
178
178
};
179
179
180
180
i2c0: i2c@11000 {
181
-
compatible = "marvell,mv64xxx-i2c";
181
+
compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
182
182
reg = <0x11000 0x20>;
183
183
#address-cells = <1>;
184
184
#size-cells = <0>;
···
189
189
};
190
190
191
191
i2c1: i2c@11100 {
192
-
compatible = "marvell,mv64xxx-i2c";
192
+
compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
193
193
reg = <0x11100 0x20>;
194
194
#address-cells = <1>;
195
195
#size-cells = <0>;
+2
-2
arch/arm/boot/dts/at91-sama5d27_som1.dtsi
+2
-2
arch/arm/boot/dts/at91-sama5d27_som1.dtsi
+15
-1
arch/arm/boot/dts/at91-sama5d2_xplained.dts
+15
-1
arch/arm/boot/dts/at91-sama5d2_xplained.dts
···
309
309
vddana-supply = <&vdd_3v3_lp_reg>;
310
310
vref-supply = <&vdd_3v3_lp_reg>;
311
311
pinctrl-names = "default";
312
-
pinctrl-0 = <&pinctrl_adc_default>;
312
+
pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
313
313
status = "okay";
314
314
};
315
315
···
338
338
pinmux = <PIN_PC26__CANTX1>,
339
339
<PIN_PC27__CANRX1>;
340
340
bias-disable;
341
+
};
342
+
343
+
/*
344
+
* The ADTRG pin can work on any edge type.
345
+
* In here it's being pulled up, so need to
346
+
* connect it to ground to get an edge e.g.
347
+
* Trigger can be configured on falling, rise
348
+
* or any edge, and the pull-up can be changed
349
+
* to pull-down or left floating according to
350
+
* needs.
351
+
*/
352
+
pinctrl_adtrg_default: adtrg_default {
353
+
pinmux = <PIN_PD31__ADTRG>;
354
+
bias-pull-up;
341
355
};
342
356
343
357
pinctrl_charger_chglev: charger_chglev {
+3
-6
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
+3
-6
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
···
18
18
compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
19
19
model = "Raspberry Pi Zero W";
20
20
21
-
/* Needed by firmware to properly init UARTs */
22
-
aliases {
23
-
uart0 = "/soc/serial@7e201000";
24
-
uart1 = "/soc/serial@7e215040";
25
-
serial0 = "/soc/serial@7e201000";
26
-
serial1 = "/soc/serial@7e215040";
21
+
chosen {
22
+
/* 8250 auxiliary UART instead of pl011 */
23
+
stdout-path = "serial1:115200n8";
27
24
};
28
25
29
26
leds {
+5
arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+5
arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+6
-1
arch/arm/boot/dts/bcm283x.dtsi
+6
-1
arch/arm/boot/dts/bcm283x.dtsi
+2
-1
arch/arm/boot/dts/gemini.dtsi
+2
-1
arch/arm/boot/dts/gemini.dtsi
···
145
145
};
146
146
147
147
watchdog@41000000 {
148
-
compatible = "cortina,gemini-watchdog";
148
+
compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
149
149
reg = <0x41000000 0x1000>;
150
150
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
151
151
resets = <&syscon GEMINI_RESET_WDOG>;
152
152
clocks = <&syscon GEMINI_CLK_APB>;
153
+
clock-names = "PCLK";
153
154
};
154
155
155
156
uart0: serial@42000000 {
+4
-4
arch/arm/boot/dts/imx7d.dtsi
+4
-4
arch/arm/boot/dts/imx7d.dtsi
···
144
144
interrupt-names = "msi";
145
145
#interrupt-cells = <1>;
146
146
interrupt-map-mask = <0 0 0 0x7>;
147
-
interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
148
-
<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
149
-
<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
150
-
<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
147
+
interrupt-map = <0 0 0 1 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
148
+
<0 0 0 2 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
149
+
<0 0 0 3 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
150
+
<0 0 0 4 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
151
151
clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
152
152
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
153
153
<&clks IMX7D_PCIE_PHY_ROOT_CLK>;
+2
-1
arch/arm/boot/dts/moxart.dtsi
+2
-1
arch/arm/boot/dts/moxart.dtsi
+1
arch/arm/boot/dts/sama5d2.dtsi
+1
arch/arm/boot/dts/sama5d2.dtsi
+8
-8
arch/arm/boot/dts/sun6i-a31.dtsi
+8
-8
arch/arm/boot/dts/sun6i-a31.dtsi
···
311
311
#size-cells = <0>;
312
312
reg = <0>;
313
313
314
-
tcon1_in_drc1: endpoint@0 {
315
-
reg = <0>;
314
+
tcon1_in_drc1: endpoint@1 {
315
+
reg = <1>;
316
316
remote-endpoint = <&drc1_out_tcon1>;
317
317
};
318
318
};
···
1012
1012
#size-cells = <0>;
1013
1013
reg = <1>;
1014
1014
1015
-
be1_out_drc1: endpoint@0 {
1016
-
reg = <0>;
1015
+
be1_out_drc1: endpoint@1 {
1016
+
reg = <1>;
1017
1017
remote-endpoint = <&drc1_in_be1>;
1018
1018
};
1019
1019
};
···
1042
1042
#size-cells = <0>;
1043
1043
reg = <0>;
1044
1044
1045
-
drc1_in_be1: endpoint@0 {
1046
-
reg = <0>;
1045
+
drc1_in_be1: endpoint@1 {
1046
+
reg = <1>;
1047
1047
remote-endpoint = <&be1_out_drc1>;
1048
1048
};
1049
1049
};
···
1053
1053
#size-cells = <0>;
1054
1054
reg = <1>;
1055
1055
1056
-
drc1_out_tcon1: endpoint@0 {
1057
-
reg = <0>;
1056
+
drc1_out_tcon1: endpoint@1 {
1057
+
reg = <1>;
1058
1058
remote-endpoint = <&tcon1_in_drc1>;
1059
1059
};
1060
1060
};
+4
arch/arm/mach-ux500/cpu-db8500.c
+4
arch/arm/mach-ux500/cpu-db8500.c
···
32
32
#include <asm/mach/arch.h>
33
33
34
34
#include "db8500-regs.h"
35
+
#include "pm_domains.h"
35
36
36
37
static int __init ux500_l2x0_unlock(void)
37
38
{
···
158
157
159
158
static void __init u8500_init_machine(void)
160
159
{
160
+
/* Initialize ux500 power domains */
161
+
ux500_pm_domains_init();
162
+
161
163
/* automatically probe child nodes of dbx5x0 devices */
162
164
if (of_machine_is_compatible("st-ericsson,u8540"))
163
165
of_platform_populate(NULL, u8500_local_bus_nodes,
-4
arch/arm/mach-ux500/pm.c
-4
arch/arm/mach-ux500/pm.c
···
19
19
#include <linux/of_address.h>
20
20
21
21
#include "db8500-regs.h"
22
-
#include "pm_domains.h"
23
22
24
23
/* ARM WFI Standby signal register */
25
24
#define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130)
···
202
203
203
204
/* Set up ux500 suspend callbacks. */
204
205
suspend_set_ops(UX500_SUSPEND_OPS);
205
-
206
-
/* Initialize ux500 power domains */
207
-
ux500_pm_domains_init();
208
206
}
+1
-8
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+1
-8
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
···
61
61
chosen {
62
62
stdout-path = "serial0:115200n8";
63
63
};
64
-
65
-
reg_vcc3v3: vcc3v3 {
66
-
compatible = "regulator-fixed";
67
-
regulator-name = "vcc3v3";
68
-
regulator-min-microvolt = <3300000>;
69
-
regulator-max-microvolt = <3300000>;
70
-
};
71
64
};
72
65
73
66
&ehci0 {
···
84
91
&mmc0 {
85
92
pinctrl-names = "default";
86
93
pinctrl-0 = <&mmc0_pins>;
87
-
vmmc-supply = <®_vcc3v3>;
94
+
vmmc-supply = <®_dcdc1>;
88
95
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
89
96
cd-inverted;
90
97
disable-wp;
+3
-3
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+3
-3
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
···
336
336
/* non-prefetchable memory */
337
337
0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
338
338
interrupt-map-mask = <0 0 0 0>;
339
-
interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
339
+
interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
340
340
interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
341
341
num-lanes = <1>;
342
342
clocks = <&cpm_clk 1 13>;
···
362
362
/* non-prefetchable memory */
363
363
0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
364
364
interrupt-map-mask = <0 0 0 0>;
365
-
interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
365
+
interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
366
366
interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
367
367
368
368
num-lanes = <1>;
···
389
389
/* non-prefetchable memory */
390
390
0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
391
391
interrupt-map-mask = <0 0 0 0>;
392
-
interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
392
+
interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
393
393
interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
394
394
395
395
num-lanes = <1>;
+3
-3
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+3
-3
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
···
335
335
/* non-prefetchable memory */
336
336
0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
337
337
interrupt-map-mask = <0 0 0 0>;
338
-
interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
338
+
interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
339
339
interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
340
340
num-lanes = <1>;
341
341
clocks = <&cps_clk 1 13>;
···
361
361
/* non-prefetchable memory */
362
362
0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
363
363
interrupt-map-mask = <0 0 0 0>;
364
-
interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
364
+
interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
365
365
interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
366
366
367
367
num-lanes = <1>;
···
388
388
/* non-prefetchable memory */
389
389
0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
390
390
interrupt-map-mask = <0 0 0 0>;
391
-
interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
391
+
interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
392
392
interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
393
393
394
394
num-lanes = <1>;
+10
arch/arm64/boot/dts/renesas/salvator-common.dtsi
+10
arch/arm64/boot/dts/renesas/salvator-common.dtsi
···
62
62
brightness-levels = <256 128 64 16 8 4 0>;
63
63
default-brightness-level = <6>;
64
64
65
+
power-supply = <®_12v>;
65
66
enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
66
67
};
67
68
···
80
79
regulator-name = "fixed-3.3V";
81
80
regulator-min-microvolt = <3300000>;
82
81
regulator-max-microvolt = <3300000>;
82
+
regulator-boot-on;
83
+
regulator-always-on;
84
+
};
85
+
86
+
reg_12v: regulator2 {
87
+
compatible = "regulator-fixed";
88
+
regulator-name = "fixed-12V";
89
+
regulator-min-microvolt = <12000000>;
90
+
regulator-max-microvolt = <12000000>;
83
91
regulator-boot-on;
84
92
regulator-always-on;
85
93
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3328.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3328.dtsi
···
582
582
vop_mmu: iommu@ff373f00 {
583
583
compatible = "rockchip,iommu";
584
584
reg = <0x0 0xff373f00 0x0 0x100>;
585
-
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
585
+
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
586
586
interrupt-names = "vop_mmu";
587
587
#iommu-cells = <0>;
588
588
status = "disabled";
+1
-1
arch/arm64/boot/dts/rockchip/rk3368.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3368.dtsi
···
740
740
iep_mmu: iommu@ff900800 {
741
741
compatible = "rockchip,iommu";
742
742
reg = <0x0 0xff900800 0x0 0x100>;
743
-
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
743
+
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
744
744
interrupt-names = "iep_mmu";
745
745
#iommu-cells = <0>;
746
746
status = "disabled";
+2
-2
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+2
-2
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
···
371
371
regulator-always-on;
372
372
regulator-boot-on;
373
373
regulator-min-microvolt = <1800000>;
374
-
regulator-max-microvolt = <3300000>;
374
+
regulator-max-microvolt = <3000000>;
375
375
regulator-state-mem {
376
376
regulator-on-in-suspend;
377
-
regulator-suspend-microvolt = <3300000>;
377
+
regulator-suspend-microvolt = <3000000>;
378
378
};
379
379
};
380
380
+2
-2
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+2
-2
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
···
325
325
vcc_sd: LDO_REG4 {
326
326
regulator-name = "vcc_sd";
327
327
regulator-min-microvolt = <1800000>;
328
-
regulator-max-microvolt = <3300000>;
328
+
regulator-max-microvolt = <3000000>;
329
329
regulator-always-on;
330
330
regulator-boot-on;
331
331
regulator-state-mem {
332
332
regulator-on-in-suspend;
333
-
regulator-suspend-microvolt = <3300000>;
333
+
regulator-suspend-microvolt = <3000000>;
334
334
};
335
335
};
336
336
+2
-2
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+2
-2
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
···
315
315
regulator-always-on;
316
316
regulator-boot-on;
317
317
regulator-min-microvolt = <1800000>;
318
-
regulator-max-microvolt = <3300000>;
318
+
regulator-max-microvolt = <3000000>;
319
319
regulator-state-mem {
320
320
regulator-on-in-suspend;
321
-
regulator-suspend-microvolt = <3300000>;
321
+
regulator-suspend-microvolt = <3000000>;
322
322
};
323
323
};
324
324
+1
-1
drivers/bus/mvebu-mbus.c
+1
-1
drivers/bus/mvebu-mbus.c
+10
-7
drivers/reset/reset-socfpga.c
+10
-7
drivers/reset/reset-socfpga.c
···
40
40
struct socfpga_reset_data *data = container_of(rcdev,
41
41
struct socfpga_reset_data,
42
42
rcdev);
43
-
int bank = id / BITS_PER_LONG;
44
-
int offset = id % BITS_PER_LONG;
43
+
int reg_width = sizeof(u32);
44
+
int bank = id / (reg_width * BITS_PER_BYTE);
45
+
int offset = id % (reg_width * BITS_PER_BYTE);
45
46
unsigned long flags;
46
47
u32 reg;
47
48
···
62
61
struct socfpga_reset_data,
63
62
rcdev);
64
63
65
-
int bank = id / BITS_PER_LONG;
66
-
int offset = id % BITS_PER_LONG;
64
+
int reg_width = sizeof(u32);
65
+
int bank = id / (reg_width * BITS_PER_BYTE);
66
+
int offset = id % (reg_width * BITS_PER_BYTE);
67
67
unsigned long flags;
68
68
u32 reg;
69
69
···
83
81
{
84
82
struct socfpga_reset_data *data = container_of(rcdev,
85
83
struct socfpga_reset_data, rcdev);
86
-
int bank = id / BITS_PER_LONG;
87
-
int offset = id % BITS_PER_LONG;
84
+
int reg_width = sizeof(u32);
85
+
int bank = id / (reg_width * BITS_PER_BYTE);
86
+
int offset = id % (reg_width * BITS_PER_BYTE);
88
87
u32 reg;
89
88
90
89
reg = readl(data->membase + (bank * BANK_INCREMENT));
···
135
132
spin_lock_init(&data->lock);
136
133
137
134
data->rcdev.owner = THIS_MODULE;
138
-
data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
135
+
data->rcdev.nr_resets = NR_BANKS * (sizeof(u32) * BITS_PER_BYTE);
139
136
data->rcdev.ops = &socfpga_reset_ops;
140
137
data->rcdev.of_node = pdev->dev.of_node;
141
138