drm/amd/display: Filter Invalid 420 Modes for HDMI TMDS

[Why]
Invalidate unsupported 420 modes on HDMI TMDS. HDMI TMDS does not
support ODM. Any modes that are horizontally wider than 4096, cannot be
supported via TMDS. So they must be filtered out and should not pass
validation.

[How]
Create fake plane for the new stream, and validate global state by going
through dml validation routine.

Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Fangzhi Zuo and committed by

Alex Deucher 3 years ago 5468c36d e366f369

+67

1 changed file

expand all

drivers

gpu

drm

amd

display

amdgpu_dm

amdgpu_dm.c

+67

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 6156 6156 create_eml_sink(aconnector); 6157 6157 } 6158 6158 6159 + static enum dc_status dm_validate_stream_and_context(struct dc *dc, 6160 + struct dc_stream_state *stream) 6161 + { 6162 + enum dc_status dc_result = DC_ERROR_UNEXPECTED; 6163 + struct dc_plane_state *dc_plane_state = NULL; 6164 + struct dc_state *dc_state = NULL; 6165 + 6166 + if (!stream) 6167 + goto cleanup; 6168 + 6169 + dc_plane_state = dc_create_plane_state(dc); 6170 + if (!dc_plane_state) 6171 + goto cleanup; 6172 + 6173 + dc_state = dc_create_state(dc); 6174 + if (!dc_state) 6175 + goto cleanup; 6176 + 6177 + /* populate stream to plane */ 6178 + dc_plane_state->src_rect.height = stream->src.height; 6179 + dc_plane_state->src_rect.width = stream->src.width; 6180 + dc_plane_state->dst_rect.height = stream->src.height; 6181 + dc_plane_state->dst_rect.width = stream->src.width; 6182 + dc_plane_state->clip_rect.height = stream->src.height; 6183 + dc_plane_state->clip_rect.width = stream->src.width; 6184 + dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; 6185 + dc_plane_state->plane_size.surface_size.height = stream->src.height; 6186 + dc_plane_state->plane_size.surface_size.width = stream->src.width; 6187 + dc_plane_state->plane_size.chroma_size.height = stream->src.height; 6188 + dc_plane_state->plane_size.chroma_size.width = stream->src.width; 6189 + dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 6190 + dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 6191 + dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 6192 + dc_plane_state->rotation = ROTATION_ANGLE_0; 6193 + dc_plane_state->is_tiling_rotated = false; 6194 + dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; 6195 + 6196 + dc_result = dc_validate_stream(dc, stream); 6197 + if (dc_result == DC_OK) 6198 + dc_result = dc_validate_plane(dc, dc_plane_state); 6199 + 6200 + if (dc_result == DC_OK) 6201 + dc_result = dc_add_stream_to_ctx(dc, dc_state, stream); 6202 + 6203 + if (dc_result == DC_OK && !dc_add_plane_to_context( 6204 + dc, 6205 + stream, 6206 + dc_plane_state, 6207 + dc_state)) 6208 + dc_result = DC_FAIL_ATTACH_SURFACES; 6209 + 6210 + if (dc_result == DC_OK) 6211 + dc_result = dc_validate_global_state(dc, dc_state, true); 6212 + 6213 + cleanup: 6214 + if (dc_state) 6215 + dc_release_state(dc_state); 6216 + 6217 + if (dc_plane_state) 6218 + dc_plane_state_release(dc_plane_state); 6219 + 6220 + return dc_result; 6221 + } 6222 + 6159 6223 struct dc_stream_state * 6160 6224 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 6161 6225 const struct drm_display_mode *drm_mode, ··· 6245 6181 dc_result = dc_validate_stream(adev->dm.dc, stream); 6246 6182 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 6247 6183 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); 6184 + 6185 + if (dc_result == DC_OK) 6186 + dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 6248 6187 6249 6188 if (dc_result != DC_OK) { 6250 6189 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",

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