Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'phy-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"New support:
- UFS PHY for Qualcomm SA8775p, SM7150
- PCIe 2 lane phy support for sc8180x and PCIe PHY for SDX65
- Mediatke hdmi phy support for mt8195
- rockchip naneng combo phy support for RK358
Updates:
- Drop Thunder Bay eMMC PHY driver
- RC support for PCIe phy for Qualcomm SDX55
- SGMII support in WIZ driver for J721E
- PCIe and multilink SGMII PHY support in cadence driver
- Big pile of platform remove callback returning void conversions"
* tag 'phy-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (77 commits)
phy: cadence: cdns-dphy-rx: Add common module reset support
phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J721E
dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G
phy: ti: j721e-wiz: Fix unreachable code in wiz_mode_select()
phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration
phy: mediatek: add support for phy-mtk-hdmi-mt8195
phy: phy-mtk-hdmi: Add generic phy configure callback
dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible
phy: tegra: xusb: Add missing tegra_xusb_port_unregister for usb2_port and ulpi_port
dt-bindings: phy: ti,phy-j721e-wiz: document clock-output-names
dt-bindings: phy: ti,phy-j721e-wiz: drop assigned-clocks
dt-bindings: phy: ti,phy-am654-serdes: drop assigned-clocks type
dt-bindings: phy: cadence-torrent: drop assigned-clocks
dt-bindings: phy: cadence-sierra: drop assigned-clocks
phy: rockchip: remove unused hw_to_inno function
phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775p
dt-bindings: phy: qmp-ufs: describe the UFS PHY for sa8775p
phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tbl
phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes
phy: qcom-qmp-ufs: Add SM7150 support
...
+1628
-973
+5
-1
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+5
-1
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+2
-2
Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml
···
2
2
# Copyright 2019 Ondrej Jirman <megous@megous.com>
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb3-phy.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb3-phy.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Allwinner H6 USB3 PHY
9
9
+1
-1
Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+1
-1
Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+2
-2
Documentation/devicetree/bindings/phy/amlogic,axg-mipi-dphy.yaml
+2
-2
Documentation/devicetree/bindings/phy/amlogic,axg-mipi-dphy.yaml
···
2
2
# Copyright 2020 BayLibre, SAS
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/amlogic,axg-mipi-dphy.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/amlogic,axg-mipi-dphy.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Amlogic AXG MIPI D-PHY
9
9
+2
-2
Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml
+2
-2
Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Amlogic G12A MIPI analog PHY
8
8
+2
-2
Documentation/devicetree/bindings/phy/amlogic,g12a-usb2-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/amlogic,g12a-usb2-phy.yaml
···
2
2
# Copyright 2019 BayLibre, SAS
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/amlogic,g12a-usb2-phy.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/amlogic,g12a-usb2-phy.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Amlogic G12A USB2 PHY
9
9
+2
-2
Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml
···
2
2
# Copyright 2019 BayLibre, SAS
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Amlogic G12A USB3 + PCIE Combo PHY
9
9
+2
-2
Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
+2
-2
Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Amlogic AXG shared MIPI/PCIE analog PHY
8
8
+2
-2
Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
+2
-2
Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-pcie.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/amlogic,meson-axg-pcie.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Amlogic AXG PCIE PHY
8
8
+2
-2
Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY
8
8
+2
-2
Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY
8
8
+2
-2
Documentation/devicetree/bindings/phy/brcm,bcm63xx-usbh-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/brcm,bcm63xx-usbh-phy.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/brcm,bcm63xx-usbh-phy.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/brcm,bcm63xx-usbh-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: BCM63xx USBH PHY
8
8
+2
-2
Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Broadcom SATA3 PHY
8
8
+2
-2
Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
···
2
2
# Copyright (c) 2020 NXP
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Cadence SALVO PHY
9
9
+2
-2
Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml
+2
-2
Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml
···
19
19
const: 0
20
20
21
21
hisilicon,pericrg-syscon:
22
-
$ref: '/schemas/types.yaml#/definitions/phandle'
22
+
$ref: /schemas/types.yaml#/definitions/phandle
23
23
description: phandle of syscon used to control iso refclk.
24
24
25
25
hisilicon,pctrl-syscon:
26
-
$ref: '/schemas/types.yaml#/definitions/phandle'
26
+
$ref: /schemas/types.yaml#/definitions/phandle
27
27
description: phandle of syscon used to control usb tcxo.
28
28
29
29
hisilicon,eye-diagram-param:
+3
-3
Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml
+3
-3
Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml
···
20
20
const: 0
21
21
22
22
hisilicon,pericrg-syscon:
23
-
$ref: '/schemas/types.yaml#/definitions/phandle'
23
+
$ref: /schemas/types.yaml#/definitions/phandle
24
24
description: phandle of syscon used to control iso refclk.
25
25
26
26
hisilicon,pctrl-syscon:
27
-
$ref: '/schemas/types.yaml#/definitions/phandle'
27
+
$ref: /schemas/types.yaml#/definitions/phandle
28
28
description: phandle of syscon used to control usb tcxo.
29
29
30
30
hisilicon,sctrl-syscon:
31
-
$ref: '/schemas/types.yaml#/definitions/phandle'
31
+
$ref: /schemas/types.yaml#/definitions/phandle
32
32
description: phandle of syscon used to control phy deep sleep.
33
33
34
34
hisilicon,eye-diagram-param:
-45
Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml
-45
Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/phy/intel,phy-thunderbay-emmc.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: Intel Thunder Bay eMMC PHY
8
-
9
-
maintainers:
10
-
- Srikandan Nandhini <nandhini.srikandan@intel.com>
11
-
12
-
properties:
13
-
compatible:
14
-
const: intel,thunderbay-emmc-phy
15
-
16
-
"#phy-cells":
17
-
const: 0
18
-
19
-
reg:
20
-
maxItems: 1
21
-
22
-
clocks:
23
-
maxItems: 1
24
-
25
-
clock-names:
26
-
items:
27
-
- const: emmcclk
28
-
29
-
required:
30
-
- "#phy-cells"
31
-
- compatible
32
-
- reg
33
-
- clocks
34
-
35
-
additionalProperties: false
36
-
37
-
examples:
38
-
- |
39
-
mmc_phy@80440800 {
40
-
#phy-cells = <0x0>;
41
-
compatible = "intel,thunderbay-emmc-phy";
42
-
reg = <0x80440800 0x100>;
43
-
clocks = <&emmc>;
44
-
clock-names = "emmcclk";
45
-
};
+2
-2
Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
···
2
2
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/marvell,armada-3700-utmi-phy.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/marvell,armada-3700-utmi-phy.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Marvell Armada UTMI/UTMI+ PHY
9
9
+2
-2
Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
···
2
2
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Marvell Armada CP110/CP115 UTMI PHY
9
9
+2
-2
Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml
···
2
2
# Copyright 2019 Lubomir Rintel <lkundrak@v3.sk>
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/marvell,mmp3-hsic-phy.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/marvell,mmp3-hsic-phy.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Marvell MMP3 HSIC PHY
9
9
+1
Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
+1
Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Mediatek Mt7621 PCIe PHY
8
8
+2
-10
Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
+2
-10
Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Cadence Sierra PHY
8
8
···
60
60
- const: cmn_refclk1_dig_div
61
61
- const: pll0_refclk
62
62
- const: pll1_refclk
63
-
64
-
assigned-clocks:
65
-
minItems: 1
66
-
maxItems: 2
67
-
68
-
assigned-clock-parents:
69
-
minItems: 1
70
-
maxItems: 2
71
63
72
64
cdns,autoconf:
73
65
type: boolean
+2
-8
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+2
-8
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Cadence Torrent SD0801 PHY
8
8
···
43
43
items:
44
44
- const: refclk
45
45
- const: phy_en_refclk
46
-
47
-
assigned-clocks:
48
-
maxItems: 3
49
-
50
-
assigned-clock-parents:
51
-
maxItems: 3
52
46
53
47
reg:
54
48
minItems: 1
+1
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
+1
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
+2
-2
Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
+2
-2
Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: NVIDIA Tegra194 & Tegra234 P2U
8
8
+2
-2
Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
···
2
2
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Qualcomm eDP PHY
9
9
+2
-2
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
···
2
2
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Qualcomm QUSB2 phy controller
9
9
+1
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+1
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+26
-1
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+26
-1
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
···
16
16
properties:
17
17
compatible:
18
18
enum:
19
+
- qcom,sa8775p-qmp-ufs-phy
19
20
- qcom,sc8280xp-qmp-ufs-phy
20
21
- qcom,sm6125-qmp-ufs-phy
22
+
- qcom,sm7150-qmp-ufs-phy
21
23
- qcom,sm8550-qmp-ufs-phy
22
24
23
25
reg:
24
26
maxItems: 1
25
27
26
28
clocks:
27
-
maxItems: 2
29
+
minItems: 2
30
+
maxItems: 3
28
31
29
32
clock-names:
33
+
minItems: 2
30
34
items:
31
35
- const: ref
32
36
- const: ref_aux
37
+
- const: qref
33
38
34
39
power-domains:
35
40
maxItems: 1
···
67
62
- vdda-phy-supply
68
63
- vdda-pll-supply
69
64
- "#phy-cells"
65
+
66
+
allOf:
67
+
- if:
68
+
properties:
69
+
compatible:
70
+
contains:
71
+
enum:
72
+
- qcom,sa8775p-qmp-ufs-phy
73
+
then:
74
+
properties:
75
+
clocks:
76
+
maxItems: 3
77
+
clock-names:
78
+
maxItems: 3
79
+
else:
80
+
properties:
81
+
clocks:
82
+
maxItems: 2
83
+
clock-names:
84
+
maxItems: 2
70
85
71
86
additionalProperties: false
72
87
+2
-2
Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml
+2
-2
Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
8
8
+2
-2
Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml
+2
-2
Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcomm Synopsys Femto High-Speed USB PHY V2
8
8
+2
-2
Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml
+2
-2
Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
8
8
+2
-2
Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcom IPQ40xx Dakota HS/SS USB PHY
8
8
+2
-2
Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
···
21
21
maxItems: 1
22
22
23
23
samsung,pmu-syscon:
24
-
$ref: '/schemas/types.yaml#/definitions/phandle'
24
+
$ref: /schemas/types.yaml#/definitions/phandle
25
25
description: phandle for PMU system controller interface, used to
26
26
control PMU registers bits for PCIe PHY
27
27
28
28
samsung,fsys-sysreg:
29
-
$ref: '/schemas/types.yaml#/definitions/phandle'
29
+
$ref: /schemas/types.yaml#/definitions/phandle
30
30
description: phandle for FSYS sysreg interface, used to control
31
31
sysreg registers bits for PCIe PHY
32
32
+1
-1
Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+1
-1
Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/sunplus,sp7021-usb2-phy.yaml
+2
-2
Documentation/devicetree/bindings/phy/sunplus,sp7021-usb2-phy.yaml
···
2
2
# Copyright (C) Sunplus Co., Ltd. 2021
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/sunplus,sp7021-usb2-phy.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/sunplus,sp7021-usb2-phy.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Sunplus SP7021 USB 2.0 PHY Controller
9
9
-5
Documentation/devicetree/bindings/phy/ti,phy-am654-serdes.yaml
-5
Documentation/devicetree/bindings/phy/ti,phy-am654-serdes.yaml
···
34
34
Three input clocks referring to left input reference clock, refclk and right input reference
35
35
clock.
36
36
37
-
assigned-clocks:
38
-
$ref: "/schemas/types.yaml#/definitions/phandle-array"
39
-
assigned-clock-parents:
40
-
$ref: "/schemas/types.yaml#/definitions/phandle-array"
41
-
42
37
'#phy-cells':
43
38
const: 2
44
39
description:
+6
-2
Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
+6
-2
Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
···
2
2
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: CPSW Port's Interface Mode Selection PHY
9
9
···
55
55
- ti,am654-phy-gmii-sel
56
56
- ti,j7200-cpsw5g-phy-gmii-sel
57
57
- ti,j721e-cpsw9g-phy-gmii-sel
58
+
- ti,j784s4-cpsw9g-phy-gmii-sel
58
59
59
60
reg:
60
61
maxItems: 1
···
88
87
- ti,am654-phy-gmii-sel
89
88
- ti,j7200-cpsw5g-phy-gmii-sel
90
89
- ti,j721e-cpsw9g-phy-gmii-sel
90
+
- ti,j784s4-cpsw9g-phy-gmii-sel
91
91
then:
92
92
properties:
93
93
'#phy-cells':
···
115
113
contains:
116
114
enum:
117
115
- ti,j721e-cpsw9g-phy-gmii-sel
116
+
- ti,j784s4-cpsw9g-phy-gmii-sel
118
117
then:
119
118
properties:
120
119
ti,qsgmii-main-ports:
···
133
130
enum:
134
131
- ti,j7200-cpsw5g-phy-gmii-sel
135
132
- ti,j721e-cpsw9g-phy-gmii-sel
133
+
- ti,j784s4-cpsw9g-phy-gmii-sel
136
134
then:
137
135
properties:
138
136
ti,qsgmii-main-ports: false
+11
-14
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+11
-14
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
···
2
2
# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: TI J721E WIZ (SERDES Wrapper)
9
9
···
54
54
55
55
ranges: true
56
56
57
-
assigned-clocks:
58
-
minItems: 1
59
-
maxItems: 2
60
-
61
-
assigned-clock-parents:
62
-
minItems: 1
63
-
maxItems: 2
64
-
65
-
assigned-clock-rates:
66
-
minItems: 1
67
-
maxItems: 2
68
-
69
57
typec-dir-gpios:
70
58
maxItems: 1
71
59
description:
···
89
101
"#clock-cells":
90
102
const: 0
91
103
104
+
clock-output-names:
105
+
maxItems: 1
106
+
92
107
assigned-clocks:
93
108
maxItems: 1
94
109
···
125
134
"#clock-cells":
126
135
const: 0
127
136
137
+
clock-output-names:
138
+
maxItems: 1
139
+
128
140
assigned-clocks:
129
141
maxItems: 1
130
142
···
155
161
156
162
"#clock-cells":
157
163
const: 0
164
+
165
+
clock-output-names:
166
+
maxItems: 1
158
167
159
168
required:
160
169
- clocks
+2
-2
Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml
+2
-2
Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/phy/ti,tcan104x-can.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/phy/ti,tcan104x-can.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: TCAN104x CAN TRANSCEIVER PHY
8
8
-7
MAINTAINERS
-7
MAINTAINERS
···
10530
10530
F: drivers/crypto/intel/keembay/ocs-hcu.c
10531
10531
F: drivers/crypto/intel/keembay/ocs-hcu.h
10532
10532
10533
-
INTEL THUNDER BAY EMMC PHY DRIVER
10534
-
M: Nandhini Srikandan <nandhini.srikandan@intel.com>
10535
-
M: Rashmi A <rashmi.a@intel.com>
10536
-
S: Maintained
10537
-
F: Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml
10538
-
F: drivers/phy/intel/phy-intel-thunderbay-emmc.c
10539
-
10540
10533
INTEL MANAGEMENT ENGINE (mei)
10541
10534
M: Tomas Winkler <tomas.winkler@intel.com>
10542
10535
L: linux-kernel@vger.kernel.org
+1
-1
drivers/phy/Kconfig
+1
-1
drivers/phy/Kconfig
···
44
44
45
45
config PHY_XGENE
46
46
tristate "APM X-Gene 15Gbps PHY support"
47
-
depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
47
+
depends on HAS_IOMEM && OF && (ARCH_XGENE || COMPILE_TEST)
48
48
select GENERIC_PHY
49
49
help
50
50
This option enables support for APM X-Gene SoC multi-purpose PHY.
+3
-5
drivers/phy/allwinner/phy-sun4i-usb.c
+3
-5
drivers/phy/allwinner/phy-sun4i-usb.c
···
698
698
return data->phys[args->args[0]].phy;
699
699
}
700
700
701
-
static int sun4i_usb_phy_remove(struct platform_device *pdev)
701
+
static void sun4i_usb_phy_remove(struct platform_device *pdev)
702
702
{
703
703
struct device *dev = &pdev->dev;
704
704
struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
···
711
711
devm_free_irq(dev, data->vbus_det_irq, data);
712
712
713
713
cancel_delayed_work_sync(&data->detect);
714
-
715
-
return 0;
716
714
}
717
715
718
716
static const unsigned int sun4i_usb_phy0_cable[] = {
···
756
758
return PTR_ERR(data->vbus_det_gpio);
757
759
}
758
760
759
-
if (of_find_property(np, "usb0_vbus_power-supply", NULL)) {
761
+
if (of_property_present(np, "usb0_vbus_power-supply")) {
760
762
data->vbus_power_supply = devm_power_supply_get_by_phandle(dev,
761
763
"usb0_vbus_power-supply");
762
764
if (IS_ERR(data->vbus_power_supply)) {
···
1052
1054
1053
1055
static struct platform_driver sun4i_usb_phy_driver = {
1054
1056
.probe = sun4i_usb_phy_probe,
1055
-
.remove = sun4i_usb_phy_remove,
1057
+
.remove_new = sun4i_usb_phy_remove,
1056
1058
.driver = {
1057
1059
.of_match_table = sun4i_usb_phy_of_match,
1058
1060
.name = "sun4i-usb-phy",
+1
-3
drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c
+1
-3
drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c
···
335
335
{
336
336
struct device *dev = &pdev->dev;
337
337
struct phy_provider *phy_provider;
338
-
struct resource *res;
339
338
struct phy_meson_axg_mipi_dphy_priv *priv;
340
339
struct phy *phy;
341
340
void __iomem *base;
···
347
348
priv->dev = dev;
348
349
platform_set_drvdata(pdev, priv);
349
350
350
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
351
-
base = devm_ioremap_resource(dev, res);
351
+
base = devm_platform_ioremap_resource(pdev, 0);
352
352
if (IS_ERR(base))
353
353
return PTR_ERR(base);
354
354
+1
-1
drivers/phy/broadcom/phy-bcm-ns-usb2.c
+1
-1
drivers/phy/broadcom/phy-bcm-ns-usb2.c
···
107
107
return -ENOMEM;
108
108
usb2->dev = dev;
109
109
110
-
if (of_find_property(dev->of_node, "brcm,syscon-clkset", NULL)) {
110
+
if (of_property_present(dev->of_node, "brcm,syscon-clkset")) {
111
111
usb2->base = devm_platform_ioremap_resource(pdev, 0);
112
112
if (IS_ERR(usb2->base)) {
113
113
dev_err(dev, "Failed to map control reg\n");
+2
-4
drivers/phy/broadcom/phy-brcm-usb.c
+2
-4
drivers/phy/broadcom/phy-brcm-usb.c
···
572
572
return PTR_ERR_OR_ZERO(phy_provider);
573
573
}
574
574
575
-
static int brcm_usb_phy_remove(struct platform_device *pdev)
575
+
static void brcm_usb_phy_remove(struct platform_device *pdev)
576
576
{
577
577
struct brcm_usb_phy_data *priv = dev_get_drvdata(&pdev->dev);
578
578
579
579
sysfs_remove_group(&pdev->dev.kobj, &brcm_usb_phy_group);
580
580
unregister_pm_notifier(&priv->pm_notifier);
581
-
582
-
return 0;
583
581
}
584
582
585
583
#ifdef CONFIG_PM_SLEEP
···
668
670
669
671
static struct platform_driver brcm_usb_driver = {
670
672
.probe = brcm_usb_phy_probe,
671
-
.remove = brcm_usb_phy_remove,
673
+
.remove_new = brcm_usb_phy_remove,
672
674
.driver = {
673
675
.name = "brcmstb-usb-phy",
674
676
.pm = &brcm_usb_phy_pm_ops,
+32
drivers/phy/cadence/cdns-dphy-rx.c
+32
drivers/phy/cadence/cdns-dphy-rx.c
···
11
11
#include <linux/phy/phy.h>
12
12
#include <linux/phy/phy-mipi-dphy.h>
13
13
#include <linux/platform_device.h>
14
+
#include <linux/sys_soc.h>
14
15
15
16
#define DPHY_PMA_CMN(reg) (reg)
16
17
#define DPHY_PCS(reg) (0xb00 + (reg))
17
18
#define DPHY_ISO(reg) (0xc00 + (reg))
19
+
#define DPHY_WRAP(reg) (0x1000 + (reg))
18
20
19
21
#define DPHY_CMN_SSM DPHY_PMA_CMN(0x20)
20
22
#define DPHY_CMN_RX_MODE_EN BIT(10)
···
34
32
35
33
#define DPHY_POWER_ISLAND_EN_CLK DPHY_PCS(0xc)
36
34
#define DPHY_POWER_ISLAND_EN_CLK_VAL 0xaa
35
+
36
+
#define DPHY_LANE DPHY_WRAP(0x0)
37
+
#define DPHY_LANE_RESET_CMN_EN BIT(23)
37
38
38
39
#define DPHY_ISO_CL_CTRL_L DPHY_ISO(0x10)
39
40
#define DPHY_ISO_DL_CTRL_L0 DPHY_ISO(0x14)
···
60
55
/* Rates are in Mbps. */
61
56
unsigned int min_rate;
62
57
unsigned int max_rate;
58
+
};
59
+
60
+
struct cdns_dphy_soc_data {
61
+
bool has_hw_cmn_rstb;
63
62
};
64
63
65
64
/* Order of bands is important since the index is the band number. */
···
151
142
return 0;
152
143
}
153
144
145
+
static struct cdns_dphy_soc_data j721e_soc_data = {
146
+
.has_hw_cmn_rstb = true,
147
+
};
148
+
149
+
static const struct soc_device_attribute cdns_dphy_socinfo[] = {
150
+
{
151
+
.family = "J721E",
152
+
.revision = "SR1.0",
153
+
.data = &j721e_soc_data,
154
+
},
155
+
{/* sentinel */}
156
+
};
157
+
154
158
static int cdns_dphy_rx_configure(struct phy *phy,
155
159
union phy_configure_opts *opts)
156
160
{
157
161
struct cdns_dphy_rx *dphy = phy_get_drvdata(phy);
158
162
unsigned int reg, lanes = opts->mipi_dphy.lanes;
163
+
const struct cdns_dphy_soc_data *soc_data = NULL;
164
+
const struct soc_device_attribute *soc;
159
165
int band_ctrl, ret;
166
+
167
+
soc = soc_device_match(cdns_dphy_socinfo);
168
+
if (soc && soc->data)
169
+
soc_data = soc->data;
170
+
if (!soc || (soc_data && !soc_data->has_hw_cmn_rstb)) {
171
+
reg = DPHY_LANE_RESET_CMN_EN;
172
+
writel(reg, dphy->regs + DPHY_LANE);
173
+
}
160
174
161
175
/* Data lanes. Minimum one lane is mandatory. */
162
176
if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX)
+2
-4
drivers/phy/cadence/cdns-dphy.c
+2
-4
drivers/phy/cadence/cdns-dphy.c
···
456
456
return PTR_ERR_OR_ZERO(phy_provider);
457
457
}
458
458
459
-
static int cdns_dphy_remove(struct platform_device *pdev)
459
+
static void cdns_dphy_remove(struct platform_device *pdev)
460
460
{
461
461
struct cdns_dphy *dphy = dev_get_drvdata(&pdev->dev);
462
462
463
463
if (dphy->ops->remove)
464
464
dphy->ops->remove(dphy);
465
-
466
-
return 0;
467
465
}
468
466
469
467
static const struct of_device_id cdns_dphy_of_match[] = {
···
473
475
474
476
static struct platform_driver cdns_dphy_platform_driver = {
475
477
.probe = cdns_dphy_probe,
476
-
.remove = cdns_dphy_remove,
478
+
.remove_new = cdns_dphy_remove,
477
479
.driver = {
478
480
.name = "cdns-mipi-dphy",
479
481
.of_match_table = cdns_dphy_of_match,
+182
-68
drivers/phy/cadence/phy-cadence-sierra.c
+182
-68
drivers/phy/cadence/phy-cadence-sierra.c
···
24
24
#include <dt-bindings/phy/phy-cadence.h>
25
25
26
26
#define NUM_SSC_MODE 3
27
-
#define NUM_PHY_TYPE 4
27
+
#define NUM_PHY_TYPE 5
28
28
29
29
/* PHY register offsets */
30
30
#define SIERRA_COMMON_CDB_OFFSET 0x0
···
46
46
#define SIERRA_CMN_REFRCV_PREG 0x98
47
47
#define SIERRA_CMN_REFRCV1_PREG 0xB8
48
48
#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
49
+
#define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG 0xC3
49
50
#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA
51
+
#define SIERRA_CMN_PLLLC1_CLK0_PREG 0xCE
50
52
#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0
51
53
#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2
52
54
···
76
74
#define SIERRA_PSC_RX_A1_PREG 0x031
77
75
#define SIERRA_PSC_RX_A2_PREG 0x032
78
76
#define SIERRA_PSC_RX_A3_PREG 0x033
77
+
#define SIERRA_PLLCTRL_FBDIV_MODE01_PREG 0x039
79
78
#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A
80
79
#define SIERRA_PLLCTRL_GEN_A_PREG 0x03B
81
80
#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E
···
209
206
#define PLL_LOCK_TIME 100000
210
207
211
208
#define CDNS_SIERRA_OUTPUT_CLOCKS 3
212
-
#define CDNS_SIERRA_INPUT_CLOCKS 5
209
+
#define CDNS_SIERRA_INPUT_CLOCKS 3
213
210
enum cdns_sierra_clock_input {
214
211
PHY_CLK,
215
212
CMN_REFCLK_DIG_DIV,
216
213
CMN_REFCLK1_DIG_DIV,
217
-
PLL0_REFCLK,
218
-
PLL1_REFCLK,
219
214
};
220
215
221
216
#define SIERRA_NUM_CMN_PLLC 2
···
275
274
#define to_cdns_sierra_pll_mux(_hw) \
276
275
container_of(_hw, struct cdns_sierra_pll_mux, hw)
277
276
278
-
static const int pll_mux_parent_index[][SIERRA_NUM_CMN_PLLC_PARENTS] = {
279
-
[CMN_PLLLC] = { PLL0_REFCLK, PLL1_REFCLK },
280
-
[CMN_PLLLC1] = { PLL1_REFCLK, PLL0_REFCLK },
277
+
#define PLL0_REFCLK_NAME "pll0_refclk"
278
+
#define PLL1_REFCLK_NAME "pll1_refclk"
279
+
280
+
static const struct clk_parent_data pll_mux_parent_data[][SIERRA_NUM_CMN_PLLC_PARENTS] = {
281
+
[CMN_PLLLC] = {
282
+
{ .fw_name = PLL0_REFCLK_NAME },
283
+
{ .fw_name = PLL1_REFCLK_NAME }
284
+
},
285
+
[CMN_PLLLC1] = {
286
+
{ .fw_name = PLL1_REFCLK_NAME },
287
+
{ .fw_name = PLL0_REFCLK_NAME }
288
+
},
281
289
};
282
290
283
291
static u32 cdns_sierra_pll_mux_table[][SIERRA_NUM_CMN_PLLC_PARENTS] = {
···
308
298
TYPE_NONE,
309
299
TYPE_PCIE,
310
300
TYPE_USB,
301
+
TYPE_SGMII,
311
302
TYPE_QSGMII
312
303
};
313
304
···
382
371
u32 num_lanes;
383
372
bool autoconf;
384
373
int already_configured;
385
-
struct clk_onecell_data clk_data;
386
-
struct clk *output_clks[CDNS_SIERRA_OUTPUT_CLOCKS];
374
+
struct clk *pll_clks[SIERRA_NUM_CMN_PLLC];
375
+
struct clk_hw_onecell_data clk_data;
387
376
};
388
377
389
378
static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
···
733
722
struct cdns_sierra_pll_mux *mux;
734
723
struct device *dev = sp->dev;
735
724
struct clk_init_data *init;
736
-
const char **parent_names;
737
-
unsigned int num_parents;
738
725
char clk_name[100];
739
-
struct clk *clk;
740
-
int i;
726
+
int ret;
741
727
742
728
mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
743
729
if (!mux)
744
730
return -ENOMEM;
745
-
746
-
num_parents = SIERRA_NUM_CMN_PLLC_PARENTS;
747
-
parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL);
748
-
if (!parent_names)
749
-
return -ENOMEM;
750
-
751
-
for (i = 0; i < num_parents; i++) {
752
-
clk = sp->input_clks[pll_mux_parent_index[clk_index][i]];
753
-
if (IS_ERR_OR_NULL(clk)) {
754
-
dev_err(dev, "No parent clock for PLL mux clocks\n");
755
-
return IS_ERR(clk) ? PTR_ERR(clk) : -ENOENT;
756
-
}
757
-
parent_names[i] = __clk_get_name(clk);
758
-
}
759
731
760
732
snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]);
761
733
···
746
752
747
753
init->ops = &cdns_sierra_pll_mux_ops;
748
754
init->flags = CLK_SET_RATE_NO_REPARENT;
749
-
init->parent_names = parent_names;
750
-
init->num_parents = num_parents;
755
+
init->parent_data = pll_mux_parent_data[clk_index];
756
+
init->num_parents = SIERRA_NUM_CMN_PLLC_PARENTS;
751
757
init->name = clk_name;
752
758
753
759
mux->pfdclk_sel_preg = pfdclk1_sel_field;
···
755
761
mux->termen_field = termen_field;
756
762
mux->hw.init = init;
757
763
758
-
clk = devm_clk_register(dev, &mux->hw);
759
-
if (IS_ERR(clk))
760
-
return PTR_ERR(clk);
764
+
ret = devm_clk_hw_register(dev, &mux->hw);
765
+
if (ret)
766
+
return ret;
761
767
762
-
sp->output_clks[clk_index] = clk;
768
+
sp->clk_data.hws[clk_index] = &mux->hw;
769
+
770
+
sp->pll_clks[clk_index] = devm_clk_hw_get_clk(dev, &mux->hw,
771
+
clk_names[clk_index]);
763
772
764
773
return 0;
765
774
}
···
835
838
struct clk_init_data *init;
836
839
struct regmap *regmap;
837
840
char clk_name[100];
838
-
struct clk *clk;
841
+
int ret;
839
842
840
843
derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
841
844
if (!derived_refclk)
···
868
871
869
872
derived_refclk->hw.init = init;
870
873
871
-
clk = devm_clk_register(dev, &derived_refclk->hw);
872
-
if (IS_ERR(clk))
873
-
return PTR_ERR(clk);
874
+
ret = devm_clk_hw_register(dev, &derived_refclk->hw);
875
+
if (ret)
876
+
return ret;
874
877
875
-
sp->output_clks[CDNS_SIERRA_DERIVED_REFCLK] = clk;
878
+
sp->clk_data.hws[CDNS_SIERRA_DERIVED_REFCLK] = &derived_refclk->hw;
876
879
877
880
return 0;
878
881
}
···
903
906
return ret;
904
907
}
905
908
906
-
sp->clk_data.clks = sp->output_clks;
907
-
sp->clk_data.clk_num = CDNS_SIERRA_OUTPUT_CLOCKS;
908
-
ret = of_clk_add_provider(node, of_clk_src_onecell_get, &sp->clk_data);
909
+
sp->clk_data.num = CDNS_SIERRA_OUTPUT_CLOCKS;
910
+
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
911
+
&sp->clk_data);
909
912
if (ret)
910
913
dev_err(dev, "Failed to add clock provider: %s\n", node->name);
911
914
···
932
935
break;
933
936
case PHY_TYPE_USB3:
934
937
inst->phy_type = TYPE_USB;
938
+
break;
939
+
case PHY_TYPE_SGMII:
940
+
inst->phy_type = TYPE_SGMII;
935
941
break;
936
942
case PHY_TYPE_QSGMII:
937
943
inst->phy_type = TYPE_QSGMII;
···
1147
1147
}
1148
1148
sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
1149
1149
1150
-
clk = devm_clk_get_optional(dev, "pll0_refclk");
1151
-
if (IS_ERR(clk)) {
1152
-
dev_err(dev, "pll0_refclk clock not found\n");
1153
-
ret = PTR_ERR(clk);
1154
-
return ret;
1155
-
}
1156
-
sp->input_clks[PLL0_REFCLK] = clk;
1157
-
1158
-
clk = devm_clk_get_optional(dev, "pll1_refclk");
1159
-
if (IS_ERR(clk)) {
1160
-
dev_err(dev, "pll1_refclk clock not found\n");
1161
-
ret = PTR_ERR(clk);
1162
-
return ret;
1163
-
}
1164
-
sp->input_clks[PLL1_REFCLK] = clk;
1165
-
1166
1150
return 0;
1167
1151
}
1168
1152
···
1174
1190
{
1175
1191
int ret;
1176
1192
1177
-
ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
1193
+
ret = clk_prepare_enable(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]);
1178
1194
if (ret)
1179
1195
return ret;
1180
1196
1181
-
ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]);
1197
+
ret = clk_prepare_enable(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]);
1182
1198
if (ret)
1183
1199
goto err_pll_cmnlc1;
1184
1200
1185
1201
return 0;
1186
1202
1187
1203
err_pll_cmnlc1:
1188
-
clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
1204
+
clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]);
1189
1205
1190
1206
return ret;
1191
1207
}
1192
1208
1193
1209
static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp)
1194
1210
{
1195
-
clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]);
1196
-
clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
1211
+
clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]);
1212
+
clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]);
1197
1213
if (!sp->already_configured)
1198
1214
clk_disable_unprepare(sp->input_clks[PHY_CLK]);
1199
1215
}
···
1323
1339
}
1324
1340
}
1325
1341
1326
-
if (phy_t1 == TYPE_QSGMII)
1342
+
if (phy_t1 == TYPE_SGMII || phy_t1 == TYPE_QSGMII)
1327
1343
reset_control_deassert(sp->phys[node].lnk_rst);
1328
1344
}
1329
1345
···
1354
1370
if (!data)
1355
1371
return -EINVAL;
1356
1372
1357
-
sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL);
1373
+
sp = devm_kzalloc(dev, struct_size(sp, clk_data.hws,
1374
+
CDNS_SIERRA_OUTPUT_CLOCKS),
1375
+
GFP_KERNEL);
1358
1376
if (!sp)
1359
1377
return -ENOMEM;
1360
1378
dev_set_drvdata(dev, sp);
···
1499
1513
return ret;
1500
1514
}
1501
1515
1502
-
static int cdns_sierra_phy_remove(struct platform_device *pdev)
1516
+
static void cdns_sierra_phy_remove(struct platform_device *pdev)
1503
1517
{
1504
1518
struct cdns_sierra_phy *phy = platform_get_drvdata(pdev);
1505
1519
int i;
···
1519
1533
}
1520
1534
1521
1535
cdns_sierra_clk_unregister(phy);
1522
-
1523
-
return 0;
1524
1536
}
1537
+
1538
+
/* SGMII PHY PMA lane configuration */
1539
+
static struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] = {
1540
+
{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
1541
+
};
1542
+
1543
+
static struct cdns_sierra_vals sgmii_phy_pma_ln_vals = {
1544
+
.reg_pairs = sgmii_phy_pma_ln_regs,
1545
+
.num_regs = ARRAY_SIZE(sgmii_phy_pma_ln_regs),
1546
+
};
1547
+
1548
+
/* SGMII refclk 100MHz, no ssc, opt3 and GE1 links using PLL LC1 */
1549
+
static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_cmn_regs[] = {
1550
+
{0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG},
1551
+
{0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
1552
+
{0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG},
1553
+
{0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
1554
+
{0x0800, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
1555
+
};
1556
+
1557
+
static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_ln_regs[] = {
1558
+
{0x688E, SIERRA_DET_STANDEC_D_PREG},
1559
+
{0x0004, SIERRA_PSC_LN_IDLE_PREG},
1560
+
{0x0FFE, SIERRA_PSC_RX_A0_PREG},
1561
+
{0x0106, SIERRA_PLLCTRL_FBDIV_MODE01_PREG},
1562
+
{0x0013, SIERRA_PLLCTRL_SUBRATE_PREG},
1563
+
{0x0003, SIERRA_PLLCTRL_GEN_A_PREG},
1564
+
{0x0106, SIERRA_PLLCTRL_GEN_D_PREG},
1565
+
{0x5231, SIERRA_PLLCTRL_CPGAIN_MODE_PREG },
1566
+
{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
1567
+
{0x9702, SIERRA_DRVCTRL_BOOST_PREG},
1568
+
{0x0051, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1569
+
{0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG},
1570
+
{0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG},
1571
+
{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
1572
+
{0x0002, SIERRA_DEQ_PHALIGN_CTRL},
1573
+
{0x0186, SIERRA_DEQ_GLUT0},
1574
+
{0x0186, SIERRA_DEQ_GLUT1},
1575
+
{0x0186, SIERRA_DEQ_GLUT2},
1576
+
{0x0186, SIERRA_DEQ_GLUT3},
1577
+
{0x0186, SIERRA_DEQ_GLUT4},
1578
+
{0x0861, SIERRA_DEQ_ALUT0},
1579
+
{0x07E0, SIERRA_DEQ_ALUT1},
1580
+
{0x079E, SIERRA_DEQ_ALUT2},
1581
+
{0x071D, SIERRA_DEQ_ALUT3},
1582
+
{0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},
1583
+
{0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
1584
+
{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1585
+
{0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},
1586
+
{0x0033, SIERRA_DEQ_PICTRL_PREG},
1587
+
{0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG},
1588
+
{0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},
1589
+
{0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},
1590
+
{0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}
1591
+
};
1592
+
1593
+
static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_cmn_vals = {
1594
+
.reg_pairs = sgmii_100_no_ssc_plllc1_opt3_cmn_regs,
1595
+
.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_cmn_regs),
1596
+
};
1597
+
1598
+
static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_ln_vals = {
1599
+
.reg_pairs = sgmii_100_no_ssc_plllc1_opt3_ln_regs,
1600
+
.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_ln_regs),
1601
+
};
1525
1602
1526
1603
/* QSGMII PHY PMA lane configuration */
1527
1604
static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = {
···
2412
2363
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2413
2364
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2414
2365
},
2366
+
[TYPE_SGMII] = {
2367
+
[NO_SSC] = &pcie_phy_pcs_cmn_vals,
2368
+
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2369
+
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2370
+
},
2415
2371
[TYPE_QSGMII] = {
2416
2372
[NO_SSC] = &pcie_phy_pcs_cmn_vals,
2417
2373
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
···
2431
2377
[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
2432
2378
[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
2433
2379
},
2380
+
[TYPE_SGMII] = {
2381
+
[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
2382
+
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
2383
+
[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
2384
+
},
2434
2385
[TYPE_QSGMII] = {
2435
2386
[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
2436
2387
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
···
2445
2386
[TYPE_USB] = {
2446
2387
[TYPE_NONE] = {
2447
2388
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
2389
+
},
2390
+
},
2391
+
[TYPE_SGMII] = {
2392
+
[TYPE_PCIE] = {
2393
+
[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2394
+
[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2395
+
[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2448
2396
},
2449
2397
},
2450
2398
[TYPE_QSGMII] = {
···
2469
2403
[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
2470
2404
[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
2471
2405
},
2406
+
[TYPE_SGMII] = {
2407
+
[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
2408
+
[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
2409
+
[INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
2410
+
},
2472
2411
[TYPE_QSGMII] = {
2473
2412
[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
2474
2413
[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
···
2483
2412
[TYPE_USB] = {
2484
2413
[TYPE_NONE] = {
2485
2414
[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
2415
+
},
2416
+
},
2417
+
[TYPE_SGMII] = {
2418
+
[TYPE_PCIE] = {
2419
+
[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2420
+
[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2421
+
[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2486
2422
},
2487
2423
},
2488
2424
[TYPE_QSGMII] = {
···
2513
2435
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2514
2436
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2515
2437
},
2438
+
[TYPE_SGMII] = {
2439
+
[NO_SSC] = &pcie_phy_pcs_cmn_vals,
2440
+
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2441
+
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2442
+
},
2516
2443
[TYPE_QSGMII] = {
2517
2444
[NO_SSC] = &pcie_phy_pcs_cmn_vals,
2518
2445
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
···
2526
2443
},
2527
2444
},
2528
2445
.phy_pma_ln_vals = {
2446
+
[TYPE_SGMII] = {
2447
+
[TYPE_PCIE] = {
2448
+
[NO_SSC] = &sgmii_phy_pma_ln_vals,
2449
+
[EXTERNAL_SSC] = &sgmii_phy_pma_ln_vals,
2450
+
[INTERNAL_SSC] = &sgmii_phy_pma_ln_vals,
2451
+
},
2452
+
},
2529
2453
[TYPE_QSGMII] = {
2530
2454
[TYPE_PCIE] = {
2531
2455
[NO_SSC] = &qsgmii_phy_pma_ln_vals,
···
2548
2458
[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
2549
2459
[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
2550
2460
},
2461
+
[TYPE_SGMII] = {
2462
+
[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
2463
+
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
2464
+
[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
2465
+
},
2551
2466
[TYPE_QSGMII] = {
2552
2467
[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
2553
2468
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
···
2562
2467
[TYPE_USB] = {
2563
2468
[TYPE_NONE] = {
2564
2469
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
2470
+
},
2471
+
},
2472
+
[TYPE_SGMII] = {
2473
+
[TYPE_PCIE] = {
2474
+
[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2475
+
[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2476
+
[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2565
2477
},
2566
2478
},
2567
2479
[TYPE_QSGMII] = {
···
2586
2484
[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
2587
2485
[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
2588
2486
},
2487
+
[TYPE_SGMII] = {
2488
+
[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,
2489
+
[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,
2490
+
[INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals,
2491
+
},
2589
2492
[TYPE_QSGMII] = {
2590
2493
[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,
2591
2494
[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,
···
2600
2493
[TYPE_USB] = {
2601
2494
[TYPE_NONE] = {
2602
2495
[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
2496
+
},
2497
+
},
2498
+
[TYPE_SGMII] = {
2499
+
[TYPE_PCIE] = {
2500
+
[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2501
+
[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2502
+
[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2603
2503
},
2604
2504
},
2605
2505
[TYPE_QSGMII] = {
···
2634
2520
2635
2521
static struct platform_driver cdns_sierra_driver = {
2636
2522
.probe = cdns_sierra_phy_probe,
2637
-
.remove = cdns_sierra_phy_remove,
2523
+
.remove_new = cdns_sierra_phy_remove,
2638
2524
.driver = {
2639
2525
.name = "cdns-sierra-phy",
2640
2526
.of_match_table = cdns_sierra_id_table,
+2
-4
drivers/phy/cadence/phy-cadence-torrent.c
+2
-4
drivers/phy/cadence/phy-cadence-torrent.c
···
2777
2777
return ret;
2778
2778
}
2779
2779
2780
-
static int cdns_torrent_phy_remove(struct platform_device *pdev)
2780
+
static void cdns_torrent_phy_remove(struct platform_device *pdev)
2781
2781
{
2782
2782
struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
2783
2783
int i;
···
2791
2791
2792
2792
clk_disable_unprepare(cdns_phy->clk);
2793
2793
cdns_torrent_clk_cleanup(cdns_phy);
2794
-
2795
-
return 0;
2796
2794
}
2797
2795
2798
2796
/* Single DisplayPort(DP) link configuration */
···
4706
4708
4707
4709
static struct platform_driver cdns_torrent_phy_driver = {
4708
4710
.probe = cdns_torrent_phy_probe,
4709
-
.remove = cdns_torrent_phy_remove,
4711
+
.remove_new = cdns_torrent_phy_remove,
4710
4712
.driver = {
4711
4713
.name = "cdns-torrent-phy",
4712
4714
.of_match_table = cdns_torrent_phy_of_match,
+2
-4
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
+2
-4
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
···
391
391
return ret;
392
392
}
393
393
394
-
static int mixel_lvds_phy_remove(struct platform_device *pdev)
394
+
static void mixel_lvds_phy_remove(struct platform_device *pdev)
395
395
{
396
396
pm_runtime_disable(&pdev->dev);
397
-
398
-
return 0;
399
397
}
400
398
401
399
static int __maybe_unused mixel_lvds_phy_runtime_suspend(struct device *dev)
···
434
436
435
437
static struct platform_driver mixel_lvds_phy_driver = {
436
438
.probe = mixel_lvds_phy_probe,
437
-
.remove = mixel_lvds_phy_remove,
439
+
.remove_new = mixel_lvds_phy_remove,
438
440
.driver = {
439
441
.pm = &mixel_lvds_phy_pm_ops,
440
442
.name = "mixel-lvds-phy",
-10
drivers/phy/intel/Kconfig
-10
drivers/phy/intel/Kconfig
···
46
46
select GENERIC_PHY
47
47
help
48
48
Enable this to support the Intel EMMC PHY
49
-
50
-
config PHY_INTEL_THUNDERBAY_EMMC
51
-
tristate "Intel Thunder Bay eMMC PHY driver"
52
-
depends on OF && (ARCH_THUNDERBAY || COMPILE_TEST)
53
-
select GENERIC_PHY
54
-
help
55
-
This option enables support for Intel Thunder Bay SoC eMMC PHY.
56
-
57
-
To compile this driver as a module, choose M here: the module
58
-
will be called phy-intel-thunderbay-emmc.ko.
-1
drivers/phy/intel/Makefile
-1
drivers/phy/intel/Makefile
+2
-3
drivers/phy/intel/phy-intel-lgm-combo.c
+2
-3
drivers/phy/intel/phy-intel-lgm-combo.c
···
589
589
return intel_cbphy_create(cbphy);
590
590
}
591
591
592
-
static int intel_cbphy_remove(struct platform_device *pdev)
592
+
static void intel_cbphy_remove(struct platform_device *pdev)
593
593
{
594
594
struct intel_combo_phy *cbphy = platform_get_drvdata(pdev);
595
595
596
596
intel_cbphy_rst_assert(cbphy);
597
597
clk_disable_unprepare(cbphy->core_clk);
598
-
return 0;
599
598
}
600
599
601
600
static const struct of_device_id of_intel_cbphy_match[] = {
···
605
606
606
607
static struct platform_driver intel_cbphy_driver = {
607
608
.probe = intel_cbphy_probe,
608
-
.remove = intel_cbphy_remove,
609
+
.remove_new = intel_cbphy_remove,
609
610
.driver = {
610
611
.name = "intel-combo-phy",
611
612
.of_match_table = of_intel_cbphy_match,
-509
drivers/phy/intel/phy-intel-thunderbay-emmc.c
-509
drivers/phy/intel/phy-intel-thunderbay-emmc.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* Intel ThunderBay eMMC PHY driver
4
-
*
5
-
* Copyright (C) 2021 Intel Corporation
6
-
*
7
-
*/
8
-
9
-
#include <linux/clk.h>
10
-
#include <linux/delay.h>
11
-
#include <linux/io.h>
12
-
#include <linux/iopoll.h>
13
-
#include <linux/module.h>
14
-
#include <linux/of.h>
15
-
#include <linux/phy/phy.h>
16
-
#include <linux/platform_device.h>
17
-
18
-
/* eMMC/SD/SDIO core/phy configuration registers */
19
-
#define CTRL_CFG_0 0x00
20
-
#define CTRL_CFG_1 0x04
21
-
#define CTRL_PRESET_0 0x08
22
-
#define CTRL_PRESET_1 0x0c
23
-
#define CTRL_PRESET_2 0x10
24
-
#define CTRL_PRESET_3 0x14
25
-
#define CTRL_PRESET_4 0x18
26
-
#define CTRL_CFG_2 0x1c
27
-
#define CTRL_CFG_3 0x20
28
-
#define PHY_CFG_0 0x24
29
-
#define PHY_CFG_1 0x28
30
-
#define PHY_CFG_2 0x2c
31
-
#define PHYBIST_CTRL 0x30
32
-
#define SDHC_STAT3 0x34
33
-
#define PHY_STAT 0x38
34
-
#define PHYBIST_STAT_0 0x3c
35
-
#define PHYBIST_STAT_1 0x40
36
-
#define EMMC_AXI 0x44
37
-
38
-
/* CTRL_PRESET_3 */
39
-
#define CTRL_PRESET3_MASK GENMASK(31, 0)
40
-
#define CTRL_PRESET3_SHIFT 0
41
-
42
-
/* CTRL_CFG_0 bit fields */
43
-
#define SUPPORT_HS_MASK BIT(26)
44
-
#define SUPPORT_HS_SHIFT 26
45
-
46
-
#define SUPPORT_8B_MASK BIT(24)
47
-
#define SUPPORT_8B_SHIFT 24
48
-
49
-
/* CTRL_CFG_1 bit fields */
50
-
#define SUPPORT_SDR50_MASK BIT(28)
51
-
#define SUPPORT_SDR50_SHIFT 28
52
-
#define SLOT_TYPE_MASK GENMASK(27, 26)
53
-
#define SLOT_TYPE_OFFSET 26
54
-
#define SUPPORT_64B_MASK BIT(24)
55
-
#define SUPPORT_64B_SHIFT 24
56
-
#define SUPPORT_HS400_MASK BIT(2)
57
-
#define SUPPORT_HS400_SHIFT 2
58
-
#define SUPPORT_DDR50_MASK BIT(1)
59
-
#define SUPPORT_DDR50_SHIFT 1
60
-
#define SUPPORT_SDR104_MASK BIT(0)
61
-
#define SUPPORT_SDR104_SHIFT 0
62
-
63
-
/* PHY_CFG_0 bit fields */
64
-
#define SEL_DLY_TXCLK_MASK BIT(29)
65
-
#define SEL_DLY_TXCLK_SHIFT 29
66
-
#define SEL_DLY_RXCLK_MASK BIT(28)
67
-
#define SEL_DLY_RXCLK_SHIFT 28
68
-
69
-
#define OTAP_DLY_ENA_MASK BIT(27)
70
-
#define OTAP_DLY_ENA_SHIFT 27
71
-
#define OTAP_DLY_SEL_MASK GENMASK(26, 23)
72
-
#define OTAP_DLY_SEL_SHIFT 23
73
-
#define ITAP_CHG_WIN_MASK BIT(22)
74
-
#define ITAP_CHG_WIN_SHIFT 22
75
-
#define ITAP_DLY_ENA_MASK BIT(21)
76
-
#define ITAP_DLY_ENA_SHIFT 21
77
-
#define ITAP_DLY_SEL_MASK GENMASK(20, 16)
78
-
#define ITAP_DLY_SEL_SHIFT 16
79
-
#define RET_ENB_MASK BIT(15)
80
-
#define RET_ENB_SHIFT 15
81
-
#define RET_EN_MASK BIT(14)
82
-
#define RET_EN_SHIFT 14
83
-
#define DLL_IFF_MASK GENMASK(13, 11)
84
-
#define DLL_IFF_SHIFT 11
85
-
#define DLL_EN_MASK BIT(10)
86
-
#define DLL_EN_SHIFT 10
87
-
#define DLL_TRIM_ICP_MASK GENMASK(9, 6)
88
-
#define DLL_TRIM_ICP_SHIFT 6
89
-
#define RETRIM_EN_MASK BIT(5)
90
-
#define RETRIM_EN_SHIFT 5
91
-
#define RETRIM_MASK BIT(4)
92
-
#define RETRIM_SHIFT 4
93
-
#define DR_TY_MASK GENMASK(3, 1)
94
-
#define DR_TY_SHIFT 1
95
-
#define PWR_DOWN_MASK BIT(0)
96
-
#define PWR_DOWN_SHIFT 0
97
-
98
-
/* PHY_CFG_1 bit fields */
99
-
#define REN_DAT_MASK GENMASK(19, 12)
100
-
#define REN_DAT_SHIFT 12
101
-
#define REN_CMD_MASK BIT(11)
102
-
#define REN_CMD_SHIFT 11
103
-
#define REN_STRB_MASK BIT(10)
104
-
#define REN_STRB_SHIFT 10
105
-
#define PU_STRB_MASK BIT(20)
106
-
#define PU_STRB_SHIFT 20
107
-
108
-
/* PHY_CFG_2 bit fields */
109
-
#define CLKBUF_MASK GENMASK(24, 21)
110
-
#define CLKBUF_SHIFT 21
111
-
#define SEL_STRB_MASK GENMASK(20, 13)
112
-
#define SEL_STRB_SHIFT 13
113
-
#define SEL_FREQ_MASK GENMASK(12, 10)
114
-
#define SEL_FREQ_SHIFT 10
115
-
116
-
/* PHY_STAT bit fields */
117
-
#define CAL_DONE BIT(6)
118
-
#define DLL_RDY BIT(5)
119
-
120
-
#define OTAP_DLY 0x0
121
-
#define ITAP_DLY 0x0
122
-
#define STRB 0x33
123
-
124
-
/* From ACS_eMMC51_16nFFC_RO1100_Userguide_v1p0.pdf p17 */
125
-
#define FREQSEL_200M_170M 0x0
126
-
#define FREQSEL_170M_140M 0x1
127
-
#define FREQSEL_140M_110M 0x2
128
-
#define FREQSEL_110M_80M 0x3
129
-
#define FREQSEL_80M_50M 0x4
130
-
#define FREQSEL_275M_250M 0x5
131
-
#define FREQSEL_250M_225M 0x6
132
-
#define FREQSEL_225M_200M 0x7
133
-
134
-
/* Phy power status */
135
-
#define PHY_UNINITIALIZED 0
136
-
#define PHY_INITIALIZED 1
137
-
138
-
/*
139
-
* During init(400KHz) phy_settings will be called with 200MHZ clock
140
-
* To avoid incorrectly setting the phy for init(400KHZ) "phy_power_sts" is used.
141
-
* When actual clock is set always phy is powered off once and then powered on.
142
-
* (sdhci_arasan_set_clock). That feature will be used to identify whether the
143
-
* settings are for init phy_power_on or actual clock phy_power_on
144
-
* 0 --> init settings
145
-
* 1 --> actual settings
146
-
*/
147
-
148
-
struct thunderbay_emmc_phy {
149
-
void __iomem *reg_base;
150
-
struct clk *emmcclk;
151
-
int phy_power_sts;
152
-
};
153
-
154
-
static inline void update_reg(struct thunderbay_emmc_phy *tbh_phy, u32 offset,
155
-
u32 mask, u32 shift, u32 val)
156
-
{
157
-
u32 tmp;
158
-
159
-
tmp = readl(tbh_phy->reg_base + offset);
160
-
tmp &= ~mask;
161
-
tmp |= val << shift;
162
-
writel(tmp, tbh_phy->reg_base + offset);
163
-
}
164
-
165
-
static int thunderbay_emmc_phy_power(struct phy *phy, bool power_on)
166
-
{
167
-
struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
168
-
unsigned int freqsel = FREQSEL_200M_170M;
169
-
unsigned long rate;
170
-
static int lock;
171
-
u32 val;
172
-
int ret;
173
-
174
-
/* Disable DLL */
175
-
rate = clk_get_rate(tbh_phy->emmcclk);
176
-
switch (rate) {
177
-
case 200000000:
178
-
/* lock dll only when it is used, i.e only if SEL_DLY_TXCLK/RXCLK are 0 */
179
-
update_reg(tbh_phy, PHY_CFG_0, DLL_EN_MASK, DLL_EN_SHIFT, 0x0);
180
-
break;
181
-
182
-
/* dll lock not required for other frequencies */
183
-
case 50000000 ... 52000000:
184
-
case 400000:
185
-
default:
186
-
break;
187
-
}
188
-
189
-
if (!power_on)
190
-
return 0;
191
-
192
-
rate = clk_get_rate(tbh_phy->emmcclk);
193
-
switch (rate) {
194
-
case 170000001 ... 200000000:
195
-
freqsel = FREQSEL_200M_170M;
196
-
break;
197
-
198
-
case 140000001 ... 170000000:
199
-
freqsel = FREQSEL_170M_140M;
200
-
break;
201
-
202
-
case 110000001 ... 140000000:
203
-
freqsel = FREQSEL_140M_110M;
204
-
break;
205
-
206
-
case 80000001 ... 110000000:
207
-
freqsel = FREQSEL_110M_80M;
208
-
break;
209
-
210
-
case 50000000 ... 80000000:
211
-
freqsel = FREQSEL_80M_50M;
212
-
break;
213
-
214
-
case 250000001 ... 275000000:
215
-
freqsel = FREQSEL_275M_250M;
216
-
break;
217
-
218
-
case 225000001 ... 250000000:
219
-
freqsel = FREQSEL_250M_225M;
220
-
break;
221
-
222
-
case 200000001 ... 225000000:
223
-
freqsel = FREQSEL_225M_200M;
224
-
break;
225
-
default:
226
-
break;
227
-
}
228
-
/* Clock rate is checked against upper limit. It may fall low during init */
229
-
if (rate > 200000000)
230
-
dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
231
-
232
-
udelay(5);
233
-
234
-
if (lock == 0) {
235
-
/* PDB will be done only once per boot */
236
-
update_reg(tbh_phy, PHY_CFG_0, PWR_DOWN_MASK,
237
-
PWR_DOWN_SHIFT, 0x1);
238
-
lock = 1;
239
-
/*
240
-
* According to the user manual, it asks driver to wait 5us for
241
-
* calpad busy trimming. However it is documented that this value is
242
-
* PVT(A.K.A. process, voltage and temperature) relevant, so some
243
-
* failure cases are found which indicates we should be more tolerant
244
-
* to calpad busy trimming.
245
-
*/
246
-
ret = readl_poll_timeout(tbh_phy->reg_base + PHY_STAT,
247
-
val, (val & CAL_DONE), 10, 50);
248
-
if (ret) {
249
-
dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);
250
-
return ret;
251
-
}
252
-
}
253
-
rate = clk_get_rate(tbh_phy->emmcclk);
254
-
switch (rate) {
255
-
case 200000000:
256
-
/* Set frequency of the DLL operation */
257
-
update_reg(tbh_phy, PHY_CFG_2, SEL_FREQ_MASK, SEL_FREQ_SHIFT, freqsel);
258
-
259
-
/* Enable DLL */
260
-
update_reg(tbh_phy, PHY_CFG_0, DLL_EN_MASK, DLL_EN_SHIFT, 0x1);
261
-
262
-
/*
263
-
* After enabling analog DLL circuits docs say that we need 10.2 us if
264
-
* our source clock is at 50 MHz and that lock time scales linearly
265
-
* with clock speed. If we are powering on the PHY and the card clock
266
-
* is super slow (like 100kHz) this could take as long as 5.1 ms as
267
-
* per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
268
-
* hopefully we won't be running at 100 kHz, but we should still make
269
-
* sure we wait long enough.
270
-
*
271
-
* NOTE: There appear to be corner cases where the DLL seems to take
272
-
* extra long to lock for reasons that aren't understood. In some
273
-
* extreme cases we've seen it take up to over 10ms (!). We'll be
274
-
* generous and give it 50ms.
275
-
*/
276
-
ret = readl_poll_timeout(tbh_phy->reg_base + PHY_STAT,
277
-
val, (val & DLL_RDY), 10, 50 * USEC_PER_MSEC);
278
-
if (ret) {
279
-
dev_err(&phy->dev, "dllrdy failed, ret=%d\n", ret);
280
-
return ret;
281
-
}
282
-
break;
283
-
284
-
default:
285
-
break;
286
-
}
287
-
return 0;
288
-
}
289
-
290
-
static int thunderbay_emmc_phy_init(struct phy *phy)
291
-
{
292
-
struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
293
-
294
-
tbh_phy->emmcclk = clk_get(&phy->dev, "emmcclk");
295
-
296
-
return PTR_ERR_OR_ZERO(tbh_phy->emmcclk);
297
-
}
298
-
299
-
static int thunderbay_emmc_phy_exit(struct phy *phy)
300
-
{
301
-
struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
302
-
303
-
clk_put(tbh_phy->emmcclk);
304
-
305
-
return 0;
306
-
}
307
-
308
-
static int thunderbay_emmc_phy_power_on(struct phy *phy)
309
-
{
310
-
struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
311
-
unsigned long rate;
312
-
313
-
/* Overwrite capability bits configurable in bootloader */
314
-
update_reg(tbh_phy, CTRL_CFG_0,
315
-
SUPPORT_HS_MASK, SUPPORT_HS_SHIFT, 0x1);
316
-
update_reg(tbh_phy, CTRL_CFG_0,
317
-
SUPPORT_8B_MASK, SUPPORT_8B_SHIFT, 0x1);
318
-
update_reg(tbh_phy, CTRL_CFG_1,
319
-
SUPPORT_SDR50_MASK, SUPPORT_SDR50_SHIFT, 0x1);
320
-
update_reg(tbh_phy, CTRL_CFG_1,
321
-
SUPPORT_DDR50_MASK, SUPPORT_DDR50_SHIFT, 0x1);
322
-
update_reg(tbh_phy, CTRL_CFG_1,
323
-
SUPPORT_SDR104_MASK, SUPPORT_SDR104_SHIFT, 0x1);
324
-
update_reg(tbh_phy, CTRL_CFG_1,
325
-
SUPPORT_HS400_MASK, SUPPORT_HS400_SHIFT, 0x1);
326
-
update_reg(tbh_phy, CTRL_CFG_1,
327
-
SUPPORT_64B_MASK, SUPPORT_64B_SHIFT, 0x1);
328
-
329
-
if (tbh_phy->phy_power_sts == PHY_UNINITIALIZED) {
330
-
/* Indicates initialization, settings for init, same as 400KHZ setting */
331
-
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK, SEL_DLY_TXCLK_SHIFT, 0x1);
332
-
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK, SEL_DLY_RXCLK_SHIFT, 0x1);
333
-
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK, ITAP_DLY_ENA_SHIFT, 0x0);
334
-
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK, ITAP_DLY_SEL_SHIFT, 0x0);
335
-
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK, OTAP_DLY_ENA_SHIFT, 0x0);
336
-
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK, OTAP_DLY_SEL_SHIFT, 0);
337
-
update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK, DLL_TRIM_ICP_SHIFT, 0);
338
-
update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK, DR_TY_SHIFT, 0x1);
339
-
340
-
} else if (tbh_phy->phy_power_sts == PHY_INITIALIZED) {
341
-
/* Indicates actual clock setting */
342
-
rate = clk_get_rate(tbh_phy->emmcclk);
343
-
switch (rate) {
344
-
case 200000000:
345
-
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
346
-
SEL_DLY_TXCLK_SHIFT, 0x0);
347
-
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
348
-
SEL_DLY_RXCLK_SHIFT, 0x0);
349
-
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
350
-
ITAP_DLY_ENA_SHIFT, 0x0);
351
-
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
352
-
ITAP_DLY_SEL_SHIFT, 0x0);
353
-
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
354
-
OTAP_DLY_ENA_SHIFT, 0x1);
355
-
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
356
-
OTAP_DLY_SEL_SHIFT, 2);
357
-
update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
358
-
DLL_TRIM_ICP_SHIFT, 0x8);
359
-
update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK,
360
-
DR_TY_SHIFT, 0x1);
361
-
/* For HS400 only */
362
-
update_reg(tbh_phy, PHY_CFG_2, SEL_STRB_MASK,
363
-
SEL_STRB_SHIFT, STRB);
364
-
break;
365
-
366
-
case 50000000 ... 52000000:
367
-
/* For both HS and DDR52 this setting works */
368
-
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
369
-
SEL_DLY_TXCLK_SHIFT, 0x1);
370
-
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
371
-
SEL_DLY_RXCLK_SHIFT, 0x1);
372
-
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
373
-
ITAP_DLY_ENA_SHIFT, 0x0);
374
-
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
375
-
ITAP_DLY_SEL_SHIFT, 0x0);
376
-
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
377
-
OTAP_DLY_ENA_SHIFT, 0x1);
378
-
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
379
-
OTAP_DLY_SEL_SHIFT, 4);
380
-
update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
381
-
DLL_TRIM_ICP_SHIFT, 0x8);
382
-
update_reg(tbh_phy, PHY_CFG_0,
383
-
DR_TY_MASK, DR_TY_SHIFT, 0x1);
384
-
break;
385
-
386
-
case 400000:
387
-
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
388
-
SEL_DLY_TXCLK_SHIFT, 0x1);
389
-
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
390
-
SEL_DLY_RXCLK_SHIFT, 0x1);
391
-
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
392
-
ITAP_DLY_ENA_SHIFT, 0x0);
393
-
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
394
-
ITAP_DLY_SEL_SHIFT, 0x0);
395
-
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
396
-
OTAP_DLY_ENA_SHIFT, 0x0);
397
-
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
398
-
OTAP_DLY_SEL_SHIFT, 0);
399
-
update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
400
-
DLL_TRIM_ICP_SHIFT, 0);
401
-
update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK, DR_TY_SHIFT, 0x1);
402
-
break;
403
-
404
-
default:
405
-
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
406
-
SEL_DLY_TXCLK_SHIFT, 0x1);
407
-
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
408
-
SEL_DLY_RXCLK_SHIFT, 0x1);
409
-
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
410
-
ITAP_DLY_ENA_SHIFT, 0x0);
411
-
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
412
-
ITAP_DLY_SEL_SHIFT, 0x0);
413
-
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
414
-
OTAP_DLY_ENA_SHIFT, 0x1);
415
-
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
416
-
OTAP_DLY_SEL_SHIFT, 2);
417
-
update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
418
-
DLL_TRIM_ICP_SHIFT, 0x8);
419
-
update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK,
420
-
DR_TY_SHIFT, 0x1);
421
-
break;
422
-
}
423
-
/* Reset, init seq called without phy_power_off, this indicates init seq */
424
-
tbh_phy->phy_power_sts = PHY_UNINITIALIZED;
425
-
}
426
-
427
-
update_reg(tbh_phy, PHY_CFG_0, RETRIM_EN_MASK, RETRIM_EN_SHIFT, 0x1);
428
-
update_reg(tbh_phy, PHY_CFG_0, RETRIM_MASK, RETRIM_SHIFT, 0x0);
429
-
430
-
return thunderbay_emmc_phy_power(phy, 1);
431
-
}
432
-
433
-
static int thunderbay_emmc_phy_power_off(struct phy *phy)
434
-
{
435
-
struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
436
-
437
-
tbh_phy->phy_power_sts = PHY_INITIALIZED;
438
-
439
-
return thunderbay_emmc_phy_power(phy, 0);
440
-
}
441
-
442
-
static const struct phy_ops thunderbay_emmc_phy_ops = {
443
-
.init = thunderbay_emmc_phy_init,
444
-
.exit = thunderbay_emmc_phy_exit,
445
-
.power_on = thunderbay_emmc_phy_power_on,
446
-
.power_off = thunderbay_emmc_phy_power_off,
447
-
.owner = THIS_MODULE,
448
-
};
449
-
450
-
static const struct of_device_id thunderbay_emmc_phy_of_match[] = {
451
-
{ .compatible = "intel,thunderbay-emmc-phy",
452
-
(void *)&thunderbay_emmc_phy_ops },
453
-
{}
454
-
};
455
-
MODULE_DEVICE_TABLE(of, thunderbay_emmc_phy_of_match);
456
-
457
-
static int thunderbay_emmc_phy_probe(struct platform_device *pdev)
458
-
{
459
-
struct thunderbay_emmc_phy *tbh_phy;
460
-
struct phy_provider *phy_provider;
461
-
struct device *dev = &pdev->dev;
462
-
const struct of_device_id *id;
463
-
struct phy *generic_phy;
464
-
struct resource *res;
465
-
466
-
if (!dev->of_node)
467
-
return -ENODEV;
468
-
469
-
tbh_phy = devm_kzalloc(dev, sizeof(*tbh_phy), GFP_KERNEL);
470
-
if (!tbh_phy)
471
-
return -ENOMEM;
472
-
473
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474
-
tbh_phy->reg_base = devm_ioremap_resource(&pdev->dev, res);
475
-
if (IS_ERR(tbh_phy->reg_base))
476
-
return PTR_ERR(tbh_phy->reg_base);
477
-
478
-
tbh_phy->phy_power_sts = PHY_UNINITIALIZED;
479
-
id = of_match_node(thunderbay_emmc_phy_of_match, pdev->dev.of_node);
480
-
if (!id) {
481
-
dev_err(dev, "failed to get match_node\n");
482
-
return -EINVAL;
483
-
}
484
-
485
-
generic_phy = devm_phy_create(dev, dev->of_node, id->data);
486
-
if (IS_ERR(generic_phy)) {
487
-
dev_err(dev, "failed to create PHY\n");
488
-
return PTR_ERR(generic_phy);
489
-
}
490
-
491
-
phy_set_drvdata(generic_phy, tbh_phy);
492
-
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
493
-
494
-
return PTR_ERR_OR_ZERO(phy_provider);
495
-
}
496
-
497
-
static struct platform_driver thunderbay_emmc_phy_driver = {
498
-
.probe = thunderbay_emmc_phy_probe,
499
-
.driver = {
500
-
.name = "thunderbay-emmc-phy",
501
-
.of_match_table = thunderbay_emmc_phy_of_match,
502
-
},
503
-
};
504
-
module_platform_driver(thunderbay_emmc_phy_driver);
505
-
506
-
MODULE_AUTHOR("Nandhini S <nandhini.srikandan@intel.com>");
507
-
MODULE_AUTHOR("Rashmi A <rashmi.a@intel.com>");
508
-
MODULE_DESCRIPTION("Intel Thunder Bay eMMC PHY driver");
509
-
MODULE_LICENSE("GPL v2");
+1
-1
drivers/phy/marvell/phy-pxa-28nm-hsic.c
+1
-1
drivers/phy/marvell/phy-pxa-28nm-hsic.c
+1
-1
drivers/phy/marvell/phy-pxa-28nm-usb2.c
+1
-1
drivers/phy/marvell/phy-pxa-28nm-usb2.c
+1
drivers/phy/mediatek/Makefile
+1
drivers/phy/mediatek/Makefile
···
12
12
phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
13
13
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
14
14
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8173.o
15
+
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8195.o
15
16
obj-$(CONFIG_PHY_MTK_HDMI) += phy-mtk-hdmi-drv.o
16
17
17
18
phy-mtk-mipi-dsi-drv-y := phy-mtk-mipi-dsi.o
+495
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
+495
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2022 MediaTek Inc.
4
+
* Copyright (c) 2022 BayLibre, SAS
5
+
*/
6
+
#include <linux/delay.h>
7
+
#include <linux/io.h>
8
+
#include <linux/mfd/syscon.h>
9
+
#include <linux/module.h>
10
+
#include <linux/phy/phy.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/types.h>
13
+
#include <linux/units.h>
14
+
#include <linux/nvmem-consumer.h>
15
+
16
+
#include "phy-mtk-io.h"
17
+
#include "phy-mtk-hdmi.h"
18
+
#include "phy-mtk-hdmi-mt8195.h"
19
+
20
+
static void mtk_hdmi_ana_fifo_en(struct mtk_hdmi_phy *hdmi_phy)
21
+
{
22
+
/* make data fifo writable for hdmi2.0 */
23
+
mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN);
24
+
}
25
+
26
+
static void
27
+
mtk_phy_tmds_clk_ratio(struct mtk_hdmi_phy *hdmi_phy, bool enable)
28
+
{
29
+
void __iomem *regs = hdmi_phy->regs;
30
+
31
+
mtk_hdmi_ana_fifo_en(hdmi_phy);
32
+
33
+
/* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G,
34
+
* clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10
35
+
*/
36
+
if (enable)
37
+
mtk_phy_update_field(regs + HDMI20_CLK_CFG, REG_TXC_DIV, 3);
38
+
else
39
+
mtk_phy_clear_bits(regs + HDMI20_CLK_CFG, REG_TXC_DIV);
40
+
}
41
+
42
+
static void mtk_hdmi_pll_sel_src(struct clk_hw *hw)
43
+
{
44
+
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
45
+
void __iomem *regs = hdmi_phy->regs;
46
+
47
+
mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_XTAL_SEL);
48
+
mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_RESPLL_SEL);
49
+
50
+
/* DA_HDMITX21_REF_CK for TXPLL input source */
51
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITXPLL_REF_CK_SEL);
52
+
}
53
+
54
+
static void mtk_hdmi_pll_perf(struct clk_hw *hw)
55
+
{
56
+
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
57
+
void __iomem *regs = hdmi_phy->regs;
58
+
59
+
mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_BP2);
60
+
mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BC);
61
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IC, 0x1);
62
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BR, 0x2);
63
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IR, 0x2);
64
+
mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BP);
65
+
mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_IBAND_FIX_EN);
66
+
mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14);
67
+
mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_HIKVCO);
68
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_HREN, 0x1);
69
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_LVR_SEL, 0x1);
70
+
mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT12_11);
71
+
mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_TCL_EN);
72
+
}
73
+
74
+
static int mtk_hdmi_pll_set_hw(struct clk_hw *hw, u8 prediv,
75
+
u8 fbkdiv_high,
76
+
u32 fbkdiv_low,
77
+
u8 fbkdiv_hs3, u8 posdiv1,
78
+
u8 posdiv2, u8 txprediv,
79
+
u8 txposdiv,
80
+
u8 digital_div)
81
+
{
82
+
u8 txposdiv_value;
83
+
u8 div3_ctrl_value;
84
+
u8 posdiv_vallue;
85
+
u8 div_ctrl_value;
86
+
u8 reserve_3_2_value;
87
+
u8 prediv_value;
88
+
u8 reserve13_value;
89
+
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
90
+
void __iomem *regs = hdmi_phy->regs;
91
+
92
+
mtk_hdmi_pll_sel_src(hw);
93
+
94
+
mtk_hdmi_pll_perf(hw);
95
+
96
+
mtk_phy_update_field(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_BG_VREF_SEL, 0x2);
97
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_VREF_SEL);
98
+
mtk_phy_update_field(regs + HDMI_1_CFG_9, RG_HDMITX21_SLDO_VREF_SEL, 0x2);
99
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_VREF_SELB);
100
+
mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDOLPF_EN);
101
+
mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_INTR_CAL, 0x11);
102
+
mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD);
103
+
104
+
/* TXPOSDIV */
105
+
txposdiv_value = ilog2(txposdiv);
106
+
107
+
mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV, txposdiv_value);
108
+
mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN);
109
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_EN);
110
+
111
+
/* TXPREDIV */
112
+
switch (txprediv) {
113
+
case 2:
114
+
div3_ctrl_value = 0x0;
115
+
posdiv_vallue = 0x0;
116
+
break;
117
+
case 4:
118
+
div3_ctrl_value = 0x0;
119
+
posdiv_vallue = 0x1;
120
+
break;
121
+
case 6:
122
+
div3_ctrl_value = 0x1;
123
+
posdiv_vallue = 0x0;
124
+
break;
125
+
case 12:
126
+
div3_ctrl_value = 0x1;
127
+
posdiv_vallue = 0x1;
128
+
break;
129
+
default:
130
+
return -EINVAL;
131
+
}
132
+
133
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV_DIV3_CTRL, div3_ctrl_value);
134
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV, posdiv_vallue);
135
+
136
+
/* POSDIV1 */
137
+
switch (posdiv1) {
138
+
case 5:
139
+
div_ctrl_value = 0x0;
140
+
break;
141
+
case 10:
142
+
div_ctrl_value = 0x1;
143
+
break;
144
+
case 12:
145
+
div_ctrl_value = 0x2;
146
+
break;
147
+
case 15:
148
+
div_ctrl_value = 0x3;
149
+
break;
150
+
default:
151
+
return -EINVAL;
152
+
}
153
+
154
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_DIV_CTRL, div_ctrl_value);
155
+
156
+
/* DE add new setting */
157
+
mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14);
158
+
159
+
/* POSDIV2 */
160
+
switch (posdiv2) {
161
+
case 1:
162
+
reserve_3_2_value = 0x0;
163
+
break;
164
+
case 2:
165
+
reserve_3_2_value = 0x1;
166
+
break;
167
+
case 4:
168
+
reserve_3_2_value = 0x2;
169
+
break;
170
+
case 6:
171
+
reserve_3_2_value = 0x3;
172
+
break;
173
+
default:
174
+
return -EINVAL;
175
+
}
176
+
177
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT3_2, reserve_3_2_value);
178
+
179
+
/* DE add new setting */
180
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT1_0, 0x2);
181
+
182
+
/* PREDIV */
183
+
prediv_value = ilog2(prediv);
184
+
185
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_PREDIV, prediv_value);
186
+
187
+
/* FBKDIV_HS3 */
188
+
reserve13_value = ilog2(fbkdiv_hs3);
189
+
190
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT13, reserve13_value);
191
+
192
+
/* FBDIV */
193
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_FBKDIV_HIGH, fbkdiv_high);
194
+
mtk_phy_update_field(regs + HDMI_1_PLL_CFG_3, RG_HDMITXPLL_FBKDIV_LOW, fbkdiv_low);
195
+
196
+
/* Digital DIVIDER */
197
+
mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_PIXEL_CLOCK_SEL);
198
+
199
+
if (digital_div == 1) {
200
+
mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK);
201
+
} else {
202
+
mtk_phy_set_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK);
203
+
mtk_phy_update_field(regs + HDMI_CTL_3, REG_HDMITXPLL_DIV, digital_div - 1);
204
+
}
205
+
206
+
return 0;
207
+
}
208
+
209
+
static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw,
210
+
unsigned long rate, unsigned long parent_rate)
211
+
{
212
+
u8 digital_div, txprediv, txposdiv, fbkdiv_high, posdiv1, posdiv2;
213
+
u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw;
214
+
u8 txpredivs[4] = { 2, 4, 6, 12 };
215
+
u32 fbkdiv_low;
216
+
int i, ret;
217
+
218
+
pixel_clk = rate;
219
+
tmds_clk = pixel_clk;
220
+
221
+
if (tmds_clk < 25 * MEGA || tmds_clk > 594 * MEGA)
222
+
return -EINVAL;
223
+
224
+
if (tmds_clk >= 340 * MEGA)
225
+
hdmi_phy->tmds_over_340M = true;
226
+
else
227
+
hdmi_phy->tmds_over_340M = false;
228
+
229
+
/* in Hz */
230
+
da_hdmitx21_ref_ck = 26 * MEGA;
231
+
232
+
/* TXPOSDIV stage treatment:
233
+
* 0M < TMDS clk < 54M /8
234
+
* 54M <= TMDS clk < 148.35M /4
235
+
* 148.35M <=TMDS clk < 296.7M /2
236
+
* 296.7 <=TMDS clk <= 594M /1
237
+
*/
238
+
if (tmds_clk < 54 * MEGA)
239
+
txposdiv = 8;
240
+
else if (tmds_clk >= 54 * MEGA && tmds_clk < 148.35 * MEGA)
241
+
txposdiv = 4;
242
+
else if (tmds_clk >= 148.35 * MEGA && tmds_clk < 296.7 * MEGA)
243
+
txposdiv = 2;
244
+
else if (tmds_clk >= 296.7 * MEGA && tmds_clk <= 594 * MEGA)
245
+
txposdiv = 1;
246
+
else
247
+
return -EINVAL;
248
+
249
+
/* calculate txprediv: can be 2, 4, 6, 12
250
+
* ICO clk = 5*TMDS_CLK*TXPOSDIV*TXPREDIV
251
+
* ICO clk constraint: 5G =< ICO clk <= 12G
252
+
*/
253
+
for (i = 0; i < ARRAY_SIZE(txpredivs); i++) {
254
+
ns_hdmipll_ck = 5 * tmds_clk * txposdiv * txpredivs[i];
255
+
if (ns_hdmipll_ck >= 5 * GIGA &&
256
+
ns_hdmipll_ck <= 1 * GIGA)
257
+
break;
258
+
}
259
+
if (i == (ARRAY_SIZE(txpredivs) - 1) &&
260
+
(ns_hdmipll_ck < 5 * GIGA || ns_hdmipll_ck > 12 * GIGA)) {
261
+
return -EINVAL;
262
+
}
263
+
if (i == ARRAY_SIZE(txpredivs))
264
+
return -EINVAL;
265
+
266
+
txprediv = txpredivs[i];
267
+
268
+
/* PCW calculation: FBKDIV
269
+
* formula: pcw=(frequency_out*2^pcw_bit) / frequency_in / FBKDIV_HS3;
270
+
* RG_HDMITXPLL_FBKDIV[32:0]:
271
+
* [32,24] 9bit integer, [23,0]:24bit fraction
272
+
*/
273
+
pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH,
274
+
da_hdmitx21_ref_ck / PLL_FBKDIV_HS3);
275
+
276
+
if (pcw > GENMASK_ULL(32, 0))
277
+
return -EINVAL;
278
+
279
+
fbkdiv_high = FIELD_GET(GENMASK_ULL(63, 32), pcw);
280
+
fbkdiv_low = FIELD_GET(GENMASK(31, 0), pcw);
281
+
282
+
/* posdiv1:
283
+
* posdiv1 stage treatment according to color_depth:
284
+
* 24bit -> posdiv1 /10, 30bit -> posdiv1 /12.5,
285
+
* 36bit -> posdiv1 /15, 48bit -> posdiv1 /10
286
+
*/
287
+
posdiv1 = 10;
288
+
posdiv2 = 1;
289
+
290
+
/* Digital clk divider, max /32 */
291
+
digital_div = div_u64((u64)ns_hdmipll_ck, posdiv1 / posdiv2 / pixel_clk);
292
+
if (!(digital_div <= 32 && digital_div >= 1))
293
+
return -EINVAL;
294
+
295
+
mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low,
296
+
PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv,
297
+
txposdiv, digital_div);
298
+
if (ret)
299
+
return -EINVAL;
300
+
301
+
return 0;
302
+
}
303
+
304
+
static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw)
305
+
{
306
+
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
307
+
void __iomem *regs = hdmi_phy->regs;
308
+
u8 data_channel_bias, clk_channel_bias;
309
+
u8 impedance, impedance_en;
310
+
u32 tmds_clk;
311
+
u32 pixel_clk = hdmi_phy->pll_rate;
312
+
313
+
tmds_clk = pixel_clk;
314
+
315
+
/* bias & impedance setting:
316
+
* 3G < data rate <= 6G: enable impedance 100ohm,
317
+
* data channel bias 24mA, clock channel bias 20mA
318
+
* pixel clk >= HD, 74.175MHZ <= pixel clk <= 300MHZ:
319
+
* enalbe impedance 100ohm
320
+
* data channel 20mA, clock channel 16mA
321
+
* 27M =< pixel clk < 74.175: disable impedance
322
+
* data channel & clock channel bias 10mA
323
+
*/
324
+
325
+
/* 3G < data rate <= 6G, 300M < tmds rate <= 594M */
326
+
if (tmds_clk > 300 * MEGA && tmds_clk <= 594 * MEGA) {
327
+
data_channel_bias = 0x3c; /* 24mA */
328
+
clk_channel_bias = 0x34; /* 20mA */
329
+
impedance_en = 0xf;
330
+
impedance = 0x36; /* 100ohm */
331
+
} else if (pixel_clk >= 74.175 * MEGA && pixel_clk <= 300 * MEGA) {
332
+
data_channel_bias = 0x34; /* 20mA */
333
+
clk_channel_bias = 0x2c; /* 16mA */
334
+
impedance_en = 0xf;
335
+
impedance = 0x36; /* 100ohm */
336
+
} else if (pixel_clk >= 27 * MEGA && pixel_clk < 74.175 * MEGA) {
337
+
data_channel_bias = 0x14; /* 10mA */
338
+
clk_channel_bias = 0x14; /* 10mA */
339
+
impedance_en = 0x0;
340
+
impedance = 0x0;
341
+
} else {
342
+
return -EINVAL;
343
+
}
344
+
345
+
/* bias */
346
+
mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D0, data_channel_bias);
347
+
mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D1, data_channel_bias);
348
+
mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D2, data_channel_bias);
349
+
mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IBIAS_CLK, clk_channel_bias);
350
+
351
+
/* impedance */
352
+
mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IMP_EN, impedance_en);
353
+
mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D0_EN1, impedance);
354
+
mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D1_EN1, impedance);
355
+
mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D2_EN1, impedance);
356
+
mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_CLK_EN1, impedance);
357
+
358
+
return 0;
359
+
}
360
+
361
+
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
362
+
{
363
+
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
364
+
void __iomem *regs = hdmi_phy->regs;
365
+
366
+
mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN);
367
+
368
+
mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_SER_EN);
369
+
mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D0_DRV_OP_EN);
370
+
mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D1_DRV_OP_EN);
371
+
mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_D2_DRV_OP_EN);
372
+
mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_CK_DRV_OP_EN);
373
+
374
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D0_EN);
375
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D1_EN);
376
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D2_EN);
377
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_CK_EN);
378
+
379
+
mtk_hdmi_pll_drv_setting(hw);
380
+
381
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD);
382
+
mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN);
383
+
mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN);
384
+
mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN);
385
+
386
+
mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON);
387
+
usleep_range(5, 10);
388
+
mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN);
389
+
usleep_range(5, 10);
390
+
mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD);
391
+
usleep_range(30, 50);
392
+
return 0;
393
+
}
394
+
395
+
static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
396
+
{
397
+
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
398
+
void __iomem *regs = hdmi_phy->regs;
399
+
400
+
mtk_phy_set_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD);
401
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN);
402
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN);
403
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN);
404
+
405
+
mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD);
406
+
usleep_range(10, 20);
407
+
mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN);
408
+
usleep_range(10, 20);
409
+
mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON);
410
+
}
411
+
412
+
static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
413
+
unsigned long parent_rate)
414
+
{
415
+
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
416
+
417
+
dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, rate,
418
+
parent_rate);
419
+
420
+
return mtk_hdmi_pll_calc(hdmi_phy, hw, rate, parent_rate);
421
+
}
422
+
423
+
static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
424
+
unsigned long *parent_rate)
425
+
{
426
+
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
427
+
428
+
hdmi_phy->pll_rate = rate;
429
+
return rate;
430
+
}
431
+
432
+
static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
433
+
unsigned long parent_rate)
434
+
{
435
+
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
436
+
437
+
return hdmi_phy->pll_rate;
438
+
}
439
+
440
+
static const struct clk_ops mtk_hdmi_pll_ops = {
441
+
.prepare = mtk_hdmi_pll_prepare,
442
+
.unprepare = mtk_hdmi_pll_unprepare,
443
+
.set_rate = mtk_hdmi_pll_set_rate,
444
+
.round_rate = mtk_hdmi_pll_round_rate,
445
+
.recalc_rate = mtk_hdmi_pll_recalc_rate,
446
+
};
447
+
448
+
static void vtx_signal_en(struct mtk_hdmi_phy *hdmi_phy, bool on)
449
+
{
450
+
void __iomem *regs = hdmi_phy->regs;
451
+
452
+
if (on)
453
+
mtk_phy_set_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN);
454
+
else
455
+
mtk_phy_clear_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN);
456
+
}
457
+
458
+
static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
459
+
{
460
+
vtx_signal_en(hdmi_phy, true);
461
+
usleep_range(100, 150);
462
+
}
463
+
464
+
static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
465
+
{
466
+
vtx_signal_en(hdmi_phy, false);
467
+
}
468
+
469
+
static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opts *opts)
470
+
{
471
+
struct phy_configure_opts_dp *dp_opts = &opts->dp;
472
+
struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
473
+
int ret;
474
+
475
+
ret = clk_set_rate(hdmi_phy->pll, dp_opts->link_rate);
476
+
477
+
if (ret)
478
+
return ret;
479
+
480
+
mtk_phy_tmds_clk_ratio(hdmi_phy, hdmi_phy->tmds_over_340M);
481
+
482
+
return ret;
483
+
}
484
+
485
+
struct mtk_hdmi_phy_conf mtk_hdmi_phy_8195_conf = {
486
+
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
487
+
.hdmi_phy_clk_ops = &mtk_hdmi_pll_ops,
488
+
.hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
489
+
.hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
490
+
.hdmi_phy_configure = mtk_hdmi_phy_configure,
491
+
};
492
+
493
+
MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
494
+
MODULE_DESCRIPTION("MediaTek MT8195 HDMI PHY Driver");
495
+
MODULE_LICENSE("GPL v2");
+113
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h
+113
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2022 MediaTek Inc.
4
+
* Copyright (c) 2022 BayLibre, SAS
5
+
*/
6
+
7
+
#ifndef _MTK_HDMI_PHY_8195_H
8
+
#define _MTK_HDMI_PHY_8195_H
9
+
10
+
#include <linux/clk.h>
11
+
#include <linux/clk-provider.h>
12
+
#include <linux/types.h>
13
+
14
+
#define PCW_DECIMAL_WIDTH 24
15
+
#define PLL_PREDIV 1
16
+
#define PLL_FBKDIV_HS3 1
17
+
18
+
#define HDMI20_CLK_CFG 0x70
19
+
#define REG_TXC_DIV GENMASK(31, 30)
20
+
21
+
#define HDMI_1_CFG_0 0x00
22
+
#define RG_HDMITX21_DRV_IBIAS_CLK GENMASK(10, 5)
23
+
#define RG_HDMITX21_DRV_IMP_EN GENMASK(23, 20)
24
+
#define RG_HDMITX21_DRV_EN GENMASK(27, 24)
25
+
#define RG_HDMITX21_SER_EN GENMASK(31, 28)
26
+
27
+
#define HDMI_1_CFG_1 0x04
28
+
#define RG_HDMITX21_DRV_IBIAS_D0 GENMASK(19, 14)
29
+
#define RG_HDMITX21_DRV_IBIAS_D1 GENMASK(25, 20)
30
+
#define RG_HDMITX21_DRV_IBIAS_D2 GENMASK(31, 26)
31
+
32
+
#define HDMI_1_CFG_10 0x40
33
+
#define RG_HDMITXPLL_REF_CK_SEL GENMASK(2, 1)
34
+
#define RG_HDMITX21_VREF_SEL BIT(4)
35
+
#define RG_HDMITX21_BIAS_PE_VREF_SELB BIT(10)
36
+
#define RG_HDMITX21_BIAS_PE_BG_VREF_SEL GENMASK(16, 15)
37
+
#define RG_HDMITX21_BG_PWD BIT(20)
38
+
39
+
#define HDMI_1_CFG_2 0x08
40
+
#define RG_HDMITX21_DRV_IMP_D0_EN1 GENMASK(13, 8)
41
+
#define RG_HDMITX21_DRV_IMP_D1_EN1 GENMASK(19, 14)
42
+
#define RG_HDMITX21_DRV_IMP_D2_EN1 GENMASK(25, 20)
43
+
#define RG_HDMITX21_DRV_IMP_CLK_EN1 GENMASK(31, 26)
44
+
45
+
#define HDMI_1_CFG_3 0x0c
46
+
#define RG_HDMITX21_CKLDO_EN BIT(3)
47
+
#define RG_HDMITX21_SLDOLPF_EN BIT(7)
48
+
#define RG_HDMITX21_SLDO_EN GENMASK(11, 8)
49
+
50
+
#define HDMI_1_CFG_6 0x18
51
+
#define RG_HDMITX21_D2_DRV_OP_EN BIT(8)
52
+
#define RG_HDMITX21_D1_DRV_OP_EN BIT(9)
53
+
#define RG_HDMITX21_D0_DRV_OP_EN BIT(10)
54
+
#define RG_HDMITX21_CK_DRV_OP_EN BIT(11)
55
+
#define RG_HDMITX21_FRL_EN BIT(12)
56
+
#define RG_HDMITX21_FRL_CK_EN BIT(13)
57
+
#define RG_HDMITX21_FRL_D0_EN BIT(14)
58
+
#define RG_HDMITX21_FRL_D1_EN BIT(15)
59
+
#define RG_HDMITX21_FRL_D2_EN BIT(16)
60
+
#define RG_HDMITX21_INTR_CAL GENMASK(22, 18)
61
+
#define RG_HDMITX21_TX_POSDIV GENMASK(27, 26)
62
+
#define RG_HDMITX21_TX_POSDIV_EN BIT(28)
63
+
#define RG_HDMITX21_BIAS_EN BIT(29)
64
+
65
+
#define HDMI_1_CFG_9 0x24
66
+
#define RG_HDMITX21_SLDO_VREF_SEL GENMASK(5, 4)
67
+
68
+
#define HDMI_1_PLL_CFG_0 0x44
69
+
#define RG_HDMITXPLL_HREN GENMASK(13, 12)
70
+
#define RG_HDMITXPLL_IBAND_FIX_EN BIT(24)
71
+
#define RG_HDMITXPLL_LVR_SEL GENMASK(27, 26)
72
+
#define RG_HDMITXPLL_BP2 BIT(30)
73
+
#define RG_HDMITXPLL_TCL_EN BIT(31)
74
+
75
+
#define HDMI_1_PLL_CFG_1 0x48
76
+
#define RG_HDMITXPLL_RESERVE_BIT1_0 GENMASK(1, 0)
77
+
#define RG_HDMITXPLL_RESERVE_BIT3_2 GENMASK(3, 2)
78
+
#define RG_HDMITXPLL_RESERVE_BIT12_11 GENMASK(12, 11)
79
+
#define RG_HDMITXPLL_RESERVE_BIT13 BIT(13)
80
+
#define RG_HDMITXPLL_RESERVE_BIT14 BIT(14)
81
+
82
+
#define HDMI_1_PLL_CFG_2 0x4c
83
+
#define RG_HDMITXPLL_BC GENMASK(28, 27)
84
+
#define RG_HDMITXPLL_IC GENMASK(26, 22)
85
+
#define RG_HDMITXPLL_BR GENMASK(21, 19)
86
+
#define RG_HDMITXPLL_IR GENMASK(18, 14)
87
+
#define RG_HDMITXPLL_BP GENMASK(13, 10)
88
+
#define RG_HDMITXPLL_HIKVCO BIT(29)
89
+
#define RG_HDMITXPLL_PWD BIT(31)
90
+
91
+
#define HDMI_1_PLL_CFG_3 0x50
92
+
#define RG_HDMITXPLL_FBKDIV_LOW GENMASK(31, 0)
93
+
94
+
#define HDMI_1_PLL_CFG_4 0x54
95
+
#define DA_HDMITXPLL_ISO_EN BIT(1)
96
+
#define DA_HDMITXPLL_PWR_ON BIT(2)
97
+
#define RG_HDMITXPLL_POSDIV_DIV3_CTRL BIT(21)
98
+
#define RG_HDMITXPLL_POSDIV GENMASK(23, 22)
99
+
#define RG_HDMITXPLL_DIV_CTRL GENMASK(25, 24)
100
+
#define RG_HDMITXPLL_PREDIV GENMASK(29, 28)
101
+
#define RG_HDMITXPLL_FBKDIV_HIGH BIT(31)
102
+
103
+
#define HDMI_ANA_CTL 0x7c
104
+
#define REG_ANA_HDMI20_FIFO_EN BIT(16)
105
+
106
+
#define HDMI_CTL_3 0xcc
107
+
#define REG_HDMITXPLL_DIV GENMASK(4, 0)
108
+
#define REG_HDMITX_REF_XTAL_SEL BIT(7)
109
+
#define REG_HDMITX_REF_RESPLL_SEL BIT(9)
110
+
#define REG_PIXEL_CLOCK_SEL BIT(10)
111
+
#define REG_HDMITX_PIXEL_CLOCK BIT(23)
112
+
113
+
#endif /* MTK_HDMI_PHY_8195_H */
+15
drivers/phy/mediatek/phy-mtk-hdmi.c
+15
drivers/phy/mediatek/phy-mtk-hdmi.c
···
8
8
9
9
static int mtk_hdmi_phy_power_on(struct phy *phy);
10
10
static int mtk_hdmi_phy_power_off(struct phy *phy);
11
+
static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opts *opts);
11
12
12
13
static const struct phy_ops mtk_hdmi_phy_dev_ops = {
13
14
.power_on = mtk_hdmi_phy_power_on,
14
15
.power_off = mtk_hdmi_phy_power_off,
16
+
.configure = mtk_hdmi_phy_configure,
15
17
.owner = THIS_MODULE,
16
18
};
17
19
···
41
39
42
40
hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
43
41
clk_disable_unprepare(hdmi_phy->pll);
42
+
43
+
return 0;
44
+
}
45
+
46
+
static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opts *opts)
47
+
{
48
+
struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
49
+
50
+
if (hdmi_phy->conf->hdmi_phy_configure)
51
+
return hdmi_phy->conf->hdmi_phy_configure(phy, opts);
44
52
45
53
return 0;
46
54
}
···
160
148
},
161
149
{ .compatible = "mediatek,mt8173-hdmi-phy",
162
150
.data = &mtk_hdmi_phy_8173_conf,
151
+
},
152
+
{ .compatible = "mediatek,mt8195-hdmi-phy",
153
+
.data = &mtk_hdmi_phy_8195_conf,
163
154
},
164
155
{},
165
156
};
+3
drivers/phy/mediatek/phy-mtk-hdmi.h
+3
drivers/phy/mediatek/phy-mtk-hdmi.h
···
24
24
const struct clk_ops *hdmi_phy_clk_ops;
25
25
void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
26
26
void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
27
+
int (*hdmi_phy_configure)(struct phy *phy, union phy_configure_opts *opts);
27
28
};
28
29
29
30
struct mtk_hdmi_phy {
···
40
39
unsigned char drv_imp_d0;
41
40
unsigned int ibias;
42
41
unsigned int ibias_up;
42
+
bool tmds_over_340M;
43
43
};
44
44
45
45
struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
46
46
47
+
extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8195_conf;
47
48
extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
48
49
extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
49
50
+2
-3
drivers/phy/mediatek/phy-mtk-mipi-dsi.c
+2
-3
drivers/phy/mediatek/phy-mtk-mipi-dsi.c
···
180
180
mipi_tx->pll);
181
181
}
182
182
183
-
static int mtk_mipi_tx_remove(struct platform_device *pdev)
183
+
static void mtk_mipi_tx_remove(struct platform_device *pdev)
184
184
{
185
185
of_clk_del_provider(pdev->dev.of_node);
186
-
return 0;
187
186
}
188
187
189
188
static const struct of_device_id mtk_mipi_tx_match[] = {
···
198
199
199
200
static struct platform_driver mtk_mipi_tx_driver = {
200
201
.probe = mtk_mipi_tx_probe,
201
-
.remove = mtk_mipi_tx_remove,
202
+
.remove_new = mtk_mipi_tx_remove,
202
203
.driver = {
203
204
.name = "mediatek-mipi-tx",
204
205
.of_match_table = mtk_mipi_tx_match,
+2
-4
drivers/phy/motorola/phy-cpcap-usb.c
+2
-4
drivers/phy/motorola/phy-cpcap-usb.c
···
692
692
return error;
693
693
}
694
694
695
-
static int cpcap_usb_phy_remove(struct platform_device *pdev)
695
+
static void cpcap_usb_phy_remove(struct platform_device *pdev)
696
696
{
697
697
struct cpcap_phy_ddata *ddata = platform_get_drvdata(pdev);
698
698
int error;
···
707
707
usb_remove_phy(&ddata->phy);
708
708
cancel_delayed_work_sync(&ddata->detect_work);
709
709
regulator_disable(ddata->vusb);
710
-
711
-
return 0;
712
710
}
713
711
714
712
static struct platform_driver cpcap_usb_phy_driver = {
715
713
.probe = cpcap_usb_phy_probe,
716
-
.remove = cpcap_usb_phy_remove,
714
+
.remove_new = cpcap_usb_phy_remove,
717
715
.driver = {
718
716
.name = "cpcap-usb-phy",
719
717
.of_match_table = of_match_ptr(cpcap_usb_phy_id_table),
+2
-4
drivers/phy/motorola/phy-mapphone-mdm6600.c
+2
-4
drivers/phy/motorola/phy-mapphone-mdm6600.c
···
634
634
return error;
635
635
}
636
636
637
-
static int phy_mdm6600_remove(struct platform_device *pdev)
637
+
static void phy_mdm6600_remove(struct platform_device *pdev)
638
638
{
639
639
struct phy_mdm6600 *ddata = platform_get_drvdata(pdev);
640
640
struct gpio_desc *reset_gpio = ddata->ctrl_gpios[PHY_MDM6600_RESET];
···
653
653
cancel_delayed_work_sync(&ddata->modem_wake_work);
654
654
cancel_delayed_work_sync(&ddata->bootup_work);
655
655
cancel_delayed_work_sync(&ddata->status_work);
656
-
657
-
return 0;
658
656
}
659
657
660
658
static struct platform_driver phy_mdm6600_driver = {
661
659
.probe = phy_mdm6600_probe,
662
-
.remove = phy_mdm6600_remove,
660
+
.remove_new = phy_mdm6600_remove,
663
661
.driver = {
664
662
.name = "phy-mapphone-mdm6600",
665
663
.pm = &phy_mdm6600_pm_ops,
+2
-4
drivers/phy/phy-lgm-usb.c
+2
-4
drivers/phy/phy-lgm-usb.c
···
252
252
return usb_add_phy_dev(phy);
253
253
}
254
254
255
-
static int phy_remove(struct platform_device *pdev)
255
+
static void phy_remove(struct platform_device *pdev)
256
256
{
257
257
struct tca_apb *ta = platform_get_drvdata(pdev);
258
258
259
259
usb_remove_phy(&ta->phy);
260
-
261
-
return 0;
262
260
}
263
261
264
262
static const struct of_device_id intel_usb_phy_dt_ids[] = {
···
271
273
.of_match_table = intel_usb_phy_dt_ids,
272
274
},
273
275
.probe = phy_probe,
274
-
.remove = phy_remove,
276
+
.remove_new = phy_remove,
275
277
};
276
278
277
279
module_platform_driver(lgm_phy_driver);
+2
-4
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
+2
-4
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
···
243
243
return 0;
244
244
}
245
245
246
-
static int qcom_apq8064_sata_phy_remove(struct platform_device *pdev)
246
+
static void qcom_apq8064_sata_phy_remove(struct platform_device *pdev)
247
247
{
248
248
struct qcom_apq8064_sata_phy *phy = platform_get_drvdata(pdev);
249
249
250
250
clk_disable_unprepare(phy->cfg_clk);
251
-
252
-
return 0;
253
251
}
254
252
255
253
static const struct of_device_id qcom_apq8064_sata_phy_of_match[] = {
···
258
260
259
261
static struct platform_driver qcom_apq8064_sata_phy_driver = {
260
262
.probe = qcom_apq8064_sata_phy_probe,
261
-
.remove = qcom_apq8064_sata_phy_remove,
263
+
.remove_new = qcom_apq8064_sata_phy_remove,
262
264
.driver = {
263
265
.name = "qcom-apq8064-sata-phy",
264
266
.of_match_table = qcom_apq8064_sata_phy_of_match,
+3
-5
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
+3
-5
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
···
223
223
return 0;
224
224
}
225
225
226
-
static int eusb2_repeater_remove(struct platform_device *pdev)
226
+
static void eusb2_repeater_remove(struct platform_device *pdev)
227
227
{
228
228
struct eusb2_repeater *rptr = platform_get_drvdata(pdev);
229
229
230
230
if (!rptr)
231
-
return 0;
231
+
return;
232
232
233
233
eusb2_repeater_exit(rptr->phy);
234
-
235
-
return 0;
236
234
}
237
235
238
236
static const struct of_device_id eusb2_repeater_of_match_table[] = {
···
244
246
245
247
static struct platform_driver eusb2_repeater_driver = {
246
248
.probe = eusb2_repeater_probe,
247
-
.remove = eusb2_repeater_remove,
249
+
.remove_new = eusb2_repeater_remove,
248
250
.driver = {
249
251
.name = "qcom-eusb2-repeater",
250
252
.of_match_table = eusb2_repeater_of_match_table,
+2
-4
drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
+2
-4
drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
···
170
170
return 0;
171
171
}
172
172
173
-
static int qcom_ipq806x_sata_phy_remove(struct platform_device *pdev)
173
+
static void qcom_ipq806x_sata_phy_remove(struct platform_device *pdev)
174
174
{
175
175
struct qcom_ipq806x_sata_phy *phy = platform_get_drvdata(pdev);
176
176
177
177
clk_disable_unprepare(phy->cfg_clk);
178
-
179
-
return 0;
180
178
}
181
179
182
180
static const struct of_device_id qcom_ipq806x_sata_phy_of_match[] = {
···
185
187
186
188
static struct platform_driver qcom_ipq806x_sata_phy_driver = {
187
189
.probe = qcom_ipq806x_sata_phy_probe,
188
-
.remove = qcom_ipq806x_sata_phy_remove,
190
+
.remove_new = qcom_ipq806x_sata_phy_remove,
189
191
.driver = {
190
192
.name = "qcom-ipq806x-sata-phy",
191
193
.of_match_table = qcom_ipq806x_sata_phy_of_match,
+2
-17
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+2
-17
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
···
1396
1396
.usb3_serdes = 0x1000,
1397
1397
.usb3_pcs_misc = 0x1a00,
1398
1398
.usb3_pcs = 0x1c00,
1399
+
.usb3_pcs_usb = 0x1f00,
1399
1400
.dp_serdes = 0x2000,
1400
1401
.dp_txa = 0x2200,
1401
1402
.dp_txb = 0x2600,
···
1415
1414
.usb3_pcs_usb = 0x1700,
1416
1415
.dp_serdes = 0x2000,
1417
1416
.dp_dp_phy = 0x2200,
1418
-
};
1419
-
1420
-
static const struct qmp_combo_offsets qmp_combo_offsets_v6 = {
1421
-
.com = 0x0000,
1422
-
.txa = 0x1200,
1423
-
.rxa = 0x1400,
1424
-
.txb = 0x1600,
1425
-
.rxb = 0x1800,
1426
-
.usb3_serdes = 0x1000,
1427
-
.usb3_pcs_misc = 0x1a00,
1428
-
.usb3_pcs = 0x1c00,
1429
-
.usb3_pcs_usb = 0x1f00,
1430
-
.dp_serdes = 0x2000,
1431
-
.dp_txa = 0x2200,
1432
-
.dp_txb = 0x2600,
1433
-
.dp_dp_phy = 0x2a00,
1434
1417
};
1435
1418
1436
1419
static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {
···
1743
1758
};
1744
1759
1745
1760
static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = {
1746
-
.offsets = &qmp_combo_offsets_v6,
1761
+
.offsets = &qmp_combo_offsets_v3,
1747
1762
1748
1763
.serdes_tbl = sm8550_usb3_serdes_tbl,
1749
1764
.serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
+242
-21
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+242
-21
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
···
725
725
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
726
726
};
727
727
728
-
static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
729
-
};
730
-
731
728
static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
732
729
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
733
730
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
···
1127
1130
};
1128
1131
1129
1132
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
1130
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
1131
1133
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
1132
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
1133
1134
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1135
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
1136
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
1137
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1138
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
1139
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1140
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
1141
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
1142
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
1143
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03),
1144
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
1145
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
1146
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
1147
+
};
1148
+
1149
+
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = {
1150
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1151
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1152
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1153
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce),
1154
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b),
1155
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97),
1156
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
1157
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1158
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a),
1159
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10),
1160
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1161
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1162
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1163
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1164
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1165
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1166
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
1167
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04),
1168
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d),
1169
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a),
1170
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a),
1171
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3),
1172
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0),
1173
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05),
1174
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55),
1175
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55),
1176
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05),
1177
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
1178
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1179
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1180
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8),
1181
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20),
1182
+
};
1183
+
1184
+
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = {
1185
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
1186
+
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
1134
1187
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
1135
1188
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
1136
1189
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
···
1188
1141
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
1189
1142
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
1190
1143
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
1191
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
1192
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
1193
1144
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
1194
1145
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
1195
1146
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
···
1199
1154
QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1200
1155
QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1201
1156
QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1202
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1203
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
1204
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1205
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
1206
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
1207
1157
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
1208
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
1209
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03),
1210
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
1211
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
1212
1158
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
1213
1159
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
1214
1160
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
1215
1161
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
1216
-
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
1217
1162
};
1218
1163
1219
1164
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
···
1255
1220
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
1256
1221
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
1257
1222
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1223
+
};
1224
+
1225
+
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = {
1226
+
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1227
+
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1228
+
};
1229
+
1230
+
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = {
1258
1231
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
1259
1232
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
1233
+
};
1234
+
1235
+
static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = {
1236
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
1237
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1238
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
1239
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1240
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
1241
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
1242
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
1243
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
1244
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
1245
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
1246
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
1247
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
1248
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
1249
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
1250
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
1251
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
1252
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
1253
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
1254
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
1255
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1256
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1257
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1258
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1259
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1260
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
1261
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1262
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1263
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1264
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1265
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
1266
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
1267
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
1268
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00),
1269
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
1270
+
};
1271
+
1272
+
static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = {
1273
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
1274
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
1275
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00),
1276
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00),
1277
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00),
1278
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
1279
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1280
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12),
1281
+
};
1282
+
1283
+
static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = {
1284
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
1285
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06),
1286
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06),
1287
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e),
1288
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e),
1289
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
1290
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
1291
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02),
1292
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d),
1293
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44),
1294
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00),
1295
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
1296
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1297
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74),
1298
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1299
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c),
1300
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03),
1301
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
1302
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04),
1303
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
1304
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
1305
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
1306
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64),
1307
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
1308
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
1309
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
1310
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c),
1311
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1312
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1313
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1314
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1315
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1316
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1317
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1318
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1319
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1320
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
1321
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
1322
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
1323
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
1324
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
1325
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
1326
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
1327
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00),
1328
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
1329
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
1330
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1331
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
1332
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac),
1333
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
1334
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
1335
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07),
1336
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
1337
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
1338
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5),
1339
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee),
1340
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
1341
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
1342
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
1343
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
1344
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
1345
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28),
1346
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1347
+
};
1348
+
1349
+
static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = {
1350
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
1351
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa),
1352
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d),
1353
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
1354
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
1355
+
};
1356
+
1357
+
static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = {
1358
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
1359
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
1360
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
1361
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d),
1362
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1363
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
1364
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
1365
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
1260
1366
};
1261
1367
1262
1368
static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {
···
2209
2033
.serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
2210
2034
.tx = sdm845_qhp_pcie_tx_tbl,
2211
2035
.tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
2212
-
.rx = sdm845_qhp_pcie_rx_tbl,
2213
-
.rx_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
2214
2036
.pcs = sdm845_qhp_pcie_pcs_tbl,
2215
2037
.pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
2216
2038
},
···
2326
2152
};
2327
2153
2328
2154
static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
2329
-
.lanes = 1,
2155
+
.lanes = 2,
2330
2156
2331
2157
.tbls = {
2332
2158
.serdes = sc8180x_qmp_pcie_serdes_tbl,
···
2475
2301
.pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl,
2476
2302
.pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
2477
2303
},
2304
+
2305
+
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2306
+
.serdes = sdx55_qmp_pcie_rc_serdes_tbl,
2307
+
.serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl),
2308
+
.pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl,
2309
+
.pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl),
2310
+
},
2311
+
2312
+
.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
2313
+
.serdes = sdx55_qmp_pcie_ep_serdes_tbl,
2314
+
.serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl),
2315
+
.pcs_misc = sdx55_qmp_pcie_ep_pcs_misc_tbl,
2316
+
.pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl),
2317
+
},
2318
+
2478
2319
.clk_list = sdm845_pciephy_clk_l,
2479
2320
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
2480
2321
.reset_list = sdm845_pciephy_reset_l,
···
2498
2309
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2499
2310
.regs = pciephy_v4_regs_layout,
2500
2311
2501
-
.pwrdn_ctrl = SW_PWRDN,
2312
+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2502
2313
.phy_status = PHYSTATUS_4_20,
2503
2314
};
2504
2315
···
2574
2385
2575
2386
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2576
2387
.phy_status = PHYSTATUS,
2388
+
};
2389
+
2390
+
static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = {
2391
+
.lanes = 2,
2392
+
2393
+
.offsets = &qmp_pcie_offsets_v6_20,
2394
+
2395
+
.tbls = {
2396
+
.serdes = sdx65_qmp_pcie_serdes_tbl,
2397
+
.serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl),
2398
+
.tx = sdx65_qmp_pcie_tx_tbl,
2399
+
.tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl),
2400
+
.rx = sdx65_qmp_pcie_rx_tbl,
2401
+
.rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl),
2402
+
.pcs = sdx65_qmp_pcie_pcs_tbl,
2403
+
.pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl),
2404
+
.pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl,
2405
+
.pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl),
2406
+
},
2407
+
.clk_list = sdm845_pciephy_clk_l,
2408
+
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
2409
+
.reset_list = sdm845_pciephy_reset_l,
2410
+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2411
+
.vreg_list = qmp_phy_vreg_l,
2412
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2413
+
.regs = pciephy_v5_regs_layout,
2414
+
2415
+
.pwrdn_ctrl = SW_PWRDN,
2416
+
.phy_status = PHYSTATUS_4_20,
2577
2417
};
2578
2418
2579
2419
static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
···
3398
3180
}, {
3399
3181
.compatible = "qcom,sdx55-qmp-pcie-phy",
3400
3182
.data = &sdx55_qmp_pciephy_cfg,
3183
+
}, {
3184
+
.compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
3185
+
.data = &sdx65_qmp_pciephy_cfg,
3401
3186
}, {
3402
3187
.compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
3403
3188
.data = &sm8250_qmp_gen3x1_pciephy_cfg,
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
···
6
6
#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
7
7
#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
8
8
9
+
#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
10
+
#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
9
11
#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
10
12
#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
11
13
#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
+3
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
+3
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
···
12
12
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
13
13
#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
14
14
#define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
15
+
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
15
16
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
16
17
#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
17
18
#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
19
+
#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24
20
+
#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28
18
21
19
22
#endif
+1
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h
+1
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h
+24
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
+24
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
···
11
11
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12
12
#define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13
13
#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14
+
#define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15
+
#define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16
+
#define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17
+
#define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
14
18
15
19
/* Only for QMP V5_20 PHY - RX registers */
16
20
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
···
23
19
#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c
24
20
#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030
25
21
#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c
22
+
#define QSERDES_V5_20_RX_DFE_1 0x088
23
+
#define QSERDES_V5_20_RX_DFE_2 0x08c
26
24
#define QSERDES_V5_20_RX_DFE_3 0x090
27
25
#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4
26
+
#define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1 0x0bc
27
+
#define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2 0x0c0
28
28
#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4
29
29
#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8
30
+
#define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1 0x0cc
31
+
#define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2 0x0d0
32
+
#define QSERDES_V5_20_RX_VGA_CAL_CNTRL1 0x0d4
33
+
#define QSERDES_V5_20_RX_VGA_CAL_CNTRL2 0x0d8
30
34
#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc
31
35
#define QSERDES_V5_20_RX_GM_CAL 0x0ec
36
+
#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2 0x100
37
+
#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3 0x104
32
38
#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108
39
+
#define QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x118
40
+
#define QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x11c
41
+
#define QSERDES_V5_20_RX_SIGDET_ENABLES 0x120
42
+
#define QSERDES_V5_20_RX_SIGDET_CNTRL 0x124
43
+
#define QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL 0x12c
44
+
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0 0x160
33
45
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164
34
46
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168
35
47
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c
48
+
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4 0x170
36
49
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174
37
50
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178
38
51
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c
···
67
46
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac
68
47
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0
69
48
#define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4
49
+
#define QSERDES_V5_20_RX_DFE_DAC_ENABLE2 0x1b8
50
+
#define QSERDES_V5_20_RX_DFE_EN_TIMER 0x1bc
70
51
#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0
52
+
#define QSERDES_V5_20_RX_DCC_CTRL1 0x1c4
71
53
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
72
54
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8
73
55
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
+98
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+98
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
···
349
349
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
350
350
};
351
351
352
+
static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = {
353
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
354
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
355
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
356
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
357
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
358
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
359
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
360
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
361
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
362
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
363
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
364
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
365
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b),
366
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
367
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
368
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
369
+
};
370
+
371
+
static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = {
372
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f),
373
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
374
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
375
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
376
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
377
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
378
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
379
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
380
+
};
381
+
352
382
static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
353
383
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
354
384
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
···
853
823
.no_pcs_sw_reset = true,
854
824
};
855
825
826
+
static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
827
+
.lanes = 2,
828
+
829
+
.offsets = &qmp_ufs_offsets,
830
+
831
+
.tbls = {
832
+
.serdes = sm8350_ufsphy_serdes,
833
+
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
834
+
.tx = sm8350_ufsphy_tx,
835
+
.tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
836
+
.rx = sm8350_ufsphy_rx,
837
+
.rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
838
+
.pcs = sm8350_ufsphy_pcs,
839
+
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
840
+
},
841
+
.tbls_hs_b = {
842
+
.serdes = sm8350_ufsphy_hs_b_serdes,
843
+
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
844
+
},
845
+
.tbls_hs_g4 = {
846
+
.tx = sm8350_ufsphy_g4_tx,
847
+
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
848
+
.rx = sm8350_ufsphy_g4_rx,
849
+
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
850
+
.pcs = sm8350_ufsphy_g4_pcs,
851
+
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
852
+
},
853
+
.clk_list = sm8450_ufs_phy_clk_l,
854
+
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
855
+
.vreg_list = qmp_phy_vreg_l,
856
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
857
+
.regs = ufsphy_v5_regs_layout,
858
+
};
859
+
856
860
static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
857
861
.lanes = 2,
858
862
···
971
907
.vreg_list = qmp_phy_vreg_l,
972
908
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
973
909
.regs = ufsphy_v2_regs_layout,
910
+
911
+
.no_pcs_sw_reset = true,
912
+
};
913
+
914
+
static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
915
+
.lanes = 1,
916
+
917
+
.offsets = &qmp_ufs_offsets,
918
+
919
+
.tbls = {
920
+
.serdes = sdm845_ufsphy_serdes,
921
+
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
922
+
.tx = sdm845_ufsphy_tx,
923
+
.tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
924
+
.rx = sm7150_ufsphy_rx,
925
+
.rx_num = ARRAY_SIZE(sm7150_ufsphy_rx),
926
+
.pcs = sm7150_ufsphy_pcs,
927
+
.pcs_num = ARRAY_SIZE(sm7150_ufsphy_pcs),
928
+
},
929
+
.tbls_hs_b = {
930
+
.serdes = sdm845_ufsphy_hs_b_serdes,
931
+
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
932
+
},
933
+
.clk_list = sdm845_ufs_phy_clk_l,
934
+
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
935
+
.vreg_list = qmp_phy_vreg_l,
936
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
937
+
.regs = ufsphy_v3_regs_layout,
974
938
975
939
.no_pcs_sw_reset = true,
976
940
};
···
1635
1543
.compatible = "qcom,msm8998-qmp-ufs-phy",
1636
1544
.data = &sdm845_ufsphy_cfg,
1637
1545
}, {
1546
+
.compatible = "qcom,sa8775p-qmp-ufs-phy",
1547
+
.data = &sa8775p_ufsphy_cfg,
1548
+
}, {
1638
1549
.compatible = "qcom,sc8180x-qmp-ufs-phy",
1639
1550
.data = &sm8150_ufsphy_cfg,
1640
1551
}, {
···
1655
1560
}, {
1656
1561
.compatible = "qcom,sm6350-qmp-ufs-phy",
1657
1562
.data = &sdm845_ufsphy_cfg,
1563
+
}, {
1564
+
.compatible = "qcom,sm7150-qmp-ufs-phy",
1565
+
.data = &sm7150_ufsphy_cfg,
1658
1566
}, {
1659
1567
.compatible = "qcom,sm8150-qmp-ufs-phy",
1660
1568
.data = &sm8150_ufsphy_cfg,
+2
-4
drivers/phy/renesas/phy-rcar-gen3-pcie.c
+2
-4
drivers/phy/renesas/phy-rcar-gen3-pcie.c
···
126
126
return error;
127
127
}
128
128
129
-
static int rcar_gen3_phy_pcie_remove(struct platform_device *pdev)
129
+
static void rcar_gen3_phy_pcie_remove(struct platform_device *pdev)
130
130
{
131
131
pm_runtime_disable(&pdev->dev);
132
-
133
-
return 0;
134
132
};
135
133
136
134
static struct platform_driver rcar_gen3_phy_driver = {
···
137
139
.of_match_table = rcar_gen3_phy_pcie_match_table,
138
140
},
139
141
.probe = rcar_gen3_phy_pcie_probe,
140
-
.remove = rcar_gen3_phy_pcie_remove,
142
+
.remove_new = rcar_gen3_phy_pcie_remove,
141
143
};
142
144
143
145
module_platform_driver(rcar_gen3_phy_driver);
+2
-4
drivers/phy/renesas/phy-rcar-gen3-usb2.c
+2
-4
drivers/phy/renesas/phy-rcar-gen3-usb2.c
···
755
755
return ret;
756
756
}
757
757
758
-
static int rcar_gen3_phy_usb2_remove(struct platform_device *pdev)
758
+
static void rcar_gen3_phy_usb2_remove(struct platform_device *pdev)
759
759
{
760
760
struct rcar_gen3_chan *channel = platform_get_drvdata(pdev);
761
761
···
763
763
device_remove_file(&pdev->dev, &dev_attr_role);
764
764
765
765
pm_runtime_disable(&pdev->dev);
766
-
767
-
return 0;
768
766
};
769
767
770
768
static struct platform_driver rcar_gen3_phy_usb2_driver = {
···
771
773
.of_match_table = rcar_gen3_phy_usb2_match_table,
772
774
},
773
775
.probe = rcar_gen3_phy_usb2_probe,
774
-
.remove = rcar_gen3_phy_usb2_remove,
776
+
.remove_new = rcar_gen3_phy_usb2_remove,
775
777
};
776
778
module_platform_driver(rcar_gen3_phy_usb2_driver);
777
779
+2
-4
drivers/phy/renesas/phy-rcar-gen3-usb3.c
+2
-4
drivers/phy/renesas/phy-rcar-gen3-usb3.c
···
199
199
return ret;
200
200
}
201
201
202
-
static int rcar_gen3_phy_usb3_remove(struct platform_device *pdev)
202
+
static void rcar_gen3_phy_usb3_remove(struct platform_device *pdev)
203
203
{
204
204
pm_runtime_disable(&pdev->dev);
205
-
206
-
return 0;
207
205
};
208
206
209
207
static struct platform_driver rcar_gen3_phy_usb3_driver = {
···
210
212
.of_match_table = rcar_gen3_phy_usb3_match_table,
211
213
},
212
214
.probe = rcar_gen3_phy_usb3_probe,
213
-
.remove = rcar_gen3_phy_usb3_remove,
215
+
.remove_new = rcar_gen3_phy_usb3_remove,
214
216
};
215
217
module_platform_driver(rcar_gen3_phy_usb3_driver);
216
218
+2
-4
drivers/phy/renesas/r8a779f0-ether-serdes.c
+2
-4
drivers/phy/renesas/r8a779f0-ether-serdes.c
···
388
388
return 0;
389
389
}
390
390
391
-
static int r8a779f0_eth_serdes_remove(struct platform_device *pdev)
391
+
static void r8a779f0_eth_serdes_remove(struct platform_device *pdev)
392
392
{
393
393
pm_runtime_put(&pdev->dev);
394
394
pm_runtime_disable(&pdev->dev);
395
395
396
396
platform_set_drvdata(pdev, NULL);
397
-
398
-
return 0;
399
397
}
400
398
401
399
static struct platform_driver r8a779f0_eth_serdes_driver_platform = {
402
400
.probe = r8a779f0_eth_serdes_probe,
403
-
.remove = r8a779f0_eth_serdes_remove,
401
+
.remove_new = r8a779f0_eth_serdes_remove,
404
402
.driver = {
405
403
.name = "r8a779f0_eth_serdes",
406
404
.of_match_table = r8a779f0_eth_serdes_of_table,
+2
-4
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
+2
-4
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
···
459
459
return 0;
460
460
}
461
461
462
-
static int rockchip_inno_csidphy_remove(struct platform_device *pdev)
462
+
static void rockchip_inno_csidphy_remove(struct platform_device *pdev)
463
463
{
464
464
struct rockchip_inno_csidphy *priv = platform_get_drvdata(pdev);
465
465
466
466
pm_runtime_disable(priv->dev);
467
-
468
-
return 0;
469
467
}
470
468
471
469
static struct platform_driver rockchip_inno_csidphy_driver = {
···
472
474
.of_match_table = rockchip_inno_csidphy_match_id,
473
475
},
474
476
.probe = rockchip_inno_csidphy_probe,
475
-
.remove = rockchip_inno_csidphy_remove,
477
+
.remove_new = rockchip_inno_csidphy_remove,
476
478
};
477
479
478
480
module_platform_driver(rockchip_inno_csidphy_driver);
+2
-9
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
+2
-9
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
···
281
281
{2500000000, 0x15, 0x54, 0x7f, 0x15, 0x6a},
282
282
};
283
283
284
-
static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw)
285
-
{
286
-
return container_of(hw, struct inno_dsidphy, pll.hw);
287
-
}
288
-
289
284
static void phy_update_bits(struct inno_dsidphy *inno,
290
285
u8 first, u8 second, u8 mask, u8 val)
291
286
{
···
750
755
return 0;
751
756
}
752
757
753
-
static int inno_dsidphy_remove(struct platform_device *pdev)
758
+
static void inno_dsidphy_remove(struct platform_device *pdev)
754
759
{
755
760
struct inno_dsidphy *inno = platform_get_drvdata(pdev);
756
761
757
762
pm_runtime_disable(inno->dev);
758
-
759
-
return 0;
760
763
}
761
764
762
765
static const struct of_device_id inno_dsidphy_of_match[] = {
···
781
788
.of_match_table = of_match_ptr(inno_dsidphy_of_match),
782
789
},
783
790
.probe = inno_dsidphy_probe,
784
-
.remove = inno_dsidphy_remove,
791
+
.remove_new = inno_dsidphy_remove,
785
792
};
786
793
module_platform_driver(inno_dsidphy_driver);
787
794
+2
-4
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+2
-4
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
···
1246
1246
return PTR_ERR_OR_ZERO(phy_provider);
1247
1247
}
1248
1248
1249
-
static int inno_hdmi_phy_remove(struct platform_device *pdev)
1249
+
static void inno_hdmi_phy_remove(struct platform_device *pdev)
1250
1250
{
1251
1251
of_clk_del_provider(pdev->dev.of_node);
1252
-
1253
-
return 0;
1254
1252
}
1255
1253
1256
1254
static const struct of_device_id inno_hdmi_phy_of_match[] = {
···
1264
1266
1265
1267
static struct platform_driver inno_hdmi_phy_driver = {
1266
1268
.probe = inno_hdmi_phy_probe,
1267
-
.remove = inno_hdmi_phy_remove,
1269
+
.remove_new = inno_hdmi_phy_remove,
1268
1270
.driver = {
1269
1271
.name = "inno-hdmi-phy",
1270
1272
.of_match_table = inno_hdmi_phy_of_match,
+184
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+184
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
···
63
63
#define PHYREG18 0x44
64
64
#define PHYREG18_PLL_LOOP 0x32
65
65
66
+
#define PHYREG27 0x6C
67
+
#define PHYREG27_RX_TRIM_RK3588 0x4C
68
+
66
69
#define PHYREG32 0x7C
67
70
#define PHYREG32_SSC_MASK GENMASK(7, 4)
68
71
#define PHYREG32_SSC_DIR_SHIFT 4
···
117
114
struct combphy_reg con2_for_sata;
118
115
struct combphy_reg con3_for_sata;
119
116
struct combphy_reg pipe_con0_for_sata;
117
+
struct combphy_reg pipe_con1_for_sata;
120
118
struct combphy_reg pipe_xpcs_phy_ready;
119
+
struct combphy_reg pipe_pcie1l0_sel;
120
+
struct combphy_reg pipe_pcie1l1_sel;
121
121
};
122
122
123
123
struct rockchip_combphy_cfg {
···
565
559
.combphy_cfg = rk3568_combphy_cfg,
566
560
};
567
561
562
+
static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
563
+
{
564
+
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
565
+
unsigned long rate;
566
+
u32 val;
567
+
568
+
switch (priv->type) {
569
+
case PHY_TYPE_PCIE:
570
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
571
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
572
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
573
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
574
+
rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
575
+
rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
576
+
break;
577
+
case PHY_TYPE_USB3:
578
+
/* Set SSC downward spread spectrum */
579
+
rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
580
+
PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
581
+
PHYREG32);
582
+
583
+
/* Enable adaptive CTLE for USB3.0 Rx. */
584
+
val = readl(priv->mmio + PHYREG15);
585
+
val |= PHYREG15_CTLE_EN;
586
+
writel(val, priv->mmio + PHYREG15);
587
+
588
+
/* Set PLL KVCO fine tuning signals. */
589
+
rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
590
+
PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
591
+
PHYREG33);
592
+
593
+
/* Enable controlling random jitter. */
594
+
writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
595
+
596
+
/* Set PLL input clock divider 1/2. */
597
+
rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
598
+
PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
599
+
PHYREG6);
600
+
601
+
writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
602
+
writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
603
+
604
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
605
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
606
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
607
+
break;
608
+
case PHY_TYPE_SATA:
609
+
/* Enable adaptive CTLE for SATA Rx. */
610
+
val = readl(priv->mmio + PHYREG15);
611
+
val |= PHYREG15_CTLE_EN;
612
+
writel(val, priv->mmio + PHYREG15);
613
+
/*
614
+
* Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
615
+
* 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
616
+
*/
617
+
val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
618
+
val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
619
+
writel(val, priv->mmio + PHYREG7);
620
+
621
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
622
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
623
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
624
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
625
+
rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
626
+
rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
627
+
break;
628
+
case PHY_TYPE_SGMII:
629
+
case PHY_TYPE_QSGMII:
630
+
default:
631
+
dev_err(priv->dev, "incompatible PHY type\n");
632
+
return -EINVAL;
633
+
}
634
+
635
+
rate = clk_get_rate(priv->refclk);
636
+
637
+
switch (rate) {
638
+
case REF_CLOCK_24MHz:
639
+
if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
640
+
/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
641
+
val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
642
+
rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
643
+
val, PHYREG15);
644
+
645
+
writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
646
+
}
647
+
break;
648
+
649
+
case REF_CLOCK_25MHz:
650
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
651
+
break;
652
+
case REF_CLOCK_100MHz:
653
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
654
+
if (priv->type == PHY_TYPE_PCIE) {
655
+
/* PLL KVCO fine tuning. */
656
+
val = 4 << PHYREG33_PLL_KVCO_SHIFT;
657
+
rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
658
+
val, PHYREG33);
659
+
660
+
/* Enable controlling random jitter. */
661
+
writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
662
+
663
+
/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
664
+
writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27);
665
+
666
+
/* Set up su_trim: */
667
+
writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
668
+
} else if (priv->type == PHY_TYPE_SATA) {
669
+
/* downward spread spectrum +500ppm */
670
+
val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
671
+
val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
672
+
rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
673
+
}
674
+
break;
675
+
default:
676
+
dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
677
+
return -EINVAL;
678
+
}
679
+
680
+
if (priv->ext_refclk) {
681
+
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
682
+
if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
683
+
val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
684
+
val |= PHYREG13_CKRCV_AMP0;
685
+
rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
686
+
687
+
val = readl(priv->mmio + PHYREG14);
688
+
val |= PHYREG14_CKRCV_AMP1;
689
+
writel(val, priv->mmio + PHYREG14);
690
+
}
691
+
}
692
+
693
+
if (priv->enable_ssc) {
694
+
val = readl(priv->mmio + PHYREG8);
695
+
val |= PHYREG8_SSC_EN;
696
+
writel(val, priv->mmio + PHYREG8);
697
+
}
698
+
699
+
return 0;
700
+
}
701
+
702
+
static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
703
+
/* pipe-phy-grf */
704
+
.pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
705
+
.usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
706
+
.pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
707
+
.pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
708
+
.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
709
+
.pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
710
+
.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
711
+
.pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
712
+
.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
713
+
.pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
714
+
.pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
715
+
.pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
716
+
.con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
717
+
.con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
718
+
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
719
+
.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
720
+
.con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
721
+
.con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
722
+
.con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
723
+
.con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
724
+
/* pipe-grf */
725
+
.pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
726
+
.pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
727
+
.pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 },
728
+
.pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 },
729
+
};
730
+
731
+
static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
732
+
.grfcfg = &rk3588_combphy_grfcfgs,
733
+
.combphy_cfg = rk3588_combphy_cfg,
734
+
};
735
+
568
736
static const struct of_device_id rockchip_combphy_of_match[] = {
569
737
{
570
738
.compatible = "rockchip,rk3568-naneng-combphy",
571
739
.data = &rk3568_combphy_cfgs,
740
+
},
741
+
{
742
+
.compatible = "rockchip,rk3588-naneng-combphy",
743
+
.data = &rk3588_combphy_cfgs,
572
744
},
573
745
{ },
574
746
};
-15
drivers/phy/rockchip/phy-rockchip-pcie.c
-15
drivers/phy/rockchip/phy-rockchip-pcie.c
···
119
119
PHY_CFG_WR_SHIFT));
120
120
}
121
121
122
-
static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy,
123
-
u32 addr)
124
-
{
125
-
u32 val;
126
-
127
-
regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
128
-
HIWORD_UPDATE(addr,
129
-
PHY_CFG_RD_MASK,
130
-
PHY_CFG_ADDR_SHIFT));
131
-
regmap_read(rk_phy->reg_base,
132
-
rk_phy->phy_data->pcie_status,
133
-
&val);
134
-
return val;
135
-
}
136
-
137
122
static int rockchip_pcie_phy_power_off(struct phy *phy)
138
123
{
139
124
struct phy_pcie_instance *inst = phy_get_drvdata(phy);
+2
-4
drivers/phy/rockchip/phy-rockchip-typec.c
+2
-4
drivers/phy/rockchip/phy-rockchip-typec.c
···
1194
1194
return 0;
1195
1195
}
1196
1196
1197
-
static int rockchip_typec_phy_remove(struct platform_device *pdev)
1197
+
static void rockchip_typec_phy_remove(struct platform_device *pdev)
1198
1198
{
1199
1199
pm_runtime_disable(&pdev->dev);
1200
-
1201
-
return 0;
1202
1200
}
1203
1201
1204
1202
static const struct of_device_id rockchip_typec_phy_dt_ids[] = {
···
1211
1213
1212
1214
static struct platform_driver rockchip_typec_phy_driver = {
1213
1215
.probe = rockchip_typec_phy_probe,
1214
-
.remove = rockchip_typec_phy_remove,
1216
+
.remove_new = rockchip_typec_phy_remove,
1215
1217
.driver = {
1216
1218
.name = "rockchip-typec-phy",
1217
1219
.of_match_table = rockchip_typec_phy_dt_ids,
+10
-32
drivers/phy/st/phy-miphy28lp.c
+10
-32
drivers/phy/st/phy-miphy28lp.c
···
9
9
10
10
#include <linux/platform_device.h>
11
11
#include <linux/io.h>
12
+
#include <linux/iopoll.h>
12
13
#include <linux/kernel.h>
13
14
#include <linux/module.h>
14
15
#include <linux/of.h>
···
485
484
486
485
static inline int miphy28lp_wait_compensation(struct miphy28lp_phy *miphy_phy)
487
486
{
488
-
unsigned long finish = jiffies + 5 * HZ;
489
487
u8 val;
490
488
491
489
/* Waiting for Compensation to complete */
492
-
do {
493
-
val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6);
494
-
495
-
if (time_after_eq(jiffies, finish))
496
-
return -EBUSY;
497
-
cpu_relax();
498
-
} while (!(val & COMP_DONE));
499
-
500
-
return 0;
490
+
return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_COMP_FSM_6,
491
+
val, val & COMP_DONE, 1, 5 * USEC_PER_SEC);
501
492
}
502
493
503
494
···
798
805
799
806
static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy)
800
807
{
801
-
unsigned long finish = jiffies + 5 * HZ;
802
808
u8 mask = HFC_PLL | HFC_RDY;
803
809
u8 val;
804
810
···
808
816
if (miphy_phy->type == PHY_TYPE_SATA)
809
817
mask |= PHY_RDY;
810
818
811
-
do {
812
-
val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1);
813
-
if ((val & mask) != mask)
814
-
cpu_relax();
815
-
else
816
-
return 0;
817
-
} while (!time_after_eq(jiffies, finish));
818
-
819
-
return -EBUSY;
819
+
return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_STATUS_1,
820
+
val, (val & mask) == mask, 1,
821
+
5 * USEC_PER_SEC);
820
822
}
821
823
822
824
static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy)
823
825
{
824
826
struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
825
-
unsigned long finish = jiffies + 5 * HZ;
826
827
u32 val;
827
828
828
829
if (!miphy_phy->osc_rdy)
···
824
839
if (!miphy_phy->syscfg_reg[SYSCFG_STATUS])
825
840
return -EINVAL;
826
841
827
-
do {
828
-
regmap_read(miphy_dev->regmap,
829
-
miphy_phy->syscfg_reg[SYSCFG_STATUS], &val);
830
-
831
-
if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY)
832
-
cpu_relax();
833
-
else
834
-
return 0;
835
-
} while (!time_after_eq(jiffies, finish));
836
-
837
-
return -EBUSY;
842
+
return regmap_read_poll_timeout(miphy_dev->regmap,
843
+
miphy_phy->syscfg_reg[SYSCFG_STATUS],
844
+
val, val & MIPHY_OSC_RDY, 1,
845
+
5 * USEC_PER_SEC);
838
846
}
839
847
840
848
static int miphy28lp_get_resource_byname(struct device_node *child,
+1
-1
drivers/phy/st/phy-spear1310-miphy.c
+1
-1
drivers/phy/st/phy-spear1310-miphy.c
+1
-1
drivers/phy/st/phy-spear1340-miphy.c
+1
-1
drivers/phy/st/phy-spear1340-miphy.c
+5
-4
drivers/phy/st/phy-stm32-usbphyc.c
+5
-4
drivers/phy/st/phy-stm32-usbphyc.c
···
317
317
318
318
stm32_usbphyc_set_bits(pll_reg, PLLEN);
319
319
320
+
/* Wait for maximum lock time */
321
+
usleep_range(200, 300);
322
+
320
323
return 0;
321
324
322
325
reg_disable:
···
769
766
return ret;
770
767
}
771
768
772
-
static int stm32_usbphyc_remove(struct platform_device *pdev)
769
+
static void stm32_usbphyc_remove(struct platform_device *pdev)
773
770
{
774
771
struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
775
772
int port;
···
782
779
stm32_usbphyc_clk48_unregister(usbphyc);
783
780
784
781
clk_disable_unprepare(usbphyc->clk);
785
-
786
-
return 0;
787
782
}
788
783
789
784
static int __maybe_unused stm32_usbphyc_resume(struct device *dev)
···
811
810
812
811
static struct platform_driver stm32_usbphyc_driver = {
813
812
.probe = stm32_usbphyc_probe,
814
-
.remove = stm32_usbphyc_remove,
813
+
.remove_new = stm32_usbphyc_remove,
815
814
.driver = {
816
815
.of_match_table = stm32_usbphyc_of_match,
817
816
.name = "stm32-usbphyc",
+20
drivers/phy/tegra/xusb-tegra186.c
+20
drivers/phy/tegra/xusb-tegra186.c
···
145
145
#define MODE_HS MODE(0)
146
146
#define MODE_RST MODE(1)
147
147
148
+
#define XUSB_AO_UTMIP_SLEEPWALK_STATUS(x) (0xa0 + (x) * 4)
149
+
148
150
#define XUSB_AO_UTMIP_SLEEPWALK_CFG(x) (0xd0 + (x) * 4)
149
151
#define XUSB_AO_UHSIC_SLEEPWALK_CFG(x) (0xf0 + (x) * 4)
150
152
#define FAKE_USBOP_VAL BIT(0)
···
174
172
#define AP_A BIT(4)
175
173
#define AN_A BIT(5)
176
174
#define HIGHZ_A BIT(6)
175
+
#define MASTER_ENABLE_A BIT(7)
177
176
/* phase B */
178
177
#define USBOP_RPD_B BIT(8)
179
178
#define USBON_RPD_B BIT(9)
180
179
#define AP_B BIT(12)
181
180
#define AN_B BIT(13)
182
181
#define HIGHZ_B BIT(14)
182
+
#define MASTER_ENABLE_B BIT(15)
183
183
/* phase C */
184
184
#define USBOP_RPD_C BIT(16)
185
185
#define USBON_RPD_C BIT(17)
186
186
#define AP_C BIT(20)
187
187
#define AN_C BIT(21)
188
188
#define HIGHZ_C BIT(22)
189
+
#define MASTER_ENABLE_C BIT(23)
189
190
/* phase D */
190
191
#define USBOP_RPD_D BIT(24)
191
192
#define USBON_RPD_D BIT(25)
192
193
#define AP_D BIT(28)
193
194
#define AN_D BIT(29)
194
195
#define HIGHZ_D BIT(30)
196
+
#define MASTER_ENABLE_D BIT(31)
197
+
#define MASTER_ENABLE_B_C_D \
198
+
(MASTER_ENABLE_B | MASTER_ENABLE_C | MASTER_ENABLE_D)
195
199
196
200
#define XUSB_AO_UHSIC_SLEEPWALK(x) (0x120 + (x) * 4)
197
201
/* phase A */
···
425
417
value |= HIGHZ_A;
426
418
value |= AP_A;
427
419
value |= AN_B | AN_C | AN_D;
420
+
if (padctl->soc->supports_lp_cfg_en)
421
+
value |= MASTER_ENABLE_B_C_D;
428
422
break;
429
423
430
424
case USB_SPEED_LOW:
···
434
424
value |= HIGHZ_A;
435
425
value |= AN_A;
436
426
value |= AP_B | AP_C | AP_D;
427
+
if (padctl->soc->supports_lp_cfg_en)
428
+
value |= MASTER_ENABLE_B_C_D;
437
429
break;
438
430
439
431
default:
···
499
487
value &= ~WAKE_VAL(~0);
500
488
value |= WAKE_VAL_NONE;
501
489
ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
490
+
491
+
if (padctl->soc->supports_lp_cfg_en) {
492
+
/* disable the four stages of sleepwalk */
493
+
value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK(index));
494
+
value &= ~(MASTER_ENABLE_A | MASTER_ENABLE_B_C_D);
495
+
ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
496
+
}
502
497
503
498
/* power down the line state detectors of the port */
504
499
value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
···
1692
1673
.supports_gen2 = true,
1693
1674
.poll_trk_completed = true,
1694
1675
.trk_hw_mode = true,
1676
+
.supports_lp_cfg_en = true,
1695
1677
};
1696
1678
EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc);
1697
1679
#endif
+4
-4
drivers/phy/tegra/xusb.c
+4
-4
drivers/phy/tegra/xusb.c
···
805
805
usb2->base.lane = usb2->base.ops->map(&usb2->base);
806
806
if (IS_ERR(usb2->base.lane)) {
807
807
err = PTR_ERR(usb2->base.lane);
808
+
tegra_xusb_port_unregister(&usb2->base);
808
809
goto out;
809
810
}
810
811
···
872
871
ulpi->base.lane = ulpi->base.ops->map(&ulpi->base);
873
872
if (IS_ERR(ulpi->base.lane)) {
874
873
err = PTR_ERR(ulpi->base.lane);
874
+
tegra_xusb_port_unregister(&ulpi->base);
875
875
goto out;
876
876
}
877
877
···
1269
1267
return err;
1270
1268
}
1271
1269
1272
-
static int tegra_xusb_padctl_remove(struct platform_device *pdev)
1270
+
static void tegra_xusb_padctl_remove(struct platform_device *pdev)
1273
1271
{
1274
1272
struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
1275
1273
int err;
···
1287
1285
dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
1288
1286
1289
1287
padctl->soc->ops->remove(padctl);
1290
-
1291
-
return 0;
1292
1288
}
1293
1289
1294
1290
static __maybe_unused int tegra_xusb_padctl_suspend_noirq(struct device *dev)
···
1321
1321
.pm = &tegra_xusb_padctl_pm_ops,
1322
1322
},
1323
1323
.probe = tegra_xusb_padctl_probe,
1324
-
.remove = tegra_xusb_padctl_remove,
1324
+
.remove_new = tegra_xusb_padctl_remove,
1325
1325
};
1326
1326
module_platform_driver(tegra_xusb_padctl_driver);
1327
1327
+1
drivers/phy/tegra/xusb.h
+1
drivers/phy/tegra/xusb.h
+2
-4
drivers/phy/ti/phy-am654-serdes.c
+2
-4
drivers/phy/ti/phy-am654-serdes.c
···
842
842
return ret;
843
843
}
844
844
845
-
static int serdes_am654_remove(struct platform_device *pdev)
845
+
static void serdes_am654_remove(struct platform_device *pdev)
846
846
{
847
847
struct serdes_am654 *am654_phy = platform_get_drvdata(pdev);
848
848
struct device_node *node = am654_phy->of_node;
849
849
850
850
pm_runtime_disable(&pdev->dev);
851
851
of_clk_del_provider(node);
852
-
853
-
return 0;
854
852
}
855
853
856
854
static struct platform_driver serdes_am654_driver = {
857
855
.probe = serdes_am654_probe,
858
-
.remove = serdes_am654_remove,
856
+
.remove_new = serdes_am654_remove,
859
857
.driver = {
860
858
.name = "phy-am654",
861
859
.of_match_table = serdes_am654_id_table,
+2
-4
drivers/phy/ti/phy-da8xx-usb.c
+2
-4
drivers/phy/ti/phy-da8xx-usb.c
···
211
211
return 0;
212
212
}
213
213
214
-
static int da8xx_usb_phy_remove(struct platform_device *pdev)
214
+
static void da8xx_usb_phy_remove(struct platform_device *pdev)
215
215
{
216
216
struct da8xx_usb_phy *d_phy = platform_get_drvdata(pdev);
217
217
···
219
219
phy_remove_lookup(d_phy->usb20_phy, "usb-phy", "musb-da8xx");
220
220
phy_remove_lookup(d_phy->usb11_phy, "usb-phy", "ohci-da8xx");
221
221
}
222
-
223
-
return 0;
224
222
}
225
223
226
224
static const struct of_device_id da8xx_usb_phy_ids[] = {
···
229
231
230
232
static struct platform_driver da8xx_usb_phy_driver = {
231
233
.probe = da8xx_usb_phy_probe,
232
-
.remove = da8xx_usb_phy_remove,
234
+
.remove_new = da8xx_usb_phy_remove,
233
235
.driver = {
234
236
.name = "da8xx-usb-phy",
235
237
.of_match_table = da8xx_usb_phy_ids,
+2
-4
drivers/phy/ti/phy-dm816x-usb.c
+2
-4
drivers/phy/ti/phy-dm816x-usb.c
···
257
257
return error;
258
258
}
259
259
260
-
static int dm816x_usb_phy_remove(struct platform_device *pdev)
260
+
static void dm816x_usb_phy_remove(struct platform_device *pdev)
261
261
{
262
262
struct dm816x_usb_phy *phy = platform_get_drvdata(pdev);
263
263
264
264
usb_remove_phy(&phy->phy);
265
265
pm_runtime_disable(phy->dev);
266
266
clk_unprepare(phy->refclk);
267
-
268
-
return 0;
269
267
}
270
268
271
269
static struct platform_driver dm816x_usb_phy_driver = {
272
270
.probe = dm816x_usb_phy_probe,
273
-
.remove = dm816x_usb_phy_remove,
271
+
.remove_new = dm816x_usb_phy_remove,
274
272
.driver = {
275
273
.name = "dm816x-usb-phy",
276
274
.pm = &dm816x_usb_phy_pm_ops,
+9
-10
drivers/phy/ti/phy-j721e-wiz.c
+9
-10
drivers/phy/ti/phy-j721e-wiz.c
···
443
443
int i;
444
444
445
445
for (i = 0; i < num_lanes; i++) {
446
-
if (wiz->lane_phy_type[i] == PHY_TYPE_DP)
446
+
if (wiz->lane_phy_type[i] == PHY_TYPE_DP) {
447
447
mode = LANE_MODE_GEN1;
448
-
else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII)
448
+
} else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
449
449
mode = LANE_MODE_GEN2;
450
-
else
451
-
continue;
452
-
453
-
if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
450
+
} else if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
454
451
ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);
455
452
ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);
456
453
ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3);
457
454
mode = LANE_MODE_GEN1;
455
+
} else {
456
+
continue;
458
457
}
459
458
460
459
ret = regmap_field_write(wiz->p_standard_mode[i], mode);
···
1234
1235
if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
1235
1236
return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
1236
1237
break;
1238
+
1239
+
case J721E_WIZ_16G:
1237
1240
case J721E_WIZ_10G:
1238
1241
case J7200_WIZ_10G:
1239
1242
case J721S2_WIZ_10G:
···
1637
1636
return ret;
1638
1637
}
1639
1638
1640
-
static int wiz_remove(struct platform_device *pdev)
1639
+
static void wiz_remove(struct platform_device *pdev)
1641
1640
{
1642
1641
struct device *dev = &pdev->dev;
1643
1642
struct device_node *node = dev->of_node;
···
1651
1650
wiz_clock_cleanup(wiz, node);
1652
1651
pm_runtime_put(dev);
1653
1652
pm_runtime_disable(dev);
1654
-
1655
-
return 0;
1656
1653
}
1657
1654
1658
1655
static struct platform_driver wiz_driver = {
1659
1656
.probe = wiz_probe,
1660
-
.remove = wiz_remove,
1657
+
.remove_new = wiz_remove,
1661
1658
.driver = {
1662
1659
.name = "wiz",
1663
1660
.of_match_table = wiz_id_table,
+5
-9
drivers/phy/ti/phy-omap-usb2.c
+5
-9
drivers/phy/ti/phy-omap-usb2.c
···
445
445
PTR_ERR(phy->wkupclk));
446
446
phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
447
447
448
-
if (IS_ERR(phy->wkupclk)) {
449
-
if (PTR_ERR(phy->wkupclk) != -EPROBE_DEFER)
450
-
dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
451
-
return PTR_ERR(phy->wkupclk);
452
-
}
448
+
if (IS_ERR(phy->wkupclk))
449
+
return dev_err_probe(&pdev->dev, PTR_ERR(phy->wkupclk),
450
+
"unable to get usb_phy_cm_clk32k\n");
453
451
454
452
dev_warn(&pdev->dev,
455
453
"found usb_phy_cm_clk32k, please fix DTS\n");
···
504
506
return 0;
505
507
}
506
508
507
-
static int omap_usb2_remove(struct platform_device *pdev)
509
+
static void omap_usb2_remove(struct platform_device *pdev)
508
510
{
509
511
struct omap_usb *phy = platform_get_drvdata(pdev);
510
512
511
513
usb_remove_phy(&phy->phy);
512
514
pm_runtime_disable(phy->dev);
513
-
514
-
return 0;
515
515
}
516
516
517
517
static struct platform_driver omap_usb2_driver = {
518
518
.probe = omap_usb2_probe,
519
-
.remove = omap_usb2_remove,
519
+
.remove_new = omap_usb2_remove,
520
520
.driver = {
521
521
.name = "omap-usb2",
522
522
.of_match_table = omap_usb2_id_table,
+2
-4
drivers/phy/ti/phy-ti-pipe3.c
+2
-4
drivers/phy/ti/phy-ti-pipe3.c
···
841
841
return PTR_ERR_OR_ZERO(phy_provider);
842
842
}
843
843
844
-
static int ti_pipe3_remove(struct platform_device *pdev)
844
+
static void ti_pipe3_remove(struct platform_device *pdev)
845
845
{
846
846
struct ti_pipe3 *phy = platform_get_drvdata(pdev);
847
847
···
850
850
phy->sata_refclk_enabled = false;
851
851
}
852
852
pm_runtime_disable(&pdev->dev);
853
-
854
-
return 0;
855
853
}
856
854
857
855
static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
···
926
928
927
929
static struct platform_driver ti_pipe3_driver = {
928
930
.probe = ti_pipe3_probe,
929
-
.remove = ti_pipe3_remove,
931
+
.remove_new = ti_pipe3_remove,
930
932
.driver = {
931
933
.name = "ti-pipe3",
932
934
.of_match_table = ti_pipe3_id_table,
+2
-4
drivers/phy/ti/phy-twl4030-usb.c
+2
-4
drivers/phy/ti/phy-twl4030-usb.c
···
787
787
return 0;
788
788
}
789
789
790
-
static int twl4030_usb_remove(struct platform_device *pdev)
790
+
static void twl4030_usb_remove(struct platform_device *pdev)
791
791
{
792
792
struct twl4030_usb *twl = platform_get_drvdata(pdev);
793
793
int val;
···
821
821
822
822
/* disable complete OTG block */
823
823
twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
824
-
825
-
return 0;
826
824
}
827
825
828
826
#ifdef CONFIG_OF
···
833
835
834
836
static struct platform_driver twl4030_usb_driver = {
835
837
.probe = twl4030_usb_probe,
836
-
.remove = twl4030_usb_remove,
838
+
.remove_new = twl4030_usb_remove,
837
839
.driver = {
838
840
.name = "twl4030_usb",
839
841
.pm = &twl4030_usb_pm_ops,
+2
-3
drivers/phy/xilinx/phy-zynqmp.c
+2
-3
drivers/phy/xilinx/phy-zynqmp.c
···
8
8
* Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>
9
9
* Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10
10
*
11
-
* This driver is tested for USB, SATA and Display Port currently.
12
-
* Other controllers PCIe and SGMII should also work but that is
13
-
* experimental as of now.
11
+
* This driver is tested for USB, SGMII, SATA and Display Port currently.
12
+
* PCIe should also work but that is experimental as of now.
14
13
*/
15
14
16
15
#include <linux/clk.h>