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bus: mhi: host: pci_generic: Set DMA mask for VFs

VFs in devices like QDU100 are capable of accessing host memory up to 40
bits, compared to 32 bits used by PFs and other non-SR-IOV capable MHI
devices.

To support this, configure `dma_mask` independently for PFs and VFs, by
introducing a new 'vf_dma_data_width' member in 'mhi_pci_dev_info' struct
and set it to 40 for QDU100.

Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
[mani: reworded subject and description]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/20250912-uevent_vdev_next-20250911-v4-6-fa2f6ccd301b@quicinc.com

authored by

Vivek Pernamitta and committed by
Manivannan Sadhasivam 54c67740 aa1a0e93

+9 -2
+9 -2
drivers/bus/mhi/host/pci_generic.c
··· 41 41 * @edl_trigger: capable of triggering EDL mode in the device (if supported) 42 42 * @bar_num: PCI base address register to use for MHI MMIO register space 43 43 * @dma_data_width: DMA transfer word size (32 or 64 bits) 44 + * @vf_dma_data_width: DMA transfer word size for VF's (optional) 44 45 * @mru_default: default MRU size for MBIM network packets 45 46 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead 46 47 * of inband wake support (such as sdx24) ··· 57 56 bool edl_trigger; 58 57 unsigned int bar_num; 59 58 unsigned int dma_data_width; 59 + unsigned int vf_dma_data_width; 60 60 unsigned int mru_default; 61 61 bool sideband_wake; 62 62 bool no_m3; ··· 302 300 .config = &mhi_qcom_qdu100_config, 303 301 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 304 302 .dma_data_width = 32, 303 + .vf_dma_data_width = 40, 305 304 .sideband_wake = false, 306 305 .no_m3 = true, 307 306 .reset_on_remove = true, ··· 1303 1300 const struct mhi_controller_config *mhi_cntrl_config; 1304 1301 struct mhi_pci_device *mhi_pdev; 1305 1302 struct mhi_controller *mhi_cntrl; 1303 + unsigned int dma_data_width; 1306 1304 int err; 1307 1305 1308 1306 dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name); ··· 1326 1322 1327 1323 mhi_cntrl = &mhi_pdev->mhi_cntrl; 1328 1324 1325 + dma_data_width = (pdev->is_virtfn && info->vf_dma_data_width) ? 1326 + info->vf_dma_data_width : info->dma_data_width; 1327 + 1329 1328 mhi_cntrl->cntrl_dev = &pdev->dev; 1330 1329 mhi_cntrl->iova_start = 0; 1331 - mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width); 1330 + mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(dma_data_width); 1332 1331 mhi_cntrl->fw_image = info->fw; 1333 1332 mhi_cntrl->edl_image = info->edl; 1334 1333 ··· 1355 1348 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; 1356 1349 } 1357 1350 1358 - err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); 1351 + err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(dma_data_width)); 1359 1352 if (err) 1360 1353 return err; 1361 1354