Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'kvm-riscv-6.20-1' of https://github.com/kvm-riscv/linux into HEAD
KVM/riscv changes for 6.20
- Fixes for issues discoverd by KVM API fuzzing in
kvm_riscv_aia_imsic_has_attr(), kvm_riscv_aia_imsic_rw_attr(),
and kvm_riscv_vcpu_aia_imsic_update()
- Allow Zalasr, Zilsd and Zclsd extensions for Guest/VM
- Add riscv vm satp modes in KVM selftests
- Transparent huge page support for G-stage
- Adjust the number of available guest irq files based on
MMIO register sizes in DeviceTree or ACPI
+330
-22
+3
arch/riscv/include/uapi/asm/kvm.h
+3
arch/riscv/include/uapi/asm/kvm.h
+1
-1
arch/riscv/kvm/aia.c
+1
-1
arch/riscv/kvm/aia.c
+11
-2
arch/riscv/kvm/aia_imsic.c
+11
-2
arch/riscv/kvm/aia_imsic.c
···
797
797
if (kvm->arch.aia.mode == KVM_DEV_RISCV_AIA_MODE_EMUL)
798
798
return 1;
799
799
800
+
/* IMSIC vCPU state may not be initialized yet */
801
+
if (!imsic)
802
+
return 1;
803
+
800
804
/* Read old IMSIC VS-file details */
801
805
read_lock_irqsave(&imsic->vsfile_lock, flags);
802
806
old_vsfile_hgei = imsic->vsfile_hgei;
···
956
952
if (!vcpu)
957
953
return -ENODEV;
958
954
959
-
isel = KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(type);
960
955
imsic = vcpu->arch.aia_context.imsic_state;
956
+
if (!imsic)
957
+
return -ENODEV;
958
+
isel = KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(type);
961
959
962
960
read_lock_irqsave(&imsic->vsfile_lock, flags);
963
961
···
999
993
if (!vcpu)
1000
994
return -ENODEV;
1001
995
1002
-
isel = KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(type);
1003
996
imsic = vcpu->arch.aia_context.imsic_state;
997
+
if (!imsic)
998
+
return -ENODEV;
999
+
1000
+
isel = KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(type);
1004
1001
return imsic_mrif_isel_check(imsic->nr_eix, isel);
1005
1002
}
1006
1003
+140
arch/riscv/kvm/mmu.c
+140
arch/riscv/kvm/mmu.c
···
305
305
return pte_young(ptep_get(ptep));
306
306
}
307
307
308
+
static bool fault_supports_gstage_huge_mapping(struct kvm_memory_slot *memslot,
309
+
unsigned long hva)
310
+
{
311
+
hva_t uaddr_start, uaddr_end;
312
+
gpa_t gpa_start;
313
+
size_t size;
314
+
315
+
size = memslot->npages * PAGE_SIZE;
316
+
uaddr_start = memslot->userspace_addr;
317
+
uaddr_end = uaddr_start + size;
318
+
319
+
gpa_start = memslot->base_gfn << PAGE_SHIFT;
320
+
321
+
/*
322
+
* Pages belonging to memslots that don't have the same alignment
323
+
* within a PMD for userspace and GPA cannot be mapped with g-stage
324
+
* PMD entries, because we'll end up mapping the wrong pages.
325
+
*
326
+
* Consider a layout like the following:
327
+
*
328
+
* memslot->userspace_addr:
329
+
* +-----+--------------------+--------------------+---+
330
+
* |abcde|fgh vs-stage block | vs-stage block tv|xyz|
331
+
* +-----+--------------------+--------------------+---+
332
+
*
333
+
* memslot->base_gfn << PAGE_SHIFT:
334
+
* +---+--------------------+--------------------+-----+
335
+
* |abc|def g-stage block | g-stage block |tvxyz|
336
+
* +---+--------------------+--------------------+-----+
337
+
*
338
+
* If we create those g-stage blocks, we'll end up with this incorrect
339
+
* mapping:
340
+
* d -> f
341
+
* e -> g
342
+
* f -> h
343
+
*/
344
+
if ((gpa_start & (PMD_SIZE - 1)) != (uaddr_start & (PMD_SIZE - 1)))
345
+
return false;
346
+
347
+
/*
348
+
* Next, let's make sure we're not trying to map anything not covered
349
+
* by the memslot. This means we have to prohibit block size mappings
350
+
* for the beginning and end of a non-block aligned and non-block sized
351
+
* memory slot (illustrated by the head and tail parts of the
352
+
* userspace view above containing pages 'abcde' and 'xyz',
353
+
* respectively).
354
+
*
355
+
* Note that it doesn't matter if we do the check using the
356
+
* userspace_addr or the base_gfn, as both are equally aligned (per
357
+
* the check above) and equally sized.
358
+
*/
359
+
return (hva >= ALIGN(uaddr_start, PMD_SIZE)) && (hva < ALIGN_DOWN(uaddr_end, PMD_SIZE));
360
+
}
361
+
362
+
static int get_hva_mapping_size(struct kvm *kvm,
363
+
unsigned long hva)
364
+
{
365
+
int size = PAGE_SIZE;
366
+
unsigned long flags;
367
+
pgd_t pgd;
368
+
p4d_t p4d;
369
+
pud_t pud;
370
+
pmd_t pmd;
371
+
372
+
/*
373
+
* Disable IRQs to prevent concurrent tear down of host page tables,
374
+
* e.g. if the primary MMU promotes a P*D to a huge page and then frees
375
+
* the original page table.
376
+
*/
377
+
local_irq_save(flags);
378
+
379
+
/*
380
+
* Read each entry once. As above, a non-leaf entry can be promoted to
381
+
* a huge page _during_ this walk. Re-reading the entry could send the
382
+
* walk into the weeks, e.g. p*d_leaf() returns false (sees the old
383
+
* value) and then p*d_offset() walks into the target huge page instead
384
+
* of the old page table (sees the new value).
385
+
*/
386
+
pgd = pgdp_get(pgd_offset(kvm->mm, hva));
387
+
if (pgd_none(pgd))
388
+
goto out;
389
+
390
+
p4d = p4dp_get(p4d_offset(&pgd, hva));
391
+
if (p4d_none(p4d) || !p4d_present(p4d))
392
+
goto out;
393
+
394
+
pud = pudp_get(pud_offset(&p4d, hva));
395
+
if (pud_none(pud) || !pud_present(pud))
396
+
goto out;
397
+
398
+
if (pud_leaf(pud)) {
399
+
size = PUD_SIZE;
400
+
goto out;
401
+
}
402
+
403
+
pmd = pmdp_get(pmd_offset(&pud, hva));
404
+
if (pmd_none(pmd) || !pmd_present(pmd))
405
+
goto out;
406
+
407
+
if (pmd_leaf(pmd))
408
+
size = PMD_SIZE;
409
+
410
+
out:
411
+
local_irq_restore(flags);
412
+
return size;
413
+
}
414
+
415
+
static unsigned long transparent_hugepage_adjust(struct kvm *kvm,
416
+
struct kvm_memory_slot *memslot,
417
+
unsigned long hva,
418
+
kvm_pfn_t *hfnp, gpa_t *gpa)
419
+
{
420
+
kvm_pfn_t hfn = *hfnp;
421
+
422
+
/*
423
+
* Make sure the adjustment is done only for THP pages. Also make
424
+
* sure that the HVA and GPA are sufficiently aligned and that the
425
+
* block map is contained within the memslot.
426
+
*/
427
+
if (fault_supports_gstage_huge_mapping(memslot, hva)) {
428
+
int sz;
429
+
430
+
sz = get_hva_mapping_size(kvm, hva);
431
+
if (sz < PMD_SIZE)
432
+
return sz;
433
+
434
+
*gpa &= PMD_MASK;
435
+
hfn &= ~(PTRS_PER_PMD - 1);
436
+
*hfnp = hfn;
437
+
438
+
return PMD_SIZE;
439
+
}
440
+
441
+
return PAGE_SIZE;
442
+
}
443
+
308
444
int kvm_riscv_mmu_map(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot,
309
445
gpa_t gpa, unsigned long hva, bool is_write,
310
446
struct kvm_gstage_mapping *out_map)
···
533
397
534
398
if (mmu_invalidate_retry(kvm, mmu_seq))
535
399
goto out_unlock;
400
+
401
+
/* Check if we are backed by a THP and thus use block mapping if possible */
402
+
if (vma_pagesize == PAGE_SIZE)
403
+
vma_pagesize = transparent_hugepage_adjust(kvm, memslot, hva, &hfn, &gpa);
536
404
537
405
if (writable) {
538
406
mark_page_dirty_in_slot(kvm, memslot, gfn);
+4
arch/riscv/kvm/vcpu_onereg.c
+4
arch/riscv/kvm/vcpu_onereg.c
···
50
50
KVM_ISA_EXT_ARR(ZAAMO),
51
51
KVM_ISA_EXT_ARR(ZABHA),
52
52
KVM_ISA_EXT_ARR(ZACAS),
53
+
KVM_ISA_EXT_ARR(ZALASR),
53
54
KVM_ISA_EXT_ARR(ZALRSC),
54
55
KVM_ISA_EXT_ARR(ZAWRS),
55
56
KVM_ISA_EXT_ARR(ZBA),
···
64
63
KVM_ISA_EXT_ARR(ZCB),
65
64
KVM_ISA_EXT_ARR(ZCD),
66
65
KVM_ISA_EXT_ARR(ZCF),
66
+
KVM_ISA_EXT_ARR(ZCLSD),
67
67
KVM_ISA_EXT_ARR(ZCMOP),
68
68
KVM_ISA_EXT_ARR(ZFA),
69
69
KVM_ISA_EXT_ARR(ZFBFMIN),
···
81
79
KVM_ISA_EXT_ARR(ZIHINTNTL),
82
80
KVM_ISA_EXT_ARR(ZIHINTPAUSE),
83
81
KVM_ISA_EXT_ARR(ZIHPM),
82
+
KVM_ISA_EXT_ARR(ZILSD),
84
83
KVM_ISA_EXT_ARR(ZIMOP),
85
84
KVM_ISA_EXT_ARR(ZKND),
86
85
KVM_ISA_EXT_ARR(ZKNE),
···
190
187
case KVM_RISCV_ISA_EXT_ZAAMO:
191
188
case KVM_RISCV_ISA_EXT_ZABHA:
192
189
case KVM_RISCV_ISA_EXT_ZACAS:
190
+
case KVM_RISCV_ISA_EXT_ZALASR:
193
191
case KVM_RISCV_ISA_EXT_ZALRSC:
194
192
case KVM_RISCV_ISA_EXT_ZAWRS:
195
193
case KVM_RISCV_ISA_EXT_ZBA:
+1
-4
arch/riscv/kvm/vcpu_pmu.c
+1
-4
arch/riscv/kvm/vcpu_pmu.c
+2
arch/riscv/mm/pgtable.c
+2
arch/riscv/mm/pgtable.c
+11
-1
drivers/irqchip/irq-riscv-imsic-state.c
+11
-1
drivers/irqchip/irq-riscv-imsic-state.c
···
784
784
785
785
int __init imsic_setup_state(struct fwnode_handle *fwnode, void *opaque)
786
786
{
787
-
u32 i, j, index, nr_parent_irqs, nr_mmios, nr_handlers = 0;
787
+
u32 i, j, index, nr_parent_irqs, nr_mmios, nr_guest_files, nr_handlers = 0;
788
788
struct imsic_global_config *global;
789
789
struct imsic_local_config *local;
790
790
void __iomem **mmios_va = NULL;
···
878
878
}
879
879
880
880
/* Configure handlers for target CPUs */
881
+
global->nr_guest_files = BIT(global->guest_index_bits) - 1;
881
882
for (i = 0; i < nr_parent_irqs; i++) {
882
883
rc = imsic_get_parent_hartid(fwnode, i, &hartid);
883
884
if (rc) {
···
918
917
local = per_cpu_ptr(global->local, cpu);
919
918
local->msi_pa = mmios[index].start + reloff;
920
919
local->msi_va = mmios_va[index] + reloff;
920
+
921
+
/*
922
+
* KVM uses global->nr_guest_files to determine the available guest
923
+
* interrupt files on each CPU. Take the minimum number of guest
924
+
* interrupt files across all CPUs to avoid KVM incorrectly allocating
925
+
* an unexisted or unmapped guest interrupt file on some CPUs.
926
+
*/
927
+
nr_guest_files = (resource_size(&mmios[index]) - reloff) / IMSIC_MMIO_PAGE_SZ - 1;
928
+
global->nr_guest_files = min(global->nr_guest_files, nr_guest_files);
921
929
922
930
nr_handlers++;
923
931
}
+3
include/linux/irqchip/riscv-imsic.h
+3
include/linux/irqchip/riscv-imsic.h
+14
-3
tools/testing/selftests/kvm/include/kvm_util.h
+14
-3
tools/testing/selftests/kvm/include/kvm_util.h
···
198
198
VM_MODE_P36V48_64K,
199
199
VM_MODE_P47V47_16K,
200
200
VM_MODE_P36V47_16K,
201
+
202
+
VM_MODE_P56V57_4K, /* For riscv64 */
203
+
VM_MODE_P56V48_4K,
204
+
VM_MODE_P56V39_4K,
205
+
VM_MODE_P50V57_4K,
206
+
VM_MODE_P50V48_4K,
207
+
VM_MODE_P50V39_4K,
208
+
VM_MODE_P41V57_4K,
209
+
VM_MODE_P41V48_4K,
210
+
VM_MODE_P41V39_4K,
211
+
201
212
NUM_VM_MODES,
202
213
};
203
214
···
233
222
shape; \
234
223
})
235
224
236
-
#if defined(__aarch64__)
237
-
238
225
extern enum vm_guest_mode vm_mode_default;
226
+
227
+
#if defined(__aarch64__)
239
228
240
229
#define VM_MODE_DEFAULT vm_mode_default
241
230
#define MIN_PAGE_SHIFT 12U
···
259
248
#error "RISC-V 32-bit kvm selftests not supported"
260
249
#endif
261
250
262
-
#define VM_MODE_DEFAULT VM_MODE_P40V48_4K
251
+
#define VM_MODE_DEFAULT vm_mode_default
263
252
#define MIN_PAGE_SHIFT 12U
264
253
#define ptes_per_page(page_size) ((page_size) / 8)
265
254
+2
tools/testing/selftests/kvm/include/riscv/processor.h
+2
tools/testing/selftests/kvm/include/riscv/processor.h
+34
-7
tools/testing/selftests/kvm/lib/guest_modes.c
+34
-7
tools/testing/selftests/kvm/lib/guest_modes.c
···
4
4
*/
5
5
#include "guest_modes.h"
6
6
7
-
#ifdef __aarch64__
7
+
#if defined(__aarch64__) || defined(__riscv)
8
8
#include "processor.h"
9
9
enum vm_guest_mode vm_mode_default;
10
10
#endif
···
13
13
14
14
void guest_modes_append_default(void)
15
15
{
16
-
#ifndef __aarch64__
16
+
#if !defined(__aarch64__) && !defined(__riscv)
17
17
guest_mode_append(VM_MODE_DEFAULT, true);
18
-
#else
18
+
#endif
19
+
20
+
#ifdef __aarch64__
19
21
{
20
22
unsigned int limit = kvm_check_cap(KVM_CAP_ARM_VM_IPA_SIZE);
21
23
uint32_t ipa4k, ipa16k, ipa64k;
···
76
74
#ifdef __riscv
77
75
{
78
76
unsigned int sz = kvm_check_cap(KVM_CAP_VM_GPA_BITS);
77
+
unsigned long satp_mode = riscv64_get_satp_mode() << SATP_MODE_SHIFT;
78
+
int i;
79
79
80
-
if (sz >= 52)
81
-
guest_mode_append(VM_MODE_P52V48_4K, true);
82
-
if (sz >= 48)
83
-
guest_mode_append(VM_MODE_P48V48_4K, true);
80
+
switch (sz) {
81
+
case 59:
82
+
guest_mode_append(VM_MODE_P56V57_4K, satp_mode >= SATP_MODE_57);
83
+
guest_mode_append(VM_MODE_P56V48_4K, satp_mode >= SATP_MODE_48);
84
+
guest_mode_append(VM_MODE_P56V39_4K, satp_mode >= SATP_MODE_39);
85
+
break;
86
+
case 50:
87
+
guest_mode_append(VM_MODE_P50V57_4K, satp_mode >= SATP_MODE_57);
88
+
guest_mode_append(VM_MODE_P50V48_4K, satp_mode >= SATP_MODE_48);
89
+
guest_mode_append(VM_MODE_P50V39_4K, satp_mode >= SATP_MODE_39);
90
+
break;
91
+
case 41:
92
+
guest_mode_append(VM_MODE_P41V57_4K, satp_mode >= SATP_MODE_57);
93
+
guest_mode_append(VM_MODE_P41V48_4K, satp_mode >= SATP_MODE_48);
94
+
guest_mode_append(VM_MODE_P41V39_4K, satp_mode >= SATP_MODE_39);
95
+
break;
96
+
default:
97
+
break;
98
+
}
99
+
100
+
/* set the first supported mode as default */
101
+
vm_mode_default = NUM_VM_MODES;
102
+
for (i = 0; vm_mode_default == NUM_VM_MODES && i < NUM_VM_MODES; i++) {
103
+
if (guest_modes[i].supported && guest_modes[i].enabled)
104
+
vm_mode_default = i;
105
+
}
106
+
TEST_ASSERT(vm_mode_default != NUM_VM_MODES, "No supported mode!");
84
107
}
85
108
#endif
86
109
}
+33
tools/testing/selftests/kvm/lib/kvm_util.c
+33
tools/testing/selftests/kvm/lib/kvm_util.c
···
209
209
[VM_MODE_P36V48_64K] = "PA-bits:36, VA-bits:48, 64K pages",
210
210
[VM_MODE_P47V47_16K] = "PA-bits:47, VA-bits:47, 16K pages",
211
211
[VM_MODE_P36V47_16K] = "PA-bits:36, VA-bits:47, 16K pages",
212
+
[VM_MODE_P56V57_4K] = "PA-bits:56, VA-bits:57, 4K pages",
213
+
[VM_MODE_P56V48_4K] = "PA-bits:56, VA-bits:48, 4K pages",
214
+
[VM_MODE_P56V39_4K] = "PA-bits:56, VA-bits:39, 4K pages",
215
+
[VM_MODE_P50V57_4K] = "PA-bits:50, VA-bits:57, 4K pages",
216
+
[VM_MODE_P50V48_4K] = "PA-bits:50, VA-bits:48, 4K pages",
217
+
[VM_MODE_P50V39_4K] = "PA-bits:50, VA-bits:39, 4K pages",
218
+
[VM_MODE_P41V57_4K] = "PA-bits:41, VA-bits:57, 4K pages",
219
+
[VM_MODE_P41V48_4K] = "PA-bits:41, VA-bits:48, 4K pages",
220
+
[VM_MODE_P41V39_4K] = "PA-bits:41, VA-bits:39, 4K pages",
212
221
};
213
222
_Static_assert(sizeof(strings)/sizeof(char *) == NUM_VM_MODES,
214
223
"Missing new mode strings?");
···
245
236
[VM_MODE_P36V48_64K] = { 36, 48, 0x10000, 16 },
246
237
[VM_MODE_P47V47_16K] = { 47, 47, 0x4000, 14 },
247
238
[VM_MODE_P36V47_16K] = { 36, 47, 0x4000, 14 },
239
+
[VM_MODE_P56V57_4K] = { 56, 57, 0x1000, 12 },
240
+
[VM_MODE_P56V48_4K] = { 56, 48, 0x1000, 12 },
241
+
[VM_MODE_P56V39_4K] = { 56, 39, 0x1000, 12 },
242
+
[VM_MODE_P50V57_4K] = { 50, 57, 0x1000, 12 },
243
+
[VM_MODE_P50V48_4K] = { 50, 48, 0x1000, 12 },
244
+
[VM_MODE_P50V39_4K] = { 50, 39, 0x1000, 12 },
245
+
[VM_MODE_P41V57_4K] = { 41, 57, 0x1000, 12 },
246
+
[VM_MODE_P41V48_4K] = { 41, 48, 0x1000, 12 },
247
+
[VM_MODE_P41V39_4K] = { 41, 39, 0x1000, 12 },
248
248
};
249
249
_Static_assert(sizeof(vm_guest_mode_params)/sizeof(struct vm_guest_mode_params) == NUM_VM_MODES,
250
250
"Missing new mode params?");
···
355
337
break;
356
338
case VM_MODE_P44V64_4K:
357
339
vm->mmu.pgtable_levels = 5;
340
+
break;
341
+
case VM_MODE_P56V57_4K:
342
+
case VM_MODE_P50V57_4K:
343
+
case VM_MODE_P41V57_4K:
344
+
vm->mmu.pgtable_levels = 5;
345
+
break;
346
+
case VM_MODE_P56V48_4K:
347
+
case VM_MODE_P50V48_4K:
348
+
case VM_MODE_P41V48_4K:
349
+
vm->mmu.pgtable_levels = 4;
350
+
break;
351
+
case VM_MODE_P56V39_4K:
352
+
case VM_MODE_P50V39_4K:
353
+
case VM_MODE_P41V39_4K:
354
+
vm->mmu.pgtable_levels = 3;
358
355
break;
359
356
default:
360
357
TEST_FAIL("Unknown guest mode: 0x%x", vm->mode);
+59
-4
tools/testing/selftests/kvm/lib/riscv/processor.c
+59
-4
tools/testing/selftests/kvm/lib/riscv/processor.c
···
8
8
#include <linux/compiler.h>
9
9
#include <assert.h>
10
10
11
+
#include "guest_modes.h"
11
12
#include "kvm_util.h"
12
13
#include "processor.h"
13
14
#include "ucall_common.h"
···
194
193
{
195
194
struct kvm_vm *vm = vcpu->vm;
196
195
unsigned long satp;
196
+
unsigned long satp_mode;
197
+
unsigned long max_satp_mode;
197
198
198
199
/*
199
200
* The RISC-V Sv48 MMU mode supports 56-bit physical address
200
201
* for 48-bit virtual address with 4KB last level page size.
201
202
*/
202
203
switch (vm->mode) {
203
-
case VM_MODE_P52V48_4K:
204
-
case VM_MODE_P48V48_4K:
205
-
case VM_MODE_P40V48_4K:
204
+
case VM_MODE_P56V57_4K:
205
+
case VM_MODE_P50V57_4K:
206
+
case VM_MODE_P41V57_4K:
207
+
satp_mode = SATP_MODE_57;
208
+
break;
209
+
case VM_MODE_P56V48_4K:
210
+
case VM_MODE_P50V48_4K:
211
+
case VM_MODE_P41V48_4K:
212
+
satp_mode = SATP_MODE_48;
213
+
break;
214
+
case VM_MODE_P56V39_4K:
215
+
case VM_MODE_P50V39_4K:
216
+
case VM_MODE_P41V39_4K:
217
+
satp_mode = SATP_MODE_39;
206
218
break;
207
219
default:
208
220
TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode);
209
221
}
210
222
223
+
max_satp_mode = vcpu_get_reg(vcpu, RISCV_CONFIG_REG(satp_mode));
224
+
225
+
if ((satp_mode >> SATP_MODE_SHIFT) > max_satp_mode)
226
+
TEST_FAIL("Unable to set satp mode 0x%lx, max mode 0x%lx\n",
227
+
satp_mode >> SATP_MODE_SHIFT, max_satp_mode);
228
+
211
229
satp = (vm->mmu.pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN;
212
-
satp |= SATP_MODE_48;
230
+
satp |= satp_mode;
213
231
214
232
vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(satp), satp);
215
233
}
···
530
510
GUEST_ASSERT(!ret.error);
531
511
532
512
return ret.value;
513
+
}
514
+
515
+
void kvm_selftest_arch_init(void)
516
+
{
517
+
/*
518
+
* riscv64 doesn't have a true default mode, so start by detecting the
519
+
* supported vm mode.
520
+
*/
521
+
guest_modes_append_default();
522
+
}
523
+
524
+
unsigned long riscv64_get_satp_mode(void)
525
+
{
526
+
int kvm_fd, vm_fd, vcpu_fd, err;
527
+
uint64_t val;
528
+
struct kvm_one_reg reg = {
529
+
.id = RISCV_CONFIG_REG(satp_mode),
530
+
.addr = (uint64_t)&val,
531
+
};
532
+
533
+
kvm_fd = open_kvm_dev_path_or_exit();
534
+
vm_fd = __kvm_ioctl(kvm_fd, KVM_CREATE_VM, NULL);
535
+
TEST_ASSERT(vm_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VM, vm_fd));
536
+
537
+
vcpu_fd = ioctl(vm_fd, KVM_CREATE_VCPU, 0);
538
+
TEST_ASSERT(vcpu_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VCPU, vcpu_fd));
539
+
540
+
err = ioctl(vcpu_fd, KVM_GET_ONE_REG, ®);
541
+
TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd));
542
+
543
+
close(vcpu_fd);
544
+
close(vm_fd);
545
+
close(kvm_fd);
546
+
547
+
return val;
533
548
}
+12
tools/testing/selftests/kvm/riscv/get-reg-list.c
+12
tools/testing/selftests/kvm/riscv/get-reg-list.c
···
65
65
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAAMO:
66
66
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZABHA:
67
67
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS:
68
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALASR:
68
69
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALRSC:
69
70
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS:
70
71
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA:
···
79
78
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB:
80
79
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD:
81
80
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF:
81
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCLSD:
82
82
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP:
83
83
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA:
84
84
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFBFMIN:
···
96
94
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTNTL:
97
95
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
98
96
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHPM:
97
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZILSD:
99
98
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIMOP:
100
99
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKND:
101
100
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNE:
···
528
525
KVM_ISA_EXT_ARR(ZAAMO),
529
526
KVM_ISA_EXT_ARR(ZABHA),
530
527
KVM_ISA_EXT_ARR(ZACAS),
528
+
KVM_ISA_EXT_ARR(ZALASR),
531
529
KVM_ISA_EXT_ARR(ZALRSC),
532
530
KVM_ISA_EXT_ARR(ZAWRS),
533
531
KVM_ISA_EXT_ARR(ZBA),
···
542
538
KVM_ISA_EXT_ARR(ZCB),
543
539
KVM_ISA_EXT_ARR(ZCD),
544
540
KVM_ISA_EXT_ARR(ZCF),
541
+
KVM_ISA_EXT_ARR(ZCLSD),
545
542
KVM_ISA_EXT_ARR(ZCMOP),
546
543
KVM_ISA_EXT_ARR(ZFA),
547
544
KVM_ISA_EXT_ARR(ZFBFMIN),
···
559
554
KVM_ISA_EXT_ARR(ZIHINTNTL),
560
555
KVM_ISA_EXT_ARR(ZIHINTPAUSE),
561
556
KVM_ISA_EXT_ARR(ZIHPM),
557
+
KVM_ISA_EXT_ARR(ZILSD),
562
558
KVM_ISA_EXT_ARR(ZIMOP),
563
559
KVM_ISA_EXT_ARR(ZKND),
564
560
KVM_ISA_EXT_ARR(ZKNE),
···
1172
1166
KVM_ISA_EXT_SIMPLE_CONFIG(zaamo, ZAAMO);
1173
1167
KVM_ISA_EXT_SIMPLE_CONFIG(zabha, ZABHA);
1174
1168
KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS);
1169
+
KVM_ISA_EXT_SIMPLE_CONFIG(zalasr, ZALASR);
1175
1170
KVM_ISA_EXT_SIMPLE_CONFIG(zalrsc, ZALRSC);
1176
1171
KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS);
1177
1172
KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);
···
1186
1179
KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB);
1187
1180
KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD);
1188
1181
KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF);
1182
+
KVM_ISA_EXT_SIMPLE_CONFIG(zclsd, ZCLSD);
1189
1183
KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP);
1190
1184
KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
1191
1185
KVM_ISA_EXT_SIMPLE_CONFIG(zfbfmin, ZFBFMIN);
···
1203
1195
KVM_ISA_EXT_SIMPLE_CONFIG(zihintntl, ZIHINTNTL);
1204
1196
KVM_ISA_EXT_SIMPLE_CONFIG(zihintpause, ZIHINTPAUSE);
1205
1197
KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM);
1198
+
KVM_ISA_EXT_SIMPLE_CONFIG(zilsd, ZILSD);
1206
1199
KVM_ISA_EXT_SIMPLE_CONFIG(zimop, ZIMOP);
1207
1200
KVM_ISA_EXT_SIMPLE_CONFIG(zknd, ZKND);
1208
1201
KVM_ISA_EXT_SIMPLE_CONFIG(zkne, ZKNE);
···
1256
1247
&config_zabha,
1257
1248
&config_zacas,
1258
1249
&config_zalrsc,
1250
+
&config_zalasr,
1259
1251
&config_zawrs,
1260
1252
&config_zba,
1261
1253
&config_zbb,
···
1269
1259
&config_zcb,
1270
1260
&config_zcd,
1271
1261
&config_zcf,
1262
+
&config_zclsd,
1272
1263
&config_zcmop,
1273
1264
&config_zfa,
1274
1265
&config_zfbfmin,
···
1286
1275
&config_zihintntl,
1287
1276
&config_zihintpause,
1288
1277
&config_zihpm,
1278
+
&config_zilsd,
1289
1279
&config_zimop,
1290
1280
&config_zknd,
1291
1281
&config_zkne,