Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'rtc-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
Pull RTC updates from Alexandre Belloni:
"There is one new driver and then most of the changes are the device
tree bindings conversions to yaml.
New driver:
- Epson RX8111
Drivers:
- Many Device Tree bindings conversions to dtschema
- pcf8563: wakeup-source support"
* tag 'rtc-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
pcf8563: add wakeup-source support
rtc: rx8111: handle VLOW flag
rtc: rx8111: demote warnings to debug level
rtc: rx6110: Constify struct regmap_config
dt-bindings: rtc: convert trivial devices into dtschema
dt-bindings: rtc: stmp3xxx-rtc: convert to dtschema
dt-bindings: rtc: pxa-rtc: convert to dtschema
rtc: Add driver for Epson RX8111
dt-bindings: rtc: Add Epson RX8111
rtc: mcp795: drop unneeded MODULE_ALIAS
rtc: nuvoton: Modify part number value
rtc: test: Split rtc unit test into slow and normal speed test
dt-bindings: rtc: nxp,lpc1788-rtc: convert to dtschema
dt-bindings: rtc: digicolor-rtc: move to trivial-rtc
dt-bindings: rtc: alphascale,asm9260-rtc: convert to dtschema
dt-bindings: rtc: armada-380-rtc: convert to dtschema
rtc: cros-ec: provide ID table for avoiding fallback match
+702
-250
-19
Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.txt
-19
Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.txt
···
1
-
* Alphascale asm9260 SoC Real Time Clock
2
-
3
-
Required properties:
4
-
- compatible: Should be "alphascale,asm9260-rtc"
5
-
- reg: Physical base address of the controller and length
6
-
of memory mapped region.
7
-
- interrupts: IRQ line for the RTC.
8
-
- clocks: Reference to the clock entry.
9
-
- clock-names: should contain:
10
-
* "ahb" for the SoC RTC clock
11
-
12
-
Example:
13
-
rtc0: rtc@800a0000 {
14
-
compatible = "alphascale,asm9260-rtc";
15
-
reg = <0x800a0000 0x100>;
16
-
clocks = <&acc CLKID_AHB_RTC>;
17
-
clock-names = "ahb";
18
-
interrupts = <2>;
19
-
};
+50
Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.yaml
+50
Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/rtc/alphascale,asm9260-rtc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Alphascale asm9260 SoC Real Time Clock
8
+
9
+
maintainers:
10
+
- Javier Carrasco <javier.carrasco.cruz@gmail.com>
11
+
12
+
allOf:
13
+
- $ref: rtc.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: alphascale,asm9260-rtc
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
clocks:
23
+
maxItems: 1
24
+
25
+
clock-names:
26
+
const: ahb
27
+
28
+
interrupts:
29
+
maxItems: 1
30
+
31
+
required:
32
+
- compatible
33
+
- reg
34
+
- clocks
35
+
- clock-names
36
+
- interrupts
37
+
38
+
unevaluatedProperties: false
39
+
40
+
examples:
41
+
- |
42
+
#include <dt-bindings/clock/alphascale,asm9260.h>
43
+
44
+
rtc@800a0000 {
45
+
compatible = "alphascale,asm9260-rtc";
46
+
reg = <0x800a0000 0x100>;
47
+
clocks = <&acc CLKID_AHB_RTC>;
48
+
clock-names = "ahb";
49
+
interrupts = <2>;
50
+
};
-24
Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
-24
Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
···
1
-
* Real Time Clock of the Armada 38x/7K/8K SoCs
2
-
3
-
RTC controller for the Armada 38x, 7K and 8K SoCs
4
-
5
-
Required properties:
6
-
- compatible : Should be one of the following:
7
-
"marvell,armada-380-rtc" for Armada 38x SoC
8
-
"marvell,armada-8k-rtc" for Aramda 7K/8K SoCs
9
-
- reg: a list of base address and size pairs, one for each entry in
10
-
reg-names
11
-
- reg names: should contain:
12
-
* "rtc" for the RTC registers
13
-
* "rtc-soc" for the SoC related registers and among them the one
14
-
related to the interrupt.
15
-
- interrupts: IRQ line for the RTC.
16
-
17
-
Example:
18
-
19
-
rtc@a3800 {
20
-
compatible = "marvell,armada-380-rtc";
21
-
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
22
-
reg-names = "rtc", "rtc-soc";
23
-
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
24
-
};
-17
Documentation/devicetree/bindings/rtc/digicolor-rtc.txt
-17
Documentation/devicetree/bindings/rtc/digicolor-rtc.txt
···
1
-
Conexant Digicolor Real Time Clock controller
2
-
3
-
This binding currently supports the CX92755 SoC.
4
-
5
-
Required properties:
6
-
- compatible: should be "cnxt,cx92755-rtc"
7
-
- reg: physical base address of the controller and length of memory mapped
8
-
region.
9
-
- interrupts: rtc alarm interrupt
10
-
11
-
Example:
12
-
13
-
rtc@f0000c30 {
14
-
compatible = "cnxt,cx92755-rtc";
15
-
reg = <0xf0000c30 0x18>;
16
-
interrupts = <25>;
17
-
};
+51
Documentation/devicetree/bindings/rtc/fsl,stmp3xxx-rtc.yaml
+51
Documentation/devicetree/bindings/rtc/fsl,stmp3xxx-rtc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/rtc/fsl,stmp3xxx-rtc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: STMP3xxx/i.MX28 Time Clock Controller
8
+
9
+
maintainers:
10
+
- Javier Carrasco <javier.carrasco.cruz@gmail.com>
11
+
12
+
allOf:
13
+
- $ref: rtc.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
oneOf:
18
+
- items:
19
+
- enum:
20
+
- fsl,imx28-rtc
21
+
- fsl,imx23-rtc
22
+
- const: fsl,stmp3xxx-rtc
23
+
- const: fsl,stmp3xxx-rtc
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
interrupts:
29
+
maxItems: 1
30
+
31
+
stmp,crystal-freq:
32
+
description:
33
+
Override crystal frequency as determined from fuse bits.
34
+
Use <0> for "no crystal".
35
+
$ref: /schemas/types.yaml#/definitions/uint32
36
+
enum: [0, 32000, 32768]
37
+
38
+
required:
39
+
- compatible
40
+
- reg
41
+
- interrupts
42
+
43
+
unevaluatedProperties: false
44
+
45
+
examples:
46
+
- |
47
+
rtc@80056000 {
48
+
compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
49
+
reg = <0x80056000 2000>;
50
+
interrupts = <29>;
51
+
};
-17
Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt
-17
Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt
···
1
-
Android Goldfish RTC
2
-
3
-
Android Goldfish RTC device used by Android emulator.
4
-
5
-
Required properties:
6
-
7
-
- compatible : should contain "google,goldfish-rtc"
8
-
- reg : <registers mapping>
9
-
- interrupts : <interrupt mapping>
10
-
11
-
Example:
12
-
13
-
goldfish_timer@9020000 {
14
-
compatible = "google,goldfish-rtc";
15
-
reg = <0x9020000 0x1000>;
16
-
interrupts = <0x3>;
17
-
};
-15
Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt
-15
Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt
···
1
-
* NXP LPC32xx SoC Real Time Clock controller
2
-
3
-
Required properties:
4
-
- compatible: must be "nxp,lpc3220-rtc"
5
-
- reg: physical base address of the controller and length of memory mapped
6
-
region.
7
-
- interrupts: The RTC interrupt
8
-
9
-
Example:
10
-
11
-
rtc@40024000 {
12
-
compatible = "nxp,lpc3220-rtc";
13
-
reg = <0x40024000 0x1000>;
14
-
interrupts = <52 0>;
15
-
};
+51
Documentation/devicetree/bindings/rtc/marvell,armada-380-rtc.yaml
+51
Documentation/devicetree/bindings/rtc/marvell,armada-380-rtc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/rtc/marvell,armada-380-rtc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: RTC controller for the Armada 38x, 7K and 8K SoCs
8
+
9
+
maintainers:
10
+
- Javier Carrasco <javier.carrasco.cruz@gmail.com>
11
+
12
+
allOf:
13
+
- $ref: rtc.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
enum:
18
+
- marvell,armada-380-rtc
19
+
- marvell,armada-8k-rtc
20
+
21
+
reg:
22
+
items:
23
+
- description: RTC base address size
24
+
- description: Base address and size of SoC related registers
25
+
26
+
reg-names:
27
+
items:
28
+
- const: rtc
29
+
- const: rtc-soc
30
+
31
+
interrupts:
32
+
maxItems: 1
33
+
34
+
required:
35
+
- compatible
36
+
- reg
37
+
- reg-names
38
+
- interrupts
39
+
40
+
unevaluatedProperties: false
41
+
42
+
examples:
43
+
- |
44
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
45
+
46
+
rtc@a3800 {
47
+
compatible = "marvell,armada-380-rtc";
48
+
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
49
+
reg-names = "rtc", "rtc-soc";
50
+
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
51
+
};
+40
Documentation/devicetree/bindings/rtc/marvell,pxa-rtc.yaml
+40
Documentation/devicetree/bindings/rtc/marvell,pxa-rtc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/rtc/marvell,pxa-rtc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: PXA Real Time Clock
8
+
9
+
maintainers:
10
+
- Javier Carrasco <javier.carrasco.cruz@gmail.com>
11
+
12
+
allOf:
13
+
- $ref: rtc.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: marvell,pxa-rtc
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
interrupts:
23
+
items:
24
+
- description: 1 Hz
25
+
- description: Alarm
26
+
27
+
required:
28
+
- compatible
29
+
- reg
30
+
- interrupts
31
+
32
+
unevaluatedProperties: false
33
+
34
+
examples:
35
+
- |
36
+
rtc@40900000 {
37
+
compatible = "marvell,pxa-rtc";
38
+
reg = <0x40900000 0x3c>;
39
+
interrupts = <30>, <31>;
40
+
};
-12
Documentation/devicetree/bindings/rtc/maxim,ds1742.txt
-12
Documentation/devicetree/bindings/rtc/maxim,ds1742.txt
···
1
-
* Maxim (Dallas) DS1742/DS1743 Real Time Clock
2
-
3
-
Required properties:
4
-
- compatible: Should contain "maxim,ds1742".
5
-
- reg: Physical base address of the RTC and length of memory
6
-
mapped region.
7
-
8
-
Example:
9
-
rtc: rtc@10000000 {
10
-
compatible = "maxim,ds1742";
11
-
reg = <0x10000000 0x800>;
12
-
};
-21
Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.txt
-21
Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.txt
···
1
-
NXP LPC1788 real-time clock
2
-
3
-
The LPC1788 RTC provides calendar and clock functionality
4
-
together with periodic tick and alarm interrupt support.
5
-
6
-
Required properties:
7
-
- compatible : must contain "nxp,lpc1788-rtc"
8
-
- reg : Specifies base physical address and size of the registers.
9
-
- interrupts : A single interrupt specifier.
10
-
- clocks : Must contain clock specifiers for rtc and register clock
11
-
- clock-names : Must contain "rtc" and "reg"
12
-
See ../clocks/clock-bindings.txt for details.
13
-
14
-
Example:
15
-
rtc: rtc@40046000 {
16
-
compatible = "nxp,lpc1788-rtc";
17
-
reg = <0x40046000 0x1000>;
18
-
interrupts = <47>;
19
-
clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
20
-
clock-names = "rtc", "reg";
21
-
};
+58
Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml
+58
Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/rtc/nxp,lpc1788-rtc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP LPC1788 real-time clock
8
+
9
+
description:
10
+
The LPC1788 RTC provides calendar and clock functionality
11
+
together with periodic tick and alarm interrupt support.
12
+
13
+
maintainers:
14
+
- Javier Carrasco <javier.carrasco.cruz@gmail.com>
15
+
16
+
allOf:
17
+
- $ref: rtc.yaml#
18
+
19
+
properties:
20
+
compatible:
21
+
const: nxp,lpc1788-rtc
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: RTC clock
29
+
- description: Register clock
30
+
31
+
clock-names:
32
+
items:
33
+
- const: rtc
34
+
- const: reg
35
+
36
+
interrupts:
37
+
maxItems: 1
38
+
39
+
required:
40
+
- compatible
41
+
- reg
42
+
- clocks
43
+
- clock-names
44
+
- interrupts
45
+
46
+
unevaluatedProperties: false
47
+
48
+
examples:
49
+
- |
50
+
#include <dt-bindings/clock/lpc18xx-ccu.h>
51
+
52
+
rtc@40046000 {
53
+
compatible = "nxp,lpc1788-rtc";
54
+
reg = <0x40046000 0x1000>;
55
+
clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
56
+
clock-names = "rtc", "reg";
57
+
interrupts = <47>;
58
+
};
-18
Documentation/devicetree/bindings/rtc/orion-rtc.txt
-18
Documentation/devicetree/bindings/rtc/orion-rtc.txt
···
1
-
* Mvebu Real Time Clock
2
-
3
-
RTC controller for the Kirkwood, the Dove, the Armada 370 and the
4
-
Armada XP SoCs
5
-
6
-
Required properties:
7
-
- compatible : Should be "marvell,orion-rtc"
8
-
- reg: physical base address of the controller and length of memory mapped
9
-
region.
10
-
- interrupts: IRQ line for the RTC.
11
-
12
-
Example:
13
-
14
-
rtc@10300 {
15
-
compatible = "marvell,orion-rtc";
16
-
reg = <0xd0010300 0x20>;
17
-
interrupts = <50>;
18
-
};
-14
Documentation/devicetree/bindings/rtc/pxa-rtc.txt
-14
Documentation/devicetree/bindings/rtc/pxa-rtc.txt
-22
Documentation/devicetree/bindings/rtc/rtc-aspeed.txt
-22
Documentation/devicetree/bindings/rtc/rtc-aspeed.txt
···
1
-
ASPEED BMC RTC
2
-
==============
3
-
4
-
Required properties:
5
-
- compatible: should be one of the following
6
-
* aspeed,ast2400-rtc for the ast2400
7
-
* aspeed,ast2500-rtc for the ast2500
8
-
* aspeed,ast2600-rtc for the ast2600
9
-
10
-
- reg: physical base address of the controller and length of memory mapped
11
-
region
12
-
13
-
- interrupts: The interrupt number
14
-
15
-
Example:
16
-
17
-
rtc@1e781000 {
18
-
compatible = "aspeed,ast2400-rtc";
19
-
reg = <0x1e781000 0x18>;
20
-
interrupts = <22>;
21
-
status = "disabled";
22
-
};
-15
Documentation/devicetree/bindings/rtc/spear-rtc.txt
-15
Documentation/devicetree/bindings/rtc/spear-rtc.txt
···
1
-
* SPEAr RTC
2
-
3
-
Required properties:
4
-
- compatible : "st,spear600-rtc"
5
-
- reg : Address range of the rtc registers
6
-
- interrupt: Should contain the rtc interrupt number
7
-
8
-
Example:
9
-
10
-
rtc@fc000000 {
11
-
compatible = "st,spear600-rtc";
12
-
reg = <0xfc000000 0x1000>;
13
-
interrupt-parent = <&vic1>;
14
-
interrupts = <12>;
15
-
};
-21
Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt
-21
Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt
···
1
-
* STMP3xxx/i.MX28 Time Clock controller
2
-
3
-
Required properties:
4
-
- compatible: should be one of the following.
5
-
* "fsl,stmp3xxx-rtc"
6
-
- reg: physical base address of the controller and length of memory mapped
7
-
region.
8
-
- interrupts: rtc alarm interrupt
9
-
10
-
Optional properties:
11
-
- stmp,crystal-freq: override crystal frequency as determined from fuse bits.
12
-
Only <32000> and <32768> are possible for the hardware. Use <0> for
13
-
"no crystal".
14
-
15
-
Example:
16
-
17
-
rtc@80056000 {
18
-
compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
19
-
reg = <0x80056000 2000>;
20
-
interrupts = <29>;
21
-
};
+21
Documentation/devicetree/bindings/rtc/trivial-rtc.yaml
+21
Documentation/devicetree/bindings/rtc/trivial-rtc.yaml
···
24
24
- abracon,abb5zes3
25
25
# AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
26
26
- abracon,abeoz9
27
+
# ASPEED BMC ast2400 Real-time Clock
28
+
- aspeed,ast2400-rtc
29
+
# ASPEED BMC ast2500 Real-time Clock
30
+
- aspeed,ast2500-rtc
31
+
# ASPEED BMC ast2600 Real-time Clock
32
+
- aspeed,ast2600-rtc
33
+
# Conexant Digicolor Real Time Clock Controller
34
+
- cnxt,cx92755-rtc
27
35
# I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
28
36
- dallas,ds1374
29
37
# Dallas DS1672 Real-time Clock
···
46
38
- epson,rx8025
47
39
- epson,rx8035
48
40
# I2C-BUS INTERFACE REAL TIME CLOCK MODULE with Battery Backed RAM
41
+
- epson,rx8111
49
42
- epson,rx8571
50
43
# I2C-BUS INTERFACE REAL TIME CLOCK MODULE
51
44
- epson,rx8581
45
+
# Android Goldfish Real-time Clock
46
+
- google,goldfish-rtc
52
47
# Intersil ISL1208 Low Power RTC with Battery Backed SRAM
53
48
- isil,isl1208
54
49
# Intersil ISL1218 Low Power RTC with Battery Backed SRAM
55
50
- isil,isl1218
51
+
# Mvebu Real-time Clock
52
+
- marvell,orion-rtc
53
+
# Maxim DS1742/DS1743 Real-time Clock
54
+
- maxim,ds1742
56
55
# SPI-BUS INTERFACE REAL TIME CLOCK MODULE
57
56
- maxim,mcp795
58
57
# Real Time Clock Module with I2C-Bus
59
58
- microcrystal,rv3029
60
59
# Real Time Clock
61
60
- microcrystal,rv8523
61
+
# NXP LPC32xx SoC Real-time Clock
62
+
- nxp,lpc3220-rtc
62
63
# Real-time Clock Module
63
64
- pericom,pt7c4338
64
65
# I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
···
84
67
- ricoh,rv5c387a
85
68
# 2-wire CMOS real-time clock
86
69
- sii,s35390a
70
+
# ST SPEAr Real-time Clock
71
+
- st,spear600-rtc
72
+
# VIA/Wondermedia VT8500 Real-time Clock
73
+
- via,vt8500-rtc
87
74
# I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
88
75
- whwave,sd3078
89
76
# Xircom X1205 I2C RTC
-15
Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
-15
Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
···
1
-
VIA/Wondermedia VT8500 Realtime Clock Controller
2
-
-----------------------------------------------------
3
-
4
-
Required properties:
5
-
- compatible : "via,vt8500-rtc"
6
-
- reg : Should contain 1 register ranges(address and length)
7
-
- interrupts : alarm interrupt
8
-
9
-
Example:
10
-
11
-
rtc@d8100000 {
12
-
compatible = "via,vt8500-rtc";
13
-
reg = <0xd8100000 0x10000>;
14
-
interrupts = <48>;
15
-
};
-1
MAINTAINERS
-1
MAINTAINERS
+10
drivers/rtc/Kconfig
+10
drivers/rtc/Kconfig
···
664
664
This driver can also be built as a module. If so, the module
665
665
will be called rtc-rx8010.
666
666
667
+
config RTC_DRV_RX8111
668
+
tristate "Epson RX8111"
669
+
select REGMAP_I2C
670
+
depends on I2C
671
+
help
672
+
If you say yes here you will get support for the Epson RX8111 RTC.
673
+
674
+
This driver can also be built as a module. If so, the module will be
675
+
called rtc-rx8111.
676
+
667
677
config RTC_DRV_RX8581
668
678
tristate "Epson RX-8571/RX-8581"
669
679
select REGMAP_I2C
+1
drivers/rtc/Makefile
+1
drivers/rtc/Makefile
···
154
154
obj-$(CONFIG_RTC_DRV_RX6110) += rtc-rx6110.o
155
155
obj-$(CONFIG_RTC_DRV_RX8010) += rtc-rx8010.o
156
156
obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o
157
+
obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o
157
158
obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o
158
159
obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o
159
160
obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o
+26
-7
drivers/rtc/lib_test.c
+26
-7
drivers/rtc/lib_test.c
···
27
27
}
28
28
29
29
/*
30
-
* Checks every day in a 160000 years interval starting on 1970-01-01
30
+
* Check every day in specified number of years interval starting on 1970-01-01
31
31
* against the expected result.
32
32
*/
33
-
static void rtc_time64_to_tm_test_date_range(struct kunit *test)
33
+
static void rtc_time64_to_tm_test_date_range(struct kunit *test, int years)
34
34
{
35
35
/*
36
-
* 160000 years = (160000 / 400) * 400 years
37
-
* = (160000 / 400) * 146097 days
38
-
* = (160000 / 400) * 146097 * 86400 seconds
36
+
* years = (years / 400) * 400 years
37
+
* = (years / 400) * 146097 days
38
+
* = (years / 400) * 146097 * 86400 seconds
39
39
*/
40
-
time64_t total_secs = ((time64_t) 160000) / 400 * 146097 * 86400;
40
+
time64_t total_secs = ((time64_t)years) / 400 * 146097 * 86400;
41
41
42
42
int year = 1970;
43
43
int month = 1;
···
66
66
}
67
67
}
68
68
69
+
/*
70
+
* Checks every day in a 160000 years interval starting on 1970-01-01
71
+
* against the expected result.
72
+
*/
73
+
static void rtc_time64_to_tm_test_date_range_160000(struct kunit *test)
74
+
{
75
+
rtc_time64_to_tm_test_date_range(test, 160000);
76
+
}
77
+
78
+
/*
79
+
* Checks every day in a 1000 years interval starting on 1970-01-01
80
+
* against the expected result.
81
+
*/
82
+
static void rtc_time64_to_tm_test_date_range_1000(struct kunit *test)
83
+
{
84
+
rtc_time64_to_tm_test_date_range(test, 1000);
85
+
}
86
+
69
87
static struct kunit_case rtc_lib_test_cases[] = {
70
-
KUNIT_CASE(rtc_time64_to_tm_test_date_range),
88
+
KUNIT_CASE(rtc_time64_to_tm_test_date_range_1000),
89
+
KUNIT_CASE_SLOW(rtc_time64_to_tm_test_date_range_160000),
71
90
{}
72
91
};
73
92
+8
-1
drivers/rtc/rtc-cros-ec.c
+8
-1
drivers/rtc/rtc-cros-ec.c
···
5
5
// Author: Stephen Barber <smbarber@chromium.org>
6
6
7
7
#include <linux/kernel.h>
8
+
#include <linux/mod_devicetable.h>
8
9
#include <linux/module.h>
9
10
#include <linux/platform_data/cros_ec_commands.h>
10
11
#include <linux/platform_data/cros_ec_proto.h>
···
393
392
dev_err(dev, "failed to unregister notifier\n");
394
393
}
395
394
395
+
static const struct platform_device_id cros_ec_rtc_id[] = {
396
+
{ DRV_NAME, 0 },
397
+
{}
398
+
};
399
+
MODULE_DEVICE_TABLE(platform, cros_ec_rtc_id);
400
+
396
401
static struct platform_driver cros_ec_rtc_driver = {
397
402
.probe = cros_ec_rtc_probe,
398
403
.remove_new = cros_ec_rtc_remove,
···
406
399
.name = DRV_NAME,
407
400
.pm = &cros_ec_rtc_pm_ops,
408
401
},
402
+
.id_table = cros_ec_rtc_id,
409
403
};
410
404
411
405
module_platform_driver(cros_ec_rtc_driver);
···
414
406
MODULE_DESCRIPTION("RTC driver for Chrome OS ECs");
415
407
MODULE_AUTHOR("Stephen Barber <smbarber@chromium.org>");
416
408
MODULE_LICENSE("GPL v2");
417
-
MODULE_ALIAS("platform:" DRV_NAME);
-1
drivers/rtc/rtc-mcp795.c
-1
drivers/rtc/rtc-mcp795.c
+9
-6
drivers/rtc/rtc-nct3018y.c
+9
-6
drivers/rtc/rtc-nct3018y.c
···
517
517
if (nct3018y->part_num < 0) {
518
518
dev_dbg(&client->dev, "Failed to read NCT3018Y_REG_PART.\n");
519
519
return nct3018y->part_num;
520
-
} else if (nct3018y->part_num == NCT3018Y_REG_PART_NCT3018Y) {
521
-
flags = NCT3018Y_BIT_HF;
522
-
err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_CTRL, flags);
523
-
if (err < 0) {
524
-
dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_CTRL.\n");
525
-
return err;
520
+
} else {
521
+
nct3018y->part_num &= 0x03; /* Part number is corresponding to bit 0 and 1 */
522
+
if (nct3018y->part_num == NCT3018Y_REG_PART_NCT3018Y) {
523
+
flags = NCT3018Y_BIT_HF;
524
+
err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_CTRL, flags);
525
+
if (err < 0) {
526
+
dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_CTRL.\n");
527
+
return err;
528
+
}
526
529
}
527
530
}
528
531
+7
-2
drivers/rtc/rtc-pcf8563.c
+7
-2
drivers/rtc/rtc-pcf8563.c
···
527
527
528
528
i2c_set_clientdata(client, pcf8563);
529
529
pcf8563->client = client;
530
-
device_set_wakeup_capable(&client->dev, 1);
531
530
532
531
/* Set timer to lowest frequency to save power (ref Haoyu datasheet) */
533
532
buf = PCF8563_TMRC_1_60;
···
552
553
/* the pcf8563 alarm only supports a minute accuracy */
553
554
set_bit(RTC_FEATURE_ALARM_RES_MINUTE, pcf8563->rtc->features);
554
555
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf8563->rtc->features);
556
+
clear_bit(RTC_FEATURE_ALARM, pcf8563->rtc->features);
555
557
pcf8563->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
556
558
pcf8563->rtc->range_max = RTC_TIMESTAMP_END_2099;
557
559
pcf8563->rtc->set_start_time = true;
···
573
573
return err;
574
574
}
575
575
} else {
576
-
clear_bit(RTC_FEATURE_ALARM, pcf8563->rtc->features);
576
+
client->irq = 0;
577
+
}
578
+
579
+
if (client->irq > 0 || device_property_read_bool(&client->dev, "wakeup-source")) {
580
+
device_init_wakeup(&client->dev, true);
581
+
set_bit(RTC_FEATURE_ALARM, pcf8563->rtc->features);
577
582
}
578
583
579
584
err = devm_rtc_register_device(pcf8563->rtc);
+2
-2
drivers/rtc/rtc-rx6110.c
+2
-2
drivers/rtc/rtc-rx6110.c
···
330
330
}
331
331
332
332
#if IS_ENABLED(CONFIG_SPI_MASTER)
333
-
static struct regmap_config regmap_spi_config = {
333
+
static const struct regmap_config regmap_spi_config = {
334
334
.reg_bits = 8,
335
335
.val_bits = 8,
336
336
.max_register = RX6110_REG_IRQ,
···
410
410
#endif /* CONFIG_SPI_MASTER */
411
411
412
412
#if IS_ENABLED(CONFIG_I2C)
413
-
static struct regmap_config regmap_i2c_config = {
413
+
static const struct regmap_config regmap_i2c_config = {
414
414
.reg_bits = 8,
415
415
.val_bits = 8,
416
416
.max_register = RX6110_REG_IRQ,
+368
drivers/rtc/rtc-rx8111.c
+368
drivers/rtc/rtc-rx8111.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Driver for Epson RX8111 RTC.
4
+
*
5
+
* Copyright (C) 2023 Axis Communications AB
6
+
*/
7
+
8
+
#include <linux/bcd.h>
9
+
#include <linux/bitfield.h>
10
+
#include <linux/i2c.h>
11
+
#include <linux/module.h>
12
+
#include <linux/regmap.h>
13
+
14
+
#include <linux/rtc.h>
15
+
16
+
#define RX8111_REG_SEC 0x10 /* Second counter. */
17
+
#define RX8111_REG_MIN 0x11 /* Minute counter */
18
+
#define RX8111_REG_HOUR 0x12 /* Hour counter. */
19
+
#define RX8111_REG_WEEK 0x13 /* Week day counter. */
20
+
#define RX8111_REG_DAY 0x14 /* Month day counter. */
21
+
#define RX8111_REG_MONTH 0x15 /* Month counter. */
22
+
#define RX8111_REG_YEAR 0x16 /* Year counter. */
23
+
24
+
#define RX8111_REG_ALARM_MIN 0x17 /* Alarm minute. */
25
+
#define RX8111_REG_ALARM_HOUR 0x18 /* Alarm hour. */
26
+
#define RX8111_REG_ALARM_WEEK_DAY 0x19 /* Alarm week or month day. */
27
+
28
+
#define RX8111_REG_TIMER_COUNTER0 0x1a /* Timer counter LSB. */
29
+
#define RX8111_REG_TIMER_COUNTER1 0x1b /* Timer counter. */
30
+
#define RX8111_REG_TIMER_COUNTER2 0x1c /* Timer counter MSB. */
31
+
32
+
#define RX8111_REG_EXT 0x1d /* Extension register. */
33
+
#define RX8111_REG_FLAG 0x1e /* Flag register. */
34
+
#define RX8111_REG_CTRL 0x1f /* Control register. */
35
+
36
+
#define RX8111_REG_TS_1_1000_SEC 0x20 /* Timestamp 256 or 512 Hz . */
37
+
#define RX8111_REG_TS_1_100_SEC 0x21 /* Timestamp 1 - 128 Hz. */
38
+
#define RX8111_REG_TS_SEC 0x22 /* Timestamp second. */
39
+
#define RX8111_REG_TS_MIN 0x23 /* Timestamp minute. */
40
+
#define RX8111_REG_TS_HOUR 0x24 /* Timestamp hour. */
41
+
#define RX8111_REG_TS_WEEK 0x25 /* Timestamp week day. */
42
+
#define RX8111_REG_TS_DAY 0x26 /* Timestamp month day. */
43
+
#define RX8111_REG_TS_MONTH 0x27 /* Timestamp month. */
44
+
#define RX8111_REG_TS_YEAR 0x28 /* Timestamp year. */
45
+
#define RX8111_REG_TS_STATUS 0x29 /* Timestamp status. */
46
+
47
+
#define RX8111_REG_EVIN_SETTING 0x2b /* Timestamp trigger setting. */
48
+
#define RX8111_REG_ALARM_SEC 0x2c /* Alarm second. */
49
+
#define RX8111_REG_TIMER_CTRL 0x2d /* Timer control. */
50
+
#define RX8111_REG_TS_CTRL0 0x2e /* Timestamp control 0. */
51
+
#define RX8111_REG_CMD_TRIGGER 0x2f /* Timestamp trigger. */
52
+
#define RX8111_REG_PWR_SWITCH_CTRL 0x32 /* Power switch control. */
53
+
#define RX8111_REG_STATUS_MON 0x33 /* Status monitor. */
54
+
#define RX8111_REG_TS_CTRL1 0x34 /* Timestamp control 1. */
55
+
#define RX8111_REG_TS_CTRL2 0x35 /* Timestamp control 2. */
56
+
#define RX8111_REG_TS_CTRL3 0x36 /* Timestamp control 3. */
57
+
58
+
#define RX8111_FLAG_XST_BIT BIT(0)
59
+
#define RX8111_FLAG_VLF_BIT BIT(1)
60
+
61
+
#define RX8111_TIME_BUF_SZ (RX8111_REG_YEAR - RX8111_REG_SEC + 1)
62
+
63
+
enum rx8111_regfield {
64
+
/* RX8111_REG_EXT. */
65
+
RX8111_REGF_TSEL0,
66
+
RX8111_REGF_TSEL1,
67
+
RX8111_REGF_ETS,
68
+
RX8111_REGF_WADA,
69
+
RX8111_REGF_TE,
70
+
RX8111_REGF_USEL,
71
+
RX8111_REGF_FSEL0,
72
+
RX8111_REGF_FSEL1,
73
+
74
+
/* RX8111_REG_FLAG. */
75
+
RX8111_REGF_XST,
76
+
RX8111_REGF_VLF,
77
+
RX8111_REGF_EVF,
78
+
RX8111_REGF_AF,
79
+
RX8111_REGF_TF,
80
+
RX8111_REGF_UF,
81
+
RX8111_REGF_POR,
82
+
83
+
/* RX8111_REG_CTRL. */
84
+
RX8111_REGF_STOP,
85
+
RX8111_REGF_EIE,
86
+
RX8111_REGF_AIE,
87
+
RX8111_REGF_TIE,
88
+
RX8111_REGF_UIE,
89
+
90
+
/* RX8111_REG_PWR_SWITCH_CTRL. */
91
+
RX8111_REGF_SMPT0,
92
+
RX8111_REGF_SMPT1,
93
+
RX8111_REGF_SWSEL0,
94
+
RX8111_REGF_SWSEL1,
95
+
RX8111_REGF_INIEN,
96
+
RX8111_REGF_CHGEN,
97
+
98
+
/* RX8111_REG_STATUS_MON. */
99
+
RX8111_REGF_VLOW,
100
+
101
+
/* Sentinel value. */
102
+
RX8111_REGF_MAX
103
+
};
104
+
105
+
static const struct reg_field rx8111_regfields[] = {
106
+
[RX8111_REGF_TSEL0] = REG_FIELD(RX8111_REG_EXT, 0, 0),
107
+
[RX8111_REGF_TSEL1] = REG_FIELD(RX8111_REG_EXT, 1, 1),
108
+
[RX8111_REGF_ETS] = REG_FIELD(RX8111_REG_EXT, 2, 2),
109
+
[RX8111_REGF_WADA] = REG_FIELD(RX8111_REG_EXT, 3, 3),
110
+
[RX8111_REGF_TE] = REG_FIELD(RX8111_REG_EXT, 4, 4),
111
+
[RX8111_REGF_USEL] = REG_FIELD(RX8111_REG_EXT, 5, 5),
112
+
[RX8111_REGF_FSEL0] = REG_FIELD(RX8111_REG_EXT, 6, 6),
113
+
[RX8111_REGF_FSEL1] = REG_FIELD(RX8111_REG_EXT, 7, 7),
114
+
115
+
[RX8111_REGF_XST] = REG_FIELD(RX8111_REG_FLAG, 0, 0),
116
+
[RX8111_REGF_VLF] = REG_FIELD(RX8111_REG_FLAG, 1, 1),
117
+
[RX8111_REGF_EVF] = REG_FIELD(RX8111_REG_FLAG, 2, 2),
118
+
[RX8111_REGF_AF] = REG_FIELD(RX8111_REG_FLAG, 3, 3),
119
+
[RX8111_REGF_TF] = REG_FIELD(RX8111_REG_FLAG, 4, 4),
120
+
[RX8111_REGF_UF] = REG_FIELD(RX8111_REG_FLAG, 5, 5),
121
+
[RX8111_REGF_POR] = REG_FIELD(RX8111_REG_FLAG, 7, 7),
122
+
123
+
[RX8111_REGF_STOP] = REG_FIELD(RX8111_REG_CTRL, 0, 0),
124
+
[RX8111_REGF_EIE] = REG_FIELD(RX8111_REG_CTRL, 2, 2),
125
+
[RX8111_REGF_AIE] = REG_FIELD(RX8111_REG_CTRL, 3, 3),
126
+
[RX8111_REGF_TIE] = REG_FIELD(RX8111_REG_CTRL, 4, 4),
127
+
[RX8111_REGF_UIE] = REG_FIELD(RX8111_REG_CTRL, 5, 5),
128
+
129
+
[RX8111_REGF_SMPT0] = REG_FIELD(RX8111_REG_PWR_SWITCH_CTRL, 0, 0),
130
+
[RX8111_REGF_SMPT1] = REG_FIELD(RX8111_REG_PWR_SWITCH_CTRL, 1, 1),
131
+
[RX8111_REGF_SWSEL0] = REG_FIELD(RX8111_REG_PWR_SWITCH_CTRL, 2, 2),
132
+
[RX8111_REGF_SWSEL1] = REG_FIELD(RX8111_REG_PWR_SWITCH_CTRL, 3, 3),
133
+
[RX8111_REGF_INIEN] = REG_FIELD(RX8111_REG_PWR_SWITCH_CTRL, 6, 6),
134
+
[RX8111_REGF_CHGEN] = REG_FIELD(RX8111_REG_PWR_SWITCH_CTRL, 7, 7),
135
+
136
+
[RX8111_REGF_VLOW] = REG_FIELD(RX8111_REG_STATUS_MON, 1, 1),
137
+
};
138
+
139
+
static const struct regmap_config rx8111_regmap_config = {
140
+
.reg_bits = 8,
141
+
.val_bits = 8,
142
+
.max_register = RX8111_REG_TS_CTRL3,
143
+
};
144
+
145
+
struct rx8111_data {
146
+
struct regmap *regmap;
147
+
struct regmap_field *regfields[RX8111_REGF_MAX];
148
+
struct device *dev;
149
+
struct rtc_device *rtc;
150
+
};
151
+
152
+
static int rx8111_read_vl_flag(struct rx8111_data *data, unsigned int *vlval)
153
+
{
154
+
int ret;
155
+
156
+
ret = regmap_field_read(data->regfields[RX8111_REGF_VLF], vlval);
157
+
if (ret)
158
+
dev_dbg(data->dev, "Could not read VL flag (%d)", ret);
159
+
160
+
return ret;
161
+
}
162
+
163
+
static int rx8111_read_time(struct device *dev, struct rtc_time *tm)
164
+
{
165
+
struct rx8111_data *data = dev_get_drvdata(dev);
166
+
u8 buf[RX8111_TIME_BUF_SZ];
167
+
unsigned int regval;
168
+
int ret;
169
+
170
+
/* Check status. */
171
+
ret = regmap_read(data->regmap, RX8111_REG_FLAG, ®val);
172
+
if (ret) {
173
+
dev_dbg(data->dev, "Could not read flag register (%d)\n", ret);
174
+
return ret;
175
+
}
176
+
177
+
if (FIELD_GET(RX8111_FLAG_XST_BIT, regval)) {
178
+
dev_dbg(data->dev,
179
+
"Crystal oscillation stopped, time is not reliable\n");
180
+
return -EINVAL;
181
+
}
182
+
183
+
if (FIELD_GET(RX8111_FLAG_VLF_BIT, regval)) {
184
+
dev_dbg(data->dev,
185
+
"Low voltage detected, time is not reliable\n");
186
+
return -EINVAL;
187
+
}
188
+
189
+
ret = regmap_field_read(data->regfields[RX8111_REGF_STOP], ®val);
190
+
if (ret) {
191
+
dev_dbg(data->dev, "Could not read clock status (%d)\n", ret);
192
+
return ret;
193
+
}
194
+
195
+
if (regval) {
196
+
dev_dbg(data->dev, "Clock stopped, time is not reliable\n");
197
+
return -EINVAL;
198
+
}
199
+
200
+
/* Read time. */
201
+
ret = regmap_bulk_read(data->regmap, RX8111_REG_SEC, buf,
202
+
ARRAY_SIZE(buf));
203
+
if (ret) {
204
+
dev_dbg(data->dev, "Could not bulk read time (%d)\n", ret);
205
+
return ret;
206
+
}
207
+
208
+
tm->tm_sec = bcd2bin(buf[0]);
209
+
tm->tm_min = bcd2bin(buf[1]);
210
+
tm->tm_hour = bcd2bin(buf[2]);
211
+
tm->tm_wday = ffs(buf[3]) - 1;
212
+
tm->tm_mday = bcd2bin(buf[4]);
213
+
tm->tm_mon = bcd2bin(buf[5]) - 1;
214
+
tm->tm_year = bcd2bin(buf[6]) + 100;
215
+
216
+
return 0;
217
+
}
218
+
219
+
static int rx8111_set_time(struct device *dev, struct rtc_time *tm)
220
+
{
221
+
struct rx8111_data *data = dev_get_drvdata(dev);
222
+
u8 buf[RX8111_TIME_BUF_SZ];
223
+
int ret;
224
+
225
+
buf[0] = bin2bcd(tm->tm_sec);
226
+
buf[1] = bin2bcd(tm->tm_min);
227
+
buf[2] = bin2bcd(tm->tm_hour);
228
+
buf[3] = BIT(tm->tm_wday);
229
+
buf[4] = bin2bcd(tm->tm_mday);
230
+
buf[5] = bin2bcd(tm->tm_mon + 1);
231
+
buf[6] = bin2bcd(tm->tm_year - 100);
232
+
233
+
ret = regmap_clear_bits(data->regmap, RX8111_REG_FLAG,
234
+
RX8111_FLAG_XST_BIT | RX8111_FLAG_VLF_BIT);
235
+
if (ret)
236
+
return ret;
237
+
238
+
/* Stop the clock. */
239
+
ret = regmap_field_write(data->regfields[RX8111_REGF_STOP], 1);
240
+
if (ret) {
241
+
dev_dbg(data->dev, "Could not stop the clock (%d)\n", ret);
242
+
return ret;
243
+
}
244
+
245
+
/* Set the time. */
246
+
ret = regmap_bulk_write(data->regmap, RX8111_REG_SEC, buf,
247
+
ARRAY_SIZE(buf));
248
+
if (ret) {
249
+
dev_dbg(data->dev, "Could not bulk write time (%d)\n", ret);
250
+
251
+
/*
252
+
* We don't bother with trying to start the clock again. We
253
+
* check for this in rx8111_read_time() (and thus force user to
254
+
* call rx8111_set_time() to try again).
255
+
*/
256
+
return ret;
257
+
}
258
+
259
+
/* Start the clock. */
260
+
ret = regmap_field_write(data->regfields[RX8111_REGF_STOP], 0);
261
+
if (ret) {
262
+
dev_dbg(data->dev, "Could not start the clock (%d)\n", ret);
263
+
return ret;
264
+
}
265
+
266
+
return 0;
267
+
}
268
+
269
+
static int rx8111_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
270
+
{
271
+
struct rx8111_data *data = dev_get_drvdata(dev);
272
+
unsigned int regval;
273
+
unsigned int vlval;
274
+
int ret;
275
+
276
+
switch (cmd) {
277
+
case RTC_VL_READ:
278
+
ret = rx8111_read_vl_flag(data, ®val);
279
+
if (ret)
280
+
return ret;
281
+
282
+
vlval = regval ? RTC_VL_DATA_INVALID : 0;
283
+
284
+
ret = regmap_field_read(data->regfields[RX8111_REGF_VLOW],
285
+
®val);
286
+
if (ret)
287
+
return ret;
288
+
289
+
vlval |= regval ? RTC_VL_BACKUP_LOW : 0;
290
+
291
+
return put_user(vlval, (typeof(vlval) __user *)arg);
292
+
default:
293
+
return -ENOIOCTLCMD;
294
+
}
295
+
}
296
+
297
+
static const struct rtc_class_ops rx8111_rtc_ops = {
298
+
.read_time = rx8111_read_time,
299
+
.set_time = rx8111_set_time,
300
+
.ioctl = rx8111_ioctl,
301
+
};
302
+
303
+
static int rx8111_probe(struct i2c_client *client)
304
+
{
305
+
struct rx8111_data *data;
306
+
struct rtc_device *rtc;
307
+
size_t i;
308
+
309
+
data = devm_kmalloc(&client->dev, sizeof(*data), GFP_KERNEL);
310
+
if (!data) {
311
+
dev_dbg(&client->dev, "Could not allocate device data\n");
312
+
return -ENOMEM;
313
+
}
314
+
315
+
data->dev = &client->dev;
316
+
dev_set_drvdata(data->dev, data);
317
+
318
+
data->regmap = devm_regmap_init_i2c(client, &rx8111_regmap_config);
319
+
if (IS_ERR(data->regmap)) {
320
+
dev_dbg(data->dev, "Could not initialize regmap\n");
321
+
return PTR_ERR(data->regmap);
322
+
}
323
+
324
+
for (i = 0; i < RX8111_REGF_MAX; ++i) {
325
+
data->regfields[i] = devm_regmap_field_alloc(
326
+
data->dev, data->regmap, rx8111_regfields[i]);
327
+
if (IS_ERR(data->regfields[i])) {
328
+
dev_dbg(data->dev,
329
+
"Could not allocate register field %zu\n", i);
330
+
return PTR_ERR(data->regfields[i]);
331
+
}
332
+
}
333
+
334
+
rtc = devm_rtc_allocate_device(data->dev);
335
+
if (IS_ERR(rtc)) {
336
+
dev_dbg(data->dev, "Could not allocate rtc device\n");
337
+
return PTR_ERR(rtc);
338
+
}
339
+
340
+
rtc->ops = &rx8111_rtc_ops;
341
+
rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
342
+
rtc->range_max = RTC_TIMESTAMP_END_2099;
343
+
344
+
clear_bit(RTC_FEATURE_ALARM, rtc->features);
345
+
346
+
return devm_rtc_register_device(rtc);
347
+
}
348
+
349
+
static const struct of_device_id rx8111_of_match[] = {
350
+
{
351
+
.compatible = "epson,rx8111",
352
+
},
353
+
{}
354
+
};
355
+
MODULE_DEVICE_TABLE(of, rx8111_of_match);
356
+
357
+
static struct i2c_driver rx8111_driver = {
358
+
.driver = {
359
+
.name = "rtc-rx8111",
360
+
.of_match_table = rx8111_of_match,
361
+
},
362
+
.probe = rx8111_probe,
363
+
};
364
+
module_i2c_driver(rx8111_driver);
365
+
366
+
MODULE_AUTHOR("Waqar Hameed <waqar.hameed@axis.com>");
367
+
MODULE_DESCRIPTION("Epson RX8111 RTC driver");
368
+
MODULE_LICENSE("GPL");