tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: Add smuio v15_0_8 ip headers v4

Add header files for smuio v15_0_8 register offsets
and shift masks
v2: Update smuio v15_0_8 ip headers
v3: Update smuio v15_0_8 ip headers
v4: Clean up registers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Hawking Zhang and committed by
Alex Deucher 550c6f5b 5287e7ef

+1625
+512
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_8_offset.h
··· 1 + /* 2 + * Copyright 2025 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _smuio_15_0_8_OFFSET_HEADER 24 + #define _smuio_15_0_8_OFFSET_HEADER 25 + 26 + 27 + 28 + // addressBlock: smuio_smuio_tsc_SmuSmuioDec 29 + // base address: 0x5a8a0 30 + #define regPWROK_REFCLK_GAP_CYCLES 0x0028 31 + #define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1 32 + #define regGOLDEN_TSC_INCREMENT_UPPER 0x002b 33 + #define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1 34 + #define regGOLDEN_TSC_INCREMENT_LOWER 0x002c 35 + #define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1 36 + #define regGOLDEN_TSC_COUNT_UPPER 0x0030 37 + #define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1 38 + #define regGOLDEN_TSC_COUNT_LOWER 0x0031 39 + #define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1 40 + #define regSOC_GOLDEN_TSC_SHADOW_UPPER 0x0032 41 + #define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 42 + #define regSOC_GOLDEN_TSC_SHADOW_LOWER 0x0033 43 + #define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 44 + #define regSOC_GAP_PWROK 0x0034 45 + #define regSOC_GAP_PWROK_BASE_IDX 1 46 + 47 + 48 + // addressBlock: smuio_smuio_swtimer_SmuSmuioDec 49 + // base address: 0x5aca8 50 + #define regPWR_VIRT_RESET_REQ 0x012a 51 + #define regPWR_VIRT_RESET_REQ_BASE_IDX 1 52 + #define regPWR_DISP_TIMER_CONTROL 0x012b 53 + #define regPWR_DISP_TIMER_CONTROL_BASE_IDX 1 54 + #define regPWR_DISP_TIMER_DEBUG 0x012c 55 + #define regPWR_DISP_TIMER_DEBUG_BASE_IDX 1 56 + #define regPWR_DISP_TIMER2_CONTROL 0x012d 57 + #define regPWR_DISP_TIMER2_CONTROL_BASE_IDX 1 58 + #define regPWR_DISP_TIMER2_DEBUG 0x012e 59 + #define regPWR_DISP_TIMER2_DEBUG_BASE_IDX 1 60 + #define regPWR_DISP_TIMER_GLOBAL_CONTROL 0x012f 61 + #define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1 62 + #define regPWR_IH_CONTROL 0x0130 63 + #define regPWR_IH_CONTROL_BASE_IDX 1 64 + 65 + 66 + // addressBlock: smuio_smuio_misc_SmuSmuioDec 67 + // base address: 0x5a000 68 + #define regSMUIO_MCM_CONFIG 0x0023 69 + #define regSMUIO_MCM_CONFIG_BASE_IDX 0 70 + #define regIP_DISCOVERY_VERSION 0x0000 71 + #define regIP_DISCOVERY_VERSION_BASE_IDX 1 72 + #define regSCRATCH_REGISTER0 0x01c9 73 + #define regSCRATCH_REGISTER0_BASE_IDX 1 74 + #define regSCRATCH_REGISTER1 0x01ca 75 + #define regSCRATCH_REGISTER1_BASE_IDX 1 76 + #define regSCRATCH_REGISTER2 0x01cb 77 + #define regSCRATCH_REGISTER2_BASE_IDX 1 78 + #define regSCRATCH_REGISTER3 0x01cc 79 + #define regSCRATCH_REGISTER3_BASE_IDX 1 80 + #define regSCRATCH_REGISTER4 0x01cd 81 + #define regSCRATCH_REGISTER4_BASE_IDX 1 82 + #define regSCRATCH_REGISTER5 0x01ce 83 + #define regSCRATCH_REGISTER5_BASE_IDX 1 84 + #define regSCRATCH_REGISTER6 0x01cf 85 + #define regSCRATCH_REGISTER6_BASE_IDX 1 86 + #define regSCRATCH_REGISTER7 0x01d0 87 + #define regSCRATCH_REGISTER7_BASE_IDX 1 88 + 89 + 90 + // addressBlock: smuio_smuio_i2c_SmuSmuioDec 91 + // base address: 0x5a100 92 + #define regCKSVII2C_IC_CON 0x0040 93 + #define regCKSVII2C_IC_CON_BASE_IDX 0 94 + #define regCKSVII2C_IC_TAR 0x0041 95 + #define regCKSVII2C_IC_TAR_BASE_IDX 0 96 + #define regCKSVII2C_IC_SAR 0x0042 97 + #define regCKSVII2C_IC_SAR_BASE_IDX 0 98 + #define regCKSVII2C_IC_HS_MADDR 0x0043 99 + #define regCKSVII2C_IC_HS_MADDR_BASE_IDX 0 100 + #define regCKSVII2C_IC_DATA_CMD 0x0044 101 + #define regCKSVII2C_IC_DATA_CMD_BASE_IDX 0 102 + #define regCKSVII2C_IC_SS_SCL_HCNT 0x0045 103 + #define regCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX 0 104 + #define regCKSVII2C_IC_SS_SCL_LCNT 0x0046 105 + #define regCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX 0 106 + #define regCKSVII2C_IC_FS_SCL_HCNT 0x0047 107 + #define regCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX 0 108 + #define regCKSVII2C_IC_FS_SCL_LCNT 0x0048 109 + #define regCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX 0 110 + #define regCKSVII2C_IC_HS_SCL_HCNT 0x0049 111 + #define regCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX 0 112 + #define regCKSVII2C_IC_HS_SCL_LCNT 0x004a 113 + #define regCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX 0 114 + #define regCKSVII2C_IC_INTR_STAT 0x004b 115 + #define regCKSVII2C_IC_INTR_STAT_BASE_IDX 0 116 + #define regCKSVII2C_IC_INTR_MASK 0x004c 117 + #define regCKSVII2C_IC_INTR_MASK_BASE_IDX 0 118 + #define regCKSVII2C_IC_RAW_INTR_STAT 0x004d 119 + #define regCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX 0 120 + #define regCKSVII2C_IC_RX_TL 0x004e 121 + #define regCKSVII2C_IC_RX_TL_BASE_IDX 0 122 + #define regCKSVII2C_IC_TX_TL 0x004f 123 + #define regCKSVII2C_IC_TX_TL_BASE_IDX 0 124 + #define regCKSVII2C_IC_CLR_INTR 0x0050 125 + #define regCKSVII2C_IC_CLR_INTR_BASE_IDX 0 126 + #define regCKSVII2C_IC_CLR_RX_UNDER 0x0051 127 + #define regCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX 0 128 + #define regCKSVII2C_IC_CLR_RX_OVER 0x0052 129 + #define regCKSVII2C_IC_CLR_RX_OVER_BASE_IDX 0 130 + #define regCKSVII2C_IC_CLR_TX_OVER 0x0053 131 + #define regCKSVII2C_IC_CLR_TX_OVER_BASE_IDX 0 132 + #define regCKSVII2C_IC_CLR_RD_REQ 0x0054 133 + #define regCKSVII2C_IC_CLR_RD_REQ_BASE_IDX 0 134 + #define regCKSVII2C_IC_CLR_TX_ABRT 0x0055 135 + #define regCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX 0 136 + #define regCKSVII2C_IC_CLR_RX_DONE 0x0056 137 + #define regCKSVII2C_IC_CLR_RX_DONE_BASE_IDX 0 138 + #define regCKSVII2C_IC_CLR_ACTIVITY 0x0057 139 + #define regCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX 0 140 + #define regCKSVII2C_IC_CLR_STOP_DET 0x0058 141 + #define regCKSVII2C_IC_CLR_STOP_DET_BASE_IDX 0 142 + #define regCKSVII2C_IC_CLR_START_DET 0x0059 143 + #define regCKSVII2C_IC_CLR_START_DET_BASE_IDX 0 144 + #define regCKSVII2C_IC_CLR_GEN_CALL 0x005a 145 + #define regCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX 0 146 + #define regCKSVII2C_IC_ENABLE 0x005b 147 + #define regCKSVII2C_IC_ENABLE_BASE_IDX 0 148 + #define regCKSVII2C_IC_STATUS 0x005c 149 + #define regCKSVII2C_IC_STATUS_BASE_IDX 0 150 + #define regCKSVII2C_IC_TXFLR 0x005d 151 + #define regCKSVII2C_IC_TXFLR_BASE_IDX 0 152 + #define regCKSVII2C_IC_RXFLR 0x005e 153 + #define regCKSVII2C_IC_RXFLR_BASE_IDX 0 154 + #define regCKSVII2C_IC_SDA_HOLD 0x005f 155 + #define regCKSVII2C_IC_SDA_HOLD_BASE_IDX 0 156 + #define regCKSVII2C_IC_TX_ABRT_SOURCE 0x0060 157 + #define regCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX 0 158 + #define regCKSVII2C_IC_SLV_DATA_NACK_ONLY 0x0061 159 + #define regCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 160 + #define regCKSVII2C_IC_DMA_CR 0x0062 161 + #define regCKSVII2C_IC_DMA_CR_BASE_IDX 0 162 + #define regCKSVII2C_IC_DMA_TDLR 0x0063 163 + #define regCKSVII2C_IC_DMA_TDLR_BASE_IDX 0 164 + #define regCKSVII2C_IC_DMA_RDLR 0x0064 165 + #define regCKSVII2C_IC_DMA_RDLR_BASE_IDX 0 166 + #define regCKSVII2C_IC_SDA_SETUP 0x0065 167 + #define regCKSVII2C_IC_SDA_SETUP_BASE_IDX 0 168 + #define regCKSVII2C_IC_ACK_GENERAL_CALL 0x0066 169 + #define regCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX 0 170 + #define regCKSVII2C_IC_ENABLE_STATUS 0x0067 171 + #define regCKSVII2C_IC_ENABLE_STATUS_BASE_IDX 0 172 + #define regCKSVII2C_IC_FS_SPKLEN 0x0068 173 + #define regCKSVII2C_IC_FS_SPKLEN_BASE_IDX 0 174 + #define regCKSVII2C_IC_HS_SPKLEN 0x0069 175 + #define regCKSVII2C_IC_HS_SPKLEN_BASE_IDX 0 176 + #define regCKSVII2C_IC_CLR_RESTART_DET 0x006a 177 + #define regCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX 0 178 + #define regCKSVII2C_IC_COMP_PARAM_1 0x006d 179 + #define regCKSVII2C_IC_COMP_PARAM_1_BASE_IDX 0 180 + #define regCKSVII2C_IC_COMP_VERSION 0x006e 181 + #define regCKSVII2C_IC_COMP_VERSION_BASE_IDX 0 182 + #define regCKSVII2C_IC_COMP_TYPE 0x006f 183 + #define regCKSVII2C_IC_COMP_TYPE_BASE_IDX 0 184 + #define regCKSVII2C1_IC_CON 0x0080 185 + #define regCKSVII2C1_IC_CON_BASE_IDX 0 186 + #define regCKSVII2C1_IC_TAR 0x0081 187 + #define regCKSVII2C1_IC_TAR_BASE_IDX 0 188 + #define regCKSVII2C1_IC_SAR 0x0082 189 + #define regCKSVII2C1_IC_SAR_BASE_IDX 0 190 + #define regCKSVII2C1_IC_HS_MADDR 0x0083 191 + #define regCKSVII2C1_IC_HS_MADDR_BASE_IDX 0 192 + #define regCKSVII2C1_IC_DATA_CMD 0x0084 193 + #define regCKSVII2C1_IC_DATA_CMD_BASE_IDX 0 194 + #define regCKSVII2C1_IC_SS_SCL_HCNT 0x0085 195 + #define regCKSVII2C1_IC_SS_SCL_HCNT_BASE_IDX 0 196 + #define regCKSVII2C1_IC_SS_SCL_LCNT 0x0086 197 + #define regCKSVII2C1_IC_SS_SCL_LCNT_BASE_IDX 0 198 + #define regCKSVII2C1_IC_FS_SCL_HCNT 0x0087 199 + #define regCKSVII2C1_IC_FS_SCL_HCNT_BASE_IDX 0 200 + #define regCKSVII2C1_IC_FS_SCL_LCNT 0x0088 201 + #define regCKSVII2C1_IC_FS_SCL_LCNT_BASE_IDX 0 202 + #define regCKSVII2C1_IC_HS_SCL_HCNT 0x0089 203 + #define regCKSVII2C1_IC_HS_SCL_HCNT_BASE_IDX 0 204 + #define regCKSVII2C1_IC_HS_SCL_LCNT 0x008a 205 + #define regCKSVII2C1_IC_HS_SCL_LCNT_BASE_IDX 0 206 + #define regCKSVII2C1_IC_INTR_STAT 0x008b 207 + #define regCKSVII2C1_IC_INTR_STAT_BASE_IDX 0 208 + #define regCKSVII2C1_IC_INTR_MASK 0x008c 209 + #define regCKSVII2C1_IC_INTR_MASK_BASE_IDX 0 210 + #define regCKSVII2C1_IC_RAW_INTR_STAT 0x008d 211 + #define regCKSVII2C1_IC_RAW_INTR_STAT_BASE_IDX 0 212 + #define regCKSVII2C1_IC_RX_TL 0x008e 213 + #define regCKSVII2C1_IC_RX_TL_BASE_IDX 0 214 + #define regCKSVII2C1_IC_TX_TL 0x008f 215 + #define regCKSVII2C1_IC_TX_TL_BASE_IDX 0 216 + #define regCKSVII2C1_IC_CLR_INTR 0x0090 217 + #define regCKSVII2C1_IC_CLR_INTR_BASE_IDX 0 218 + #define regCKSVII2C1_IC_CLR_RX_UNDER 0x0091 219 + #define regCKSVII2C1_IC_CLR_RX_UNDER_BASE_IDX 0 220 + #define regCKSVII2C1_IC_CLR_RX_OVER 0x0092 221 + #define regCKSVII2C1_IC_CLR_RX_OVER_BASE_IDX 0 222 + #define regCKSVII2C1_IC_CLR_TX_OVER 0x0093 223 + #define regCKSVII2C1_IC_CLR_TX_OVER_BASE_IDX 0 224 + #define regCKSVII2C1_IC_CLR_RD_REQ 0x0094 225 + #define regCKSVII2C1_IC_CLR_RD_REQ_BASE_IDX 0 226 + #define regCKSVII2C1_IC_CLR_TX_ABRT 0x0095 227 + #define regCKSVII2C1_IC_CLR_TX_ABRT_BASE_IDX 0 228 + #define regCKSVII2C1_IC_CLR_RX_DONE 0x0096 229 + #define regCKSVII2C1_IC_CLR_RX_DONE_BASE_IDX 0 230 + #define regCKSVII2C1_IC_CLR_ACTIVITY 0x0097 231 + #define regCKSVII2C1_IC_CLR_ACTIVITY_BASE_IDX 0 232 + #define regCKSVII2C1_IC_CLR_STOP_DET 0x0098 233 + #define regCKSVII2C1_IC_CLR_STOP_DET_BASE_IDX 0 234 + #define regCKSVII2C1_IC_CLR_START_DET 0x0099 235 + #define regCKSVII2C1_IC_CLR_START_DET_BASE_IDX 0 236 + #define regCKSVII2C1_IC_CLR_GEN_CALL 0x009a 237 + #define regCKSVII2C1_IC_CLR_GEN_CALL_BASE_IDX 0 238 + #define regCKSVII2C1_IC_ENABLE 0x009b 239 + #define regCKSVII2C1_IC_ENABLE_BASE_IDX 0 240 + #define regCKSVII2C1_IC_STATUS 0x009c 241 + #define regCKSVII2C1_IC_STATUS_BASE_IDX 0 242 + #define regCKSVII2C1_IC_TXFLR 0x009d 243 + #define regCKSVII2C1_IC_TXFLR_BASE_IDX 0 244 + #define regCKSVII2C1_IC_RXFLR 0x009e 245 + #define regCKSVII2C1_IC_RXFLR_BASE_IDX 0 246 + #define regCKSVII2C1_IC_SDA_HOLD 0x009f 247 + #define regCKSVII2C1_IC_SDA_HOLD_BASE_IDX 0 248 + #define regCKSVII2C1_IC_TX_ABRT_SOURCE 0x00a0 249 + #define regCKSVII2C1_IC_TX_ABRT_SOURCE_BASE_IDX 0 250 + #define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY 0x00a1 251 + #define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 252 + #define regCKSVII2C1_IC_DMA_CR 0x00a2 253 + #define regCKSVII2C1_IC_DMA_CR_BASE_IDX 0 254 + #define regCKSVII2C1_IC_DMA_TDLR 0x00a3 255 + #define regCKSVII2C1_IC_DMA_TDLR_BASE_IDX 0 256 + #define regCKSVII2C1_IC_DMA_RDLR 0x00a4 257 + #define regCKSVII2C1_IC_DMA_RDLR_BASE_IDX 0 258 + #define regCKSVII2C1_IC_SDA_SETUP 0x00a5 259 + #define regCKSVII2C1_IC_SDA_SETUP_BASE_IDX 0 260 + #define regCKSVII2C1_IC_ACK_GENERAL_CALL 0x00a6 261 + #define regCKSVII2C1_IC_ACK_GENERAL_CALL_BASE_IDX 0 262 + #define regCKSVII2C1_IC_ENABLE_STATUS 0x00a7 263 + #define regCKSVII2C1_IC_ENABLE_STATUS_BASE_IDX 0 264 + #define regCKSVII2C1_IC_FS_SPKLEN 0x00a8 265 + #define regCKSVII2C1_IC_FS_SPKLEN_BASE_IDX 0 266 + #define regCKSVII2C1_IC_HS_SPKLEN 0x00a9 267 + #define regCKSVII2C1_IC_HS_SPKLEN_BASE_IDX 0 268 + #define regCKSVII2C1_IC_CLR_RESTART_DET 0x00aa 269 + #define regCKSVII2C1_IC_CLR_RESTART_DET_BASE_IDX 0 270 + #define regCKSVII2C1_IC_COMP_PARAM_1 0x00ad 271 + #define regCKSVII2C1_IC_COMP_PARAM_1_BASE_IDX 0 272 + #define regCKSVII2C1_IC_COMP_VERSION 0x00ae 273 + #define regCKSVII2C1_IC_COMP_VERSION_BASE_IDX 0 274 + #define regCKSVII2C1_IC_COMP_TYPE 0x00af 275 + #define regCKSVII2C1_IC_COMP_TYPE_BASE_IDX 0 276 + #define regSMUIO_PWRMGT 0x018c 277 + #define regSMUIO_PWRMGT_BASE_IDX 0 278 + 279 + 280 + // addressBlock: smuio_smuio_rom_SmuSmuioDec 281 + // base address: 0x5a380 282 + #define regROM_CNTL 0x00e0 283 + #define regROM_CNTL_BASE_IDX 0 284 + #define regPAGE_MIRROR_CNTL 0x00e1 285 + #define regPAGE_MIRROR_CNTL_BASE_IDX 0 286 + #define regROM_STATUS 0x00e2 287 + #define regROM_STATUS_BASE_IDX 0 288 + #define regCGTT_ROM_CLK_CTRL0 0x00e3 289 + #define regCGTT_ROM_CLK_CTRL0_BASE_IDX 0 290 + #define regROM_INDEX 0x00e4 291 + #define regROM_INDEX_BASE_IDX 0 292 + #define regROM_DATA 0x00e5 293 + #define regROM_DATA_BASE_IDX 0 294 + #define regROM_START 0x00e6 295 + #define regROM_START_BASE_IDX 0 296 + #define regROM_SW_CNTL 0x00e8 297 + #define regROM_SW_CNTL_BASE_IDX 0 298 + #define regROM_SW_STATUS 0x00e9 299 + #define regROM_SW_STATUS_BASE_IDX 0 300 + #define regROM_SW_COMMAND 0x00ea 301 + #define regROM_SW_COMMAND_BASE_IDX 0 302 + #define regROM_SW_DATA_1 0x00ec 303 + #define regROM_SW_DATA_1_BASE_IDX 0 304 + #define regROM_SW_DATA_2 0x00ed 305 + #define regROM_SW_DATA_2_BASE_IDX 0 306 + #define regROM_SW_DATA_3 0x00ee 307 + #define regROM_SW_DATA_3_BASE_IDX 0 308 + #define regROM_SW_DATA_4 0x00ef 309 + #define regROM_SW_DATA_4_BASE_IDX 0 310 + #define regROM_SW_DATA_5 0x00f0 311 + #define regROM_SW_DATA_5_BASE_IDX 0 312 + #define regROM_SW_DATA_6 0x00f1 313 + #define regROM_SW_DATA_6_BASE_IDX 0 314 + #define regROM_SW_DATA_7 0x00f2 315 + #define regROM_SW_DATA_7_BASE_IDX 0 316 + #define regROM_SW_DATA_8 0x00f3 317 + #define regROM_SW_DATA_8_BASE_IDX 0 318 + #define regROM_SW_DATA_9 0x00f4 319 + #define regROM_SW_DATA_9_BASE_IDX 0 320 + #define regROM_SW_DATA_10 0x00f5 321 + #define regROM_SW_DATA_10_BASE_IDX 0 322 + #define regROM_SW_DATA_11 0x00f6 323 + #define regROM_SW_DATA_11_BASE_IDX 0 324 + #define regROM_SW_DATA_12 0x00f7 325 + #define regROM_SW_DATA_12_BASE_IDX 0 326 + #define regROM_SW_DATA_13 0x00f8 327 + #define regROM_SW_DATA_13_BASE_IDX 0 328 + #define regROM_SW_DATA_14 0x00f9 329 + #define regROM_SW_DATA_14_BASE_IDX 0 330 + #define regROM_SW_DATA_15 0x00fa 331 + #define regROM_SW_DATA_15_BASE_IDX 0 332 + #define regROM_SW_DATA_16 0x00fb 333 + #define regROM_SW_DATA_16_BASE_IDX 0 334 + #define regROM_SW_DATA_17 0x00fc 335 + #define regROM_SW_DATA_17_BASE_IDX 0 336 + #define regROM_SW_DATA_18 0x00fd 337 + #define regROM_SW_DATA_18_BASE_IDX 0 338 + #define regROM_SW_DATA_19 0x00fe 339 + #define regROM_SW_DATA_19_BASE_IDX 0 340 + #define regROM_SW_DATA_20 0x00ff 341 + #define regROM_SW_DATA_20_BASE_IDX 0 342 + #define regROM_SW_DATA_21 0x0100 343 + #define regROM_SW_DATA_21_BASE_IDX 0 344 + #define regROM_SW_DATA_22 0x0101 345 + #define regROM_SW_DATA_22_BASE_IDX 0 346 + #define regROM_SW_DATA_23 0x0102 347 + #define regROM_SW_DATA_23_BASE_IDX 0 348 + #define regROM_SW_DATA_24 0x0103 349 + #define regROM_SW_DATA_24_BASE_IDX 0 350 + #define regROM_SW_DATA_25 0x0104 351 + #define regROM_SW_DATA_25_BASE_IDX 0 352 + #define regROM_SW_DATA_26 0x0105 353 + #define regROM_SW_DATA_26_BASE_IDX 0 354 + #define regROM_SW_DATA_27 0x0106 355 + #define regROM_SW_DATA_27_BASE_IDX 0 356 + #define regROM_SW_DATA_28 0x0107 357 + #define regROM_SW_DATA_28_BASE_IDX 0 358 + #define regROM_SW_DATA_29 0x0108 359 + #define regROM_SW_DATA_29_BASE_IDX 0 360 + #define regROM_SW_DATA_30 0x0109 361 + #define regROM_SW_DATA_30_BASE_IDX 0 362 + #define regROM_SW_DATA_31 0x010a 363 + #define regROM_SW_DATA_31_BASE_IDX 0 364 + #define regROM_SW_DATA_32 0x010b 365 + #define regROM_SW_DATA_32_BASE_IDX 0 366 + #define regROM_SW_DATA_33 0x010c 367 + #define regROM_SW_DATA_33_BASE_IDX 0 368 + #define regROM_SW_DATA_34 0x010d 369 + #define regROM_SW_DATA_34_BASE_IDX 0 370 + #define regROM_SW_DATA_35 0x010e 371 + #define regROM_SW_DATA_35_BASE_IDX 0 372 + #define regROM_SW_DATA_36 0x010f 373 + #define regROM_SW_DATA_36_BASE_IDX 0 374 + #define regROM_SW_DATA_37 0x0110 375 + #define regROM_SW_DATA_37_BASE_IDX 0 376 + #define regROM_SW_DATA_38 0x0111 377 + #define regROM_SW_DATA_38_BASE_IDX 0 378 + #define regROM_SW_DATA_39 0x0112 379 + #define regROM_SW_DATA_39_BASE_IDX 0 380 + #define regROM_SW_DATA_40 0x0113 381 + #define regROM_SW_DATA_40_BASE_IDX 0 382 + #define regROM_SW_DATA_41 0x0114 383 + #define regROM_SW_DATA_41_BASE_IDX 0 384 + #define regROM_SW_DATA_42 0x0115 385 + #define regROM_SW_DATA_42_BASE_IDX 0 386 + #define regROM_SW_DATA_43 0x0116 387 + #define regROM_SW_DATA_43_BASE_IDX 0 388 + #define regROM_SW_DATA_44 0x0117 389 + #define regROM_SW_DATA_44_BASE_IDX 0 390 + #define regROM_SW_DATA_45 0x0118 391 + #define regROM_SW_DATA_45_BASE_IDX 0 392 + #define regROM_SW_DATA_46 0x0119 393 + #define regROM_SW_DATA_46_BASE_IDX 0 394 + #define regROM_SW_DATA_47 0x011a 395 + #define regROM_SW_DATA_47_BASE_IDX 0 396 + #define regROM_SW_DATA_48 0x011b 397 + #define regROM_SW_DATA_48_BASE_IDX 0 398 + #define regROM_SW_DATA_49 0x011c 399 + #define regROM_SW_DATA_49_BASE_IDX 0 400 + #define regROM_SW_DATA_50 0x011d 401 + #define regROM_SW_DATA_50_BASE_IDX 0 402 + #define regROM_SW_DATA_51 0x011e 403 + #define regROM_SW_DATA_51_BASE_IDX 0 404 + #define regROM_SW_DATA_52 0x011f 405 + #define regROM_SW_DATA_52_BASE_IDX 0 406 + #define regROM_SW_DATA_53 0x0120 407 + #define regROM_SW_DATA_53_BASE_IDX 0 408 + #define regROM_SW_DATA_54 0x0121 409 + #define regROM_SW_DATA_54_BASE_IDX 0 410 + #define regROM_SW_DATA_55 0x0122 411 + #define regROM_SW_DATA_55_BASE_IDX 0 412 + #define regROM_SW_DATA_56 0x0123 413 + #define regROM_SW_DATA_56_BASE_IDX 0 414 + #define regROM_SW_DATA_57 0x0124 415 + #define regROM_SW_DATA_57_BASE_IDX 0 416 + #define regROM_SW_DATA_58 0x0125 417 + #define regROM_SW_DATA_58_BASE_IDX 0 418 + #define regROM_SW_DATA_59 0x0126 419 + #define regROM_SW_DATA_59_BASE_IDX 0 420 + #define regROM_SW_DATA_60 0x0127 421 + #define regROM_SW_DATA_60_BASE_IDX 0 422 + #define regROM_SW_DATA_61 0x0128 423 + #define regROM_SW_DATA_61_BASE_IDX 0 424 + #define regROM_SW_DATA_62 0x0129 425 + #define regROM_SW_DATA_62_BASE_IDX 0 426 + #define regROM_SW_DATA_63 0x012a 427 + #define regROM_SW_DATA_63_BASE_IDX 0 428 + #define regROM_SW_DATA_64 0x012b 429 + #define regROM_SW_DATA_64_BASE_IDX 0 430 + 431 + 432 + // addressBlock: smuio_smuio_gpio_SmuSmuioDec 433 + // base address: 0x5a500 434 + #define regSMU_GPIOPAD_SW_INT_STAT 0x0140 435 + #define regSMU_GPIOPAD_SW_INT_STAT_BASE_IDX 0 436 + #define regSMU_GPIOPAD_MASK 0x0141 437 + #define regSMU_GPIOPAD_MASK_BASE_IDX 0 438 + #define regSMU_GPIOPAD_A 0x0142 439 + #define regSMU_GPIOPAD_A_BASE_IDX 0 440 + #define regSMU_GPIOPAD_TXIMPSEL 0x0143 441 + #define regSMU_GPIOPAD_TXIMPSEL_BASE_IDX 0 442 + #define regSMU_GPIOPAD_EN 0x0144 443 + #define regSMU_GPIOPAD_EN_BASE_IDX 0 444 + #define regSMU_GPIOPAD_Y 0x0145 445 + #define regSMU_GPIOPAD_Y_BASE_IDX 0 446 + #define regSMU_GPIOPAD_RXEN 0x0146 447 + #define regSMU_GPIOPAD_RXEN_BASE_IDX 0 448 + #define regSMU_GPIOPAD_RCVR_SEL0 0x0147 449 + #define regSMU_GPIOPAD_RCVR_SEL0_BASE_IDX 0 450 + #define regSMU_GPIOPAD_RCVR_SEL1 0x0148 451 + #define regSMU_GPIOPAD_RCVR_SEL1_BASE_IDX 0 452 + #define regSMU_GPIOPAD_PU_EN 0x0149 453 + #define regSMU_GPIOPAD_PU_EN_BASE_IDX 0 454 + #define regSMU_GPIOPAD_PD_EN 0x014a 455 + #define regSMU_GPIOPAD_PD_EN_BASE_IDX 0 456 + #define regSMU_GPIOPAD_PINSTRAPS 0x014b 457 + #define regSMU_GPIOPAD_PINSTRAPS_BASE_IDX 0 458 + #define regDFT_PINSTRAPS 0x014c 459 + #define regDFT_PINSTRAPS_BASE_IDX 0 460 + #define regSMU_GPIOPAD_INT_STAT_EN 0x014d 461 + #define regSMU_GPIOPAD_INT_STAT_EN_BASE_IDX 0 462 + #define regSMU_GPIOPAD_INT_STAT 0x014e 463 + #define regSMU_GPIOPAD_INT_STAT_BASE_IDX 0 464 + #define regSMU_GPIOPAD_INT_STAT_AK 0x014f 465 + #define regSMU_GPIOPAD_INT_STAT_AK_BASE_IDX 0 466 + #define regSMU_GPIOPAD_INT_EN 0x0150 467 + #define regSMU_GPIOPAD_INT_EN_BASE_IDX 0 468 + #define regSMU_GPIOPAD_INT_TYPE 0x0151 469 + #define regSMU_GPIOPAD_INT_TYPE_BASE_IDX 0 470 + #define regSMU_GPIOPAD_INT_POLARITY 0x0152 471 + #define regSMU_GPIOPAD_INT_POLARITY_BASE_IDX 0 472 + #define regSMUIO_PCC_GPIO_SELECT 0x0155 473 + #define regSMUIO_PCC_GPIO_SELECT_BASE_IDX 0 474 + #define regSMU_GPIOPAD_S0 0x0156 475 + #define regSMU_GPIOPAD_S0_BASE_IDX 0 476 + #define regSMU_GPIOPAD_S1 0x0157 477 + #define regSMU_GPIOPAD_S1_BASE_IDX 0 478 + #define regSMU_GPIOPAD_SCHMEN 0x0158 479 + #define regSMU_GPIOPAD_SCHMEN_BASE_IDX 0 480 + #define regSMU_GPIOPAD_SCL_EN 0x0159 481 + #define regSMU_GPIOPAD_SCL_EN_BASE_IDX 0 482 + #define regSMU_GPIOPAD_SDA_EN 0x015a 483 + #define regSMU_GPIOPAD_SDA_EN_BASE_IDX 0 484 + #define regSMUIO_GPIO_INT0_SELECT 0x015b 485 + #define regSMUIO_GPIO_INT0_SELECT_BASE_IDX 0 486 + #define regSMUIO_GPIO_INT1_SELECT 0x015c 487 + #define regSMUIO_GPIO_INT1_SELECT_BASE_IDX 0 488 + #define regSMUIO_GPIO_INT2_SELECT 0x015d 489 + #define regSMUIO_GPIO_INT2_SELECT_BASE_IDX 0 490 + #define regSMUIO_GPIO_INT3_SELECT 0x015e 491 + #define regSMUIO_GPIO_INT3_SELECT_BASE_IDX 0 492 + #define regSMU_GPIOPAD_MP_INT0_STAT 0x015f 493 + #define regSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX 0 494 + #define regSMU_GPIOPAD_MP_INT1_STAT 0x0160 495 + #define regSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX 0 496 + #define regSMU_GPIOPAD_MP_INT2_STAT 0x0161 497 + #define regSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX 0 498 + #define regSMU_GPIOPAD_MP_INT3_STAT 0x0162 499 + #define regSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX 0 500 + #define regSMIO_INDEX 0x0163 501 + #define regSMIO_INDEX_BASE_IDX 0 502 + #define regS0_VID_SMIO_CNTL 0x0164 503 + #define regS0_VID_SMIO_CNTL_BASE_IDX 0 504 + #define regS1_VID_SMIO_CNTL 0x0165 505 + #define regS1_VID_SMIO_CNTL_BASE_IDX 0 506 + #define regOPEN_DRAIN_SELECT 0x0166 507 + #define regOPEN_DRAIN_SELECT_BASE_IDX 0 508 + #define regSMIO_ENABLE 0x0167 509 + #define regSMIO_ENABLE_BASE_IDX 0 510 + 511 + 512 + #endif
+1113
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_8_sh_mask.h
··· 1 + /* 2 + * Copyright 2025 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _smuio_15_0_8_SH_MASK_HEADER 24 + #define _smuio_15_0_8_SH_MASK_HEADER 25 + 26 + 27 + // addressBlock: smuio_smuio_tsc_SmuSmuioDec 28 + //PWROK_REFCLK_GAP_CYCLES 29 + #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0 30 + #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8 31 + #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL 32 + #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L 33 + //GOLDEN_TSC_INCREMENT_UPPER 34 + #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0 35 + #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL 36 + //GOLDEN_TSC_INCREMENT_LOWER 37 + #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0 38 + #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL 39 + //GOLDEN_TSC_COUNT_UPPER 40 + #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0 41 + #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL 42 + //GOLDEN_TSC_COUNT_LOWER 43 + #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0 44 + #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL 45 + //SOC_GOLDEN_TSC_SHADOW_UPPER 46 + #define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT 0x0 47 + #define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK 0x00FFFFFFL 48 + //SOC_GOLDEN_TSC_SHADOW_LOWER 49 + #define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT 0x0 50 + #define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK 0xFFFFFFFFL 51 + //SOC_GAP_PWROK 52 + #define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0 53 + #define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L 54 + 55 + 56 + // addressBlock: smuio_smuio_swtimer_SmuSmuioDec 57 + //PWR_VIRT_RESET_REQ 58 + #define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 59 + #define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f 60 + #define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL 61 + #define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L 62 + //PWR_DISP_TIMER_CONTROL 63 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 64 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 65 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 66 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 67 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 68 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 69 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 70 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 71 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 72 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 73 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 74 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 75 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 76 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 77 + //PWR_DISP_TIMER_DEBUG 78 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 79 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 80 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 81 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 82 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L 83 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L 84 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x00000004L 85 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L 86 + //PWR_DISP_TIMER2_CONTROL 87 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 88 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 89 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 90 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 91 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 92 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 93 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 94 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 95 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 96 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 97 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 98 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 99 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 100 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 101 + //PWR_DISP_TIMER2_DEBUG 102 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 103 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 104 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 105 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 106 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L 107 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L 108 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x00000004L 109 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L 110 + //PWR_DISP_TIMER_GLOBAL_CONTROL 111 + #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 112 + #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa 113 + #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL 114 + #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L 115 + //PWR_IH_CONTROL 116 + #define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0 117 + #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5 118 + #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6 119 + #define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT 0x1f 120 + #define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL 121 + #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L 122 + #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L 123 + #define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK 0x80000000L 124 + 125 + 126 + // addressBlock: smuio_smuio_misc_SmuSmuioDec 127 + //SMUIO_MCM_CONFIG 128 + #define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0 129 + #define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2 130 + #define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x8 131 + #define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT 0x10 132 + #define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT 0x11 133 + #define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x12 134 + #define SMUIO_MCM_CONFIG__TOPOLOGY_ID__SHIFT 0x13 135 + #define SMUIO_MCM_CONFIG__PKG_TYPE_DFX__SHIFT 0x18 136 + #define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L 137 + #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000003CL 138 + #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00001F00L 139 + #define SMUIO_MCM_CONFIG__CONSOLE_K_MASK 0x00010000L 140 + #define SMUIO_MCM_CONFIG__CONSOLE_A_MASK 0x00020000L 141 + #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x00040000L 142 + #define SMUIO_MCM_CONFIG__TOPOLOGY_ID_MASK 0x00F80000L 143 + //IP_DISCOVERY_VERSION 144 + #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0 145 + #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL 146 + //SCRATCH_REGISTER0 147 + #define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0 148 + #define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL 149 + //SCRATCH_REGISTER1 150 + #define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0 151 + #define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL 152 + //SCRATCH_REGISTER2 153 + #define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0 154 + #define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL 155 + //SCRATCH_REGISTER3 156 + #define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0 157 + #define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL 158 + //SCRATCH_REGISTER4 159 + #define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0 160 + #define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL 161 + //SCRATCH_REGISTER5 162 + #define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0 163 + #define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL 164 + //SCRATCH_REGISTER6 165 + #define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0 166 + #define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL 167 + //SCRATCH_REGISTER7 168 + #define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0 169 + #define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL 170 + 171 + 172 + // addressBlock: smuio_smuio_i2c_SmuSmuioDec 173 + //CKSVII2C_IC_CON 174 + #define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT 0x0 175 + #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT 0x1 176 + #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT 0x3 177 + #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT 0x4 178 + #define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5 179 + #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT 0x6 180 + #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT 0x7 181 + #define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT 0x8 182 + #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT 0x9 183 + #define CKSVII2C_IC_CON__BUS_CLEAR_FEATURE_CTRL__SHIFT 0xb 184 + #define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK 0x00000001L 185 + #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK 0x00000006L 186 + #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK 0x00000008L 187 + #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK 0x00000010L 188 + #define CKSVII2C_IC_CON__IC_RESTART_EN_MASK 0x00000020L 189 + #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK 0x00000040L 190 + #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK 0x00000080L 191 + #define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK 0x00000100L 192 + #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK 0x00000200L 193 + //CKSVII2C_IC_TAR 194 + #define CKSVII2C_IC_TAR__IC_TAR__SHIFT 0x0 195 + #define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa 196 + #define CKSVII2C_IC_TAR__SPECIAL__SHIFT 0xb 197 + #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT 0xc 198 + #define CKSVII2C_IC_TAR__IC_TAR_MASK 0x000003FFL 199 + #define CKSVII2C_IC_TAR__GC_OR_START_MASK 0x00000400L 200 + #define CKSVII2C_IC_TAR__SPECIAL_MASK 0x00000800L 201 + #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK 0x00001000L 202 + //CKSVII2C_IC_SAR 203 + #define CKSVII2C_IC_SAR__IC_SAR__SHIFT 0x0 204 + #define CKSVII2C_IC_SAR__IC_SAR_MASK 0x000003FFL 205 + //CKSVII2C_IC_HS_MADDR 206 + #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT 0x0 207 + #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK 0x00000007L 208 + //CKSVII2C_IC_DATA_CMD 209 + #define CKSVII2C_IC_DATA_CMD__DAT__SHIFT 0x0 210 + #define CKSVII2C_IC_DATA_CMD__CMD__SHIFT 0x8 211 + #define CKSVII2C_IC_DATA_CMD__STOP__SHIFT 0x9 212 + #define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa 213 + #define CKSVII2C_IC_DATA_CMD__FIRST_DATA_BYTE__SHIFT 0xb 214 + #define CKSVII2C_IC_DATA_CMD__DAT_MASK 0x000000FFL 215 + #define CKSVII2C_IC_DATA_CMD__CMD_MASK 0x00000100L 216 + #define CKSVII2C_IC_DATA_CMD__STOP_MASK 0x00000200L 217 + #define CKSVII2C_IC_DATA_CMD__RESTART_MASK 0x00000400L 218 + //CKSVII2C_IC_SS_SCL_HCNT 219 + #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT 0x0 220 + #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK 0x0000FFFFL 221 + //CKSVII2C_IC_SS_SCL_LCNT 222 + #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT 0x0 223 + #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK 0x0000FFFFL 224 + //CKSVII2C_IC_FS_SCL_HCNT 225 + #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT 0x0 226 + #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK 0x0000FFFFL 227 + //CKSVII2C_IC_FS_SCL_LCNT 228 + #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT 0x0 229 + #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK 0x0000FFFFL 230 + //CKSVII2C_IC_HS_SCL_HCNT 231 + #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT 0x0 232 + #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK 0x0000FFFFL 233 + //CKSVII2C_IC_HS_SCL_LCNT 234 + #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT 0x0 235 + #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK 0x0000FFFFL 236 + //CKSVII2C_IC_INTR_STAT 237 + #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT 0x0 238 + #define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT 0x1 239 + #define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT 0x2 240 + #define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT 0x3 241 + #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT 0x4 242 + #define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT 0x5 243 + #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT 0x6 244 + #define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT 0x7 245 + #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT 0x8 246 + #define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT 0x9 247 + #define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa 248 + #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT 0xb 249 + #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT 0xc 250 + #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd 251 + #define CKSVII2C_IC_INTR_STAT__R_SCL_STUCK_AT_LOW__SHIFT 0xe 252 + #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK 0x00000001L 253 + #define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK 0x00000002L 254 + #define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK 0x00000004L 255 + #define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK 0x00000008L 256 + #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L 257 + #define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK 0x00000020L 258 + #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK 0x00000040L 259 + #define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK 0x00000080L 260 + #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK 0x00000100L 261 + #define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK 0x00000200L 262 + #define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK 0x00000400L 263 + #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK 0x00000800L 264 + #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK 0x00001000L 265 + #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L 266 + //CKSVII2C_IC_INTR_MASK 267 + #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT 0x0 268 + #define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT 0x1 269 + #define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT 0x2 270 + #define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT 0x3 271 + #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT 0x4 272 + #define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT 0x5 273 + #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT 0x6 274 + #define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT 0x7 275 + #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT 0x8 276 + #define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT 0x9 277 + #define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa 278 + #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT 0xb 279 + #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT 0xc 280 + #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT 0xd 281 + #define CKSVII2C_IC_INTR_MASK__M_SCL_STUCK_AT_LOW__SHIFT 0xe 282 + #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK 0x00000001L 283 + #define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK 0x00000002L 284 + #define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK 0x00000004L 285 + #define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK 0x00000008L 286 + #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK 0x00000010L 287 + #define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK 0x00000020L 288 + #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK 0x00000040L 289 + #define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK 0x00000080L 290 + #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK 0x00000100L 291 + #define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK 0x00000200L 292 + #define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK 0x00000400L 293 + #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK 0x00000800L 294 + #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK 0x00001000L 295 + #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK 0x00002000L 296 + //CKSVII2C_IC_RAW_INTR_STAT 297 + //CKSVII2C_IC_RX_TL 298 + #define CKSVII2C_IC_RX_TL__RX_TL__SHIFT 0x0 299 + //CKSVII2C_IC_TX_TL 300 + #define CKSVII2C_IC_TX_TL__TX_TL__SHIFT 0x0 301 + //CKSVII2C_IC_CLR_INTR 302 + //CKSVII2C_IC_CLR_RX_UNDER 303 + //CKSVII2C_IC_CLR_RX_OVER 304 + //CKSVII2C_IC_CLR_TX_OVER 305 + //CKSVII2C_IC_CLR_RD_REQ 306 + //CKSVII2C_IC_CLR_TX_ABRT 307 + //CKSVII2C_IC_CLR_RX_DONE 308 + //CKSVII2C_IC_CLR_ACTIVITY 309 + //CKSVII2C_IC_CLR_STOP_DET 310 + //CKSVII2C_IC_CLR_START_DET 311 + //CKSVII2C_IC_CLR_GEN_CALL 312 + //CKSVII2C_IC_ENABLE 313 + #define CKSVII2C_IC_ENABLE__ENABLE__SHIFT 0x0 314 + #define CKSVII2C_IC_ENABLE__ABORT__SHIFT 0x1 315 + #define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK__SHIFT 0x2 316 + #define CKSVII2C_IC_ENABLE__SDA_STUCK_RECOVERY_ENABLE__SHIFT 0x3 317 + #define CKSVII2C_IC_ENABLE__ENABLE_MASK 0x00000001L 318 + #define CKSVII2C_IC_ENABLE__ABORT_MASK 0x00000002L 319 + //CKSVII2C_IC_STATUS 320 + #define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT 0x0 321 + #define CKSVII2C_IC_STATUS__TFNF__SHIFT 0x1 322 + #define CKSVII2C_IC_STATUS__TFE__SHIFT 0x2 323 + #define CKSVII2C_IC_STATUS__RFNE__SHIFT 0x3 324 + #define CKSVII2C_IC_STATUS__RFF__SHIFT 0x4 325 + #define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT 0x5 326 + #define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT 0x6 327 + #define CKSVII2C_IC_STATUS__MST_HOLD_TX_FIFO_EMPTY__SHIFT 0x7 328 + #define CKSVII2C_IC_STATUS__MST_HOLD_RX_FIFO_FULL__SHIFT 0x8 329 + #define CKSVII2C_IC_STATUS__SLV_HOLD_TX_FIFO_EMPTY__SHIFT 0x9 330 + #define CKSVII2C_IC_STATUS__SLV_HOLD_RX_FIFO_FULL__SHIFT 0xa 331 + #define CKSVII2C_IC_STATUS__SDA_STUCK_NOT_RECOVERED__SHIFT 0xb 332 + #define CKSVII2C_IC_STATUS__ACTIVITY_MASK 0x00000001L 333 + #define CKSVII2C_IC_STATUS__TFNF_MASK 0x00000002L 334 + #define CKSVII2C_IC_STATUS__TFE_MASK 0x00000004L 335 + #define CKSVII2C_IC_STATUS__RFNE_MASK 0x00000008L 336 + #define CKSVII2C_IC_STATUS__RFF_MASK 0x00000010L 337 + #define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK 0x00000020L 338 + #define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK 0x00000040L 339 + //CKSVII2C_IC_TXFLR 340 + #define CKSVII2C_IC_TXFLR__TXFLR__SHIFT 0x0 341 + //CKSVII2C_IC_RXFLR 342 + #define CKSVII2C_IC_RXFLR__RXFLR__SHIFT 0x0 343 + //CKSVII2C_IC_SDA_HOLD 344 + #define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD__SHIFT 0x0 345 + #define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD__SHIFT 0x10 346 + //CKSVII2C_IC_TX_ABRT_SOURCE 347 + //CKSVII2C_IC_SLV_DATA_NACK_ONLY 348 + //CKSVII2C_IC_DMA_CR 349 + //CKSVII2C_IC_DMA_TDLR 350 + //CKSVII2C_IC_DMA_RDLR 351 + //CKSVII2C_IC_SDA_SETUP 352 + #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT 0x0 353 + #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK 0x000000FFL 354 + //CKSVII2C_IC_ACK_GENERAL_CALL 355 + #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL__SHIFT 0x0 356 + #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL_MASK 0x00000001L 357 + //CKSVII2C_IC_ENABLE_STATUS 358 + #define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT 0x0 359 + #define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY__SHIFT 0x1 360 + #define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST__SHIFT 0x2 361 + #define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK 0x00000001L 362 + //CKSVII2C_IC_FS_SPKLEN 363 + #define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN__SHIFT 0x0 364 + #define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN_MASK 0x000000FFL 365 + //CKSVII2C_IC_HS_SPKLEN 366 + #define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN__SHIFT 0x0 367 + #define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN_MASK 0x000000FFL 368 + //CKSVII2C_IC_CLR_RESTART_DET 369 + //CKSVII2C_IC_COMP_PARAM_1 370 + #define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH__SHIFT 0x0 371 + #define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE__SHIFT 0x2 372 + #define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES__SHIFT 0x4 373 + #define CKSVII2C_IC_COMP_PARAM_1__INTR_IO__SHIFT 0x5 374 + #define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA__SHIFT 0x6 375 + #define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS__SHIFT 0x7 376 + #define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH__SHIFT 0x8 377 + #define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH__SHIFT 0x10 378 + //CKSVII2C_IC_COMP_VERSION 379 + #define CKSVII2C_IC_COMP_VERSION__COMP_VERSION__SHIFT 0x0 380 + #define CKSVII2C_IC_COMP_VERSION__COMP_VERSION_MASK 0xFFFFFFFFL 381 + //CKSVII2C_IC_COMP_TYPE 382 + #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT 0x0 383 + #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK 0xFFFFFFFFL 384 + //CKSVII2C1_IC_CON 385 + #define CKSVII2C1_IC_CON__IC1_MASTER_MODE__SHIFT 0x0 386 + #define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE__SHIFT 0x1 387 + #define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE__SHIFT 0x3 388 + #define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER__SHIFT 0x4 389 + #define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT 0x5 390 + #define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE__SHIFT 0x6 391 + #define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED__SHIFT 0x7 392 + #define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL__SHIFT 0x8 393 + #define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL__SHIFT 0x9 394 + #define CKSVII2C1_IC_CON__BUS_CLEAR_FEATURE_CTRL1__SHIFT 0xb 395 + #define CKSVII2C1_IC_CON__IC1_MASTER_MODE_MASK 0x00000001L 396 + #define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE_MASK 0x00000006L 397 + #define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE_MASK 0x00000008L 398 + #define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER_MASK 0x00000010L 399 + #define CKSVII2C1_IC_CON__IC1_RESTART_EN_MASK 0x00000020L 400 + #define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE_MASK 0x00000040L 401 + #define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED_MASK 0x00000080L 402 + #define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL_MASK 0x00000100L 403 + #define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL_MASK 0x00000200L 404 + //CKSVII2C1_IC_TAR 405 + #define CKSVII2C1_IC_TAR__IC1_TAR__SHIFT 0x0 406 + #define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa 407 + #define CKSVII2C1_IC_TAR__SPECIAL1__SHIFT 0xb 408 + #define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER__SHIFT 0xc 409 + #define CKSVII2C1_IC_TAR__IC1_TAR_MASK 0x000003FFL 410 + #define CKSVII2C1_IC_TAR__GC1_OR_START_MASK 0x00000400L 411 + #define CKSVII2C1_IC_TAR__SPECIAL1_MASK 0x00000800L 412 + #define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER_MASK 0x00001000L 413 + //CKSVII2C1_IC_SAR 414 + #define CKSVII2C1_IC_SAR__IC1_SAR__SHIFT 0x0 415 + #define CKSVII2C1_IC_SAR__IC1_SAR_MASK 0x000003FFL 416 + //CKSVII2C1_IC_HS_MADDR 417 + #define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR__SHIFT 0x0 418 + #define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR_MASK 0x00000007L 419 + //CKSVII2C1_IC_DATA_CMD 420 + #define CKSVII2C1_IC_DATA_CMD__DAT1__SHIFT 0x0 421 + #define CKSVII2C1_IC_DATA_CMD__CMD1__SHIFT 0x8 422 + #define CKSVII2C1_IC_DATA_CMD__STOP1__SHIFT 0x9 423 + #define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa 424 + #define CKSVII2C1_IC_DATA_CMD__FIRST1_DATA_BYTE__SHIFT 0xb 425 + #define CKSVII2C1_IC_DATA_CMD__DAT1_MASK 0x000000FFL 426 + #define CKSVII2C1_IC_DATA_CMD__CMD1_MASK 0x00000100L 427 + #define CKSVII2C1_IC_DATA_CMD__STOP1_MASK 0x00000200L 428 + #define CKSVII2C1_IC_DATA_CMD__RESTART1_MASK 0x00000400L 429 + //CKSVII2C1_IC_SS_SCL_HCNT 430 + #define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT__SHIFT 0x0 431 + #define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT_MASK 0x0000FFFFL 432 + //CKSVII2C1_IC_SS_SCL_LCNT 433 + #define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT__SHIFT 0x0 434 + #define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT_MASK 0x0000FFFFL 435 + //CKSVII2C1_IC_FS_SCL_HCNT 436 + #define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT__SHIFT 0x0 437 + #define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT_MASK 0x0000FFFFL 438 + //CKSVII2C1_IC_FS_SCL_LCNT 439 + #define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT__SHIFT 0x0 440 + #define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT_MASK 0x0000FFFFL 441 + //CKSVII2C1_IC_HS_SCL_HCNT 442 + #define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT__SHIFT 0x0 443 + #define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT_MASK 0x0000FFFFL 444 + //CKSVII2C1_IC_HS_SCL_LCNT 445 + #define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT__SHIFT 0x0 446 + #define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT_MASK 0x0000FFFFL 447 + //CKSVII2C1_IC_INTR_STAT 448 + #define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER__SHIFT 0x0 449 + #define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER__SHIFT 0x1 450 + #define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL__SHIFT 0x2 451 + #define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER__SHIFT 0x3 452 + #define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY__SHIFT 0x4 453 + #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT 0x5 454 + #define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT__SHIFT 0x6 455 + #define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE__SHIFT 0x7 456 + #define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY__SHIFT 0x8 457 + #define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET__SHIFT 0x9 458 + #define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa 459 + #define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL__SHIFT 0xb 460 + #define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET__SHIFT 0xc 461 + #define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD__SHIFT 0xd 462 + #define CKSVII2C1_IC_INTR_STAT__R1_SCL_STUCK_AT_LOW__SHIFT 0xe 463 + #define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER_MASK 0x00000001L 464 + #define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER_MASK 0x00000002L 465 + #define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL_MASK 0x00000004L 466 + #define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER_MASK 0x00000008L 467 + #define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY_MASK 0x00000010L 468 + #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ_MASK 0x00000020L 469 + #define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT_MASK 0x00000040L 470 + #define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE_MASK 0x00000080L 471 + #define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY_MASK 0x00000100L 472 + #define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET_MASK 0x00000200L 473 + #define CKSVII2C1_IC_INTR_STAT__R1_START_DET_MASK 0x00000400L 474 + #define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL_MASK 0x00000800L 475 + #define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET_MASK 0x00001000L 476 + #define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD_MASK 0x00002000L 477 + //CKSVII2C1_IC_INTR_MASK 478 + #define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER__SHIFT 0x0 479 + #define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER__SHIFT 0x1 480 + #define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL__SHIFT 0x2 481 + #define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER__SHIFT 0x3 482 + #define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY__SHIFT 0x4 483 + #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT 0x5 484 + #define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT__SHIFT 0x6 485 + #define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE__SHIFT 0x7 486 + #define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY__SHIFT 0x8 487 + #define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET__SHIFT 0x9 488 + #define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa 489 + #define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL__SHIFT 0xb 490 + #define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET__SHIFT 0xc 491 + #define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD__SHIFT 0xd 492 + #define CKSVII2C1_IC_INTR_MASK__M1_SCL_STUCK_AT_LOW__SHIFT 0xe 493 + #define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER_MASK 0x00000001L 494 + #define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER_MASK 0x00000002L 495 + #define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL_MASK 0x00000004L 496 + #define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER_MASK 0x00000008L 497 + #define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY_MASK 0x00000010L 498 + #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ_MASK 0x00000020L 499 + #define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT_MASK 0x00000040L 500 + #define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE_MASK 0x00000080L 501 + #define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY_MASK 0x00000100L 502 + #define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET_MASK 0x00000200L 503 + #define CKSVII2C1_IC_INTR_MASK__M1_START_DET_MASK 0x00000400L 504 + #define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL_MASK 0x00000800L 505 + #define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET_MASK 0x00001000L 506 + #define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD_MASK 0x00002000L 507 + //CKSVII2C1_IC_RAW_INTR_STAT 508 + //CKSVII2C1_IC_RX_TL 509 + #define CKSVII2C1_IC_RX_TL__RX1_TL__SHIFT 0x0 510 + //CKSVII2C1_IC_TX_TL 511 + #define CKSVII2C1_IC_TX_TL__TX1_TL__SHIFT 0x0 512 + //CKSVII2C1_IC_CLR_INTR 513 + //CKSVII2C1_IC_CLR_RX_UNDER 514 + //CKSVII2C1_IC_CLR_RX_OVER 515 + //CKSVII2C1_IC_CLR_TX_OVER 516 + //CKSVII2C1_IC_CLR_RD_REQ 517 + //CKSVII2C1_IC_CLR_TX_ABRT 518 + //CKSVII2C1_IC_CLR_RX_DONE 519 + //CKSVII2C1_IC_CLR_ACTIVITY 520 + //CKSVII2C1_IC_CLR_STOP_DET 521 + //CKSVII2C1_IC_CLR_START_DET 522 + //CKSVII2C1_IC_CLR_GEN_CALL 523 + //CKSVII2C1_IC_ENABLE 524 + #define CKSVII2C1_IC_ENABLE__ENABLE1__SHIFT 0x0 525 + #define CKSVII2C1_IC_ENABLE__ABORT1__SHIFT 0x1 526 + #define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK__SHIFT 0x2 527 + #define CKSVII2C1_IC_ENABLE__SDA1_STUCK_RECOVERY_ENABLE__SHIFT 0x3 528 + #define CKSVII2C1_IC_ENABLE__ENABLE1_MASK 0x00000001L 529 + #define CKSVII2C1_IC_ENABLE__ABORT1_MASK 0x00000002L 530 + //CKSVII2C1_IC_STATUS 531 + #define CKSVII2C1_IC_STATUS__ACTIVITY1__SHIFT 0x0 532 + #define CKSVII2C1_IC_STATUS__TFNF1__SHIFT 0x1 533 + #define CKSVII2C1_IC_STATUS__TFE1__SHIFT 0x2 534 + #define CKSVII2C1_IC_STATUS__RFNE1__SHIFT 0x3 535 + #define CKSVII2C1_IC_STATUS__RFF1__SHIFT 0x4 536 + #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT 0x5 537 + #define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY__SHIFT 0x6 538 + #define CKSVII2C1_IC_STATUS__MST1_HOLD_TX_FIFO_EMPTY__SHIFT 0x7 539 + #define CKSVII2C1_IC_STATUS__MST1_HOLD_RX_FIFO_FULL__SHIFT 0x8 540 + #define CKSVII2C1_IC_STATUS__SLV1_HOLD_TX_FIFO_EMPTY__SHIFT 0x9 541 + #define CKSVII2C1_IC_STATUS__SLV1_HOLD_RX_FIFO_FULL__SHIFT 0xa 542 + #define CKSVII2C1_IC_STATUS__SDA1_STUCK_NOT_RECOVERED__SHIFT 0xb 543 + #define CKSVII2C1_IC_STATUS__ACTIVITY1_MASK 0x00000001L 544 + #define CKSVII2C1_IC_STATUS__TFNF1_MASK 0x00000002L 545 + #define CKSVII2C1_IC_STATUS__TFE1_MASK 0x00000004L 546 + #define CKSVII2C1_IC_STATUS__RFNE1_MASK 0x00000008L 547 + #define CKSVII2C1_IC_STATUS__RFF1_MASK 0x00000010L 548 + #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY_MASK 0x00000020L 549 + #define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY_MASK 0x00000040L 550 + //CKSVII2C1_IC_TXFLR 551 + #define CKSVII2C1_IC_TXFLR__TXFLR1__SHIFT 0x0 552 + //CKSVII2C1_IC_RXFLR 553 + #define CKSVII2C1_IC_RXFLR__RXFLR1__SHIFT 0x0 554 + //CKSVII2C1_IC_SDA_HOLD 555 + #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD__SHIFT 0x0 556 + #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD__SHIFT 0x10 557 + //CKSVII2C1_IC_TX_ABRT_SOURCE 558 + //CKSVII2C1_IC_SLV_DATA_NACK_ONLY 559 + //CKSVII2C1_IC_DMA_CR 560 + //CKSVII2C1_IC_DMA_TDLR 561 + //CKSVII2C1_IC_DMA_RDLR 562 + //CKSVII2C1_IC_SDA_SETUP 563 + #define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP__SHIFT 0x0 564 + #define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP_MASK 0x000000FFL 565 + //CKSVII2C1_IC_ACK_GENERAL_CALL 566 + #define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL__SHIFT 0x0 567 + #define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL_MASK 0x00000001L 568 + //CKSVII2C1_IC_ENABLE_STATUS 569 + #define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN__SHIFT 0x0 570 + #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY__SHIFT 0x1 571 + #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST__SHIFT 0x2 572 + #define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN_MASK 0x00000001L 573 + //CKSVII2C1_IC_FS_SPKLEN 574 + #define CKSVII2C1_IC_FS_SPKLEN__FS1_SPKLEN__SHIFT 0x0 575 + //CKSVII2C1_IC_HS_SPKLEN 576 + #define CKSVII2C1_IC_HS_SPKLEN__HS1_SPKLEN__SHIFT 0x0 577 + //CKSVII2C1_IC_CLR_RESTART_DET 578 + //CKSVII2C1_IC_COMP_PARAM_1 579 + #define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH__SHIFT 0x0 580 + #define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE__SHIFT 0x2 581 + #define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES__SHIFT 0x4 582 + #define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO__SHIFT 0x5 583 + #define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA__SHIFT 0x6 584 + #define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS__SHIFT 0x7 585 + #define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH__SHIFT 0x8 586 + #define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH__SHIFT 0x10 587 + //CKSVII2C1_IC_COMP_VERSION 588 + #define CKSVII2C1_IC_COMP_VERSION__COMP1_VERSION__SHIFT 0x0 589 + //CKSVII2C1_IC_COMP_TYPE 590 + #define CKSVII2C1_IC_COMP_TYPE__COMP1_TYPE__SHIFT 0x0 591 + //SMUIO_PWRMGT 592 + #define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0 593 + #define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x8 594 + #define SMUIO_PWRMGT__i2c_reg_reset__SHIFT 0x10 595 + #define SMUIO_PWRMGT__i2c_dwc_reset_en__SHIFT 0x11 596 + #define SMUIO_PWRMGT__i2c1_reg_reset__SHIFT 0x18 597 + #define SMUIO_PWRMGT__i2c1_dwc_reset_en__SHIFT 0x19 598 + #define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L 599 + #define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000100L 600 + 601 + 602 + // addressBlock: smuio_smuio_rom_SmuSmuioDec 603 + //ROM_CNTL 604 + #define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0 605 + #define ROM_CNTL__READ_MODE__SHIFT 0x1 606 + #define ROM_CNTL__READ_MODE_OVERRIDE__SHIFT 0x3 607 + #define ROM_CNTL__SPI_TIMING_RELAX_SCK__SHIFT 0x4 608 + #define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE__SHIFT 0x5 609 + #define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE__SHIFT 0x6 610 + #define ROM_CNTL__DUMMY_CYCLE_NUM__SHIFT 0x8 611 + #define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x13 612 + #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x14 613 + #define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x15 614 + #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x16 615 + #define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x17 616 + #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c 617 + #define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE__SHIFT 0x1d 618 + #define ROM_CNTL__PAD_SAMPLE_MODE__SHIFT 0x1e 619 + #define ROM_CNTL__PAD_SAMPLE_MODE_OVERRIDE__SHIFT 0x1f 620 + #define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L 621 + #define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00080000L 622 + #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00100000L 623 + #define ROM_CNTL__SPI_FAST_MODE_MASK 0x00200000L 624 + #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00400000L 625 + #define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F800000L 626 + #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L 627 + //PAGE_MIRROR_CNTL 628 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 629 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 630 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a 631 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x1c 632 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x01FFFFFFL 633 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L 634 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L 635 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x10000000L 636 + //ROM_STATUS 637 + #define ROM_STATUS__ROM_BUSY__SHIFT 0x0 638 + #define ROM_STATUS__ROM_BUSY_MASK 0x00000001L 639 + //CGTT_ROM_CLK_CTRL0 640 + #define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 641 + #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 642 + #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 643 + #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 644 + #define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL 645 + #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L 646 + #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L 647 + #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L 648 + //ROM_INDEX 649 + #define ROM_INDEX__ROM_INDEX__SHIFT 0x0 650 + #define ROM_INDEX__ROM_INDEX_MASK 0x01FFFFFFL 651 + //ROM_DATA 652 + #define ROM_DATA__ROM_DATA__SHIFT 0x0 653 + #define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL 654 + //ROM_START 655 + #define ROM_START__ROM_START__SHIFT 0x0 656 + #define ROM_START__ROM_START_MASK 0x01FFFFFFL 657 + //ROM_SW_CNTL 658 + #define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 659 + #define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 660 + #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x13 661 + #define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL 662 + #define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00070000L 663 + #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00080000L 664 + //ROM_SW_STATUS 665 + #define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 666 + #define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L 667 + //ROM_SW_COMMAND 668 + #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 669 + #define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 670 + #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL 671 + #define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L 672 + //ROM_SW_DATA_1 673 + #define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 674 + #define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL 675 + //ROM_SW_DATA_2 676 + #define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 677 + #define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL 678 + //ROM_SW_DATA_3 679 + #define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 680 + #define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL 681 + //ROM_SW_DATA_4 682 + #define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 683 + #define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL 684 + //ROM_SW_DATA_5 685 + #define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 686 + #define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL 687 + //ROM_SW_DATA_6 688 + #define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 689 + #define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL 690 + //ROM_SW_DATA_7 691 + #define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 692 + #define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL 693 + //ROM_SW_DATA_8 694 + #define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 695 + #define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL 696 + //ROM_SW_DATA_9 697 + #define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 698 + #define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL 699 + //ROM_SW_DATA_10 700 + #define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 701 + #define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL 702 + //ROM_SW_DATA_11 703 + #define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 704 + #define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL 705 + //ROM_SW_DATA_12 706 + #define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 707 + #define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL 708 + //ROM_SW_DATA_13 709 + #define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 710 + #define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL 711 + //ROM_SW_DATA_14 712 + #define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 713 + #define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL 714 + //ROM_SW_DATA_15 715 + #define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 716 + #define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL 717 + //ROM_SW_DATA_16 718 + #define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 719 + #define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL 720 + //ROM_SW_DATA_17 721 + #define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 722 + #define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL 723 + //ROM_SW_DATA_18 724 + #define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 725 + #define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL 726 + //ROM_SW_DATA_19 727 + #define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 728 + #define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL 729 + //ROM_SW_DATA_20 730 + #define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 731 + #define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL 732 + //ROM_SW_DATA_21 733 + #define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 734 + #define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL 735 + //ROM_SW_DATA_22 736 + #define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 737 + #define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL 738 + //ROM_SW_DATA_23 739 + #define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 740 + #define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL 741 + //ROM_SW_DATA_24 742 + #define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 743 + #define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL 744 + //ROM_SW_DATA_25 745 + #define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 746 + #define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL 747 + //ROM_SW_DATA_26 748 + #define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 749 + #define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL 750 + //ROM_SW_DATA_27 751 + #define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 752 + #define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL 753 + //ROM_SW_DATA_28 754 + #define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 755 + #define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL 756 + //ROM_SW_DATA_29 757 + #define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 758 + #define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL 759 + //ROM_SW_DATA_30 760 + #define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 761 + #define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL 762 + //ROM_SW_DATA_31 763 + #define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 764 + #define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL 765 + //ROM_SW_DATA_32 766 + #define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 767 + #define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL 768 + //ROM_SW_DATA_33 769 + #define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 770 + #define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL 771 + //ROM_SW_DATA_34 772 + #define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 773 + #define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL 774 + //ROM_SW_DATA_35 775 + #define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 776 + #define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL 777 + //ROM_SW_DATA_36 778 + #define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 779 + #define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL 780 + //ROM_SW_DATA_37 781 + #define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 782 + #define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL 783 + //ROM_SW_DATA_38 784 + #define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 785 + #define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL 786 + //ROM_SW_DATA_39 787 + #define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 788 + #define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL 789 + //ROM_SW_DATA_40 790 + #define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 791 + #define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL 792 + //ROM_SW_DATA_41 793 + #define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 794 + #define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL 795 + //ROM_SW_DATA_42 796 + #define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 797 + #define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL 798 + //ROM_SW_DATA_43 799 + #define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 800 + #define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL 801 + //ROM_SW_DATA_44 802 + #define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 803 + #define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL 804 + //ROM_SW_DATA_45 805 + #define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 806 + #define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL 807 + //ROM_SW_DATA_46 808 + #define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 809 + #define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL 810 + //ROM_SW_DATA_47 811 + #define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 812 + #define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL 813 + //ROM_SW_DATA_48 814 + #define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 815 + #define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL 816 + //ROM_SW_DATA_49 817 + #define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 818 + #define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL 819 + //ROM_SW_DATA_50 820 + #define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 821 + #define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL 822 + //ROM_SW_DATA_51 823 + #define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 824 + #define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL 825 + //ROM_SW_DATA_52 826 + #define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 827 + #define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL 828 + //ROM_SW_DATA_53 829 + #define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 830 + #define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL 831 + //ROM_SW_DATA_54 832 + #define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 833 + #define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL 834 + //ROM_SW_DATA_55 835 + #define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 836 + #define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL 837 + //ROM_SW_DATA_56 838 + #define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 839 + #define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL 840 + //ROM_SW_DATA_57 841 + #define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 842 + #define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL 843 + //ROM_SW_DATA_58 844 + #define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 845 + #define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL 846 + //ROM_SW_DATA_59 847 + #define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 848 + #define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL 849 + //ROM_SW_DATA_60 850 + #define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 851 + #define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL 852 + //ROM_SW_DATA_61 853 + #define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 854 + #define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL 855 + //ROM_SW_DATA_62 856 + #define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 857 + #define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL 858 + //ROM_SW_DATA_63 859 + #define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 860 + #define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL 861 + //ROM_SW_DATA_64 862 + #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 863 + #define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL 864 + 865 + 866 + // addressBlock: smuio_smuio_gpio_SmuSmuioDec 867 + //SMU_GPIOPAD_SW_INT_STAT 868 + #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 869 + #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L 870 + //SMU_GPIOPAD_MASK 871 + #define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 872 + #define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL 873 + //SMU_GPIOPAD_A 874 + #define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0 875 + #define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL 876 + //SMU_GPIOPAD_TXIMPSEL 877 + #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0 878 + #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL 879 + //SMU_GPIOPAD_EN 880 + #define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0 881 + #define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL 882 + //SMU_GPIOPAD_Y 883 + #define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0 884 + #define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL 885 + //SMU_GPIOPAD_RXEN 886 + #define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0 887 + #define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL 888 + //SMU_GPIOPAD_RCVR_SEL0 889 + #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0 890 + #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL 891 + //SMU_GPIOPAD_RCVR_SEL1 892 + #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0 893 + #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL 894 + //SMU_GPIOPAD_PU_EN 895 + #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 896 + #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL 897 + //SMU_GPIOPAD_PD_EN 898 + #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 899 + #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL 900 + //SMU_GPIOPAD_PINSTRAPS 901 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 902 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 903 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 904 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 905 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 906 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 907 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 908 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 909 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 910 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 911 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa 912 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb 913 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc 914 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd 915 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe 916 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf 917 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 918 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 919 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 920 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 921 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 922 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 923 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 924 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 925 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 926 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 927 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a 928 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b 929 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c 930 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d 931 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e 932 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L 933 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L 934 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L 935 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L 936 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L 937 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L 938 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L 939 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L 940 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L 941 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L 942 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L 943 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L 944 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L 945 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L 946 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L 947 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L 948 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L 949 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L 950 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L 951 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L 952 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L 953 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L 954 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L 955 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L 956 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L 957 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L 958 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L 959 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L 960 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L 961 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L 962 + #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L 963 + //DFT_PINSTRAPS 964 + #define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0 965 + #define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000003FFL 966 + //SMU_GPIOPAD_INT_STAT_EN 967 + #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 968 + #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f 969 + #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL 970 + #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L 971 + //SMU_GPIOPAD_INT_STAT 972 + #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 973 + #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f 974 + #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL 975 + #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L 976 + //SMU_GPIOPAD_INT_STAT_AK 977 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 978 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 979 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 980 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 981 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 982 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 983 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 984 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 985 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 986 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 987 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa 988 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb 989 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc 990 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd 991 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe 992 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf 993 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 994 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 995 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 996 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 997 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 998 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 999 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 1000 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 1001 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 1002 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 1003 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a 1004 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b 1005 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c 1006 + #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f 1007 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L 1008 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L 1009 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L 1010 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L 1011 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L 1012 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L 1013 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L 1014 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L 1015 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L 1016 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L 1017 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L 1018 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L 1019 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L 1020 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L 1021 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L 1022 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L 1023 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L 1024 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L 1025 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L 1026 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L 1027 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L 1028 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L 1029 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L 1030 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L 1031 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L 1032 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L 1033 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L 1034 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L 1035 + #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L 1036 + #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L 1037 + //SMU_GPIOPAD_INT_EN 1038 + #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 1039 + #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f 1040 + #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL 1041 + #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L 1042 + //SMU_GPIOPAD_INT_TYPE 1043 + #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 1044 + #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f 1045 + #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL 1046 + #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L 1047 + //SMU_GPIOPAD_INT_POLARITY 1048 + #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 1049 + #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f 1050 + #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL 1051 + #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L 1052 + //SMUIO_PCC_GPIO_SELECT 1053 + #define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 1054 + #define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL 1055 + //SMU_GPIOPAD_S0 1056 + #define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0 1057 + #define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL 1058 + //SMU_GPIOPAD_S1 1059 + #define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0 1060 + #define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL 1061 + //SMU_GPIOPAD_SCHMEN 1062 + #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0 1063 + #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL 1064 + //SMU_GPIOPAD_SCL_EN 1065 + #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0 1066 + #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL 1067 + //SMU_GPIOPAD_SDA_EN 1068 + #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0 1069 + #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL 1070 + //SMUIO_GPIO_INT0_SELECT 1071 + #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0 1072 + #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL 1073 + //SMUIO_GPIO_INT1_SELECT 1074 + #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0 1075 + #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL 1076 + //SMUIO_GPIO_INT2_SELECT 1077 + #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0 1078 + #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL 1079 + //SMUIO_GPIO_INT3_SELECT 1080 + #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0 1081 + #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL 1082 + //SMU_GPIOPAD_MP_INT0_STAT 1083 + #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0 1084 + #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL 1085 + //SMU_GPIOPAD_MP_INT1_STAT 1086 + #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0 1087 + #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL 1088 + //SMU_GPIOPAD_MP_INT2_STAT 1089 + #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0 1090 + #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL 1091 + //SMU_GPIOPAD_MP_INT3_STAT 1092 + #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0 1093 + #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL 1094 + //SMIO_INDEX 1095 + #define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0 1096 + #define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L 1097 + //S0_VID_SMIO_CNTL 1098 + #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0 1099 + #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL 1100 + //S1_VID_SMIO_CNTL 1101 + #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0 1102 + #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL 1103 + //OPEN_DRAIN_SELECT 1104 + #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0 1105 + #define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f 1106 + #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL 1107 + #define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L 1108 + //SMIO_ENABLE 1109 + #define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0 1110 + #define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL 1111 + 1112 + 1113 + #endif