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ARM: use BIT() and GENMASK() for fault status register fields

Modernise the fault status field definitions by using BIT() and
GENMASK().

Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

+6 -6
+6 -6
arch/arm/mm/fault.h
··· 5 5 /* 6 6 * Fault status register encodings. We steal bit 31 for our own purposes. 7 7 */ 8 - #define FSR_LNX_PF (1 << 31) 9 - #define FSR_CM (1 << 13) 10 - #define FSR_WRITE (1 << 11) 11 - #define FSR_FS4 (1 << 10) 12 - #define FSR_FS3_0 (15) 13 - #define FSR_FS5_0 (0x3f) 8 + #define FSR_LNX_PF BIT(31) 9 + #define FSR_CM BIT(13) 10 + #define FSR_WRITE BIT(11) 11 + #define FSR_FS4 BIT(10) 12 + #define FSR_FS3_0 GENMASK(3, 0) 13 + #define FSR_FS5_0 GENMASK(5, 0) 14 14 15 15 #ifdef CONFIG_ARM_LPAE 16 16 #define FSR_FS_AEA 17