Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull intel drm fixes from Dave Airlie:
"Intel fixes came in late, but since I debugged one of them I'll send
them on,
Two reverts, a quirk and one warn regression"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
Revert "drm/i915: reverse dp link param selection, prefer fast over wide again"
drm/i915: Track the primary plane correctly when reassigning planes
drm/i915: Ignore VBT backlight presence check on HP Chromebook 14
Revert "drm/i915: Don't set the 8to6 dither flag when not scaling"
+17
-6
+4
drivers/gpu/drm/i915/intel_display.c
+4
drivers/gpu/drm/i915/intel_display.c
···
11673
11673
11674
11674
/* Toshiba CB35 Chromebook (Celeron 2955U) */
11675
11675
{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
11676
+
11677
+
/* HP Chromebook 14 (Celeron 2955U) */
11678
+
{ 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
11676
11679
};
11677
11680
11678
11681
static void intel_init_quirks(struct drm_device *dev)
···
11914
11911
* ... */
11915
11912
plane = crtc->plane;
11916
11913
crtc->plane = !plane;
11914
+
crtc->primary_enabled = true;
11917
11915
dev_priv->display.crtc_disable(&crtc->base);
11918
11916
crtc->plane = plane;
11919
11917
+2
-2
drivers/gpu/drm/i915/intel_dp.c
+2
-2
drivers/gpu/drm/i915/intel_dp.c
···
906
906
mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
907
907
bpp);
908
908
909
-
for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
910
-
for (clock = min_clock; clock <= max_clock; clock++) {
909
+
for (clock = min_clock; clock <= max_clock; clock++) {
910
+
for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
911
911
link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
912
912
link_avail = intel_dp_max_data_rate(link_clock,
913
913
lane_count);
+7
drivers/gpu/drm/i915/intel_lvds.c
+7
drivers/gpu/drm/i915/intel_lvds.c
···
111
111
112
112
pipe_config->adjusted_mode.flags |= flags;
113
113
114
+
/* gen2/3 store dither state in pfit control, needs to match */
115
+
if (INTEL_INFO(dev)->gen < 4) {
116
+
tmp = I915_READ(PFIT_CONTROL);
117
+
118
+
pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
119
+
}
120
+
114
121
dotclock = pipe_config->port_clock;
115
122
116
123
if (HAS_PCH_SPLIT(dev_priv->dev))
+4
-4
drivers/gpu/drm/i915/intel_panel.c
+4
-4
drivers/gpu/drm/i915/intel_panel.c
···
361
361
pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
362
362
PFIT_FILTER_FUZZY);
363
363
364
-
/* Make sure pre-965 set dither correctly for 18bpp panels. */
365
-
if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
366
-
pfit_control |= PANEL_8TO6_DITHER_ENABLE;
367
-
368
364
out:
369
365
if ((pfit_control & PFIT_ENABLE) == 0) {
370
366
pfit_control = 0;
371
367
pfit_pgm_ratios = 0;
372
368
}
369
+
370
+
/* Make sure pre-965 set dither correctly for 18bpp panels. */
371
+
if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
372
+
pfit_control |= PANEL_8TO6_DITHER_ENABLE;
373
373
374
374
pipe_config->gmch_pfit.control = pfit_control;
375
375
pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;