Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A handful of clk driver fixes and one core framework fix
- Do a DT/firmware lookup in clk_core_get() even when the DT index is
a nonsensical value
- Fix some clk data typos in the Amlogic DT headers/code
- Avoid returning junk in the TI clk driver when an invalid clk is
looked for
- Fix dividers for the emac clks on Stratix10 SoCs
- Fix default HDA rates on Tegra210 to correct distorted audio"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: socfpga: stratix10: fix divider entry for the emac clocks
clk: Do a DT parent lookup even when index < 0
clk: tegra210: Fix default rates for HDA clocks
clk: ti: clkctrl: Fix returning uninitialized data
clk: meson: meson8b: fix a typo in the VPU parent names array variable
clk: meson: fix MPLL 50M binding id typo
+19
-14
+1
-1
drivers/clk/clk.c
+1
-1
drivers/clk/clk.c
+2
-2
drivers/clk/meson/g12a.c
+2
-2
drivers/clk/meson/g12a.c
···
2734
2734
[CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
2735
2735
[CLKID_MALI_1] = &g12a_mali_1.hw,
2736
2736
[CLKID_MALI] = &g12a_mali.hw,
2737
-
[CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw,
2738
-
[CLKID_MPLL_5OM] = &g12a_mpll_50m.hw,
2737
+
[CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
2738
+
[CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
2739
2739
[CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
2740
2740
[CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
2741
2741
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
+1
-1
drivers/clk/meson/g12a.h
+1
-1
drivers/clk/meson/g12a.h
···
166
166
#define CLKID_HDMI_DIV 167
167
167
#define CLKID_MALI_0_DIV 170
168
168
#define CLKID_MALI_1_DIV 173
169
-
#define CLKID_MPLL_5OM_DIV 176
169
+
#define CLKID_MPLL_50M_DIV 176
170
170
#define CLKID_SYS_PLL_DIV16_EN 178
171
171
#define CLKID_SYS_PLL_DIV16 179
172
172
#define CLKID_CPU_CLK_DYN0_SEL 180
+5
-5
drivers/clk/meson/meson8b.c
+5
-5
drivers/clk/meson/meson8b.c
···
1761
1761
},
1762
1762
};
1763
1763
1764
-
static const char * const mmeson8b_vpu_0_1_parent_names[] = {
1764
+
static const char * const meson8b_vpu_0_1_parent_names[] = {
1765
1765
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1766
1766
};
1767
1767
···
1778
1778
.hw.init = &(struct clk_init_data){
1779
1779
.name = "vpu_0_sel",
1780
1780
.ops = &clk_regmap_mux_ops,
1781
-
.parent_names = mmeson8b_vpu_0_1_parent_names,
1782
-
.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
1781
+
.parent_names = meson8b_vpu_0_1_parent_names,
1782
+
.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
1783
1783
.flags = CLK_SET_RATE_PARENT,
1784
1784
},
1785
1785
};
···
1837
1837
.hw.init = &(struct clk_init_data){
1838
1838
.name = "vpu_1_sel",
1839
1839
.ops = &clk_regmap_mux_ops,
1840
-
.parent_names = mmeson8b_vpu_0_1_parent_names,
1841
-
.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
1840
+
.parent_names = meson8b_vpu_0_1_parent_names,
1841
+
.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
1842
1842
.flags = CLK_SET_RATE_PARENT,
1843
1843
},
1844
1844
};
+2
-2
drivers/clk/socfpga/clk-s10.c
+2
-2
drivers/clk/socfpga/clk-s10.c
···
103
103
{ STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
104
104
0, 0, 0, 0x3C, 1},
105
105
{ STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
106
-
0, 0, 4, 0xB0, 0},
106
+
0, 0, 2, 0xB0, 0},
107
107
{ STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
108
-
0, 0, 4, 0xB0, 1},
108
+
0, 0, 2, 0xB0, 1},
109
109
{ STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
110
110
ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 4, 0xB0, 2},
111
111
{ STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
+2
drivers/clk/tegra/clk-tegra210.c
+2
drivers/clk/tegra/clk-tegra210.c
···
3366
3366
{ TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3367
3367
{ TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3368
3368
{ TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3369
+
{ TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
3370
+
{ TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
3369
3371
/* This MUST be the last entry. */
3370
3372
{ TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
3371
3373
};
+5
-2
drivers/clk/ti/clkctrl.c
+5
-2
drivers/clk/ti/clkctrl.c
···
229
229
{
230
230
struct omap_clkctrl_provider *provider = data;
231
231
struct omap_clkctrl_clk *entry;
232
+
bool found = false;
232
233
233
234
if (clkspec->args_count != 2)
234
235
return ERR_PTR(-EINVAL);
···
239
238
240
239
list_for_each_entry(entry, &provider->clocks, node) {
241
240
if (entry->reg_offset == clkspec->args[0] &&
242
-
entry->bit_offset == clkspec->args[1])
241
+
entry->bit_offset == clkspec->args[1]) {
242
+
found = true;
243
243
break;
244
+
}
244
245
}
245
246
246
-
if (!entry)
247
+
if (!found)
247
248
return ERR_PTR(-EINVAL);
248
249
249
250
return entry->clk;
+1
-1
include/dt-bindings/clock/g12a-clkc.h
+1
-1
include/dt-bindings/clock/g12a-clkc.h