Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mips_6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer:
"Just cleanups and fixes"
* tag 'mips_6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
MIPS: vpe-mt: drop physical_memsize
mips: fix syscall_get_nr
MIPS: SMP-CPS: fix build error when HOTPLUG_CPU not set
MIPS: DTS: jz4780: add #clock-cells to rtc_dev
MIPS: dts: Boston: Fix dtc 'pci_device_reg' warning
mips: dts: ralink: mt7621: add port@5 as CPU port
mips: dts: align LED node names with dtschema
MIPS: ralink: Use devm_platform_get_and_ioremap_resource()
MIPS: pci-mt7620: Use devm_platform_get_and_ioremap_resource()
MIPS: pci: lantiq: Use devm_platform_get_and_ioremap_resource()
MIPS: lantiq: xway: Use devm_platform_get_and_ioremap_resource()
MIPS: BCM47XX: Add support for Linksys E2500 V3
mips: ralink: make SOC_MT7621 select PINCTRL_MT7621 and fix help section
MIPS: DTS: CI20: fix otg power gpio
MIPS: dts: lantiq: Remove bogus interrupt-parent; line
MIPS: Fix a compilation issue
MIPS: remove CONFIG_MIPS_LD_CAN_LINK_VDSO
mips: Realtek RTL: select NO_EXCEPT_FILL
MIPS: OCTEON: octeon-usb: Consolidate error messages
+136
-144
+1
arch/mips/Kconfig
+1
arch/mips/Kconfig
+1
arch/mips/bcm47xx/board.c
+1
arch/mips/bcm47xx/board.c
···
130
130
{{BCM47XX_BOARD_LINKSYS_E1000V21, "Linksys E1000 V2.1"}, "E1000", "2.1"},
131
131
{{BCM47XX_BOARD_LINKSYS_E1200V2, "Linksys E1200 V2"}, "E1200", "2.0"},
132
132
{{BCM47XX_BOARD_LINKSYS_E2000V1, "Linksys E2000 V1"}, "Linksys E2000", "1.0"},
133
+
{{BCM47XX_BOARD_LINKSYS_E2500V3, "Linksys E2500 V3"}, "E2500", "1.0"},
133
134
/* like WRT610N v2.0 */
134
135
{{BCM47XX_BOARD_LINKSYS_E3000V1, "Linksys E3000 V1"}, "E300", "1.0"},
135
136
{{BCM47XX_BOARD_LINKSYS_E3200V1, "Linksys E3200 V1"}, "E3200", "1.0"},
+5
-5
arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts
+5
-5
arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts
···
20
20
leds {
21
21
compatible = "gpio-leds";
22
22
23
-
usb1 {
23
+
led-usb1 {
24
24
label = "usb1";
25
25
gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
26
26
};
27
27
28
-
usb2 {
28
+
led-usb2 {
29
29
label = "usb2";
30
30
gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
31
31
};
32
32
33
-
wps {
33
+
led-wps {
34
34
label = "wps";
35
35
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
36
36
};
37
37
38
-
wireless1 {
38
+
led-wireless1 {
39
39
label = "5g";
40
40
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
41
41
};
42
42
43
-
wireless2 {
43
+
led-wireless2 {
44
44
label = "2.4g";
45
45
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
46
46
};
+3
-3
arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts
+3
-3
arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts
···
21
21
leds {
22
22
compatible = "gpio-leds";
23
23
24
-
usb {
24
+
led-usb {
25
25
gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
26
26
};
27
27
28
-
wps {
28
+
led-wps {
29
29
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
30
30
};
31
31
32
-
wireless {
32
+
led-wireless {
33
33
label = "2.4g";
34
34
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
35
35
};
+1
-1
arch/mips/boot/dts/img/boston.dts
+1
-1
arch/mips/boot/dts/img/boston.dts
+5
-5
arch/mips/boot/dts/ingenic/ci20.dts
+5
-5
arch/mips/boot/dts/ingenic/ci20.dts
···
42
42
leds {
43
43
compatible = "gpio-leds";
44
44
45
-
led0 {
45
+
led-0 {
46
46
label = "ci20:red:led0";
47
47
gpios = <&gpc 3 GPIO_ACTIVE_HIGH>;
48
48
linux,default-trigger = "none";
49
49
};
50
50
51
-
led1 {
51
+
led-1 {
52
52
label = "ci20:red:led1";
53
53
gpios = <&gpc 2 GPIO_ACTIVE_HIGH>;
54
54
linux,default-trigger = "nand-disk";
55
55
};
56
56
57
-
led2 {
57
+
led-2 {
58
58
label = "ci20:red:led2";
59
59
gpios = <&gpc 1 GPIO_ACTIVE_HIGH>;
60
60
linux,default-trigger = "cpu1";
61
61
};
62
62
63
-
led3 {
63
+
led-3 {
64
64
label = "ci20:red:led3";
65
65
gpios = <&gpc 0 GPIO_ACTIVE_HIGH>;
66
66
linux,default-trigger = "cpu0";
···
113
113
regulator-min-microvolt = <5000000>;
114
114
regulator-max-microvolt = <5000000>;
115
115
116
-
gpio = <&gpf 14 GPIO_ACTIVE_LOW>;
116
+
gpio = <&gpf 15 GPIO_ACTIVE_LOW>;
117
117
enable-active-high;
118
118
};
119
119
};
+2
arch/mips/boot/dts/ingenic/jz4780.dtsi
+2
arch/mips/boot/dts/ingenic/jz4780.dtsi
-1
arch/mips/boot/dts/lantiq/danube.dtsi
-1
arch/mips/boot/dts/lantiq/danube.dtsi
+3
-3
arch/mips/boot/dts/pic32/pic32mzda_sk.dts
+3
-3
arch/mips/boot/dts/pic32/pic32mzda_sk.dts
···
28
28
pinctrl-names = "default";
29
29
pinctrl-0 = <&user_leds_s0>;
30
30
31
-
led@1 {
31
+
led-1 {
32
32
label = "pic32mzda_sk:red:led1";
33
33
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
34
34
linux,default-trigger = "heartbeat";
35
35
};
36
36
37
-
led@2 {
37
+
led-2 {
38
38
label = "pic32mzda_sk:yellow:led2";
39
39
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
40
40
linux,default-trigger = "mmc0";
41
41
};
42
42
43
-
led@3 {
43
+
led-3 {
44
44
label = "pic32mzda_sk:green:led3";
45
45
gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
46
46
default-state = "on";
+4
-4
arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
+4
-4
arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
···
41
41
42
42
leds {
43
43
compatible = "gpio-leds";
44
-
led@0 {
44
+
led-0 {
45
45
label = "tp-link:green:usb";
46
46
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
47
47
};
48
48
49
-
led@1 {
49
+
led-1 {
50
50
label = "tp-link:green:system";
51
51
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
52
52
linux,default-trigger = "heartbeat";
53
53
};
54
54
55
-
led@2 {
55
+
led-2 {
56
56
label = "tp-link:green:qss";
57
57
gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
58
58
};
59
59
60
-
led@3 {
60
+
led-3 {
61
61
label = "tp-link:green:wlan";
62
62
gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
63
63
};
+4
-4
arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts
+4
-4
arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts
···
22
22
leds {
23
23
compatible = "gpio-leds";
24
24
25
-
wlan {
25
+
led-wlan {
26
26
label = "dragino2:red:wlan";
27
27
gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
28
28
default-state = "off";
29
29
};
30
30
31
-
lan {
31
+
led-lan {
32
32
label = "dragino2:red:lan";
33
33
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
34
34
default-state = "off";
35
35
};
36
36
37
-
wan {
37
+
led-wan {
38
38
label = "dragino2:red:wan";
39
39
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
40
40
default-state = "off";
41
41
};
42
42
43
-
system {
43
+
led-system {
44
44
label = "dragino2:red:system";
45
45
gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
46
46
default-state = "off";
+1
-1
arch/mips/boot/dts/qca/ar9331_omega.dts
+1
-1
arch/mips/boot/dts/qca/ar9331_omega.dts
+4
-4
arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts
+4
-4
arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts
···
22
22
leds {
23
23
compatible = "gpio-leds";
24
24
25
-
wlan {
25
+
led-wlan {
26
26
label = "tp-link:green:wlan";
27
27
gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
28
28
default-state = "off";
29
29
};
30
30
31
-
lan {
31
+
led-lan {
32
32
label = "tp-link:green:lan";
33
33
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
34
34
default-state = "off";
35
35
};
36
36
37
-
wps {
37
+
led-wps {
38
38
label = "tp-link:green:wps";
39
39
gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
40
40
default-state = "off";
41
41
};
42
42
43
-
led3g {
43
+
led-led3g {
44
44
label = "tp-link:green:3g";
45
45
gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
46
46
default-state = "off";
+11
-11
arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts
+11
-11
arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts
···
47
47
* (see below). So we can't include it in this LED node.
48
48
*/
49
49
50
-
power_blue {
50
+
led-power-blue {
51
51
label = "smartgw:power:blue";
52
52
gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
53
53
default-state = "off";
54
54
};
55
55
56
-
power_green {
56
+
led-power-green {
57
57
label = "smartgw:power:green";
58
58
gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
59
59
default-state = "off";
60
60
};
61
61
62
-
power_red {
62
+
led-power-red {
63
63
label = "smartgw:power:red";
64
64
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
65
65
default-state = "off";
66
66
};
67
67
68
-
radio_blue {
68
+
led-radio-blue {
69
69
label = "smartgw:radio:blue";
70
70
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
71
71
default-state = "off";
72
72
};
73
73
74
-
radio_green {
74
+
led-radio-green {
75
75
label = "smartgw:radio:green";
76
76
gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
77
77
default-state = "off";
78
78
};
79
79
80
-
radio_red {
80
+
led-radio-red {
81
81
label = "smartgw:radio:red";
82
82
gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
83
83
default-state = "off";
84
84
};
85
85
86
-
internet_blue {
86
+
led-internet-blue {
87
87
label = "smartgw:internet:blue";
88
88
gpios = <&gpio 26 GPIO_ACTIVE_HIGH>;
89
89
default-state = "off";
90
90
};
91
91
92
-
internet_green {
92
+
led-internet-green {
93
93
label = "smartgw:internet:green";
94
94
gpios = <&gpio 27 GPIO_ACTIVE_HIGH>;
95
95
default-state = "off";
96
96
};
97
97
98
-
internet_red {
98
+
led-internet-red {
99
99
label = "smartgw:internet:red";
100
100
gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
101
101
default-state = "off";
102
102
};
103
103
104
-
ethernet_link {
104
+
led-ethernet-link {
105
105
label = "smartgw:eth:link";
106
106
gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
107
107
linux,default-trigger = "netdev";
108
108
};
109
109
110
-
ethernet_activity {
110
+
led-ethernet-activity {
111
111
label = "smartgw:eth:act";
112
112
gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
113
113
linux,default-trigger = "netdev";
+7
-13
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts
+7
-13
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts
···
33
33
gpio-leds {
34
34
compatible = "gpio-leds";
35
35
36
-
power {
36
+
led-power {
37
37
label = "green:power";
38
38
gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
39
39
linux,default-trigger = "default-on";
40
40
};
41
41
42
-
system {
42
+
led-system {
43
43
label = "green:system";
44
44
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
45
45
linux,default-trigger = "disk-activity";
···
91
91
status = "okay";
92
92
};
93
93
94
-
&gmac1 {
95
-
status = "okay";
96
-
phy-handle = <ðphy4>;
97
-
};
98
-
99
-
&mdio {
100
-
ethphy4: ethernet-phy@4 {
101
-
reg = <4>;
102
-
};
103
-
};
104
-
105
94
&switch0 {
106
95
ports {
107
96
port@0 {
108
97
status = "okay";
109
98
label = "ethblack";
99
+
};
100
+
101
+
port@4 {
102
+
status = "okay";
103
+
label = "ethblue";
110
104
};
111
105
};
112
106
};
+14
-7
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
+14
-7
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
···
33
33
gpio-leds {
34
34
compatible = "gpio-leds";
35
35
36
-
ethblack-green {
36
+
led-ethblack-green {
37
37
label = "green:ethblack";
38
38
gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
39
39
};
40
40
41
-
ethblue-green {
41
+
led-ethblue-green {
42
42
label = "green:ethblue";
43
43
gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
44
44
};
45
45
46
-
ethyellow-green {
46
+
led-ethyellow-green {
47
47
label = "green:ethyellow";
48
48
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
49
49
};
50
50
51
-
ethyellow-orange {
51
+
led-ethyellow-orange {
52
52
label = "orange:ethyellow";
53
53
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
54
54
};
55
55
56
-
power {
56
+
led-power {
57
57
label = "green:power";
58
58
gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
59
59
linux,default-trigger = "default-on";
60
60
};
61
61
62
-
system {
62
+
led-system {
63
63
label = "green:system";
64
64
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
65
65
linux,default-trigger = "disk-activity";
···
112
112
};
113
113
114
114
&gmac1 {
115
-
status = "okay";
116
115
phy-mode = "rgmii-rxid";
117
116
phy-handle = <ðphy5>;
117
+
118
+
fixed-link {
119
+
status = "disabled";
120
+
};
118
121
};
119
122
120
123
&mdio {
···
136
133
port@4 {
137
134
status = "okay";
138
135
label = "ethblue";
136
+
};
137
+
138
+
port@5 {
139
+
status = "disabled";
139
140
};
140
141
};
141
142
};
+18
-1
arch/mips/boot/dts/ralink/mt7621.dtsi
+18
-1
arch/mips/boot/dts/ralink/mt7621.dtsi
···
332
332
gmac1: mac@1 {
333
333
compatible = "mediatek,eth-mac";
334
334
reg = <1>;
335
-
status = "disabled";
336
335
phy-mode = "rgmii";
336
+
337
+
fixed-link {
338
+
speed = <1000>;
339
+
full-duplex;
340
+
pause;
341
+
};
337
342
};
338
343
339
344
mdio: mdio-bus {
···
387
382
status = "disabled";
388
383
reg = <4>;
389
384
label = "swp4";
385
+
};
386
+
387
+
port@5 {
388
+
reg = <5>;
389
+
ethernet = <&gmac1>;
390
+
phy-mode = "rgmii";
391
+
392
+
fixed-link {
393
+
speed = <1000>;
394
+
full-duplex;
395
+
pause;
396
+
};
390
397
};
391
398
392
399
port@6 {
+20
-22
arch/mips/cavium-octeon/octeon-usb.c
+20
-22
arch/mips/cavium-octeon/octeon-usb.c
···
245
245
power_active_low = 0;
246
246
gpio = gpio_pwr[1];
247
247
} else {
248
-
dev_err(dev, "dwc3 controller clock init failure.\n");
248
+
dev_err(dev, "invalid power configuration\n");
249
249
return -EINVAL;
250
250
}
251
251
if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
···
278
278
uctl_host_cfg.s.ppc_en = 0;
279
279
uctl_host_cfg.s.ppc_active_high_en = 0;
280
280
cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
281
-
dev_warn(dev, "dwc3 controller clock init failure.\n");
281
+
dev_info(dev, "power control disabled\n");
282
282
}
283
283
return 0;
284
284
}
···
301
301
i = of_property_read_u32(dev->of_node,
302
302
"refclk-frequency", &clock_rate);
303
303
if (i) {
304
-
pr_err("No UCTL \"refclk-frequency\"\n");
304
+
dev_err(dev, "No UCTL \"refclk-frequency\"\n");
305
305
return -EINVAL;
306
306
}
307
307
i = of_property_read_string(dev->of_node,
308
308
"refclk-type-ss", &ss_clock_type);
309
309
if (i) {
310
-
pr_err("No UCTL \"refclk-type-ss\"\n");
310
+
dev_err(dev, "No UCTL \"refclk-type-ss\"\n");
311
311
return -EINVAL;
312
312
}
313
313
i = of_property_read_string(dev->of_node,
314
314
"refclk-type-hs", &hs_clock_type);
315
315
if (i) {
316
-
pr_err("No UCTL \"refclk-type-hs\"\n");
316
+
dev_err(dev, "No UCTL \"refclk-type-hs\"\n");
317
317
return -EINVAL;
318
318
}
319
319
if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
···
322
322
else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
323
323
ref_clk_sel = 2;
324
324
else
325
-
pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n",
326
-
hs_clock_type);
325
+
dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
326
+
hs_clock_type);
327
327
} else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
328
328
if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)
329
329
ref_clk_sel = 1;
330
330
else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
331
331
ref_clk_sel = 3;
332
332
else {
333
-
pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n",
334
-
hs_clock_type);
333
+
dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
334
+
hs_clock_type);
335
335
ref_clk_sel = 3;
336
336
}
337
337
} else
338
-
pr_err("Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
339
-
ss_clock_type);
338
+
dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
339
+
ss_clock_type);
340
340
341
341
if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
342
-
(clock_rate != 100000000))
343
-
pr_err("Invalid UCTL clock rate of %u, using 100000000 instead\n",
344
-
clock_rate);
342
+
(clock_rate != 100000000))
343
+
dev_warn(dev, "Invalid UCTL clock rate of %u, using 100000000 instead\n",
344
+
clock_rate);
345
345
346
346
} else {
347
-
pr_err("No USB UCTL device node\n");
347
+
dev_err(dev, "No USB UCTL device node\n");
348
348
return -EINVAL;
349
349
}
350
350
···
396
396
uctl_ctl.s.ref_clk_div2 = 0;
397
397
switch (clock_rate) {
398
398
default:
399
-
dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n",
400
-
clock_rate);
399
+
dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n",
400
+
clock_rate);
401
401
fallthrough;
402
402
case 100000000:
403
403
mpll_mul = 0x19;
···
438
438
udelay(10);
439
439
440
440
/* Steo 8c: Setup power-power control. */
441
-
if (dwc3_octeon_config_power(dev, base)) {
442
-
dev_err(dev, "Error configuring power.\n");
441
+
if (dwc3_octeon_config_power(dev, base))
443
442
return -EINVAL;
444
-
}
445
443
446
444
/* Step 8d: Deassert UAHC reset signal. */
447
445
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
···
527
529
}
528
530
529
531
mutex_lock(&dwc3_octeon_clocks_mutex);
530
-
dwc3_octeon_clocks_start(&pdev->dev, (u64)base);
532
+
if (dwc3_octeon_clocks_start(&pdev->dev, (u64)base) == 0)
533
+
dev_info(&pdev->dev, "clocks initialized.\n");
531
534
dwc3_octeon_set_endian_mode((u64)base);
532
535
dwc3_octeon_phy_reset((u64)base);
533
-
dev_info(&pdev->dev, "clocks initialized.\n");
534
536
mutex_unlock(&dwc3_octeon_clocks_mutex);
535
537
devm_iounmap(&pdev->dev, base);
536
538
devm_release_mem_region(&pdev->dev, res->start,
+1
arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+1
arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+1
-1
arch/mips/include/asm/mach-rc32434/pci.h
+1
-1
arch/mips/include/asm/mach-rc32434/pci.h
+1
-1
arch/mips/include/asm/syscall.h
+1
-1
arch/mips/include/asm/syscall.h
-1
arch/mips/include/asm/vpe.h
-1
arch/mips/include/asm/vpe.h
+5
-3
arch/mips/kernel/smp-cps.c
+5
-3
arch/mips/kernel/smp-cps.c
···
424
424
wmb();
425
425
}
426
426
} else {
427
-
pr_debug("Gating power to core %d\n", core);
428
-
/* Power down the core */
429
-
cps_pm_enter_state(CPS_PM_POWER_GATED);
427
+
if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) {
428
+
pr_debug("Gating power to core %d\n", core);
429
+
/* Power down the core */
430
+
cps_pm_enter_state(CPS_PM_POWER_GATED);
431
+
}
430
432
}
431
433
}
432
434
+3
-4
arch/mips/kernel/vpe-mt.c
+3
-4
arch/mips/kernel/vpe-mt.c
···
92
92
write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H);
93
93
94
94
/*
95
-
* The sde-kit passes 'memsize' to __start in $a3, so set something
96
-
* here... Or set $a3 to zero and define DFLT_STACK_SIZE and
97
-
* DFLT_HEAP_SIZE when you compile your program
95
+
* We don't pass the memsize here, so VPE programs need to be
96
+
* compiled with DFLT_STACK_SIZE and DFLT_HEAP_SIZE defined.
98
97
*/
98
+
mttgpr(7, 0);
99
99
mttgpr(6, v->ntcs);
100
-
mttgpr(7, physical_memsize);
101
100
102
101
/* set up VPE1 */
103
102
/*
-6
arch/mips/lantiq/prom.c
-6
arch/mips/lantiq/prom.c
···
23
23
EXPORT_SYMBOL_GPL(ebu_lock);
24
24
25
25
/*
26
-
* This is needed by the VPE loader code, just set it to 0 and assume
27
-
* that the firmware hardcodes this value to something useful.
28
-
*/
29
-
unsigned long physical_memsize = 0L;
30
-
31
-
/*
32
26
* this struct is filled by the soc specific detection code and holds
33
27
* information about the specific soc type, revision and name
34
28
*/
+1
-4
arch/mips/lantiq/xway/dcdc.c
+1
-4
arch/mips/lantiq/xway/dcdc.c
···
22
22
23
23
static int dcdc_probe(struct platform_device *pdev)
24
24
{
25
-
struct resource *res;
26
-
27
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
28
-
dcdc_membase = devm_ioremap_resource(&pdev->dev, res);
25
+
dcdc_membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
29
26
if (IS_ERR(dcdc_membase))
30
27
return PTR_ERR(dcdc_membase);
31
28
+1
-3
arch/mips/lantiq/xway/dma.c
+1
-3
arch/mips/lantiq/xway/dma.c
···
239
239
ltq_dma_init(struct platform_device *pdev)
240
240
{
241
241
struct clk *clk;
242
-
struct resource *res;
243
242
unsigned int id, nchannels;
244
243
int i;
245
244
246
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
247
-
ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res);
245
+
ltq_dma_membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
248
246
if (IS_ERR(ltq_dma_membase))
249
247
panic("Failed to remap dma resource");
250
248
+1
-4
arch/mips/lantiq/xway/gptu.c
+1
-4
arch/mips/lantiq/xway/gptu.c
···
136
136
static int gptu_probe(struct platform_device *pdev)
137
137
{
138
138
struct clk *clk;
139
-
struct resource *res;
140
139
141
140
if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 6) != 6) {
142
141
dev_err(&pdev->dev, "Failed to get IRQ list\n");
143
142
return -EINVAL;
144
143
}
145
144
146
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
147
-
148
145
/* remap gptu register range */
149
-
gptu_membase = devm_ioremap_resource(&pdev->dev, res);
146
+
gptu_membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
150
147
if (IS_ERR(gptu_membase))
151
148
return PTR_ERR(gptu_membase);
152
149
+2
-6
arch/mips/pci/pci-lantiq.c
+2
-6
arch/mips/pci/pci-lantiq.c
···
204
204
205
205
static int ltq_pci_probe(struct platform_device *pdev)
206
206
{
207
-
struct resource *res_cfg, *res_bridge;
208
-
209
207
pci_clear_flags(PCI_PROBE_ONLY);
210
208
211
-
res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
212
-
ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
209
+
ltq_pci_membase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
213
210
if (IS_ERR(ltq_pci_membase))
214
211
return PTR_ERR(ltq_pci_membase);
215
212
216
-
res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
217
-
ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
213
+
ltq_pci_mapped_cfg = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
218
214
if (IS_ERR(ltq_pci_mapped_cfg))
219
215
return PTR_ERR(ltq_pci_mapped_cfg);
220
216
+2
-6
arch/mips/pci/pci-mt7620.c
+2
-6
arch/mips/pci/pci-mt7620.c
···
282
282
283
283
static int mt7620_pci_probe(struct platform_device *pdev)
284
284
{
285
-
struct resource *bridge_res = platform_get_resource(pdev,
286
-
IORESOURCE_MEM, 0);
287
-
struct resource *pcie_res = platform_get_resource(pdev,
288
-
IORESOURCE_MEM, 1);
289
285
u32 val = 0;
290
286
291
287
rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0");
292
288
if (IS_ERR(rstpcie0))
293
289
return PTR_ERR(rstpcie0);
294
290
295
-
bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
291
+
bridge_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
296
292
if (IS_ERR(bridge_base))
297
293
return PTR_ERR(bridge_base);
298
294
299
-
pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
295
+
pcie_base = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
300
296
if (IS_ERR(pcie_base))
301
297
return PTR_ERR(pcie_base);
302
298
+3
-2
arch/mips/ralink/Kconfig
+3
-2
arch/mips/ralink/Kconfig
···
54
54
select HAVE_PCI
55
55
select PCI_DRIVERS_GENERIC
56
56
select SOC_BUS
57
+
select PINCTRL_MT7621
57
58
58
59
help
59
-
The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc dual-core CPU,
60
-
a 5-port 10/100/1000 switch/PHY and one RGMII.
60
+
The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc
61
+
dual-core CPU, a 5-port 10/100/1000 switch/PHY and one RGMII.
61
62
endchoice
62
63
63
64
choice
+1
-2
arch/mips/ralink/timer.c
+1
-2
arch/mips/ralink/timer.c
···
95
95
96
96
static int rt_timer_probe(struct platform_device *pdev)
97
97
{
98
-
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
99
98
struct rt_timer *rt;
100
99
struct clk *clk;
101
100
···
108
109
if (rt->irq < 0)
109
110
return rt->irq;
110
111
111
-
rt->membase = devm_ioremap_resource(&pdev->dev, res);
112
+
rt->membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
112
113
if (IS_ERR(rt->membase))
113
114
return PTR_ERR(rt->membase);
114
115
+1
-13
arch/mips/vdso/Kconfig
+1
-13
arch/mips/vdso/Kconfig
···
1
-
# For the pre-R6 code in arch/mips/vdso/vdso.h for locating
2
-
# the base address of VDSO, the linker will emit a R_MIPS_PC32
3
-
# relocation in binutils > 2.25 but it will fail with older versions
4
-
# because that relocation is not supported for that symbol. As a result
5
-
# of which we are forced to disable the VDSO symbols when building
6
-
# with < 2.25 binutils on pre-R6 kernels. For more references on why we
7
-
# can't use other methods to get the base address of VDSO please refer to
8
-
# the comments on that file.
9
-
#
10
1
# GCC (at least up to version 9.2) appears to emit function calls that make use
11
2
# of the GOT when targeting microMIPS, which we can't use in the VDSO due to
12
3
# the lack of relocations. As such, we disable the VDSO for microMIPS builds.
13
4
14
-
config MIPS_LD_CAN_LINK_VDSO
15
-
def_bool LD_VERSION >= 22500 || LD_IS_LLD
16
-
17
5
config MIPS_DISABLE_VDSO
18
-
def_bool CPU_MICROMIPS || (!CPU_MIPSR6 && !MIPS_LD_CAN_LINK_VDSO)
6
+
def_bool CPU_MICROMIPS
-3
arch/mips/vdso/Makefile
-3
arch/mips/vdso/Makefile