Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'timers-core-2022-10-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer updates from Thomas Gleixner:
"A boring time, timekeeping, timers update:
- No core code changes
- No new clocksource/event driver
- Cleanup of the TI DM clocksource/event driver
- The usual set of device tree binding updates
- Small improvement, fixes and cleanups all over the place"
* tag 'timers-core-2022-10-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits)
clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value
clocksource/drivers/imx-sysctr: handle nxp,no-divider property
dt-bindings: timer: nxp,sysctr-timer: add nxp,no-divider property
clocksource/drivers/timer-ti-dm: Get clock in probe with devm_clk_get()
clocksource/drivers/timer-ti-dm: Add flag to detect omap1
clocksource/drivers/timer-ti-dm: Move struct omap_dm_timer fields to driver
clocksource/drivers/timer-ti-dm: Use runtime PM directly and check errors
clocksource/drivers/timer-ti-dm: Move private defines to the driver
clocksource/drivers/timer-ti-dm: Simplify register access further
clocksource/drivers/timer-ti-dm: Simplify register writes with dmtimer_write()
clocksource/drivers/timer-ti-dm: Simplify register reads with dmtimer_read()
clocksource/drivers/timer-ti-dm: Drop unused functions
clocksource/drivers/timer-gxp: Add missing error handling in gxp_timer_probe
clocksource/drivers/arm_arch_timer: Fix handling of ARM erratum 858921
clocksource/drivers/exynos_mct: Enable building on ARTPEC
clocksource/drivers/exynos_mct: Support local-timers property
clocksource/drivers/exynos_mct: Support frc-shared property
dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support
clocksource/drivers/sun4i: Add definition of clear interrupt
clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC
...
+557
-385
+1
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+1
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
···
25
25
For those SoCs that use SYST
26
26
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
27
27
* "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
28
+
* "mediatek,mt8188-timer" for MT8188 compatible timers (SYST)
28
29
* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
29
30
* "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
30
31
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
+4
Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml
+4
Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml
+1
Documentation/devicetree/bindings/timer/renesas,tmu.yaml
+1
Documentation/devicetree/bindings/timer/renesas,tmu.yaml
+26
Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
+26
Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
···
25
25
- samsung,exynos4412-mct
26
26
- items:
27
27
- enum:
28
+
- axis,artpec8-mct
28
29
- samsung,exynos3250-mct
29
30
- samsung,exynos5250-mct
30
31
- samsung,exynos5260-mct
···
45
44
46
45
reg:
47
46
maxItems: 1
47
+
48
+
samsung,frc-shared:
49
+
type: boolean
50
+
description: |
51
+
Indicates that the hardware requires that this processor share the
52
+
free-running counter with a different (main) processor.
53
+
54
+
samsung,local-timers:
55
+
$ref: /schemas/types.yaml#/definitions/uint32-array
56
+
minItems: 1
57
+
maxItems: 16
58
+
description: |
59
+
List of indices of local timers usable from this processor.
48
60
49
61
interrupts:
50
62
description: |
···
89
75
90
76
allOf:
91
77
- if:
78
+
not:
79
+
properties:
80
+
compatible:
81
+
contains:
82
+
enum:
83
+
- axis,artpec8-mct
84
+
then:
85
+
properties:
86
+
samsung,local-timers: false
87
+
samsung,frc-shared: false
88
+
- if:
92
89
properties:
93
90
compatible:
94
91
contains:
···
126
101
compatible:
127
102
contains:
128
103
enum:
104
+
- axis,artpec8-mct
129
105
- samsung,exynos5260-mct
130
106
- samsung,exynos5420-mct
131
107
- samsung,exynos5433-mct
+1
-1
drivers/clocksource/Kconfig
+1
-1
drivers/clocksource/Kconfig
···
434
434
config CLKSRC_EXYNOS_MCT
435
435
bool "Exynos multi core timer driver" if COMPILE_TEST
436
436
depends on ARM || ARM64
437
-
depends on ARCH_EXYNOS || COMPILE_TEST
437
+
depends on ARCH_ARTPEC || ARCH_EXYNOS || COMPILE_TEST
438
438
help
439
439
Support for Multi Core Timer controller on Exynos SoCs.
440
440
+4
-2
drivers/clocksource/arm_arch_timer.c
+4
-2
drivers/clocksource/arm_arch_timer.c
···
44
44
#define CNTACR_RWVT BIT(4)
45
45
#define CNTACR_RWPT BIT(5)
46
46
47
-
#define CNTVCT_LO 0x00
48
-
#define CNTPCT_LO 0x08
47
+
#define CNTPCT_LO 0x00
48
+
#define CNTVCT_LO 0x08
49
49
#define CNTFRQ 0x10
50
50
#define CNTP_CVAL_LO 0x20
51
51
#define CNTP_CTL 0x2c
···
473
473
.desc = "ARM erratum 858921",
474
474
.read_cntpct_el0 = arm64_858921_read_cntpct_el0,
475
475
.read_cntvct_el0 = arm64_858921_read_cntvct_el0,
476
+
.set_next_event_phys = erratum_set_next_event_phys,
477
+
.set_next_event_virt = erratum_set_next_event_virt,
476
478
},
477
479
#endif
478
480
#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
+74
-9
drivers/clocksource/exynos_mct.c
+74
-9
drivers/clocksource/exynos_mct.c
···
33
33
#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
34
34
#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
35
35
#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
36
-
#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
36
+
#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * (x)))
37
37
#define EXYNOS4_MCT_L_MASK (0xffffff00)
38
38
39
39
#define MCT_L_TCNTB_OFFSET (0x00)
···
66
66
#define MCT_L0_IRQ 4
67
67
/* Max number of IRQ as per DT binding document */
68
68
#define MCT_NR_IRQS 20
69
+
/* Max number of local timers */
70
+
#define MCT_NR_LOCAL (MCT_NR_IRQS - MCT_L0_IRQ)
69
71
70
72
enum {
71
73
MCT_INT_SPI,
···
235
233
}
236
234
#endif
237
235
238
-
static int __init exynos4_clocksource_init(void)
236
+
static int __init exynos4_clocksource_init(bool frc_shared)
239
237
{
240
-
exynos4_mct_frc_start();
238
+
/*
239
+
* When the frc is shared, the main processer should have already
240
+
* turned it on and we shouldn't be writing to TCON.
241
+
*/
242
+
if (frc_shared)
243
+
mct_frc.resume = NULL;
244
+
else
245
+
exynos4_mct_frc_start();
241
246
242
247
#if defined(CONFIG_ARM)
243
248
exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
···
458
449
per_cpu_ptr(&percpu_mct_tick, cpu);
459
450
struct clock_event_device *evt = &mevt->evt;
460
451
461
-
mevt->base = EXYNOS4_MCT_L_BASE(cpu);
462
452
snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
463
453
464
454
evt->name = mevt->name;
···
528
520
return 0;
529
521
}
530
522
523
+
/**
524
+
* exynos4_timer_interrupts - initialize MCT interrupts
525
+
* @np: device node for MCT
526
+
* @int_type: interrupt type, MCT_INT_PPI or MCT_INT_SPI
527
+
* @local_idx: array mapping CPU numbers to local timer indices
528
+
* @nr_local: size of @local_idx array
529
+
*/
531
530
static int __init exynos4_timer_interrupts(struct device_node *np,
532
-
unsigned int int_type)
531
+
unsigned int int_type,
532
+
const u32 *local_idx,
533
+
size_t nr_local)
533
534
{
534
535
int nr_irqs, i, err, cpu;
535
536
···
571
554
} else {
572
555
for_each_possible_cpu(cpu) {
573
556
int mct_irq;
557
+
unsigned int irq_idx;
574
558
struct mct_clock_event_device *pcpu_mevt =
575
559
per_cpu_ptr(&percpu_mct_tick, cpu);
576
560
561
+
if (cpu >= nr_local) {
562
+
err = -EINVAL;
563
+
goto out_irq;
564
+
}
565
+
566
+
irq_idx = MCT_L0_IRQ + local_idx[cpu];
567
+
577
568
pcpu_mevt->evt.irq = -1;
578
-
if (MCT_L0_IRQ + cpu >= ARRAY_SIZE(mct_irqs))
569
+
if (irq_idx >= ARRAY_SIZE(mct_irqs))
579
570
break;
580
-
mct_irq = mct_irqs[MCT_L0_IRQ + cpu];
571
+
mct_irq = mct_irqs[irq_idx];
581
572
582
573
irq_set_status_flags(mct_irq, IRQ_NOAUTOEN);
583
574
if (request_irq(mct_irq,
···
599
574
}
600
575
pcpu_mevt->evt.irq = mct_irq;
601
576
}
577
+
}
578
+
579
+
for_each_possible_cpu(cpu) {
580
+
struct mct_clock_event_device *mevt = per_cpu_ptr(&percpu_mct_tick, cpu);
581
+
582
+
if (cpu >= nr_local) {
583
+
err = -EINVAL;
584
+
goto out_irq;
585
+
}
586
+
587
+
mevt->base = EXYNOS4_MCT_L_BASE(local_idx[cpu]);
602
588
}
603
589
604
590
/* Install hotplug callbacks which configure the timer on this CPU */
···
641
605
642
606
static int __init mct_init_dt(struct device_node *np, unsigned int int_type)
643
607
{
608
+
bool frc_shared = of_property_read_bool(np, "samsung,frc-shared");
609
+
u32 local_idx[MCT_NR_LOCAL] = {0};
610
+
int nr_local;
644
611
int ret;
612
+
613
+
nr_local = of_property_count_u32_elems(np, "samsung,local-timers");
614
+
if (nr_local == 0)
615
+
return -EINVAL;
616
+
if (nr_local > 0) {
617
+
if (nr_local > ARRAY_SIZE(local_idx))
618
+
return -EINVAL;
619
+
620
+
ret = of_property_read_u32_array(np, "samsung,local-timers",
621
+
local_idx, nr_local);
622
+
if (ret)
623
+
return ret;
624
+
} else {
625
+
int i;
626
+
627
+
nr_local = ARRAY_SIZE(local_idx);
628
+
for (i = 0; i < nr_local; i++)
629
+
local_idx[i] = i;
630
+
}
645
631
646
632
ret = exynos4_timer_resources(np);
647
633
if (ret)
648
634
return ret;
649
635
650
-
ret = exynos4_timer_interrupts(np, int_type);
636
+
ret = exynos4_timer_interrupts(np, int_type, local_idx, nr_local);
651
637
if (ret)
652
638
return ret;
653
639
654
-
ret = exynos4_clocksource_init();
640
+
ret = exynos4_clocksource_init(frc_shared);
655
641
if (ret)
642
+
return ret;
643
+
644
+
/*
645
+
* When the FRC is shared with a main processor, this secondary
646
+
* processor cannot use the global comparator.
647
+
*/
648
+
if (frc_shared)
656
649
return ret;
657
650
658
651
return exynos4_clockevent_init();
+1
-1
drivers/clocksource/renesas-ostm.c
+1
-1
drivers/clocksource/renesas-ostm.c
+6
-1
drivers/clocksource/timer-gxp.c
+6
-1
drivers/clocksource/timer-gxp.c
···
171
171
{
172
172
struct platform_device *gxp_watchdog_device;
173
173
struct device *dev = &pdev->dev;
174
+
int ret;
174
175
175
176
if (!gxp_timer) {
176
177
pr_err("Gxp Timer not initialized, cannot create watchdog");
···
188
187
gxp_watchdog_device->dev.platform_data = gxp_timer->counter;
189
188
gxp_watchdog_device->dev.parent = dev;
190
189
191
-
return platform_device_add(gxp_watchdog_device);
190
+
ret = platform_device_add(gxp_watchdog_device);
191
+
if (ret)
192
+
platform_device_put(gxp_watchdog_device);
193
+
194
+
return ret;
192
195
}
193
196
194
197
static const struct of_device_id gxp_timer_of_match[] = {
+4
-2
drivers/clocksource/timer-imx-sysctr.c
+4
-2
drivers/clocksource/timer-imx-sysctr.c
···
134
134
if (ret)
135
135
return ret;
136
136
137
-
/* system counter clock is divided by 3 internally */
138
-
to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
137
+
if (!of_property_read_bool(np, "nxp,no-divider")) {
138
+
/* system counter clock is divided by 3 internally */
139
+
to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
140
+
}
139
141
140
142
sys_ctr_base = timer_of_base(&to_sysctr);
141
143
cmpcr = readl(sys_ctr_base + CMPCR);
+2
-1
drivers/clocksource/timer-sun4i.c
+2
-1
drivers/clocksource/timer-sun4i.c
···
26
26
#define TIMER_IRQ_EN_REG 0x00
27
27
#define TIMER_IRQ_EN(val) BIT(val)
28
28
#define TIMER_IRQ_ST_REG 0x04
29
+
#define TIMER_IRQ_CLEAR(val) BIT(val)
29
30
#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
30
31
#define TIMER_CTL_ENABLE BIT(0)
31
32
#define TIMER_CTL_RELOAD BIT(1)
···
124
123
125
124
static void sun4i_timer_clear_interrupt(void __iomem *base)
126
125
{
127
-
writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG);
126
+
writel(TIMER_IRQ_CLEAR(0), base + TIMER_IRQ_ST_REG);
128
127
}
129
128
130
129
static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
+433
-256
drivers/clocksource/timer-ti-dm.c
+433
-256
drivers/clocksource/timer-ti-dm.c
···
33
33
34
34
#include <clocksource/timer-ti-dm.h>
35
35
36
+
/*
37
+
* timer errata flags
38
+
*
39
+
* Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
40
+
* errata prevents us from using posted mode on these devices, unless the
41
+
* timer counter register is never read. For more details please refer to
42
+
* the OMAP3/4/5 errata documents.
43
+
*/
44
+
#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
45
+
46
+
/* posted mode types */
47
+
#define OMAP_TIMER_NONPOSTED 0x00
48
+
#define OMAP_TIMER_POSTED 0x01
49
+
50
+
/* register offsets with the write pending bit encoded */
51
+
#define WPSHIFT 16
52
+
53
+
#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
54
+
| (WP_NONE << WPSHIFT))
55
+
56
+
#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
57
+
| (WP_TCLR << WPSHIFT))
58
+
59
+
#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
60
+
| (WP_TCRR << WPSHIFT))
61
+
62
+
#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
63
+
| (WP_TLDR << WPSHIFT))
64
+
65
+
#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
66
+
| (WP_TTGR << WPSHIFT))
67
+
68
+
#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
69
+
| (WP_NONE << WPSHIFT))
70
+
71
+
#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
72
+
| (WP_TMAR << WPSHIFT))
73
+
74
+
#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
75
+
| (WP_NONE << WPSHIFT))
76
+
77
+
#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
78
+
| (WP_NONE << WPSHIFT))
79
+
80
+
#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
81
+
| (WP_NONE << WPSHIFT))
82
+
83
+
#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
84
+
| (WP_TPIR << WPSHIFT))
85
+
86
+
#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
87
+
| (WP_TNIR << WPSHIFT))
88
+
89
+
#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
90
+
| (WP_TCVR << WPSHIFT))
91
+
92
+
#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
93
+
(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
94
+
95
+
#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
96
+
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
97
+
98
+
struct timer_regs {
99
+
u32 ocp_cfg;
100
+
u32 tidr;
101
+
u32 tier;
102
+
u32 twer;
103
+
u32 tclr;
104
+
u32 tcrr;
105
+
u32 tldr;
106
+
u32 ttrg;
107
+
u32 twps;
108
+
u32 tmar;
109
+
u32 tcar1;
110
+
u32 tsicr;
111
+
u32 tcar2;
112
+
u32 tpir;
113
+
u32 tnir;
114
+
u32 tcvr;
115
+
u32 tocr;
116
+
u32 towr;
117
+
};
118
+
119
+
struct dmtimer {
120
+
struct omap_dm_timer cookie;
121
+
int id;
122
+
int irq;
123
+
struct clk *fclk;
124
+
125
+
void __iomem *io_base;
126
+
int irq_stat; /* TISR/IRQSTATUS interrupt status */
127
+
int irq_ena; /* irq enable */
128
+
int irq_dis; /* irq disable, only on v2 ip */
129
+
void __iomem *pend; /* write pending */
130
+
void __iomem *func_base; /* function register base */
131
+
132
+
atomic_t enabled;
133
+
unsigned long rate;
134
+
unsigned reserved:1;
135
+
unsigned posted:1;
136
+
unsigned omap1:1;
137
+
struct timer_regs context;
138
+
int revision;
139
+
u32 capability;
140
+
u32 errata;
141
+
struct platform_device *pdev;
142
+
struct list_head node;
143
+
struct notifier_block nb;
144
+
};
145
+
36
146
static u32 omap_reserved_systimers;
37
147
static LIST_HEAD(omap_timer_list);
38
148
static DEFINE_SPINLOCK(dm_timer_lock);
···
154
44
REQUEST_BY_NODE,
155
45
};
156
46
157
-
static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
158
-
int posted)
47
+
/**
48
+
* dmtimer_read - read timer registers in posted and non-posted mode
49
+
* @timer: timer pointer over which read operation to perform
50
+
* @reg: lowest byte holds the register offset
51
+
*
52
+
* The posted mode bit is encoded in reg. Note that in posted mode, write
53
+
* pending bit must be checked. Otherwise a read of a non completed write
54
+
* will produce an error.
55
+
*/
56
+
static inline u32 dmtimer_read(struct dmtimer *timer, u32 reg)
159
57
{
160
-
if (posted)
161
-
while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
58
+
u16 wp, offset;
59
+
60
+
wp = reg >> WPSHIFT;
61
+
offset = reg & 0xff;
62
+
63
+
/* Wait for a possible write pending bit in posted mode */
64
+
if (wp && timer->posted)
65
+
while (readl_relaxed(timer->pend) & wp)
162
66
cpu_relax();
163
67
164
-
return readl_relaxed(timer->func_base + (reg & 0xff));
68
+
return readl_relaxed(timer->func_base + offset);
165
69
}
166
70
167
-
static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
168
-
u32 reg, u32 val, int posted)
71
+
/**
72
+
* dmtimer_write - write timer registers in posted and non-posted mode
73
+
* @timer: timer pointer over which write operation is to perform
74
+
* @reg: lowest byte holds the register offset
75
+
* @value: data to write into the register
76
+
*
77
+
* The posted mode bit is encoded in reg. Note that in posted mode, the write
78
+
* pending bit must be checked. Otherwise a write on a register which has a
79
+
* pending write will be lost.
80
+
*/
81
+
static inline void dmtimer_write(struct dmtimer *timer, u32 reg, u32 val)
169
82
{
170
-
if (posted)
171
-
while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
83
+
u16 wp, offset;
84
+
85
+
wp = reg >> WPSHIFT;
86
+
offset = reg & 0xff;
87
+
88
+
/* Wait for a possible write pending bit in posted mode */
89
+
if (wp && timer->posted)
90
+
while (readl_relaxed(timer->pend) & wp)
172
91
cpu_relax();
173
92
174
-
writel_relaxed(val, timer->func_base + (reg & 0xff));
93
+
writel_relaxed(val, timer->func_base + offset);
175
94
}
176
95
177
-
static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
96
+
static inline void __omap_dm_timer_init_regs(struct dmtimer *timer)
178
97
{
179
98
u32 tidr;
180
99
···
211
72
tidr = readl_relaxed(timer->io_base);
212
73
if (!(tidr >> 16)) {
213
74
timer->revision = 1;
214
-
timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
215
-
timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
216
-
timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
75
+
timer->irq_stat = OMAP_TIMER_V1_STAT_OFFSET;
76
+
timer->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET;
77
+
timer->irq_dis = OMAP_TIMER_V1_INT_EN_OFFSET;
217
78
timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
218
79
timer->func_base = timer->io_base;
219
80
} else {
220
81
timer->revision = 2;
221
-
timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
222
-
timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
223
-
timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
82
+
timer->irq_stat = OMAP_TIMER_V2_IRQSTATUS - OMAP_TIMER_V2_FUNC_OFFSET;
83
+
timer->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET - OMAP_TIMER_V2_FUNC_OFFSET;
84
+
timer->irq_dis = OMAP_TIMER_V2_IRQENABLE_CLR - OMAP_TIMER_V2_FUNC_OFFSET;
224
85
timer->pend = timer->io_base +
225
86
_OMAP_TIMER_WRITE_PEND_OFFSET +
226
87
OMAP_TIMER_V2_FUNC_OFFSET;
···
238
99
* complete. Enabling this feature can improve performance for writing to the
239
100
* timer registers.
240
101
*/
241
-
static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
102
+
static inline void __omap_dm_timer_enable_posted(struct dmtimer *timer)
242
103
{
243
104
if (timer->posted)
244
105
return;
245
106
246
107
if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
247
108
timer->posted = OMAP_TIMER_NONPOSTED;
248
-
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
109
+
dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0);
249
110
return;
250
111
}
251
112
252
-
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
253
-
OMAP_TIMER_CTRL_POSTED, 0);
113
+
dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED);
254
114
timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
255
115
timer->posted = OMAP_TIMER_POSTED;
256
116
}
257
117
258
-
static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
259
-
int posted, unsigned long rate)
118
+
static inline void __omap_dm_timer_stop(struct dmtimer *timer,
119
+
unsigned long rate)
260
120
{
261
121
u32 l;
262
122
263
-
l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
123
+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
264
124
if (l & OMAP_TIMER_CTRL_ST) {
265
125
l &= ~0x1;
266
-
__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
126
+
dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
267
127
#ifdef CONFIG_ARCH_OMAP2PLUS
268
128
/* Readback to make sure write has completed */
269
-
__omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
129
+
dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
270
130
/*
271
131
* Wait for functional clock period x 3.5 to make sure that
272
132
* timer is stopped
···
275
137
}
276
138
277
139
/* Ack possibly pending interrupt */
278
-
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
140
+
dmtimer_write(timer, timer->irq_stat, OMAP_TIMER_INT_OVERFLOW);
279
141
}
280
142
281
-
static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
282
-
unsigned int value)
143
+
static inline void __omap_dm_timer_int_enable(struct dmtimer *timer,
144
+
unsigned int value)
283
145
{
284
-
writel_relaxed(value, timer->irq_ena);
285
-
__omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
146
+
dmtimer_write(timer, timer->irq_ena, value);
147
+
dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
286
148
}
287
149
288
150
static inline unsigned int
289
-
__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
151
+
__omap_dm_timer_read_counter(struct dmtimer *timer)
290
152
{
291
-
return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
153
+
return dmtimer_read(timer, OMAP_TIMER_COUNTER_REG);
292
154
}
293
155
294
-
static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
156
+
static inline void __omap_dm_timer_write_status(struct dmtimer *timer,
295
157
unsigned int value)
296
158
{
297
-
writel_relaxed(value, timer->irq_stat);
159
+
dmtimer_write(timer, timer->irq_stat, value);
298
160
}
299
161
300
-
/**
301
-
* omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
302
-
* @timer: timer pointer over which read operation to perform
303
-
* @reg: lowest byte holds the register offset
304
-
*
305
-
* The posted mode bit is encoded in reg. Note that in posted mode write
306
-
* pending bit must be checked. Otherwise a read of a non completed write
307
-
* will produce an error.
308
-
*/
309
-
static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
162
+
static void omap_timer_restore_context(struct dmtimer *timer)
310
163
{
311
-
WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
312
-
return __omap_dm_timer_read(timer, reg, timer->posted);
164
+
dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg);
165
+
166
+
dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer);
167
+
dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, timer->context.tcrr);
168
+
dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr);
169
+
dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar);
170
+
dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr);
171
+
dmtimer_write(timer, timer->irq_ena, timer->context.tier);
172
+
dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr);
313
173
}
314
174
315
-
/**
316
-
* omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
317
-
* @timer: timer pointer over which write operation is to perform
318
-
* @reg: lowest byte holds the register offset
319
-
* @value: data to write into the register
320
-
*
321
-
* The posted mode bit is encoded in reg. Note that in posted mode the write
322
-
* pending bit must be checked. Otherwise a write on a register which has a
323
-
* pending write will be lost.
324
-
*/
325
-
static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
326
-
u32 value)
175
+
static void omap_timer_save_context(struct dmtimer *timer)
327
176
{
328
-
WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
329
-
__omap_dm_timer_write(timer, reg, value, timer->posted);
330
-
}
177
+
timer->context.ocp_cfg = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
331
178
332
-
static void omap_timer_restore_context(struct omap_dm_timer *timer)
333
-
{
334
-
__omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET,
335
-
timer->context.ocp_cfg, 0);
336
-
337
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
338
-
timer->context.twer);
339
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
340
-
timer->context.tcrr);
341
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
342
-
timer->context.tldr);
343
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
344
-
timer->context.tmar);
345
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
346
-
timer->context.tsicr);
347
-
writel_relaxed(timer->context.tier, timer->irq_ena);
348
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
349
-
timer->context.tclr);
350
-
}
351
-
352
-
static void omap_timer_save_context(struct omap_dm_timer *timer)
353
-
{
354
-
timer->context.ocp_cfg =
355
-
__omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
356
-
357
-
timer->context.tclr =
358
-
omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
359
-
timer->context.twer =
360
-
omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG);
361
-
timer->context.tldr =
362
-
omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG);
363
-
timer->context.tmar =
364
-
omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG);
365
-
timer->context.tier = readl_relaxed(timer->irq_ena);
366
-
timer->context.tsicr =
367
-
omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG);
179
+
timer->context.tclr = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
180
+
timer->context.twer = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG);
181
+
timer->context.tldr = dmtimer_read(timer, OMAP_TIMER_LOAD_REG);
182
+
timer->context.tmar = dmtimer_read(timer, OMAP_TIMER_MATCH_REG);
183
+
timer->context.tier = dmtimer_read(timer, timer->irq_ena);
184
+
timer->context.tsicr = dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG);
368
185
}
369
186
370
187
static int omap_timer_context_notifier(struct notifier_block *nb,
371
188
unsigned long cmd, void *v)
372
189
{
373
-
struct omap_dm_timer *timer;
190
+
struct dmtimer *timer;
374
191
375
-
timer = container_of(nb, struct omap_dm_timer, nb);
192
+
timer = container_of(nb, struct dmtimer, nb);
376
193
377
194
switch (cmd) {
378
195
case CPU_CLUSTER_PM_ENTER:
···
349
256
return NOTIFY_OK;
350
257
}
351
258
352
-
static int omap_dm_timer_reset(struct omap_dm_timer *timer)
259
+
static int omap_dm_timer_reset(struct dmtimer *timer)
353
260
{
354
261
u32 l, timeout = 100000;
355
262
356
263
if (timer->revision != 1)
357
264
return -EINVAL;
358
265
359
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
266
+
dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
360
267
361
268
do {
362
-
l = __omap_dm_timer_read(timer,
363
-
OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
269
+
l = dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET);
364
270
} while (!l && timeout--);
365
271
366
272
if (!timeout) {
···
368
276
}
369
277
370
278
/* Configure timer for smart-idle mode */
371
-
l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
279
+
l = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
372
280
l |= 0x2 << 0x3;
373
-
__omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
281
+
dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l);
374
282
375
283
timer->posted = 0;
376
284
377
285
return 0;
378
286
}
379
287
380
-
static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
288
+
/*
289
+
* Functions exposed to PWM and remoteproc drivers via platform_data.
290
+
* Do not use these in the driver, these will get deprecated and will
291
+
* will be replaced by Linux generic framework functions such as
292
+
* chained interrupts and clock framework.
293
+
*/
294
+
static struct dmtimer *to_dmtimer(struct omap_dm_timer *cookie)
295
+
{
296
+
if (!cookie)
297
+
return NULL;
298
+
299
+
return container_of(cookie, struct dmtimer, cookie);
300
+
}
301
+
302
+
static int omap_dm_timer_set_source(struct omap_dm_timer *cookie, int source)
381
303
{
382
304
int ret;
383
305
const char *parent_name;
384
306
struct clk *parent;
385
307
struct dmtimer_platform_data *pdata;
308
+
struct dmtimer *timer;
386
309
310
+
timer = to_dmtimer(cookie);
387
311
if (unlikely(!timer) || IS_ERR(timer->fclk))
388
312
return -EINVAL;
389
313
···
424
316
* use the clock framework to set the parent clock. To be removed
425
317
* once OMAP1 migrated to using clock framework for dmtimers
426
318
*/
427
-
if (pdata && pdata->set_timer_src)
319
+
if (timer->omap1 && pdata && pdata->set_timer_src)
428
320
return pdata->set_timer_src(timer->pdev, source);
429
321
430
322
#if defined(CONFIG_COMMON_CLK)
···
449
341
return ret;
450
342
}
451
343
452
-
static void omap_dm_timer_enable(struct omap_dm_timer *timer)
344
+
static void omap_dm_timer_enable(struct omap_dm_timer *cookie)
453
345
{
454
-
pm_runtime_get_sync(&timer->pdev->dev);
455
-
}
456
-
457
-
static void omap_dm_timer_disable(struct omap_dm_timer *timer)
458
-
{
459
-
pm_runtime_put_sync(&timer->pdev->dev);
460
-
}
461
-
462
-
static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
463
-
{
346
+
struct dmtimer *timer = to_dmtimer(cookie);
347
+
struct device *dev = &timer->pdev->dev;
464
348
int rc;
465
349
466
-
/*
467
-
* FIXME: OMAP1 devices do not use the clock framework for dmtimers so
468
-
* do not call clk_get() for these devices.
469
-
*/
470
-
if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
471
-
timer->fclk = clk_get(&timer->pdev->dev, "fck");
472
-
if (WARN_ON_ONCE(IS_ERR(timer->fclk))) {
473
-
dev_err(&timer->pdev->dev, ": No fclk handle.\n");
474
-
return -EINVAL;
475
-
}
476
-
}
350
+
rc = pm_runtime_resume_and_get(dev);
351
+
if (rc)
352
+
dev_err(dev, "could not enable timer\n");
353
+
}
477
354
478
-
omap_dm_timer_enable(timer);
355
+
static void omap_dm_timer_disable(struct omap_dm_timer *cookie)
356
+
{
357
+
struct dmtimer *timer = to_dmtimer(cookie);
358
+
struct device *dev = &timer->pdev->dev;
359
+
360
+
pm_runtime_put_sync(dev);
361
+
}
362
+
363
+
static int omap_dm_timer_prepare(struct dmtimer *timer)
364
+
{
365
+
struct device *dev = &timer->pdev->dev;
366
+
int rc;
367
+
368
+
rc = pm_runtime_resume_and_get(dev);
369
+
if (rc)
370
+
return rc;
479
371
480
372
if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
481
373
rc = omap_dm_timer_reset(timer);
482
374
if (rc) {
483
-
omap_dm_timer_disable(timer);
375
+
pm_runtime_put_sync(dev);
484
376
return rc;
485
377
}
486
378
}
487
379
488
380
__omap_dm_timer_enable_posted(timer);
489
-
omap_dm_timer_disable(timer);
381
+
pm_runtime_put_sync(dev);
490
382
491
383
return 0;
492
384
}
···
496
388
return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
497
389
}
498
390
499
-
int omap_dm_timer_reserve_systimer(int id)
391
+
static struct dmtimer *_omap_dm_timer_request(int req_type, void *data)
500
392
{
501
-
if (omap_dm_timer_reserved_systimer(id))
502
-
return -ENODEV;
503
-
504
-
omap_reserved_systimers |= (1 << (id - 1));
505
-
506
-
return 0;
507
-
}
508
-
509
-
static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
510
-
{
511
-
struct omap_dm_timer *timer = NULL, *t;
393
+
struct dmtimer *timer = NULL, *t;
512
394
struct device_node *np = NULL;
513
395
unsigned long flags;
514
396
u32 cap = 0;
···
582
484
583
485
static struct omap_dm_timer *omap_dm_timer_request(void)
584
486
{
585
-
return _omap_dm_timer_request(REQUEST_ANY, NULL);
487
+
struct dmtimer *timer;
488
+
489
+
timer = _omap_dm_timer_request(REQUEST_ANY, NULL);
490
+
if (!timer)
491
+
return NULL;
492
+
493
+
return &timer->cookie;
586
494
}
587
495
588
496
static struct omap_dm_timer *omap_dm_timer_request_specific(int id)
589
497
{
498
+
struct dmtimer *timer;
499
+
590
500
/* Requesting timer by ID is not supported when device tree is used */
591
501
if (of_have_populated_dt()) {
592
502
pr_warn("%s: Please use omap_dm_timer_request_by_node()\n",
···
602
496
return NULL;
603
497
}
604
498
605
-
return _omap_dm_timer_request(REQUEST_BY_ID, &id);
606
-
}
499
+
timer = _omap_dm_timer_request(REQUEST_BY_ID, &id);
500
+
if (!timer)
501
+
return NULL;
607
502
608
-
/**
609
-
* omap_dm_timer_request_by_cap - Request a timer by capability
610
-
* @cap: Bit mask of capabilities to match
611
-
*
612
-
* Find a timer based upon capabilities bit mask. Callers of this function
613
-
* should use the definitions found in the plat/dmtimer.h file under the
614
-
* comment "timer capabilities used in hwmod database". Returns pointer to
615
-
* timer handle on success and a NULL pointer on failure.
616
-
*/
617
-
struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
618
-
{
619
-
return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
503
+
return &timer->cookie;
620
504
}
621
505
622
506
/**
···
618
522
*/
619
523
static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
620
524
{
525
+
struct dmtimer *timer;
526
+
621
527
if (!np)
622
528
return NULL;
623
529
624
-
return _omap_dm_timer_request(REQUEST_BY_NODE, np);
530
+
timer = _omap_dm_timer_request(REQUEST_BY_NODE, np);
531
+
if (!timer)
532
+
return NULL;
533
+
534
+
return &timer->cookie;
625
535
}
626
536
627
-
static int omap_dm_timer_free(struct omap_dm_timer *timer)
537
+
static int omap_dm_timer_free(struct omap_dm_timer *cookie)
628
538
{
539
+
struct dmtimer *timer;
540
+
541
+
timer = to_dmtimer(cookie);
629
542
if (unlikely(!timer))
630
543
return -EINVAL;
631
-
632
-
clk_put(timer->fclk);
633
544
634
545
WARN_ON(!timer->reserved);
635
546
timer->reserved = 0;
636
547
return 0;
637
548
}
638
549
639
-
int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
550
+
int omap_dm_timer_get_irq(struct omap_dm_timer *cookie)
640
551
{
552
+
struct dmtimer *timer = to_dmtimer(cookie);
641
553
if (timer)
642
554
return timer->irq;
643
555
return -EINVAL;
···
654
550
#if defined(CONFIG_ARCH_OMAP1)
655
551
#include <linux/soc/ti/omap1-io.h>
656
552
657
-
static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
553
+
static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie)
658
554
{
659
555
return NULL;
660
556
}
···
666
562
__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
667
563
{
668
564
int i = 0;
669
-
struct omap_dm_timer *timer = NULL;
565
+
struct dmtimer *timer = NULL;
670
566
unsigned long flags;
671
567
672
568
/* If ARMXOR cannot be idled this function call is unnecessary */
···
678
574
list_for_each_entry(timer, &omap_timer_list, node) {
679
575
u32 l;
680
576
681
-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
577
+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
682
578
if (l & OMAP_TIMER_CTRL_ST) {
683
579
if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
684
580
inputmask &= ~(1 << 1);
···
694
590
695
591
#else
696
592
697
-
static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
593
+
static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie)
698
594
{
595
+
struct dmtimer *timer = to_dmtimer(cookie);
596
+
699
597
if (timer && !IS_ERR(timer->fclk))
700
598
return timer->fclk;
701
599
return NULL;
···
712
606
713
607
#endif
714
608
715
-
int omap_dm_timer_trigger(struct omap_dm_timer *timer)
609
+
static int omap_dm_timer_start(struct omap_dm_timer *cookie)
716
610
{
717
-
if (unlikely(!timer || !atomic_read(&timer->enabled))) {
718
-
pr_err("%s: timer not available or enabled.\n", __func__);
719
-
return -EINVAL;
720
-
}
721
-
722
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
723
-
return 0;
724
-
}
725
-
726
-
static int omap_dm_timer_start(struct omap_dm_timer *timer)
727
-
{
611
+
struct dmtimer *timer;
612
+
struct device *dev;
613
+
int rc;
728
614
u32 l;
729
615
616
+
timer = to_dmtimer(cookie);
730
617
if (unlikely(!timer))
731
618
return -EINVAL;
732
619
733
-
omap_dm_timer_enable(timer);
620
+
dev = &timer->pdev->dev;
734
621
735
-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
622
+
rc = pm_runtime_resume_and_get(dev);
623
+
if (rc)
624
+
return rc;
625
+
626
+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
736
627
if (!(l & OMAP_TIMER_CTRL_ST)) {
737
628
l |= OMAP_TIMER_CTRL_ST;
738
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
629
+
dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
739
630
}
740
631
741
632
return 0;
742
633
}
743
634
744
-
static int omap_dm_timer_stop(struct omap_dm_timer *timer)
635
+
static int omap_dm_timer_stop(struct omap_dm_timer *cookie)
745
636
{
637
+
struct dmtimer *timer;
638
+
struct device *dev;
746
639
unsigned long rate = 0;
747
640
641
+
timer = to_dmtimer(cookie);
748
642
if (unlikely(!timer))
749
643
return -EINVAL;
750
644
751
-
if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
645
+
dev = &timer->pdev->dev;
646
+
647
+
if (!timer->omap1)
752
648
rate = clk_get_rate(timer->fclk);
753
649
754
-
__omap_dm_timer_stop(timer, timer->posted, rate);
650
+
__omap_dm_timer_stop(timer, rate);
755
651
756
-
omap_dm_timer_disable(timer);
652
+
pm_runtime_put_sync(dev);
653
+
757
654
return 0;
758
655
}
759
656
760
-
static int omap_dm_timer_set_load(struct omap_dm_timer *timer,
657
+
static int omap_dm_timer_set_load(struct omap_dm_timer *cookie,
761
658
unsigned int load)
762
659
{
660
+
struct dmtimer *timer;
661
+
struct device *dev;
662
+
int rc;
663
+
664
+
timer = to_dmtimer(cookie);
763
665
if (unlikely(!timer))
764
666
return -EINVAL;
765
667
766
-
omap_dm_timer_enable(timer);
767
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
668
+
dev = &timer->pdev->dev;
669
+
rc = pm_runtime_resume_and_get(dev);
670
+
if (rc)
671
+
return rc;
768
672
769
-
omap_dm_timer_disable(timer);
673
+
dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load);
674
+
675
+
pm_runtime_put_sync(dev);
676
+
770
677
return 0;
771
678
}
772
679
773
-
static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
680
+
static int omap_dm_timer_set_match(struct omap_dm_timer *cookie, int enable,
774
681
unsigned int match)
775
682
{
683
+
struct dmtimer *timer;
684
+
struct device *dev;
685
+
int rc;
776
686
u32 l;
777
687
688
+
timer = to_dmtimer(cookie);
778
689
if (unlikely(!timer))
779
690
return -EINVAL;
780
691
781
-
omap_dm_timer_enable(timer);
782
-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
692
+
dev = &timer->pdev->dev;
693
+
rc = pm_runtime_resume_and_get(dev);
694
+
if (rc)
695
+
return rc;
696
+
697
+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
783
698
if (enable)
784
699
l |= OMAP_TIMER_CTRL_CE;
785
700
else
786
701
l &= ~OMAP_TIMER_CTRL_CE;
787
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
788
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
702
+
dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match);
703
+
dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
789
704
790
-
omap_dm_timer_disable(timer);
705
+
pm_runtime_put_sync(dev);
706
+
791
707
return 0;
792
708
}
793
709
794
-
static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
710
+
static int omap_dm_timer_set_pwm(struct omap_dm_timer *cookie, int def_on,
795
711
int toggle, int trigger, int autoreload)
796
712
{
713
+
struct dmtimer *timer;
714
+
struct device *dev;
715
+
int rc;
797
716
u32 l;
798
717
718
+
timer = to_dmtimer(cookie);
799
719
if (unlikely(!timer))
800
720
return -EINVAL;
801
721
802
-
omap_dm_timer_enable(timer);
803
-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
722
+
dev = &timer->pdev->dev;
723
+
rc = pm_runtime_resume_and_get(dev);
724
+
if (rc)
725
+
return rc;
726
+
727
+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
804
728
l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
805
729
OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR);
806
730
if (def_on)
···
840
704
l |= trigger << 10;
841
705
if (autoreload)
842
706
l |= OMAP_TIMER_CTRL_AR;
843
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
707
+
dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
844
708
845
-
omap_dm_timer_disable(timer);
709
+
pm_runtime_put_sync(dev);
710
+
846
711
return 0;
847
712
}
848
713
849
-
static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer)
714
+
static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *cookie)
850
715
{
716
+
struct dmtimer *timer;
717
+
struct device *dev;
718
+
int rc;
851
719
u32 l;
852
720
721
+
timer = to_dmtimer(cookie);
853
722
if (unlikely(!timer))
854
723
return -EINVAL;
855
724
856
-
omap_dm_timer_enable(timer);
857
-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
858
-
omap_dm_timer_disable(timer);
725
+
dev = &timer->pdev->dev;
726
+
rc = pm_runtime_resume_and_get(dev);
727
+
if (rc)
728
+
return rc;
729
+
730
+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
731
+
732
+
pm_runtime_put_sync(dev);
859
733
860
734
return l;
861
735
}
862
736
863
-
static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
864
-
int prescaler)
737
+
static int omap_dm_timer_set_prescaler(struct omap_dm_timer *cookie,
738
+
int prescaler)
865
739
{
740
+
struct dmtimer *timer;
741
+
struct device *dev;
742
+
int rc;
866
743
u32 l;
867
744
745
+
timer = to_dmtimer(cookie);
868
746
if (unlikely(!timer) || prescaler < -1 || prescaler > 7)
869
747
return -EINVAL;
870
748
871
-
omap_dm_timer_enable(timer);
872
-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
749
+
dev = &timer->pdev->dev;
750
+
rc = pm_runtime_resume_and_get(dev);
751
+
if (rc)
752
+
return rc;
753
+
754
+
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
873
755
l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
874
756
if (prescaler >= 0) {
875
757
l |= OMAP_TIMER_CTRL_PRE;
876
758
l |= prescaler << 2;
877
759
}
878
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
760
+
dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
879
761
880
-
omap_dm_timer_disable(timer);
762
+
pm_runtime_put_sync(dev);
763
+
881
764
return 0;
882
765
}
883
766
884
-
static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
767
+
static int omap_dm_timer_set_int_enable(struct omap_dm_timer *cookie,
885
768
unsigned int value)
886
769
{
770
+
struct dmtimer *timer;
771
+
struct device *dev;
772
+
int rc;
773
+
774
+
timer = to_dmtimer(cookie);
887
775
if (unlikely(!timer))
888
776
return -EINVAL;
889
777
890
-
omap_dm_timer_enable(timer);
778
+
dev = &timer->pdev->dev;
779
+
rc = pm_runtime_resume_and_get(dev);
780
+
if (rc)
781
+
return rc;
782
+
891
783
__omap_dm_timer_int_enable(timer, value);
892
784
893
-
omap_dm_timer_disable(timer);
785
+
pm_runtime_put_sync(dev);
786
+
894
787
return 0;
895
788
}
896
789
···
930
765
*
931
766
* Disables the specified timer interrupts for a timer.
932
767
*/
933
-
static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
768
+
static int omap_dm_timer_set_int_disable(struct omap_dm_timer *cookie, u32 mask)
934
769
{
770
+
struct dmtimer *timer;
771
+
struct device *dev;
935
772
u32 l = mask;
773
+
int rc;
936
774
775
+
timer = to_dmtimer(cookie);
937
776
if (unlikely(!timer))
938
777
return -EINVAL;
939
778
940
-
omap_dm_timer_enable(timer);
779
+
dev = &timer->pdev->dev;
780
+
rc = pm_runtime_resume_and_get(dev);
781
+
if (rc)
782
+
return rc;
941
783
942
784
if (timer->revision == 1)
943
-
l = readl_relaxed(timer->irq_ena) & ~mask;
785
+
l = dmtimer_read(timer, timer->irq_ena) & ~mask;
944
786
945
-
writel_relaxed(l, timer->irq_dis);
946
-
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
947
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
787
+
dmtimer_write(timer, timer->irq_dis, l);
788
+
l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
789
+
dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
948
790
949
-
omap_dm_timer_disable(timer);
791
+
pm_runtime_put_sync(dev);
792
+
950
793
return 0;
951
794
}
952
795
953
-
static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
796
+
static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *cookie)
954
797
{
798
+
struct dmtimer *timer;
955
799
unsigned int l;
956
800
801
+
timer = to_dmtimer(cookie);
957
802
if (unlikely(!timer || !atomic_read(&timer->enabled))) {
958
803
pr_err("%s: timer not available or enabled.\n", __func__);
959
804
return 0;
960
805
}
961
806
962
-
l = readl_relaxed(timer->irq_stat);
807
+
l = dmtimer_read(timer, timer->irq_stat);
963
808
964
809
return l;
965
810
}
966
811
967
-
static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
812
+
static int omap_dm_timer_write_status(struct omap_dm_timer *cookie, unsigned int value)
968
813
{
814
+
struct dmtimer *timer;
815
+
816
+
timer = to_dmtimer(cookie);
969
817
if (unlikely(!timer || !atomic_read(&timer->enabled)))
970
818
return -EINVAL;
971
819
···
987
809
return 0;
988
810
}
989
811
990
-
static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
812
+
static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *cookie)
991
813
{
814
+
struct dmtimer *timer;
815
+
816
+
timer = to_dmtimer(cookie);
992
817
if (unlikely(!timer || !atomic_read(&timer->enabled))) {
993
818
pr_err("%s: timer not iavailable or enabled.\n", __func__);
994
819
return 0;
995
820
}
996
821
997
-
return __omap_dm_timer_read_counter(timer, timer->posted);
822
+
return __omap_dm_timer_read_counter(timer);
998
823
}
999
824
1000
-
static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
825
+
static int omap_dm_timer_write_counter(struct omap_dm_timer *cookie, unsigned int value)
1001
826
{
827
+
struct dmtimer *timer;
828
+
829
+
timer = to_dmtimer(cookie);
1002
830
if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1003
831
pr_err("%s: timer not available or enabled.\n", __func__);
1004
832
return -EINVAL;
1005
833
}
1006
834
1007
-
omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
835
+
dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value);
1008
836
1009
837
/* Save the context */
1010
838
timer->context.tcrr = value;
1011
839
return 0;
1012
840
}
1013
841
1014
-
int omap_dm_timers_active(void)
1015
-
{
1016
-
struct omap_dm_timer *timer;
1017
-
1018
-
list_for_each_entry(timer, &omap_timer_list, node) {
1019
-
if (!timer->reserved)
1020
-
continue;
1021
-
1022
-
if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
1023
-
OMAP_TIMER_CTRL_ST) {
1024
-
return 1;
1025
-
}
1026
-
}
1027
-
return 0;
1028
-
}
1029
-
1030
842
static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev)
1031
843
{
1032
-
struct omap_dm_timer *timer = dev_get_drvdata(dev);
844
+
struct dmtimer *timer = dev_get_drvdata(dev);
1033
845
1034
846
atomic_set(&timer->enabled, 0);
1035
847
···
1033
865
1034
866
static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev)
1035
867
{
1036
-
struct omap_dm_timer *timer = dev_get_drvdata(dev);
868
+
struct dmtimer *timer = dev_get_drvdata(dev);
1037
869
1038
870
if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base)
1039
871
omap_timer_restore_context(timer);
···
1060
892
static int omap_dm_timer_probe(struct platform_device *pdev)
1061
893
{
1062
894
unsigned long flags;
1063
-
struct omap_dm_timer *timer;
895
+
struct dmtimer *timer;
1064
896
struct device *dev = &pdev->dev;
1065
897
const struct dmtimer_platform_data *pdata;
1066
898
int ret;
···
1084
916
if (timer->irq < 0)
1085
917
return timer->irq;
1086
918
1087
-
timer->fclk = ERR_PTR(-ENODEV);
1088
919
timer->io_base = devm_platform_ioremap_resource(pdev, 0);
1089
920
if (IS_ERR(timer->io_base))
1090
921
return PTR_ERR(timer->io_base);
···
1105
938
timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
1106
939
}
1107
940
941
+
timer->omap1 = timer->capability & OMAP_TIMER_NEEDS_RESET;
942
+
943
+
/* OMAP1 devices do not yet use the clock framework for dmtimers */
944
+
if (!timer->omap1) {
945
+
timer->fclk = devm_clk_get(dev, "fck");
946
+
if (IS_ERR(timer->fclk))
947
+
return PTR_ERR(timer->fclk);
948
+
} else {
949
+
timer->fclk = ERR_PTR(-ENODEV);
950
+
}
951
+
1108
952
if (!(timer->capability & OMAP_TIMER_ALWON)) {
1109
953
timer->nb.notifier_call = omap_timer_context_notifier;
1110
954
cpu_pm_register_notifier(&timer->nb);
···
1128
950
pm_runtime_enable(dev);
1129
951
1130
952
if (!timer->reserved) {
1131
-
ret = pm_runtime_get_sync(dev);
1132
-
if (ret < 0) {
953
+
ret = pm_runtime_resume_and_get(dev);
954
+
if (ret) {
1133
955
dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
1134
956
__func__);
1135
-
goto err_get_sync;
957
+
goto err_disable;
1136
958
}
1137
959
__omap_dm_timer_init_regs(timer);
1138
960
pm_runtime_put(dev);
···
1147
969
1148
970
return 0;
1149
971
1150
-
err_get_sync:
1151
-
pm_runtime_put_noidle(dev);
972
+
err_disable:
1152
973
pm_runtime_disable(dev);
1153
974
return ret;
1154
975
}
···
1162
985
*/
1163
986
static int omap_dm_timer_remove(struct platform_device *pdev)
1164
987
{
1165
-
struct omap_dm_timer *timer;
988
+
struct dmtimer *timer;
1166
989
unsigned long flags;
1167
990
int ret = -EINVAL;
1168
991
-112
include/clocksource/timer-ti-dm.h
-112
include/clocksource/timer-ti-dm.h
···
52
52
#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
53
53
#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
54
54
55
-
/* posted mode types */
56
-
#define OMAP_TIMER_NONPOSTED 0x00
57
-
#define OMAP_TIMER_POSTED 0x01
58
-
59
55
/* timer capabilities used in hwmod database */
60
56
#define OMAP_TIMER_SECURE 0x80000000
61
57
#define OMAP_TIMER_ALWON 0x40000000
···
59
63
#define OMAP_TIMER_NEEDS_RESET 0x10000000
60
64
#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
61
65
62
-
/*
63
-
* timer errata flags
64
-
*
65
-
* Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
66
-
* errata prevents us from using posted mode on these devices, unless the
67
-
* timer counter register is never read. For more details please refer to
68
-
* the OMAP3/4/5 errata documents.
69
-
*/
70
-
#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
71
-
72
-
struct timer_regs {
73
-
u32 ocp_cfg;
74
-
u32 tidr;
75
-
u32 tier;
76
-
u32 twer;
77
-
u32 tclr;
78
-
u32 tcrr;
79
-
u32 tldr;
80
-
u32 ttrg;
81
-
u32 twps;
82
-
u32 tmar;
83
-
u32 tcar1;
84
-
u32 tsicr;
85
-
u32 tcar2;
86
-
u32 tpir;
87
-
u32 tnir;
88
-
u32 tcvr;
89
-
u32 tocr;
90
-
u32 towr;
91
-
};
92
-
93
66
struct omap_dm_timer {
94
-
int id;
95
-
int irq;
96
-
struct clk *fclk;
97
-
98
-
void __iomem *io_base;
99
-
void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
100
-
void __iomem *irq_ena; /* irq enable */
101
-
void __iomem *irq_dis; /* irq disable, only on v2 ip */
102
-
void __iomem *pend; /* write pending */
103
-
void __iomem *func_base; /* function register base */
104
-
105
-
atomic_t enabled;
106
-
unsigned long rate;
107
-
unsigned reserved:1;
108
-
unsigned posted:1;
109
-
struct timer_regs context;
110
-
int revision;
111
-
u32 capability;
112
-
u32 errata;
113
-
struct platform_device *pdev;
114
-
struct list_head node;
115
-
struct notifier_block nb;
116
67
};
117
-
118
-
int omap_dm_timer_reserve_systimer(int id);
119
-
struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
120
68
121
69
int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
122
70
123
71
u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
124
-
125
-
int omap_dm_timer_trigger(struct omap_dm_timer *timer);
126
-
127
-
int omap_dm_timers_active(void);
128
72
129
73
/*
130
74
* Do not use the defines below, they are not needed. They should be only
···
134
198
#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
135
199
#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
136
200
#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
137
-
138
-
/* register offsets with the write pending bit encoded */
139
-
#define WPSHIFT 16
140
-
141
-
#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
142
-
| (WP_NONE << WPSHIFT))
143
-
144
-
#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
145
-
| (WP_TCLR << WPSHIFT))
146
-
147
-
#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
148
-
| (WP_TCRR << WPSHIFT))
149
-
150
-
#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
151
-
| (WP_TLDR << WPSHIFT))
152
-
153
-
#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
154
-
| (WP_TTGR << WPSHIFT))
155
-
156
-
#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
157
-
| (WP_NONE << WPSHIFT))
158
-
159
-
#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
160
-
| (WP_TMAR << WPSHIFT))
161
-
162
-
#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
163
-
| (WP_NONE << WPSHIFT))
164
-
165
-
#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
166
-
| (WP_NONE << WPSHIFT))
167
-
168
-
#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
169
-
| (WP_NONE << WPSHIFT))
170
-
171
-
#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
172
-
| (WP_TPIR << WPSHIFT))
173
-
174
-
#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
175
-
| (WP_TNIR << WPSHIFT))
176
-
177
-
#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
178
-
| (WP_TCVR << WPSHIFT))
179
-
180
-
#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
181
-
(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
182
-
183
-
#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
184
-
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
185
201
186
202
#endif /* __CLOCKSOURCE_DMTIMER_H */