Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'renesas-dts-for-v6.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.18 (take two)
- Add pin control and I2C support for the RZ/N2H SoC and its
evaluation board,
- Add LED, EEPROM, eMMC, SD card, watchdog, and USB2.0 support for the
RZ/T2H and RZ/N2H SoCs and their evaluation boards,
- Add I3C support for the RZ/V2H and RZ/V2N SoCs,
- Add IMX219 and IMX462 camera overlay support for the Sparrow Hawk
board,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (26 commits)
arm64: dts: renesas: sparrow-hawk-fan-pwm: Rework hwmon comment
arm64: dts: renesas: sparrow-hawk: Add overlay for IMX462 on J2
arm64: dts: renesas: sparrow-hawk: Add overlay for IMX462 on J1
arm64: dts: renesas: sparrow-hawk: Add overlay for IMX219 on J2
arm64: dts: renesas: sparrow-hawk: Add overlay for IMX219 on J1
arm64: dts: renesas: rcar: Rename dsi-encoder to dsi
arm64: dts: renesas: r9a09g056: Add I3C node
arm64: dts: renesas: r9a09g057: Add I3C node
arm64: dts: renesas: rzt2h-n2h-evk: Enable USB2.0 support
arm64: dts: renesas: r9a09g047e57-smarc: Use Schmitt input for NMI function
arm64: dts: renesas: r9a09g047e57-smarc: Fix gpio key's pin control node
arm64: dts: renesas: r9a09g047: Enable Tx coe support
arm64: dts: renesas: r9a09g087: Add USB2.0 support
arm64: dts: renesas: r9a09g077: Add USB2.0 support
arm64: dts: renesas: rzt2h-n2h-evk-common: Enable WDT2
arm64: dts: renesas: r9a09g087: Add WDT nodes
arm64: dts: renesas: r9a09g077: Add WDT nodes
arm64: dts: renesas: rzt2h-rzn2h-evk: Enable SD card slot
arm64: dts: renesas: rzt2h-rzn2h-evk: Enable MicroSD card slot
arm64: dts: renesas: rzt2h-rzn2h-evk: Enable eMMC
...
Link: https://lore.kernel.org/r/cover.1757669917.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+1357
-27
+12
arch/arm64/boot/dts/renesas/Makefile
+12
arch/arm64/boot/dts/renesas/Makefile
···
96
96
97
97
DTC_FLAGS_r8a779g3-sparrow-hawk += -Wno-spi_bus_bridge
98
98
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk.dtb
99
+
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx219.dtbo
100
+
r8a779g3-sparrow-hawk-camera-j1-imx219-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j1-imx219.dtbo
101
+
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx219.dtb
102
+
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx462.dtbo
103
+
r8a779g3-sparrow-hawk-camera-j1-imx462-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j1-imx462.dtbo
104
+
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx462.dtb
105
+
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtbo
106
+
r8a779g3-sparrow-hawk-camera-j2-imx219-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j2-imx219.dtbo
107
+
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtb
108
+
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx462.dtbo
109
+
r8a779g3-sparrow-hawk-camera-j2-imx462-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j2-imx462.dtbo
110
+
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx462.dtb
99
111
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtbo
100
112
r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo
101
113
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb
+2
-2
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+2
-2
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
···
2949
2949
};
2950
2950
};
2951
2951
2952
-
dsi0: dsi-encoder@fed80000 {
2952
+
dsi0: dsi@fed80000 {
2953
2953
compatible = "renesas,r8a779a0-dsi-csi2-tx";
2954
2954
reg = <0 0xfed80000 0 0x10000>;
2955
2955
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
···
2977
2977
};
2978
2978
};
2979
2979
2980
-
dsi1: dsi-encoder@fed90000 {
2980
+
dsi1: dsi@fed90000 {
2981
2981
compatible = "renesas,r8a779a0-dsi-csi2-tx";
2982
2982
reg = <0 0xfed90000 0 0x10000>;
2983
2983
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+2
-2
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+2
-2
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
···
2476
2476
};
2477
2477
};
2478
2478
2479
-
dsi0: dsi-encoder@fed80000 {
2479
+
dsi0: dsi@fed80000 {
2480
2480
compatible = "renesas,r8a779g0-dsi-csi2-tx";
2481
2481
reg = <0 0xfed80000 0 0x10000>;
2482
2482
clocks = <&cpg CPG_MOD 415>,
···
2505
2505
};
2506
2506
};
2507
2507
2508
-
dsi1: dsi-encoder@fed90000 {
2508
+
dsi1: dsi@fed90000 {
2509
2509
compatible = "renesas,r8a779g0-dsi-csi2-tx";
2510
2510
reg = <0 0xfed90000 0 0x10000>;
2511
2511
clocks = <&cpg CPG_MOD 416>,
+116
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx219.dtso
+116
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx219.dtso
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Overlay for an IMX219 camera sensor on connector J1 on R-Car V4H
4
+
* ES3.0 Sparrow Hawk board.
5
+
*
6
+
* Copyright 2025 Renesas Electronics Corp.
7
+
* Copyright 2025 Niklas Söderlund <niklas.soderlund@ragnatech.se>
8
+
*/
9
+
10
+
/dts-v1/;
11
+
/plugin/;
12
+
13
+
#include <dt-bindings/gpio/gpio.h>
14
+
#include <dt-bindings/media/video-interfaces.h>
15
+
16
+
&{/} {
17
+
clk_cam_j1: clk-cam-j1 {
18
+
compatible = "fixed-clock";
19
+
#clock-cells = <0>;
20
+
clock-frequency = <24000000>;
21
+
};
22
+
23
+
/* Page 29 / CSI_IF_CN / J1 */
24
+
reg_cam_j1: reg-cam-j1 {
25
+
compatible = "regulator-fixed";
26
+
regulator-name = "cam-J1";
27
+
enable-active-high;
28
+
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
29
+
};
30
+
};
31
+
32
+
&i2c1 {
33
+
#address-cells = <1>;
34
+
#size-cells = <0>;
35
+
status = "okay";
36
+
37
+
cam@10 {
38
+
compatible = "sony,imx219";
39
+
reg = <0x10>;
40
+
41
+
clocks = <&clk_cam_j1>;
42
+
43
+
VANA-supply = <®_cam_j1>;
44
+
VDIG-supply = <®_cam_j1>;
45
+
VDDL-supply = <®_cam_j1>;
46
+
47
+
orientation = <2>;
48
+
rotation = <0>;
49
+
50
+
port {
51
+
imx219_j1_out: endpoint {
52
+
clock-noncontinuous;
53
+
link-frequencies = /bits/ 64 <456000000>;
54
+
data-lanes = <1 2>;
55
+
remote-endpoint = <&csi40_in>;
56
+
};
57
+
};
58
+
};
59
+
};
60
+
61
+
/* Page 29 / CSI_IF_CN */
62
+
&csi40 {
63
+
status = "okay";
64
+
65
+
ports {
66
+
#address-cells = <1>;
67
+
#size-cells = <0>;
68
+
69
+
port@0 {
70
+
reg = <0>;
71
+
72
+
csi40_in: endpoint {
73
+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
74
+
clock-lanes = <0>;
75
+
data-lanes = <1 2>;
76
+
remote-endpoint = <&imx219_j1_out>;
77
+
};
78
+
};
79
+
};
80
+
};
81
+
82
+
&isp0 {
83
+
status = "okay";
84
+
};
85
+
86
+
&vin00 {
87
+
status = "okay";
88
+
};
89
+
90
+
&vin01 {
91
+
status = "okay";
92
+
};
93
+
94
+
&vin02 {
95
+
status = "okay";
96
+
};
97
+
98
+
&vin03 {
99
+
status = "okay";
100
+
};
101
+
102
+
&vin04 {
103
+
status = "okay";
104
+
};
105
+
106
+
&vin05 {
107
+
status = "okay";
108
+
};
109
+
110
+
&vin06 {
111
+
status = "okay";
112
+
};
113
+
114
+
&vin07 {
115
+
status = "okay";
116
+
};
+117
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx462.dtso
+117
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx462.dtso
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Overlay for an IMX462 camera sensor on connector J1 on R-Car V4H
4
+
* ES3.0 Sparrow Hawk board.
5
+
*
6
+
* Copyright 2025 Renesas Electronics Corp.
7
+
* Copyright 2025 Niklas Söderlund <niklas.soderlund@ragnatech.se>
8
+
*/
9
+
10
+
/dts-v1/;
11
+
/plugin/;
12
+
13
+
#include <dt-bindings/gpio/gpio.h>
14
+
#include <dt-bindings/media/video-interfaces.h>
15
+
16
+
&{/} {
17
+
clk_cam_j1: clk-cam-j1 {
18
+
compatible = "fixed-clock";
19
+
#clock-cells = <0>;
20
+
clock-frequency = <37125000>;
21
+
};
22
+
23
+
/* Page 29 / CSI_IF_CN / J1 */
24
+
reg_cam_j1: reg-cam-j1 {
25
+
compatible = "regulator-fixed";
26
+
regulator-name = "cam-J1";
27
+
enable-active-high;
28
+
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
29
+
};
30
+
};
31
+
32
+
&i2c1 {
33
+
#address-cells = <1>;
34
+
#size-cells = <0>;
35
+
status = "okay";
36
+
37
+
cam@1a {
38
+
compatible = "sony,imx462lqr";
39
+
reg = <0x1a>;
40
+
41
+
clocks = <&clk_cam_j1>;
42
+
clock-names = "xclk";
43
+
clock-frequency = <37125000>;
44
+
45
+
vdddo-supply = <®_cam_j1>;
46
+
vdda-supply = <®_cam_j1>;
47
+
vddd-supply = <®_cam_j1>;
48
+
49
+
orientation = <2>;
50
+
rotation = <0>;
51
+
52
+
port {
53
+
imx462_j1_out: endpoint {
54
+
link-frequencies = /bits/ 64 <222750000 148500000>;
55
+
data-lanes = <1 2 3 4>;
56
+
remote-endpoint = <&csi40_in>;
57
+
};
58
+
};
59
+
};
60
+
};
61
+
62
+
/* Page 29 / CSI_IF_CN */
63
+
&csi40 {
64
+
status = "okay";
65
+
66
+
ports {
67
+
#address-cells = <1>;
68
+
#size-cells = <0>;
69
+
70
+
port@0 {
71
+
reg = <0>;
72
+
73
+
csi40_in: endpoint {
74
+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
75
+
clock-lanes = <0>;
76
+
data-lanes = <1 2 3 4>;
77
+
remote-endpoint = <&imx462_j1_out>;
78
+
};
79
+
};
80
+
};
81
+
};
82
+
83
+
&isp0 {
84
+
status = "okay";
85
+
};
86
+
87
+
&vin00 {
88
+
status = "okay";
89
+
};
90
+
91
+
&vin01 {
92
+
status = "okay";
93
+
};
94
+
95
+
&vin02 {
96
+
status = "okay";
97
+
};
98
+
99
+
&vin03 {
100
+
status = "okay";
101
+
};
102
+
103
+
&vin04 {
104
+
status = "okay";
105
+
};
106
+
107
+
&vin05 {
108
+
status = "okay";
109
+
};
110
+
111
+
&vin06 {
112
+
status = "okay";
113
+
};
114
+
115
+
&vin07 {
116
+
status = "okay";
117
+
};
+116
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx219.dtso
+116
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx219.dtso
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Overlay for an IMX219 camera sensor on connector J2 on R-Car V4H
4
+
* ES3.0 Sparrow Hawk board.
5
+
*
6
+
* Copyright 2025 Renesas Electronics Corp.
7
+
* Copyright 2025 Niklas Söderlund <niklas.soderlund@ragnatech.se>
8
+
*/
9
+
10
+
/dts-v1/;
11
+
/plugin/;
12
+
13
+
#include <dt-bindings/gpio/gpio.h>
14
+
#include <dt-bindings/media/video-interfaces.h>
15
+
16
+
&{/} {
17
+
clk_cam_j2: clk-cam-j2 {
18
+
compatible = "fixed-clock";
19
+
#clock-cells = <0>;
20
+
clock-frequency = <24000000>;
21
+
};
22
+
23
+
/* Page 29 / CSI_IF_CN / J2 */
24
+
reg_cam_j2: reg-cam-j2 {
25
+
compatible = "regulator-fixed";
26
+
regulator-name = "cam-J2";
27
+
enable-active-high;
28
+
gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
29
+
};
30
+
};
31
+
32
+
&i2c2 {
33
+
#address-cells = <1>;
34
+
#size-cells = <0>;
35
+
status = "okay";
36
+
37
+
cam@10 {
38
+
compatible = "sony,imx219";
39
+
reg = <0x10>;
40
+
41
+
clocks = <&clk_cam_j2>;
42
+
43
+
VANA-supply = <®_cam_j2>;
44
+
VDIG-supply = <®_cam_j2>;
45
+
VDDL-supply = <®_cam_j2>;
46
+
47
+
orientation = <2>;
48
+
rotation = <0>;
49
+
50
+
port {
51
+
imx219_j2_out: endpoint {
52
+
clock-noncontinuous;
53
+
link-frequencies = /bits/ 64 <456000000>;
54
+
data-lanes = <1 2>;
55
+
remote-endpoint = <&csi41_in>;
56
+
};
57
+
};
58
+
};
59
+
};
60
+
61
+
/* Page 29 / CSI_IF_CN */
62
+
&csi41 {
63
+
status = "okay";
64
+
65
+
ports {
66
+
#address-cells = <1>;
67
+
#size-cells = <0>;
68
+
69
+
port@0 {
70
+
reg = <0>;
71
+
72
+
csi41_in: endpoint {
73
+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
74
+
clock-lanes = <0>;
75
+
data-lanes = <1 2>;
76
+
remote-endpoint = <&imx219_j2_out>;
77
+
};
78
+
};
79
+
};
80
+
};
81
+
82
+
&isp1 {
83
+
status = "okay";
84
+
};
85
+
86
+
&vin08 {
87
+
status = "okay";
88
+
};
89
+
90
+
&vin09 {
91
+
status = "okay";
92
+
};
93
+
94
+
&vin10 {
95
+
status = "okay";
96
+
};
97
+
98
+
&vin11 {
99
+
status = "okay";
100
+
};
101
+
102
+
&vin12 {
103
+
status = "okay";
104
+
};
105
+
106
+
&vin13 {
107
+
status = "okay";
108
+
};
109
+
110
+
&vin14 {
111
+
status = "okay";
112
+
};
113
+
114
+
&vin15 {
115
+
status = "okay";
116
+
};
+117
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx462.dtso
+117
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx462.dtso
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Overlay for an IMX462 camera sensor on connector J2 on R-Car V4H
4
+
* ES3.0 Sparrow Hawk board.
5
+
*
6
+
* Copyright 2025 Renesas Electronics Corp.
7
+
* Copyright 2025 Niklas Söderlund <niklas.soderlund@ragnatech.se>
8
+
*/
9
+
10
+
/dts-v1/;
11
+
/plugin/;
12
+
13
+
#include <dt-bindings/gpio/gpio.h>
14
+
#include <dt-bindings/media/video-interfaces.h>
15
+
16
+
&{/} {
17
+
clk_cam_j2: clk-cam-j2 {
18
+
compatible = "fixed-clock";
19
+
#clock-cells = <0>;
20
+
clock-frequency = <37125000>;
21
+
};
22
+
23
+
/* Page 29 / CSI_IF_CN / J2 */
24
+
reg_cam_j2: reg-cam-j2 {
25
+
compatible = "regulator-fixed";
26
+
regulator-name = "cam-J2";
27
+
enable-active-high;
28
+
gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
29
+
};
30
+
};
31
+
32
+
&i2c2 {
33
+
#address-cells = <1>;
34
+
#size-cells = <0>;
35
+
status = "okay";
36
+
37
+
cam@1a {
38
+
compatible = "sony,imx462lqr";
39
+
reg = <0x1a>;
40
+
41
+
clocks = <&clk_cam_j2>;
42
+
clock-names = "xclk";
43
+
clock-frequency = <37125000>;
44
+
45
+
vdddo-supply = <®_cam_j2>;
46
+
vdda-supply = <®_cam_j2>;
47
+
vddd-supply = <®_cam_j2>;
48
+
49
+
orientation = <2>;
50
+
rotation = <0>;
51
+
52
+
port {
53
+
imx462_j2_out: endpoint {
54
+
link-frequencies = /bits/ 64 <222750000 148500000>;
55
+
data-lanes = <1 2 3 4>;
56
+
remote-endpoint = <&csi41_in>;
57
+
};
58
+
};
59
+
};
60
+
};
61
+
62
+
/* Page 29 / CSI_IF_CN */
63
+
&csi41 {
64
+
status = "okay";
65
+
66
+
ports {
67
+
#address-cells = <1>;
68
+
#size-cells = <0>;
69
+
70
+
port@0 {
71
+
reg = <0>;
72
+
73
+
csi41_in: endpoint {
74
+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
75
+
clock-lanes = <0>;
76
+
data-lanes = <1 2 3 4>;
77
+
remote-endpoint = <&imx462_j2_out>;
78
+
};
79
+
};
80
+
};
81
+
};
82
+
83
+
&isp1 {
84
+
status = "okay";
85
+
};
86
+
87
+
&vin08 {
88
+
status = "okay";
89
+
};
90
+
91
+
&vin09 {
92
+
status = "okay";
93
+
};
94
+
95
+
&vin10 {
96
+
status = "okay";
97
+
};
98
+
99
+
&vin11 {
100
+
status = "okay";
101
+
};
102
+
103
+
&vin12 {
104
+
status = "okay";
105
+
};
106
+
107
+
&vin13 {
108
+
status = "okay";
109
+
};
110
+
111
+
&vin14 {
112
+
status = "okay";
113
+
};
114
+
115
+
&vin15 {
116
+
status = "okay";
117
+
};
+5
-10
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso
+5
-10
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso
···
1
1
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
/*
3
-
* Device Tree Overlay for the PWM controlled blower fan in connector J3:FAN
3
+
* Device Tree Overlay for the PWM controlled blower fan on connector J3:FAN
4
4
* on R-Car V4H ES3.0 Sparrow Hawk board
5
5
*
6
6
* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
···
9
9
*
10
10
* # Localize hwmon sysfs directory that matches the PWM fan,
11
11
* # enable the PWM fan, and configure the fan speed manually.
12
-
* r8a779g3-sparrow-hawk$ grep -H . /sys/class/hwmon/hwmon?/name
13
-
* /sys/class/hwmon/hwmon0/name:sensor1_thermal
14
-
* /sys/class/hwmon/hwmon1/name:sensor2_thermal
15
-
* /sys/class/hwmon/hwmon2/name:sensor3_thermal
16
-
* /sys/class/hwmon/hwmon3/name:sensor4_thermal
17
-
* /sys/class/hwmon/hwmon4/name:pwmfan
18
-
* ^ ^^^^^^
12
+
* r8a779g3-sparrow-hawk$ ls -1 /sys/devices/platform/pwm-fan/hwmon/hwmon?/pwm?_enable
13
+
* /sys/devices/platform/pwm-fan/hwmon/hwmon4/pwm1_enable
19
14
*
20
15
* # Select mode 2 , enable fan PWM and regulator and keep them enabled.
21
16
* # For details, see Linux Documentation/hwmon/pwm-fan.rst
22
-
* r8a779g3-sparrow-hawk$ echo 2 > /sys/class/hwmon/hwmon4/pwm1_enable
17
+
* r8a779g3-sparrow-hawk$ echo 2 > /sys/devices/platform/pwm-fan/hwmon/hwmon4/pwm1_enable
23
18
*
24
19
* # Configure PWM fan speed in range 0..255 , 0 is stopped , 255 is full speed .
25
20
* # Fan speed 101 is about 2/5 of the PWM fan speed:
26
-
* r8a779g3-sparrow-hawk$ echo 101 > /sys/class/hwmon/hwmon4/pwm1
21
+
* r8a779g3-sparrow-hawk$ echo 101 > /sys/devices/platform/pwm-fan/hwmon/hwmon4/pwm1
27
22
*/
28
23
29
24
/dts-v1/;
+1
-1
arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+1
-1
arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+4
-6
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+4
-6
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
···
927
927
snps,perfect-filter-entries = <128>;
928
928
rx-fifo-depth = <8192>;
929
929
tx-fifo-depth = <8192>;
930
-
snps,fixed-burst;
931
-
snps,no-pbl-x8;
932
-
snps,force_thresh_dma_mode;
930
+
snps,mixed-burst;
931
+
snps,force_sf_dma_mode;
933
932
snps,axi-config = <&stmmac_axi_setup>;
934
933
snps,mtl-rx-config = <&mtl_rx_setup0>;
935
934
snps,mtl-tx-config = <&mtl_tx_setup0>;
···
1027
1028
snps,perfect-filter-entries = <128>;
1028
1029
rx-fifo-depth = <8192>;
1029
1030
tx-fifo-depth = <8192>;
1030
-
snps,fixed-burst;
1031
-
snps,no-pbl-x8;
1032
-
snps,force_thresh_dma_mode;
1031
+
snps,mixed-burst;
1032
+
snps,force_sf_dma_mode;
1033
1033
snps,axi-config = <&stmmac_axi_setup>;
1034
1034
snps,mtl-rx-config = <&mtl_rx_setup1>;
1035
1035
snps,mtl-tx-config = <&mtl_tx_setup1>;
+4
-3
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+4
-3
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
···
90
90
};
91
91
92
92
&keys {
93
-
key-sleep {
94
-
pinctrl-0 = <&nmi_pins>;
95
-
pinctrl-names = "default";
93
+
pinctrl-0 = <&nmi_pins>;
94
+
pinctrl-names = "default";
96
95
96
+
key-sleep {
97
97
interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>;
98
98
linux,code = <KEY_SLEEP>;
99
99
label = "SLEEP";
···
132
132
133
133
nmi_pins: nmi {
134
134
pinmux = <RZG3E_PORT_PINMUX(S, 0, 0)>; /* NMI */
135
+
input-schmitt-enable;
135
136
};
136
137
137
138
scif_pins: scif {
+33
arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+33
arch/arm64/boot/dts/renesas/r9a09g056.dtsi
···
369
369
status = "disabled";
370
370
};
371
371
372
+
i3c: i3c@12400000 {
373
+
compatible = "renesas,r9a09g056-i3c", "renesas,r9a09g047-i3c";
374
+
reg = <0 0x12400000 0 0x10000>;
375
+
clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>;
376
+
clock-names = "pclk", "tclk", "pclkrw";
377
+
interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
378
+
<GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
379
+
<GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>,
380
+
<GIC_SPI 677 IRQ_TYPE_EDGE_RISING>,
381
+
<GIC_SPI 678 IRQ_TYPE_EDGE_RISING>,
382
+
<GIC_SPI 679 IRQ_TYPE_EDGE_RISING>,
383
+
<GIC_SPI 680 IRQ_TYPE_EDGE_RISING>,
384
+
<GIC_SPI 681 IRQ_TYPE_EDGE_RISING>,
385
+
<GIC_SPI 682 IRQ_TYPE_EDGE_RISING>,
386
+
<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
387
+
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
388
+
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
389
+
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
390
+
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
391
+
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
392
+
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
393
+
interrupt-names = "ierr", "terr", "abort", "resp",
394
+
"cmd", "ibi", "rx", "tx", "rcv",
395
+
"st", "sp", "tend", "nack",
396
+
"al", "tmo", "wu";
397
+
resets = <&cpg 0x96>, <&cpg 0x97>;
398
+
reset-names = "presetn", "tresetn";
399
+
power-domains = <&cpg>;
400
+
#address-cells = <3>;
401
+
#size-cells = <0>;
402
+
status = "disabled";
403
+
};
404
+
372
405
i2c0: i2c@14400400 {
373
406
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
374
407
reg = <0 0x14400400 0 0x400>;
+33
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+33
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
···
607
607
status = "disabled";
608
608
};
609
609
610
+
i3c: i3c@12400000 {
611
+
compatible = "renesas,r9a09g057-i3c", "renesas,r9a09g047-i3c";
612
+
reg = <0 0x12400000 0 0x10000>;
613
+
clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>;
614
+
clock-names = "pclk", "tclk", "pclkrw";
615
+
interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
616
+
<GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
617
+
<GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>,
618
+
<GIC_SPI 677 IRQ_TYPE_EDGE_RISING>,
619
+
<GIC_SPI 678 IRQ_TYPE_EDGE_RISING>,
620
+
<GIC_SPI 679 IRQ_TYPE_EDGE_RISING>,
621
+
<GIC_SPI 680 IRQ_TYPE_EDGE_RISING>,
622
+
<GIC_SPI 681 IRQ_TYPE_EDGE_RISING>,
623
+
<GIC_SPI 682 IRQ_TYPE_EDGE_RISING>,
624
+
<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
625
+
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
626
+
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
627
+
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
628
+
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
629
+
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
630
+
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
631
+
interrupt-names = "ierr", "terr", "abort", "resp",
632
+
"cmd", "ibi", "rx", "tx", "rcv",
633
+
"st", "sp", "tend", "nack",
634
+
"al", "tmo", "wu";
635
+
resets = <&cpg 0x96>, <&cpg 0x97>;
636
+
reset-names = "presetn", "tresetn";
637
+
power-domains = <&cpg>;
638
+
#address-cells = <3>;
639
+
#size-cells = <0>;
640
+
status = "disabled";
641
+
};
642
+
610
643
rspi0: spi@12800000 {
611
644
compatible = "renesas,r9a09g057-rspi";
612
645
reg = <0x0 0x12800000 0x0 0x400>;
+107
arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+107
arch/arm64/boot/dts/renesas/r9a09g077.dtsi
···
160
160
status = "disabled";
161
161
};
162
162
163
+
wdt0: watchdog@80082000 {
164
+
compatible = "renesas,r9a09g077-wdt";
165
+
reg = <0 0x80082000 0 0x400>,
166
+
<0 0x81295100 0 0x04>;
167
+
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
168
+
clock-names = "pclk";
169
+
power-domains = <&cpg>;
170
+
status = "disabled";
171
+
};
172
+
173
+
wdt1: watchdog@80082400 {
174
+
compatible = "renesas,r9a09g077-wdt";
175
+
reg = <0 0x80082400 0 0x400>,
176
+
<0 0x81295104 0 0x04>;
177
+
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
178
+
clock-names = "pclk";
179
+
power-domains = <&cpg>;
180
+
status = "disabled";
181
+
};
182
+
183
+
wdt2: watchdog@80082800 {
184
+
compatible = "renesas,r9a09g077-wdt";
185
+
reg = <0 0x80082800 0 0x400>,
186
+
<0 0x81295108 0 0x04>;
187
+
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
188
+
clock-names = "pclk";
189
+
power-domains = <&cpg>;
190
+
status = "disabled";
191
+
};
192
+
193
+
wdt3: watchdog@80082c00 {
194
+
compatible = "renesas,r9a09g077-wdt";
195
+
reg = <0 0x80082c00 0 0x400>,
196
+
<0 0x8129510c 0 0x04>;
197
+
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
198
+
clock-names = "pclk";
199
+
power-domains = <&cpg>;
200
+
status = "disabled";
201
+
};
202
+
203
+
wdt4: watchdog@80083000 {
204
+
compatible = "renesas,r9a09g077-wdt";
205
+
reg = <0 0x80083000 0 0x400>,
206
+
<0 0x81295110 0 0x04>;
207
+
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
208
+
clock-names = "pclk";
209
+
power-domains = <&cpg>;
210
+
status = "disabled";
211
+
};
212
+
213
+
wdt5: watchdog@80083400 {
214
+
compatible = "renesas,r9a09g077-wdt";
215
+
reg = <0 0x80083400 0 0x400>,
216
+
<0 0x81295114 0 0x04>;
217
+
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
218
+
clock-names = "pclk";
219
+
power-domains = <&cpg>;
220
+
status = "disabled";
221
+
};
222
+
163
223
i2c0: i2c@80088000 {
164
224
compatible = "renesas,riic-r9a09g077";
165
225
reg = <0 0x80088000 0 0x400>;
···
297
237
#address-cells = <0>;
298
238
interrupt-controller;
299
239
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
240
+
};
241
+
242
+
ohci: usb@92040000 {
243
+
compatible = "generic-ohci";
244
+
reg = <0 0x92040000 0 0x100>;
245
+
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
246
+
clocks = <&cpg CPG_MOD 408>;
247
+
phys = <&usb2_phy 1>;
248
+
phy-names = "usb";
249
+
power-domains = <&cpg>;
250
+
status = "disabled";
251
+
};
252
+
253
+
ehci: usb@92040100 {
254
+
compatible = "generic-ehci";
255
+
reg = <0 0x92040100 0 0x100>;
256
+
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
257
+
clocks = <&cpg CPG_MOD 408>;
258
+
phys = <&usb2_phy 2>;
259
+
phy-names = "usb";
260
+
companion = <&ohci>;
261
+
power-domains = <&cpg>;
262
+
status = "disabled";
263
+
};
264
+
265
+
usb2_phy: usb-phy@92040200 {
266
+
compatible = "renesas,usb2-phy-r9a09g077";
267
+
reg = <0 0x92040200 0 0x700>;
268
+
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
269
+
clocks = <&cpg CPG_MOD 408>,
270
+
<&cpg CPG_CORE R9A09G077_USB_CLK>;
271
+
#phy-cells = <1>;
272
+
power-domains = <&cpg>;
273
+
status = "disabled";
274
+
};
275
+
276
+
hsusb: usb@92041000 {
277
+
compatible = "renesas,usbhs-r9a09g077";
278
+
reg = <0 0x92041000 0 0x1000>;
279
+
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
280
+
<GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
281
+
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
282
+
clocks = <&cpg CPG_MOD 408>;
283
+
phys = <&usb2_phy 3>;
284
+
phy-names = "usb";
285
+
power-domains = <&cpg>;
286
+
status = "disabled";
300
287
};
301
288
302
289
sdhi0: mmc@92080000 {
+134
-2
arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+134
-2
arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
···
7
7
8
8
/dts-v1/;
9
9
10
-
#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
11
-
12
10
#include "r9a09g077m44.dtsi"
11
+
12
+
/*
13
+
* SD0 can be connected to either eMMC (IC49) or SD card slot CN31
14
+
* Lets by default enable the eMMC, note we need the below SW settings
15
+
* for eMMC.
16
+
* SW2[1] = ON; SW2[2] = ON
17
+
*
18
+
* To enable SD card and disable eMMC on SDHI0 disable the below macro
19
+
* and set the below switch setting:
20
+
* SW2[1] = OFF; SW2[2] = ON
21
+
*/
22
+
#define SD0_EMMC 1
23
+
#define SD0_SD (!SD0_EMMC)
24
+
25
+
/*
26
+
* P17_4 = SD1_CD; SW2[3] = ON
27
+
* P08_5 = SD1_PWEN; SW2[3] = ON
28
+
* P08_6 = SD1_IOVS; SW2[3] = ON; SW5[3] = OFF; SW5[4] = ON
29
+
*/
30
+
#define SD1_MICRO_SD 1
31
+
32
+
/*
33
+
* USB Pin Configuration:
34
+
*
35
+
* This board is equipped with three USB connectors: Type-A (CN80), Mini-B
36
+
* (CN79), and Micro-AB (CN33). The RZ/T2H SoC has a single USB channel, so
37
+
* either the USB host interface or the USB function interface can be used,
38
+
* but not both simultaneously when using the CN79 and CN80 connectors.
39
+
*
40
+
* By default, the Type-A (CN80) and Mini-B (CN79) connectors are enabled.
41
+
* Configure the switches as follows:
42
+
* - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON
43
+
* - USB_VBUSIN (used for USB function): SW7[7] = OFF; SW7[8] = ON
44
+
* - USB_VBUSEN (used for USB_HF_VBUSEN): SW7[9] = OFF; SW7[10] = ON
45
+
*
46
+
* To enable the Micro-AB (CN33) USB OTG connector, set the following macro
47
+
* to 1 and configure the switches as follows:
48
+
* - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON
49
+
* - USB_VBUSIN (used for USB OTG): SW7[7] = ON; SW7[8] = OFF
50
+
* - USB_VBUSEN (used for USB_OTG_VBUSEN): SW7[9] = ON; SW7[10] = OFF
51
+
*/
52
+
#define USB_OTG 0
53
+
13
54
#include "rzt2h-n2h-evk-common.dtsi"
14
55
15
56
/ {
16
57
model = "Renesas RZ/T2H EVK Board based on r9a09g077m44";
17
58
compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077";
59
+
60
+
leds {
61
+
compatible = "gpio-leds";
62
+
63
+
led-0 {
64
+
/* SW8-9: ON, SW8-10: OFF */
65
+
gpios = <&pinctrl RZT2H_GPIO(23, 1) GPIO_ACTIVE_HIGH>;
66
+
color = <LED_COLOR_ID_GREEN>;
67
+
function = LED_FUNCTION_DEBUG;
68
+
function-enumerator = <0>;
69
+
};
70
+
71
+
led-1 {
72
+
/* SW5-1: OFF, SW5-2: ON */
73
+
gpios = <&pinctrl RZT2H_GPIO(32, 2) GPIO_ACTIVE_HIGH>;
74
+
color = <LED_COLOR_ID_GREEN>;
75
+
function = LED_FUNCTION_DEBUG;
76
+
function-enumerator = <1>;
77
+
};
78
+
79
+
led-2 {
80
+
gpios = <&pinctrl RZT2H_GPIO(6, 7) GPIO_ACTIVE_HIGH>;
81
+
color = <LED_COLOR_ID_YELLOW>;
82
+
function = LED_FUNCTION_DEBUG;
83
+
function-enumerator = <2>;
84
+
};
85
+
86
+
#if (!SD1_MICRO_SD)
87
+
led-3 {
88
+
/* SW2-3: OFF */
89
+
gpios = <&pinctrl RZT2H_GPIO(8, 5) GPIO_ACTIVE_HIGH>;
90
+
color = <LED_COLOR_ID_RED>;
91
+
function = LED_FUNCTION_DEBUG;
92
+
function-enumerator = <3>;
93
+
};
94
+
#endif
95
+
96
+
led-4 {
97
+
/* SW8-3: ON, SW8-4: OFF */
98
+
gpios = <&pinctrl RZT2H_GPIO(18, 0) GPIO_ACTIVE_HIGH>;
99
+
color = <LED_COLOR_ID_GREEN>;
100
+
function = LED_FUNCTION_DEBUG;
101
+
function-enumerator = <4>;
102
+
};
103
+
104
+
led-5 {
105
+
/* SW8-1: ON, SW8-2: OFF */
106
+
gpios = <&pinctrl RZT2H_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
107
+
color = <LED_COLOR_ID_RED>;
108
+
function = LED_FUNCTION_DEBUG;
109
+
function-enumerator = <5>;
110
+
};
111
+
112
+
led-6 {
113
+
/* SW5-9: OFF, SW5-10: ON */
114
+
gpios = <&pinctrl RZT2H_GPIO(22, 7) GPIO_ACTIVE_HIGH>;
115
+
color = <LED_COLOR_ID_GREEN>;
116
+
function = LED_FUNCTION_DEBUG;
117
+
function-enumerator = <6>;
118
+
};
119
+
120
+
led-7 {
121
+
/* SW5-7: OFF, SW5-8: ON */
122
+
gpios = <&pinctrl RZT2H_GPIO(23, 0) GPIO_ACTIVE_HIGH>;
123
+
color = <LED_COLOR_ID_GREEN>;
124
+
function = LED_FUNCTION_DEBUG;
125
+
function-enumerator = <7>;
126
+
};
127
+
128
+
led-8 {
129
+
/* SW7-5: OFF, SW7-6: ON */
130
+
gpios = <&pinctrl RZT2H_GPIO(23, 5) GPIO_ACTIVE_HIGH>;
131
+
color = <LED_COLOR_ID_GREEN>;
132
+
function = LED_FUNCTION_DEBUG;
133
+
function-enumerator = <8>;
134
+
};
135
+
};
18
136
};
19
137
20
138
&i2c0 {
···
166
48
i2c1_pins: i2c1-pins {
167
49
pinmux = <RZT2H_PORT_PINMUX(5, 0, 0x17)>, /* SDA */
168
50
<RZT2H_PORT_PINMUX(4, 7, 0x17)>; /* SCL */
51
+
};
52
+
53
+
#if USB_OTG
54
+
usb-exicen-hog {
55
+
gpio-hog;
56
+
gpios = <RZT2H_GPIO(0, 2) GPIO_ACTIVE_HIGH>;
57
+
output-high;
58
+
line-name = "usb_exicen_a";
59
+
};
60
+
#endif
61
+
62
+
usb_pins: usb-pins {
63
+
pinmux = <RZT2H_PORT_PINMUX(0, 0, 0x13)>, /* VBUSEN */
64
+
<RZT2H_PORT_PINMUX(0, 1, 0x13)>; /* OVRCUR */
169
65
};
170
66
};
+120
arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+120
arch/arm64/boot/dts/renesas/r9a09g087.dtsi
···
160
160
status = "disabled";
161
161
};
162
162
163
+
wdt0: watchdog@80082000 {
164
+
compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
165
+
reg = <0 0x80082000 0 0x400>,
166
+
<0 0x81295100 0 0x04>;
167
+
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>;
168
+
clock-names = "pclk";
169
+
power-domains = <&cpg>;
170
+
status = "disabled";
171
+
};
172
+
173
+
wdt1: watchdog@80082400 {
174
+
compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
175
+
reg = <0 0x80082400 0 0x400>,
176
+
<0 0x81295104 0 0x04>;
177
+
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>;
178
+
clock-names = "pclk";
179
+
power-domains = <&cpg>;
180
+
status = "disabled";
181
+
};
182
+
183
+
wdt2: watchdog@80082800 {
184
+
compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
185
+
reg = <0 0x80082800 0 0x400>,
186
+
<0 0x81295108 0 0x04>;
187
+
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>;
188
+
clock-names = "pclk";
189
+
power-domains = <&cpg>;
190
+
status = "disabled";
191
+
};
192
+
193
+
wdt3: watchdog@80082c00 {
194
+
compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
195
+
reg = <0 0x80082c00 0 0x400>,
196
+
<0 0x8129510c 0 0x04>;
197
+
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>;
198
+
clock-names = "pclk";
199
+
power-domains = <&cpg>;
200
+
status = "disabled";
201
+
};
202
+
203
+
wdt4: watchdog@80083000 {
204
+
compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
205
+
reg = <0 0x80083000 0 0x400>,
206
+
<0 0x81295110 0 0x04>;
207
+
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>;
208
+
clock-names = "pclk";
209
+
power-domains = <&cpg>;
210
+
status = "disabled";
211
+
};
212
+
213
+
wdt5: watchdog@80083400 {
214
+
compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
215
+
reg = <0 0x80083400 0 0x400>,
216
+
<0 0x81295114 0 0x04>;
217
+
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>;
218
+
clock-names = "pclk";
219
+
power-domains = <&cpg>;
220
+
status = "disabled";
221
+
};
222
+
163
223
i2c0: i2c@80088000 {
164
224
compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
165
225
reg = <0 0x80088000 0 0x400>;
···
276
216
#power-domain-cells = <0>;
277
217
};
278
218
219
+
pinctrl: pinctrl@802c0000 {
220
+
compatible = "renesas,r9a09g087-pinctrl";
221
+
reg = <0 0x802c0000 0 0x10000>,
222
+
<0 0x812c0000 0 0x10000>,
223
+
<0 0x802b0000 0 0x10000>;
224
+
reg-names = "nsr", "srs", "srn";
225
+
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
226
+
gpio-controller;
227
+
#gpio-cells = <2>;
228
+
gpio-ranges = <&pinctrl 0 0 280>;
229
+
power-domains = <&cpg>;
230
+
};
231
+
279
232
gic: interrupt-controller@83000000 {
280
233
compatible = "arm,gic-v3";
281
234
reg = <0x0 0x83000000 0 0x40000>,
···
297
224
#address-cells = <0>;
298
225
interrupt-controller;
299
226
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
227
+
};
228
+
229
+
ohci: usb@92040000 {
230
+
compatible = "generic-ohci";
231
+
reg = <0 0x92040000 0 0x100>;
232
+
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
233
+
clocks = <&cpg CPG_MOD 408>;
234
+
phys = <&usb2_phy 1>;
235
+
phy-names = "usb";
236
+
power-domains = <&cpg>;
237
+
status = "disabled";
238
+
};
239
+
240
+
ehci: usb@92040100 {
241
+
compatible = "generic-ehci";
242
+
reg = <0 0x92040100 0 0x100>;
243
+
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
244
+
clocks = <&cpg CPG_MOD 408>;
245
+
phys = <&usb2_phy 2>;
246
+
phy-names = "usb";
247
+
companion = <&ohci>;
248
+
power-domains = <&cpg>;
249
+
status = "disabled";
250
+
};
251
+
252
+
usb2_phy: usb-phy@92040200 {
253
+
compatible = "renesas,usb2-phy-r9a09g087", "renesas,usb2-phy-r9a09g077";
254
+
reg = <0 0x92040200 0 0x700>;
255
+
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
256
+
clocks = <&cpg CPG_MOD 408>,
257
+
<&cpg CPG_CORE R9A09G087_USB_CLK>;
258
+
#phy-cells = <1>;
259
+
power-domains = <&cpg>;
260
+
status = "disabled";
261
+
};
262
+
263
+
hsusb: usb@92041000 {
264
+
compatible = "renesas,usbhs-r9a09g087", "renesas,usbhs-r9a09g077";
265
+
reg = <0 0x92041000 0 0x1000>;
266
+
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
267
+
<GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
268
+
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
269
+
clocks = <&cpg CPG_MOD 408>;
270
+
phys = <&usb2_phy 3>;
271
+
phy-names = "usb";
272
+
power-domains = <&cpg>;
273
+
status = "disabled";
300
274
};
301
275
302
276
sdhi0: mmc@92080000 {
+213
arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+213
arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
···
8
8
/dts-v1/;
9
9
10
10
#include "r9a09g087m44.dtsi"
11
+
12
+
/*
13
+
* SD0 can be connected to either eMMC (U33) or SD card slot CN21
14
+
* Lets by default enable the eMMC, note we need the below SW settings
15
+
* for eMMC.
16
+
* DSW5[1] = ON; DSW5[2] = ON
17
+
* DSW17[5] = OFF; DSW17[6] = ON
18
+
*
19
+
* To enable SD card and disable eMMC on SDHI0 disable the below macro
20
+
* and set the below switch setting:
21
+
* DSW5[1] = OFF; DSW5[2] = ON
22
+
* P22_6 = SD0_WP; DSW15[1] = OFF; DSW15[2] = ON
23
+
* P22_5 = SD0_CD; DSW15[3] = OFF; DSW15[4] = ON
24
+
* P02_6 = SD0_IOVS; DSW17[5] = OFF; DSW17[6] = ON
25
+
* P02_5 = SD0_PWEN; DSW17[7] = OFF; DSW17[8] = ON
26
+
*/
27
+
#define SD0_EMMC 1
28
+
#define SD0_SD (!SD0_EMMC)
29
+
30
+
/*
31
+
* P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON
32
+
* P08_6 = SD1_IOVS; DSW5[3] = ON
33
+
*/
34
+
#define SD1_MICRO_SD 1
35
+
36
+
/*
37
+
* USB Pin Configuration:
38
+
*
39
+
* This board is equipped with three USB connectors: Type-A (CN7), Mini-B
40
+
* (CN8), and Micro-AB (CN9). The RZ/N2H SoC has a single USB channel, so
41
+
* either the USB host interface or the USB function interface can be used,
42
+
* but not both simultaneously when using the CN7 and CN8 connectors.
43
+
*
44
+
* By default, the Type-A (CN7) and Mini-B (CN8) connectors are enabled.
45
+
* Configure the switches as follows:
46
+
* - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF;
47
+
* - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON
48
+
* - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON
49
+
* - USB_VBUSIN (used for VBUS of CN8): DSW16[1] = OFF; DSW16[2] = ON
50
+
* - USB_VBUSEN (used for USB_HF_VBUSEN): DSW16[3] = OFF; DSW16[4] = ON
51
+
*
52
+
* To enable the Micro-AB (CN9) USB OTG connector, set the following macro
53
+
* to 1 and configure the switches as follows:
54
+
* - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF;
55
+
* - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON
56
+
* - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON
57
+
* - USB_VBUSIN (used for VBUS for OTG): DSW16[1] = ON; DSW16[2] = OFF
58
+
* - USB_VBUSEN (used for USB_OTG_VBUSEN): DSW16[3] = ON; DSW16[4] = OFF
59
+
* - USB_EXICEN (used for USB OTG EXICEN): DSW14[3] = OFF; DSW14[4] = ON
60
+
*/
61
+
#define USB_OTG 0
62
+
11
63
#include "rzt2h-n2h-evk-common.dtsi"
64
+
65
+
/*
66
+
* I2C0 and LED8/9 share the same pins use the below
67
+
* macro to choose (and set approopriate DIP switches).
68
+
*/
69
+
#define I2C0 1
70
+
#define LED8 (!I2C0)
71
+
#define LED9 (!I2C0)
12
72
13
73
/ {
14
74
model = "Renesas RZ/N2H EVK Board based on r9a09g087m44";
15
75
compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087";
76
+
77
+
leds {
78
+
compatible = "gpio-leds";
79
+
80
+
led-3 {
81
+
/* DSW18-7: ON, DSW18-8: OFF */
82
+
gpios = <&pinctrl RZT2H_GPIO(31, 6) GPIO_ACTIVE_HIGH>;
83
+
color = <LED_COLOR_ID_GREEN>;
84
+
function = LED_FUNCTION_DEBUG;
85
+
function-enumerator = <4>;
86
+
};
87
+
88
+
led-4 {
89
+
/* DSW18-9: ON, DSW18-10: OFF */
90
+
gpios = <&pinctrl RZT2H_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
91
+
color = <LED_COLOR_ID_RED>;
92
+
function = LED_FUNCTION_DEBUG;
93
+
function-enumerator = <5>;
94
+
};
95
+
96
+
led-5 {
97
+
/* DSW18-1: ON, DSW18-2: OFF */
98
+
gpios = <&pinctrl RZT2H_GPIO(22, 7) GPIO_ACTIVE_HIGH>;
99
+
color = <LED_COLOR_ID_GREEN>;
100
+
function = LED_FUNCTION_DEBUG;
101
+
function-enumerator = <6>;
102
+
};
103
+
104
+
led-6 {
105
+
/* DSW18-3: ON, DSW18-4: OFF */
106
+
gpios = <&pinctrl RZT2H_GPIO(23, 0) GPIO_ACTIVE_HIGH>;
107
+
color = <LED_COLOR_ID_GREEN>;
108
+
function = LED_FUNCTION_DEBUG;
109
+
function-enumerator = <7>;
110
+
};
111
+
112
+
led-7 {
113
+
/*
114
+
* DSW18-5: ON, DSW18-6: OFF
115
+
* DSW19-3: OFF, DSW19-4: ON
116
+
*/
117
+
gpios = <&pinctrl RZT2H_GPIO(14, 3) GPIO_ACTIVE_HIGH>;
118
+
color = <LED_COLOR_ID_GREEN>;
119
+
function = LED_FUNCTION_DEBUG;
120
+
function-enumerator = <8>;
121
+
};
122
+
123
+
#if LED8
124
+
led-8 {
125
+
/*
126
+
* USER_LED0
127
+
* DSW15-8: OFF, DSW15-9: OFF, DSW15-10: ON
128
+
*/
129
+
gpios = <&pinctrl RZT2H_GPIO(14, 6) GPIO_ACTIVE_HIGH>;
130
+
color = <LED_COLOR_ID_GREEN>;
131
+
function = LED_FUNCTION_DEBUG;
132
+
function-enumerator = <0>;
133
+
};
134
+
#endif
135
+
136
+
#if LED9
137
+
led-9 {
138
+
/*
139
+
* USER_LED1
140
+
* DSW15-5: OFF, DSW15-6: ON
141
+
*/
142
+
gpios = <&pinctrl RZT2H_GPIO(14, 7) GPIO_ACTIVE_HIGH>;
143
+
color = <LED_COLOR_ID_GREEN>;
144
+
function = LED_FUNCTION_DEBUG;
145
+
function-enumerator = <1>;
146
+
};
147
+
#endif
148
+
149
+
led-10 {
150
+
/*
151
+
* USER_LED2
152
+
* DSW17-3: OFF, DSW17-4: ON
153
+
*/
154
+
gpios = <&pinctrl RZT2H_GPIO(2, 7) GPIO_ACTIVE_HIGH>;
155
+
color = <LED_COLOR_ID_YELLOW>;
156
+
function = LED_FUNCTION_DEBUG;
157
+
function-enumerator = <2>;
158
+
};
159
+
160
+
led-11 {
161
+
/*
162
+
* USER_LED3
163
+
* DSW17-1: OFF, DSW17-2: ON
164
+
*/
165
+
gpios = <&pinctrl RZT2H_GPIO(3, 0) GPIO_ACTIVE_HIGH>;
166
+
color = <LED_COLOR_ID_RED>;
167
+
function = LED_FUNCTION_DEBUG;
168
+
function-enumerator = <3>;
169
+
};
170
+
};
171
+
};
172
+
173
+
#if I2C0
174
+
&i2c0 {
175
+
pinctrl-0 = <&i2c0_pins>;
176
+
pinctrl-names = "default";
177
+
clock-frequency = <400000>;
178
+
status = "okay";
179
+
};
180
+
#endif
181
+
182
+
&i2c1 {
183
+
pinctrl-0 = <&i2c1_pins>;
184
+
pinctrl-names = "default";
185
+
clock-frequency = <400000>;
186
+
status = "okay";
187
+
};
188
+
189
+
&pinctrl {
190
+
/*
191
+
* I2C0 Pin Configuration:
192
+
* ------------------------
193
+
* Signal | Pin | DSW15
194
+
* -------|---------|--------------
195
+
* SCL | P14_6 | 8: OFF, 9: ON, 10: OFF
196
+
* SDA | P14_7 | 5: ON, 6: OFF
197
+
*/
198
+
i2c0_pins: i2c0-pins {
199
+
pinmux = <RZT2H_PORT_PINMUX(14, 6, 0x17)>,
200
+
<RZT2H_PORT_PINMUX(14, 7, 0x17)>;
201
+
};
202
+
203
+
/*
204
+
* I2C1 Pin Configuration:
205
+
* ------------------------
206
+
* Signal | Pin | DSW7
207
+
* -------|---------|--------------
208
+
* SCL | P03_3 | 1: ON, 2: OFF
209
+
* SDA | P03_4 | 3: ON, 4: OFF
210
+
*/
211
+
i2c1_pins: i2c1-pins {
212
+
pinmux = <RZT2H_PORT_PINMUX(3, 3, 0x17)>,
213
+
<RZT2H_PORT_PINMUX(3, 4, 0x17)>;
214
+
};
215
+
216
+
#if USB_OTG
217
+
usb-exicen-hog {
218
+
gpio-hog;
219
+
gpios = <RZT2H_GPIO(2, 4) GPIO_ACTIVE_HIGH>;
220
+
output-high;
221
+
line-name = "usb_exicen_a";
222
+
};
223
+
#endif
224
+
225
+
usb_pins: usb-pins {
226
+
pinmux = <RZT2H_PORT_PINMUX(2, 2, 0x13)>, /* VBUSEN */
227
+
<RZT2H_PORT_PINMUX(2, 3, 0x13)>; /* OVRCUR */
228
+
};
16
229
};
+221
-1
arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+221
-1
arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
···
5
5
* Copyright (C) 2025 Renesas Electronics Corp.
6
6
*/
7
7
8
+
#include <dt-bindings/gpio/gpio.h>
9
+
#include <dt-bindings/leds/common.h>
10
+
#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
11
+
8
12
/ {
9
13
aliases {
10
14
i2c0 = &i2c0;
11
15
i2c1 = &i2c1;
16
+
mmc0 = &sdhi0;
17
+
mmc1 = &sdhi1;
12
18
serial0 = &sci0;
13
19
};
14
20
15
21
chosen {
16
22
stdout-path = "serial0:115200n8";
17
23
};
24
+
25
+
reg_1p8v: regulator-1p8v {
26
+
compatible = "regulator-fixed";
27
+
regulator-name = "fixed-1.8V";
28
+
regulator-min-microvolt = <1800000>;
29
+
regulator-max-microvolt = <1800000>;
30
+
regulator-boot-on;
31
+
regulator-always-on;
32
+
};
33
+
34
+
reg_3p3v: regulator-3p3v {
35
+
compatible = "regulator-fixed";
36
+
regulator-name = "fixed-3.3V";
37
+
regulator-min-microvolt = <3300000>;
38
+
regulator-max-microvolt = <3300000>;
39
+
regulator-boot-on;
40
+
regulator-always-on;
41
+
};
42
+
43
+
#if SD0_SD
44
+
vqmmc_sdhi0: regulator-vqmmc-sdhi0 {
45
+
compatible = "regulator-gpio";
46
+
regulator-name = "SDHI0 VqmmC";
47
+
gpios = <&pinctrl RZT2H_GPIO(2, 6) GPIO_ACTIVE_HIGH>;
48
+
regulator-min-microvolt = <1800000>;
49
+
regulator-max-microvolt = <3300000>;
50
+
gpios-states = <0>;
51
+
states = <3300000 0>, <1800000 1>;
52
+
};
53
+
#endif
54
+
55
+
#if SD1_MICRO_SD
56
+
vccq_sdhi1: regulator-vccq-sdhi1 {
57
+
compatible = "regulator-gpio";
58
+
regulator-name = "SDHI1 VccQ";
59
+
regulator-min-microvolt = <1800000>;
60
+
regulator-max-microvolt = <3300000>;
61
+
gpios = <&pinctrl RZT2H_GPIO(8, 6) GPIO_ACTIVE_HIGH>;
62
+
gpios-states = <0>;
63
+
states = <3300000 0>, <1800000 1>;
64
+
};
65
+
#endif
66
+
};
67
+
68
+
&ehci {
69
+
dr_mode = "otg";
70
+
status = "okay";
18
71
};
19
72
20
73
&extal_clk {
21
74
clock-frequency = <25000000>;
22
75
};
23
76
24
-
&sci0 {
77
+
&hsusb {
78
+
dr_mode = "otg";
25
79
status = "okay";
80
+
};
81
+
82
+
&i2c0 {
83
+
eeprom: eeprom@50 {
84
+
compatible = "renesas,r1ex24016", "atmel,24c16";
85
+
reg = <0x50>;
86
+
pagesize = <16>;
87
+
};
88
+
};
89
+
90
+
&ohci {
91
+
dr_mode = "otg";
92
+
status = "okay";
93
+
};
94
+
95
+
&pinctrl {
96
+
/*
97
+
* SCI0 Pin Configuration:
98
+
* ------------------------
99
+
* Signal | Pin | RZ/T2H (SW4) | RZ/N2H (DSW9)
100
+
* -----------|---------|--------------|---------------
101
+
* SCI0_RXD | P27_4 | 5: ON, 6: OFF| 1: ON, 2: OFF
102
+
* SCI0_TXD | P27_5 | 7: ON, 8: OFF| 3: ON, 4: OFF
103
+
*/
104
+
sci0_pins: sci0-pins {
105
+
pinmux = <RZT2H_PORT_PINMUX(27, 4, 0x14)>,
106
+
<RZT2H_PORT_PINMUX(27, 5, 0x14)>;
107
+
};
108
+
109
+
#if SD0_EMMC
110
+
sdhi0-emmc-iovs-hog {
111
+
gpio-hog;
112
+
gpios = <RZT2H_GPIO(2, 6) GPIO_ACTIVE_HIGH>;
113
+
output-high;
114
+
line-name = "SD0_IOVS";
115
+
};
116
+
#endif
117
+
118
+
sdhi0_emmc_pins: sd0-emmc-group {
119
+
data-pins {
120
+
pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */
121
+
<RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
122
+
<RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
123
+
<RZT2H_PORT_PINMUX(12, 5, 0x29)>, /* SD0_DATA3 */
124
+
<RZT2H_PORT_PINMUX(12, 6, 0x29)>, /* SD0_DATA4 */
125
+
<RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */
126
+
<RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */
127
+
<RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */
128
+
};
129
+
130
+
ctrl-pins {
131
+
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
132
+
<RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
133
+
<RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
134
+
};
135
+
};
136
+
137
+
#if SD0_SD
138
+
sdhi0-pwen-hog {
139
+
gpio-hog;
140
+
gpios = <RZT2H_GPIO(2, 5) GPIO_ACTIVE_HIGH>;
141
+
output-high;
142
+
line-name = "SD0_PWEN";
143
+
};
144
+
#endif
145
+
146
+
sdhi0_sd_pins: sd0-sd-group {
147
+
data-pins {
148
+
pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */
149
+
<RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
150
+
<RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
151
+
<RZT2H_PORT_PINMUX(12, 5, 0x29)>; /* SD0_DATA3 */
152
+
};
153
+
154
+
ctrl-pins {
155
+
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
156
+
<RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
157
+
<RZT2H_PORT_PINMUX(22, 5, 0x29)>, /* SD0_CD */
158
+
<RZT2H_PORT_PINMUX(22, 6, 0x29)>; /* SD0_WP */
159
+
};
160
+
};
161
+
162
+
#if SD1_MICRO_SD
163
+
sdhi1-pwen-hog {
164
+
gpio-hog;
165
+
gpios = <RZT2H_GPIO(8, 5) GPIO_ACTIVE_HIGH>;
166
+
output-high;
167
+
line-name = "SD1_PWEN";
168
+
};
169
+
#endif
170
+
171
+
sdhi1_pins: sd1-group {
172
+
data-pins {
173
+
pinmux = <RZT2H_PORT_PINMUX(16, 7, 0x29)>, /* SD1_DATA0 */
174
+
<RZT2H_PORT_PINMUX(17, 0, 0x29)>, /* SD1_DATA1 */
175
+
<RZT2H_PORT_PINMUX(17, 1, 0x29)>, /* SD1_DATA2 */
176
+
<RZT2H_PORT_PINMUX(17, 2, 0x29)>; /* SD1_DATA3 */
177
+
};
178
+
179
+
ctrl-pins {
180
+
pinmux = <RZT2H_PORT_PINMUX(16, 5, 0x29)>, /* SD1_CLK */
181
+
<RZT2H_PORT_PINMUX(16, 6, 0x29)>, /* SD1_CMD */
182
+
<RZT2H_PORT_PINMUX(17, 4, 0x29)>; /* SD1_CD */
183
+
};
184
+
};
185
+
};
186
+
187
+
&sci0 {
188
+
pinctrl-0 = <&sci0_pins>;
189
+
pinctrl-names = "default";
190
+
status = "okay";
191
+
};
192
+
193
+
#if SD0_EMMC
194
+
&sdhi0 {
195
+
pinctrl-0 = <&sdhi0_emmc_pins>;
196
+
pinctrl-1 = <&sdhi0_emmc_pins>;
197
+
pinctrl-names = "default", "state_uhs";
198
+
vmmc-supply = <®_3p3v>;
199
+
vqmmc-supply = <®_1p8v>;
200
+
bus-width = <8>;
201
+
non-removable;
202
+
mmc-hs200-1_8v;
203
+
fixed-emmc-driver-type = <1>;
204
+
status = "okay";
205
+
};
206
+
#endif
207
+
208
+
#if SD0_SD
209
+
&sdhi0 {
210
+
pinctrl-0 = <&sdhi0_sd_pins>;
211
+
pinctrl-1 = <&sdhi0_sd_pins>;
212
+
pinctrl-names = "default", "state_uhs";
213
+
vmmc-supply = <®_3p3v>;
214
+
vqmmc-supply = <&vqmmc_sdhi0>;
215
+
bus-width = <4>;
216
+
sd-uhs-sdr50;
217
+
sd-uhs-sdr104;
218
+
status = "okay";
219
+
};
220
+
#endif
221
+
222
+
#if SD1_MICRO_SD
223
+
&sdhi1 {
224
+
pinctrl-0 = <&sdhi1_pins>;
225
+
pinctrl-1 = <&sdhi1_pins>;
226
+
pinctrl-names = "default", "state_uhs";
227
+
vmmc-supply = <®_3p3v>;
228
+
vqmmc-supply = <&vccq_sdhi1>;
229
+
bus-width = <4>;
230
+
sd-uhs-sdr50;
231
+
sd-uhs-sdr104;
232
+
status = "okay";
233
+
};
234
+
#endif
235
+
236
+
&usb2_phy {
237
+
pinctrl-0 = <&usb_pins>;
238
+
pinctrl-names = "default";
239
+
240
+
status = "okay";
241
+
};
242
+
243
+
&wdt2 {
244
+
status = "okay";
245
+
timeout-sec = <60>;
26
246
};