Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux

+53 -18

2 changed files

expand all

drivers

net

ethernet

mellanox

mlx5

core

steering

hws

definer.c

include

linux

mlx5

mlx5_ifc.h

+8 -5

drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c

··· 727 727 u32 *s_ipv6, *d_ipv6; 728 728 729 729 if (HWS_IS_FLD_SET_SZ(match_param, outer_headers.l4_type, 0x2) || 730 - HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_c2, 0xe) || 731 - HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_c4, 0x4)) { 730 + HWS_IS_FLD_SET_SZ(match_param, outer_headers.l4_type_ext, 0x4) || 731 + HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_c6, 0xa) || 732 + HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_d4, 0x4)) { 732 733 mlx5hws_err(cd->ctx, "Unsupported outer parameters set\n"); 733 734 return -EINVAL; 734 735 } ··· 904 903 u32 *s_ipv6, *d_ipv6; 905 904 906 905 if (HWS_IS_FLD_SET_SZ(match_param, inner_headers.l4_type, 0x2) || 907 - HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_c2, 0xe) || 908 - HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_c4, 0x4)) { 906 + HWS_IS_FLD_SET_SZ(match_param, inner_headers.l4_type_ext, 0x4) || 907 + HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_c6, 0xa) || 908 + HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_d4, 0x4)) { 909 909 mlx5hws_err(cd->ctx, "Unsupported inner parameters set\n"); 910 910 return -EINVAL; 911 911 } ··· 1281 1279 struct mlx5hws_definer_fc *curr_fc; 1282 1280 1283 1281 if (HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1a0, 0x8) || 1284 - HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1b8, 0x8) || 1282 + HWS_IS_FLD_SET_SZ(match_param, 1283 + misc_parameters_2.ipsec_next_header, 0x8) || 1285 1284 HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1c0, 0x40) || 1286 1285 HWS_IS_FLD_SET(match_param, misc_parameters_2.macsec_syndrome) || 1287 1286 HWS_IS_FLD_SET(match_param, misc_parameters_2.ipsec_syndrome)) {

+45 -13

include/linux/mlx5/mlx5_ifc.h

··· 420 420 421 421 /* Table 2170 - Flow Table Fields Supported 2 Format */ 422 422 struct mlx5_ifc_flow_table_fields_supported_2_bits { 423 - u8 reserved_at_0[0x2]; 423 + u8 inner_l4_type_ext[0x1]; 424 + u8 outer_l4_type_ext[0x1]; 424 425 u8 inner_l4_type[0x1]; 425 426 u8 outer_l4_type[0x1]; 426 427 u8 reserved_at_4[0xa]; ··· 430 429 u8 tunnel_header_0_1[0x1]; 431 430 u8 reserved_at_11[0xf]; 432 431 433 - u8 reserved_at_20[0x60]; 432 + u8 reserved_at_20[0xf]; 433 + u8 ipsec_next_header[0x1]; 434 + u8 reserved_at_30[0x10]; 435 + 436 + u8 reserved_at_40[0x40]; 434 437 }; 435 438 436 439 struct mlx5_ifc_flow_table_prop_layout_bits { ··· 557 552 MLX5_PACKET_L4_TYPE_UDP, 558 553 }; 559 554 555 + enum { 556 + MLX5_PACKET_L4_TYPE_EXT_NONE, 557 + MLX5_PACKET_L4_TYPE_EXT_TCP, 558 + MLX5_PACKET_L4_TYPE_EXT_UDP, 559 + MLX5_PACKET_L4_TYPE_EXT_ICMP, 560 + }; 561 + 560 562 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 561 563 u8 smac_47_16[0x20]; 562 564 ··· 590 578 u8 tcp_dport[0x10]; 591 579 592 580 u8 l4_type[0x2]; 593 - u8 reserved_at_c2[0xe]; 581 + u8 l4_type_ext[0x4]; 582 + u8 reserved_at_c6[0xa]; 594 583 u8 ipv4_ihl[0x4]; 595 - u8 reserved_at_c4[0x4]; 596 - 584 + u8 reserved_at_d4[0x4]; 597 585 u8 ttl_hoplimit[0x8]; 598 586 599 587 u8 udp_sport[0x10]; ··· 701 689 u8 metadata_reg_a[0x20]; 702 690 703 691 u8 reserved_at_1a0[0x8]; 704 - 705 692 u8 macsec_syndrome[0x8]; 706 693 u8 ipsec_syndrome[0x8]; 707 - u8 reserved_at_1b8[0x8]; 694 + u8 ipsec_next_header[0x8]; 708 695 709 696 u8 reserved_at_1c0[0x40]; 710 697 }; ··· 9994 9983 u8 reserved_at_20[0x60]; 9995 9984 }; 9996 9985 9986 + enum { 9987 + MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7, 9988 + }; 9989 + 9997 9990 struct mlx5_ifc_ptys_reg_bits { 9998 9991 u8 reserved_at_0[0x1]; 9999 9992 u8 an_disable_admin[0x1]; ··· 10034 10019 u8 ib_link_width_oper[0x10]; 10035 10020 u8 ib_proto_oper[0x10]; 10036 10021 10037 - u8 reserved_at_160[0x1c]; 10022 + u8 reserved_at_160[0x8]; 10023 + u8 lane_rate_oper[0x14]; 10038 10024 u8 connector_type[0x4]; 10039 10025 10040 10026 u8 eth_proto_lp_advertise[0x20]; ··· 10479 10463 u8 port_filter_update_en[8][0x20]; 10480 10464 }; 10481 10465 10466 + enum { 10467 + MLX5_BUF_OWNERSHIP_UNKNOWN = 0x0, 10468 + MLX5_BUF_OWNERSHIP_FW_OWNED = 0x1, 10469 + MLX5_BUF_OWNERSHIP_SW_OWNED = 0x2, 10470 + }; 10471 + 10482 10472 struct mlx5_ifc_pfcc_reg_bits { 10483 - u8 reserved_at_0[0x8]; 10473 + u8 reserved_at_0[0x4]; 10474 + u8 buf_ownership[0x2]; 10475 + u8 reserved_at_6[0x2]; 10484 10476 u8 local_port[0x8]; 10485 - u8 reserved_at_10[0xb]; 10477 + u8 reserved_at_10[0xa]; 10478 + u8 cable_length_mask[0x1]; 10486 10479 u8 ppan_mask_n[0x1]; 10487 10480 u8 minor_stall_mask[0x1]; 10488 10481 u8 critical_stall_mask[0x1]; ··· 10520 10495 u8 device_stall_minor_watermark[0x10]; 10521 10496 u8 device_stall_critical_watermark[0x10]; 10522 10497 10523 - u8 reserved_at_a0[0x60]; 10498 + u8 reserved_at_a0[0x18]; 10499 + u8 cable_length[0x8]; 10500 + 10501 + u8 reserved_at_c0[0x40]; 10524 10502 }; 10525 10503 10526 10504 struct mlx5_ifc_pelc_reg_bits { ··· 10624 10596 struct mlx5_ifc_pcam_enhanced_features_bits { 10625 10597 u8 reserved_at_0[0x10]; 10626 10598 u8 ppcnt_recovery_counters[0x1]; 10627 - u8 reserved_at_11[0xc]; 10599 + u8 reserved_at_11[0x7]; 10600 + u8 cable_length[0x1]; 10601 + u8 reserved_at_19[0x4]; 10628 10602 u8 fec_200G_per_lane_in_pplm[0x1]; 10629 10603 u8 reserved_at_1e[0x2a]; 10630 10604 u8 fec_100G_per_lane_in_pplm[0x1]; 10631 - u8 reserved_at_49[0x1f]; 10605 + u8 reserved_at_49[0xa]; 10606 + u8 buffer_ownership[0x1]; 10607 + u8 resereved_at_54[0x14]; 10632 10608 u8 fec_50G_per_lane_in_pplm[0x1]; 10633 10609 u8 reserved_at_69[0x4]; 10634 10610 u8 rx_icrc_encapsulated_counter[0x1];

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