Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2021-05-29' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Pretty quiet this week, couple of amdgpu, one i915, and a few misc otherwise.
ttm:
- prevent irrelevant swapout
amdgpu:
- MultiGPU fan fix
- VCN powergating fixes
amdkfd:
- Fix SDMA register offset error
meson:
- fix shutdown crash
i915:
- Re-enable LTTPR non-transparent LT mode for DPCD_REV < 1.4"
* tag 'drm-fixes-2021-05-29' of git://anongit.freedesktop.org/drm/drm:
drm/ttm: Skip swapout if ttm object is not populated
drm/i915: Reenable LTTPR non-transparent LT mode for DPCD_REV<1.4
drm/meson: fix shutdown crash when component not probed
drm/amdgpu/jpeg3: add cancel_delayed_work_sync before power gate
drm/amdgpu/jpeg2.5: add cancel_delayed_work_sync before power gate
drm/amdgpu/jpeg2.0: add cancel_delayed_work_sync before power gate
drm/amdgpu/vcn3: add cancel_delayed_work_sync before power gate
drm/amdgpu/vcn2.5: add cancel_delayed_work_sync before power gate
drm/amdgpu/vcn2.0: add cancel_delayed_work_sync before power gate
drm/amdgpu/vcn1: add cancel_delayed_work_sync before power gate
drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error
drm/amd/pm: correct MGpuFanBoost setting
+81
-57
+6
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
+6
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
···
156
156
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
157
157
break;
158
158
case 1:
159
-
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
159
+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
160
160
mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
161
161
break;
162
162
case 2:
163
-
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
164
-
mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
163
+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
164
+
mmSDMA2_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
165
165
break;
166
166
case 3:
167
-
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
168
-
mmSDMA3_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
167
+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
168
+
mmSDMA3_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
169
169
break;
170
170
}
171
171
···
450
450
engine_id, queue_id);
451
451
uint32_t i = 0, reg;
452
452
#undef HQD_N_REGS
453
-
#define HQD_N_REGS (19+6+7+10)
453
+
#define HQD_N_REGS (19+6+7+12)
454
454
455
455
*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
456
456
if (*dump == NULL)
+2
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+2
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
···
172
172
{
173
173
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
174
174
175
+
cancel_delayed_work_sync(&adev->vcn.idle_work);
176
+
175
177
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
176
178
RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
177
179
jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+2
-2
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+2
-2
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
···
187
187
static int jpeg_v2_5_hw_fini(void *handle)
188
188
{
189
189
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
190
-
struct amdgpu_ring *ring;
191
190
int i;
191
+
192
+
cancel_delayed_work_sync(&adev->vcn.idle_work);
192
193
193
194
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
194
195
if (adev->jpeg.harvest_config & (1 << i))
195
196
continue;
196
197
197
-
ring = &adev->jpeg.inst[i].ring_dec;
198
198
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
199
199
RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
200
200
jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+2
-2
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+2
-2
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
···
159
159
static int jpeg_v3_0_hw_fini(void *handle)
160
160
{
161
161
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
162
-
struct amdgpu_ring *ring;
163
162
164
-
ring = &adev->jpeg.inst->ring_dec;
163
+
cancel_delayed_work_sync(&adev->vcn.idle_work);
164
+
165
165
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
166
166
RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
167
167
jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+5
-1
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+5
-1
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
···
231
231
{
232
232
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
233
233
234
+
cancel_delayed_work_sync(&adev->vcn.idle_work);
235
+
234
236
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
235
-
RREG32_SOC15(VCN, 0, mmUVD_STATUS))
237
+
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
238
+
RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
236
239
vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
240
+
}
237
241
238
242
return 0;
239
243
}
+2
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+2
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
···
262
262
{
263
263
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
264
264
265
+
cancel_delayed_work_sync(&adev->vcn.idle_work);
266
+
265
267
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
266
268
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
267
269
RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
+2
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+2
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+2
-3
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+2
-3
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
···
372
372
static int vcn_v3_0_hw_fini(void *handle)
373
373
{
374
374
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
375
-
struct amdgpu_ring *ring;
376
375
int i;
376
+
377
+
cancel_delayed_work_sync(&adev->vcn.idle_work);
377
378
378
379
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
379
380
if (adev->vcn.harvest_config & (1 << i))
380
381
continue;
381
-
382
-
ring = &adev->vcn.inst[i].ring_dec;
383
382
384
383
if (!amdgpu_sriov_vf(adev)) {
385
384
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+10
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+10
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
···
3027
3027
3028
3028
static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
3029
3029
{
3030
+
struct smu_table_context *table_context = &smu->smu_table;
3031
+
PPTable_t *smc_pptable = table_context->driver_pptable;
3032
+
3033
+
/*
3034
+
* Skip the MGpuFanBoost setting for those ASICs
3035
+
* which do not support it
3036
+
*/
3037
+
if (!smc_pptable->MGpuFanBoostLimitRpm)
3038
+
return 0;
3039
+
3030
3040
return smu_cmn_send_smc_msg_with_param(smu,
3031
3041
SMU_MSG_SetMGpuFanBoostLimitRpm,
3032
3042
0,
+33
-38
drivers/gpu/drm/i915/display/intel_dp_link_training.c
+33
-38
drivers/gpu/drm/i915/display/intel_dp_link_training.c
···
128
128
return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
129
129
}
130
130
131
-
/**
132
-
* intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
133
-
* @intel_dp: Intel DP struct
134
-
*
135
-
* Read the LTTPR common and DPRX capabilities and switch to non-transparent
136
-
* link training mode if any is detected and read the PHY capabilities for all
137
-
* detected LTTPRs. In case of an LTTPR detection error or if the number of
138
-
* LTTPRs is more than is supported (8), fall back to the no-LTTPR,
139
-
* transparent mode link training mode.
140
-
*
141
-
* Returns:
142
-
* >0 if LTTPRs were detected and the non-transparent LT mode was set. The
143
-
* DPRX capabilities are read out.
144
-
* 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a
145
-
* detection failure and the transparent LT mode was set. The DPRX
146
-
* capabilities are read out.
147
-
* <0 Reading out the DPRX capabilities failed.
148
-
*/
149
-
int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
131
+
static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
150
132
{
151
133
int lttpr_count;
152
-
bool ret;
153
134
int i;
154
135
155
-
ret = intel_dp_read_lttpr_common_caps(intel_dp);
156
-
157
-
/* The DPTX shall read the DPRX caps after LTTPR detection. */
158
-
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
159
-
intel_dp_reset_lttpr_common_caps(intel_dp);
160
-
return -EIO;
161
-
}
162
-
163
-
if (!ret)
136
+
if (!intel_dp_read_lttpr_common_caps(intel_dp))
164
137
return 0;
165
-
166
-
/*
167
-
* The 0xF0000-0xF02FF range is only valid if the DPCD revision is
168
-
* at least 1.4.
169
-
*/
170
-
if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) {
171
-
intel_dp_reset_lttpr_common_caps(intel_dp);
172
-
return 0;
173
-
}
174
138
175
139
lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
176
140
/*
···
172
208
173
209
for (i = 0; i < lttpr_count; i++)
174
210
intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
211
+
212
+
return lttpr_count;
213
+
}
214
+
215
+
/**
216
+
* intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
217
+
* @intel_dp: Intel DP struct
218
+
*
219
+
* Read the LTTPR common and DPRX capabilities and switch to non-transparent
220
+
* link training mode if any is detected and read the PHY capabilities for all
221
+
* detected LTTPRs. In case of an LTTPR detection error or if the number of
222
+
* LTTPRs is more than is supported (8), fall back to the no-LTTPR,
223
+
* transparent mode link training mode.
224
+
*
225
+
* Returns:
226
+
* >0 if LTTPRs were detected and the non-transparent LT mode was set. The
227
+
* DPRX capabilities are read out.
228
+
* 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a
229
+
* detection failure and the transparent LT mode was set. The DPRX
230
+
* capabilities are read out.
231
+
* <0 Reading out the DPRX capabilities failed.
232
+
*/
233
+
int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
234
+
{
235
+
int lttpr_count = intel_dp_init_lttpr(intel_dp);
236
+
237
+
/* The DPTX shall read the DPRX caps after LTTPR detection. */
238
+
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
239
+
intel_dp_reset_lttpr_common_caps(intel_dp);
240
+
return -EIO;
241
+
}
175
242
176
243
return lttpr_count;
177
244
}
+5
-4
drivers/gpu/drm/meson/meson_drv.c
+5
-4
drivers/gpu/drm/meson/meson_drv.c
···
485
485
static void meson_drv_shutdown(struct platform_device *pdev)
486
486
{
487
487
struct meson_drm *priv = dev_get_drvdata(&pdev->dev);
488
-
struct drm_device *drm = priv->drm;
489
488
490
-
DRM_DEBUG_DRIVER("\n");
491
-
drm_kms_helper_poll_fini(drm);
492
-
drm_atomic_helper_shutdown(drm);
489
+
if (!priv)
490
+
return;
491
+
492
+
drm_kms_helper_poll_fini(priv->drm);
493
+
drm_atomic_helper_shutdown(priv->drm);
493
494
}
494
495
495
496
static int meson_drv_probe(struct platform_device *pdev)
+1
-1
drivers/gpu/drm/ttm/ttm_device.c
+1
-1
drivers/gpu/drm/ttm/ttm_device.c