Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"A fair number of fixes across the field. Nothing terribly
complicated; the one liners in below changelog should be fairly
descriptive.
Noteworthy is the SB1 change which the result of changes to binutils
resulting in one big gas warning for most files being assembled as
well as the asid_cache and branch emulation fixes which fix corruption
or possible uninteded behaviour of kernel or application code. The
remainder of fixes are more platforms or subsystem specific"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: R46000: Fix Micro-assembler field overflow for R4600 V2
MIPS: ptrace: Avoid smp_processor_id() in preemptible code
MIPS: Lemote 2F: cs5536: mfgpt: use raw locks
MIPS: SB1: Fix excessive kernel warnings.
MIPS: RC32434: fix broken PCI resource initialization
MIPS: malta: memory.c: Initialize the 'memsize' variable
MIPS: Fix typo when reporting cache and ftlb errors for ImgTec cores
MIPS: Fix inconsistancy of __NR_Linux_syscalls value
MIPS: Fix branch emulation of branch likely instructions.
MIPS: Fix a typo error in AUDIT_ARCH definition
MIPS: Change type of asid_cache to unsigned long
+28
-30
+1
-1
arch/mips/Makefile
+1
-1
arch/mips/Makefile
···
151
151
-Wa,--trap
152
152
cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \
153
153
-Wa,--trap
154
-
cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \
154
+
cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1 -mno-mdmx -mno-mips3d,-march=r5000) \
155
155
-Wa,--trap
156
156
cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap
157
157
cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \
+2
-2
arch/mips/include/asm/cpu-info.h
+2
-2
arch/mips/include/asm/cpu-info.h
···
39
39
#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
40
40
41
41
struct cpuinfo_mips {
42
-
unsigned int udelay_val;
43
-
unsigned int asid_cache;
42
+
unsigned long asid_cache;
44
43
45
44
/*
46
45
* Capability and feature descriptor structure for MIPS CPU
47
46
*/
48
47
unsigned long options;
49
48
unsigned long ases;
49
+
unsigned int udelay_val;
50
50
unsigned int processor_id;
51
51
unsigned int fpu_id;
52
52
unsigned int msa_id;
+3
-3
arch/mips/include/uapi/asm/unistd.h
+3
-3
arch/mips/include/uapi/asm/unistd.h
···
381
381
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
382
382
383
383
#define __NR_O32_Linux 4000
384
-
#define __NR_O32_Linux_syscalls 350
384
+
#define __NR_O32_Linux_syscalls 351
385
385
386
386
#if _MIPS_SIM == _MIPS_SIM_ABI64
387
387
···
710
710
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
711
711
712
712
#define __NR_64_Linux 5000
713
-
#define __NR_64_Linux_syscalls 310
713
+
#define __NR_64_Linux_syscalls 311
714
714
715
715
#if _MIPS_SIM == _MIPS_SIM_NABI32
716
716
···
1043
1043
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
1044
1044
1045
1045
#define __NR_N32_Linux 6000
1046
-
#define __NR_N32_Linux_syscalls 314
1046
+
#define __NR_N32_Linux_syscalls 315
1047
1047
1048
1048
#endif /* _UAPI_ASM_UNISTD_H */
+4
-4
arch/mips/kernel/branch.c
+4
-4
arch/mips/kernel/branch.c
···
317
317
if (regs->regs[insn.i_format.rs] ==
318
318
regs->regs[insn.i_format.rt]) {
319
319
epc = epc + 4 + (insn.i_format.simmediate << 2);
320
-
if (insn.i_format.rt == beql_op)
320
+
if (insn.i_format.opcode == beql_op)
321
321
ret = BRANCH_LIKELY_TAKEN;
322
322
} else
323
323
epc += 8;
···
329
329
if (regs->regs[insn.i_format.rs] !=
330
330
regs->regs[insn.i_format.rt]) {
331
331
epc = epc + 4 + (insn.i_format.simmediate << 2);
332
-
if (insn.i_format.rt == bnel_op)
332
+
if (insn.i_format.opcode == bnel_op)
333
333
ret = BRANCH_LIKELY_TAKEN;
334
334
} else
335
335
epc += 8;
···
341
341
/* rt field assumed to be zero */
342
342
if ((long)regs->regs[insn.i_format.rs] <= 0) {
343
343
epc = epc + 4 + (insn.i_format.simmediate << 2);
344
-
if (insn.i_format.rt == bnel_op)
344
+
if (insn.i_format.opcode == blezl_op)
345
345
ret = BRANCH_LIKELY_TAKEN;
346
346
} else
347
347
epc += 8;
···
353
353
/* rt field assumed to be zero */
354
354
if ((long)regs->regs[insn.i_format.rs] > 0) {
355
355
epc = epc + 4 + (insn.i_format.simmediate << 2);
356
-
if (insn.i_format.rt == bnel_op)
356
+
if (insn.i_format.opcode == bgtzl_op)
357
357
ret = BRANCH_LIKELY_TAKEN;
358
358
} else
359
359
epc += 8;
+7
-7
arch/mips/kernel/ptrace.c
+7
-7
arch/mips/kernel/ptrace.c
···
163
163
enum pt_watch_style style;
164
164
int i;
165
165
166
-
if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
166
+
if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
167
167
return -EIO;
168
168
if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
169
169
return -EIO;
···
177
177
#endif
178
178
179
179
__put_user(style, &addr->style);
180
-
__put_user(current_cpu_data.watch_reg_use_cnt,
180
+
__put_user(boot_cpu_data.watch_reg_use_cnt,
181
181
&addr->WATCH_STYLE.num_valid);
182
-
for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
182
+
for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
183
183
__put_user(child->thread.watch.mips3264.watchlo[i],
184
184
&addr->WATCH_STYLE.watchlo[i]);
185
185
__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
186
186
&addr->WATCH_STYLE.watchhi[i]);
187
-
__put_user(current_cpu_data.watch_reg_masks[i],
187
+
__put_user(boot_cpu_data.watch_reg_masks[i],
188
188
&addr->WATCH_STYLE.watch_masks[i]);
189
189
}
190
190
for (; i < 8; i++) {
···
204
204
unsigned long lt[NUM_WATCH_REGS];
205
205
u16 ht[NUM_WATCH_REGS];
206
206
207
-
if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
207
+
if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
208
208
return -EIO;
209
209
if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
210
210
return -EIO;
211
211
/* Check the values. */
212
-
for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
212
+
for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
213
213
__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
214
214
#ifdef CONFIG_32BIT
215
215
if (lt[i] & __UA_LIMIT)
···
228
228
return -EINVAL;
229
229
}
230
230
/* Install them. */
231
-
for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
231
+
for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
232
232
if (lt[i] & 7)
233
233
watch_active = 1;
234
234
child->thread.watch.mips3264.watchlo[i] = lt[i];
+2
-2
arch/mips/kernel/traps.c
+2
-2
arch/mips/kernel/traps.c
···
1545
1545
reg_val & (1<<30) ? "secondary" : "primary",
1546
1546
reg_val & (1<<31) ? "data" : "insn");
1547
1547
if (cpu_has_mips_r2 &&
1548
-
((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) {
1548
+
((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1549
1549
pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1550
1550
reg_val & (1<<29) ? "ED " : "",
1551
1551
reg_val & (1<<28) ? "ET " : "",
···
1585
1585
1586
1586
/* For the moment, report the problem and hang. */
1587
1587
if (cpu_has_mips_r2 &&
1588
-
((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) {
1588
+
((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1589
1589
pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1590
1590
read_c0_ecc());
1591
1591
pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
+5
-6
arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
+5
-6
arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
···
27
27
28
28
#include <cs5536/cs5536_mfgpt.h>
29
29
30
-
DEFINE_SPINLOCK(mfgpt_lock);
31
-
EXPORT_SYMBOL(mfgpt_lock);
30
+
static DEFINE_RAW_SPINLOCK(mfgpt_lock);
32
31
33
32
static u32 mfgpt_base;
34
33
···
54
55
static void init_mfgpt_timer(enum clock_event_mode mode,
55
56
struct clock_event_device *evt)
56
57
{
57
-
spin_lock(&mfgpt_lock);
58
+
raw_spin_lock(&mfgpt_lock);
58
59
59
60
switch (mode) {
60
61
case CLOCK_EVT_MODE_PERIODIC:
···
78
79
/* Nothing to do here */
79
80
break;
80
81
}
81
-
spin_unlock(&mfgpt_lock);
82
+
raw_spin_unlock(&mfgpt_lock);
82
83
}
83
84
84
85
static struct clock_event_device mfgpt_clockevent = {
···
156
157
static int old_count;
157
158
static u32 old_jifs;
158
159
159
-
spin_lock_irqsave(&mfgpt_lock, flags);
160
+
raw_spin_lock_irqsave(&mfgpt_lock, flags);
160
161
/*
161
162
* Although our caller may have the read side of xtime_lock,
162
163
* this is now a seqlock, and we are cheating in this routine
···
190
191
old_count = count;
191
192
old_jifs = jifs;
192
193
193
-
spin_unlock_irqrestore(&mfgpt_lock, flags);
194
+
raw_spin_unlock_irqrestore(&mfgpt_lock, flags);
194
195
195
196
return (cycle_t) (jifs * COMPARE) + count;
196
197
}
+2
-2
arch/mips/mm/page.c
+2
-2
arch/mips/mm/page.c
···
273
273
uasm_i_ori(&buf, A2, A0, off);
274
274
275
275
if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
276
-
uasm_i_lui(&buf, AT, 0xa000);
276
+
uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
277
277
278
278
off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
279
279
* cache_line_size : 0;
···
424
424
uasm_i_ori(&buf, A2, A0, off);
425
425
426
426
if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
427
-
uasm_i_lui(&buf, AT, 0xa000);
427
+
uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
428
428
429
429
off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
430
430
cache_line_size : 0;
+1
-1
arch/mips/mti-malta/malta-memory.c
+1
-1
arch/mips/mti-malta/malta-memory.c
···
27
27
fw_memblock_t * __init fw_getmdesc(int eva)
28
28
{
29
29
char *memsize_str, *ememsize_str __maybe_unused = NULL, *ptr;
30
-
unsigned long memsize, ememsize __maybe_unused = 0;
30
+
unsigned long memsize = 0, ememsize __maybe_unused = 0;
31
31
static char cmdline[COMMAND_LINE_SIZE] __initdata;
32
32
int tmp;
33
33
-1
arch/mips/pci/pci-rc32434.c
-1
arch/mips/pci/pci-rc32434.c
+1
-1
include/uapi/linux/audit.h
+1
-1
include/uapi/linux/audit.h
···
357
357
#define AUDIT_ARCH_MIPS64N32 (EM_MIPS|__AUDIT_ARCH_64BIT|\
358
358
__AUDIT_ARCH_CONVENTION_MIPS64_N32)
359
359
#define AUDIT_ARCH_MIPSEL64 (EM_MIPS|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
360
-
#define AUDIT_ARCH_MIPSEL64N32 (EM_MIPS|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE\
360
+
#define AUDIT_ARCH_MIPSEL64N32 (EM_MIPS|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE|\
361
361
__AUDIT_ARCH_CONVENTION_MIPS64_N32)
362
362
#define AUDIT_ARCH_OPENRISC (EM_OPENRISC)
363
363
#define AUDIT_ARCH_PARISC (EM_PARISC)