drm/msm/gpu: Add per-submission statistics

Add infrastructure to track statistics for GPU submissions
by sampling certain perfcounters before and after a submission.

To store the statistics, the per-ring memptrs region is
expanded to include room for up to 64 entries - this should
cover a reasonable amount of inflight submissions without
worrying about losing data. The target specific code inserts
PM4 commands to sample the counters before and after
submission and store them in the data region. The CPU can
access the data after the submission retires to make sense
of the statistics and communicate them to the user.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

authored by

Jordan Crouse and committed by

Rob Clark 7 years ago 56869210 93f7abf1

+54 -16

3 changed files

expand all

drivers

gpu

drm

msm

adreno

a6xx_gmu.c

a6xx_gpu.c

msm_ringbuffer.h

+12 -8

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

··· 346 346 ret = gmu_poll_timeout(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 347 347 !val, 100, 10000); 348 348 349 - if (!ret) { 350 - gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 351 - 352 - /* Re-enable the power counter */ 353 - gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 354 - return 0; 349 + if (ret) { 350 + DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 351 + return ret; 355 352 } 356 353 357 - DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 358 - return ret; 354 + gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 355 + 356 + /* Set up CX GMU counter 0 to count busy ticks */ 357 + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 358 + gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); 359 + 360 + /* Enable the power counter */ 361 + gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 362 + return 0; 359 363 } 360 364 361 365 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)

+26 -8

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

··· 67 67 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 68 68 } 69 69 70 + static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 71 + u64 iova) 72 + { 73 + OUT_PKT7(ring, CP_REG_TO_MEM, 3); 74 + OUT_RING(ring, counter | (1 << 30) | (2 << 18)); 75 + OUT_RING(ring, lower_32_bits(iova)); 76 + OUT_RING(ring, upper_32_bits(iova)); 77 + } 78 + 70 79 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 71 80 struct msm_file_private *ctx) 72 81 { 82 + unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 73 83 struct msm_drm_private *priv = gpu->dev->dev_private; 74 84 struct msm_ringbuffer *ring = submit->ring; 75 85 unsigned int i; 86 + 87 + get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 88 + rbmemptr_stats(ring, index, cpcycles_start)); 89 + 90 + /* 91 + * For PM4 the GMU register offsets are calculated from the base of the 92 + * GPU registers so we need to add 0x1a800 to the register value on A630 93 + * to get the right value from PM4. 94 + */ 95 + get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800, 96 + rbmemptr_stats(ring, index, alwayson_start)); 76 97 77 98 /* Invalidate CCU depth and color */ 78 99 OUT_PKT7(ring, CP_EVENT_WRITE, 1); ··· 118 97 break; 119 98 } 120 99 } 100 + 101 + get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 102 + rbmemptr_stats(ring, index, cpcycles_end)); 103 + get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800, 104 + rbmemptr_stats(ring, index, alwayson_end)); 121 105 122 106 /* Write the fence to the scratch register */ 123 107 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); ··· 412 386 413 387 /* Select CP0 to always count cycles */ 414 388 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); 415 - 416 - /* FIXME: not sure if this should live here or in a6xx_gmu.c */ 417 - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 418 - 0xff000000); 419 - gmu_rmw(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 420 - 0xff, 0x20); 421 - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 422 - 0x01); 423 389 424 390 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1); 425 391 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);

+16

drivers/gpu/drm/msm/msm_ringbuffer.h

··· 23 23 #define rbmemptr(ring, member) \ 24 24 ((ring)->memptrs_iova + offsetof(struct msm_rbmemptrs, member)) 25 25 26 + #define rbmemptr_stats(ring, index, member) \ 27 + (rbmemptr((ring), stats) + \ 28 + ((index) * sizeof(struct msm_gpu_submit_stats)) + \ 29 + offsetof(struct msm_gpu_submit_stats, member)) 30 + 31 + struct msm_gpu_submit_stats { 32 + u64 cpcycles_start; 33 + u64 cpcycles_end; 34 + u64 alwayson_start; 35 + u64 alwayson_end; 36 + }; 37 + 38 + #define MSM_GPU_SUBMIT_STATS_COUNT 64 39 + 26 40 struct msm_rbmemptrs { 27 41 volatile uint32_t rptr; 28 42 volatile uint32_t fence; 43 + 44 + volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT]; 29 45 }; 30 46 31 47 struct msm_ringbuffer {

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