Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"Boston platform support:
- Document DT bindings
- Add CLK driver for board clocks
CM:
- Avoid per-core locking with CM3 & higher
- WARN on attempt to lock invalid VP, not BUG
CPS:
- Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6
- Prevent multi-core with dcache aliasing
- Handle cores not powering down more gracefully
- Handle spurious VP starts more gracefully
DSP:
- Add lwx & lhx missaligned access support
eBPF:
- Add MIPS support along with many supporting change to add the
required infrastructure
Generic arch code:
- Misc sysmips MIPS_ATOMIC_SET fixes
- Drop duplicate HAVE_SYSCALL_TRACEPOINTS
- Negate error syscall return in trace
- Correct forced syscall errors
- Traced negative syscalls should return -ENOSYS
- Allow samples/bpf/tracex5 to access syscall arguments for sane
traces
- Cleanup from old Kconfig options in defconfigs
- Fix PREF instruction usage by memcpy for MIPS R6
- Fix various special cases in the FPU eulation
- Fix some special cases in MIPS16e2 support
- Fix MIPS I ISA /proc/cpuinfo reporting
- Sort MIPS Kconfig alphabetically
- Fix minimum alignment requirement of IRQ stack as required by
ABI / GCC
- Fix special cases in the module loader
- Perform post-DMA cache flushes on systems with MAARs
- Probe the I6500 CPU
- Cleanup cmpxchg and add support for 1 and 2 byte operations
- Use queued read/write locks (qrwlock)
- Use queued spinlocks (qspinlock)
- Add CPU shared FTLB feature detection
- Handle tlbex-tlbp race condition
- Allow storing pgd in C0_CONTEXT for MIPSr6
- Use current_cpu_type() in m4kc_tlbp_war()
- Support Boston in the generic kernel
Generic platform:
- yamon-dt: Pull YAMON DT shim code out of SEAD-3 board
- yamon-dt: Support > 256MB of RAM
- yamon-dt: Use serial* rather than uart* aliases
- Abstract FDT fixup application
- Set RTC_ALWAYS_BCD to 0
- Add a MAINTAINERS entry
core kernel:
- qspinlock.c: include linux/prefetch.h
Loongson 3:
- Add support
Perf:
- Add I6500 support
SEAD-3:
- Remove GIC timer from DT
- Set interrupt-parent per-device, not at root node
- Fix GIC interrupt specifiers
SMP:
- Skip IPI setup if we only have a single CPU
VDSO:
- Make comment match reality
- Improvements to time code in VDSO"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (86 commits)
locking/qspinlock: Include linux/prefetch.h
MIPS: Fix MIPS I ISA /proc/cpuinfo reporting
MIPS: Fix minimum alignment requirement of IRQ stack
MIPS: generic: Support MIPS Boston development boards
MIPS: DTS: img: Don't attempt to build-in all .dtb files
clk: boston: Add a driver for MIPS Boston board clocks
dt-bindings: Document img,boston-clock binding
MIPS: Traced negative syscalls should return -ENOSYS
MIPS: Correct forced syscall errors
MIPS: Negate error syscall return in trace
MIPS: Drop duplicate HAVE_SYSCALL_TRACEPOINTS select
MIPS16e2: Provide feature overrides for non-MIPS16 systems
MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfo
MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructions
MIPS: MIPS16e2: Identify ASE presence
MIPS: VDSO: Fix a mismatch between comment and preprocessor constant
MIPS: VDSO: Add implementation of gettimeofday() fallback
MIPS: VDSO: Add implementation of clock_gettime() fallback
MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse()
MIPS: Use current_cpu_type() in m4kc_tlbp_war()
...
+2462
-1845
+31
Documentation/devicetree/bindings/clock/img,boston-clock.txt
+31
Documentation/devicetree/bindings/clock/img,boston-clock.txt
···
1
+
Binding for Imagination Technologies MIPS Boston clock sources.
2
+
3
+
This binding uses the common clock binding[1].
4
+
5
+
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
+
7
+
The device node must be a child node of the syscon node corresponding to the
8
+
Boston system's platform registers.
9
+
10
+
Required properties:
11
+
- compatible : Should be "img,boston-clock".
12
+
- #clock-cells : Should be set to 1.
13
+
Values available for clock consumers can be found in the header file:
14
+
<dt-bindings/clock/boston-clock.h>
15
+
16
+
Example:
17
+
18
+
system-controller@17ffd000 {
19
+
compatible = "img,boston-platform-regs", "syscon";
20
+
reg = <0x17ffd000 0x1000>;
21
+
22
+
clk_boston: clock {
23
+
compatible = "img,boston-clock";
24
+
#clock-cells = <1>;
25
+
};
26
+
};
27
+
28
+
uart0: uart@17ffe000 {
29
+
/* ... */
30
+
clocks = <&clk_boston BOSTON_CLK_SYS>;
31
+
};
+16
MAINTAINERS
+16
MAINTAINERS
···
8732
8732
F: Documentation/mips/
8733
8733
F: arch/mips/
8734
8734
8735
+
MIPS GENERIC PLATFORM
8736
+
M: Paul Burton <paul.burton@imgtec.com>
8737
+
L: linux-mips@linux-mips.org
8738
+
S: Supported
8739
+
F: arch/mips/generic/
8740
+
8735
8741
MIPS/LOONGSON1 ARCHITECTURE
8736
8742
M: Keguang Zhang <keguang.zhang@gmail.com>
8737
8743
L: linux-mips@linux-mips.org
···
8746
8740
F: arch/mips/include/asm/mach-loongson32/
8747
8741
F: drivers/*/*loongson1*
8748
8742
F: drivers/*/*/*loongson1*
8743
+
8744
+
MIPS BOSTON DEVELOPMENT BOARD
8745
+
M: Paul Burton <paul.burton@imgtec.com>
8746
+
L: linux-mips@linux-mips.org
8747
+
S: Maintained
8748
+
F: Documentation/devicetree/bindings/clock/img,boston-clock.txt
8749
+
F: arch/mips/boot/dts/img/boston.dts
8750
+
F: arch/mips/configs/generic/board-boston.config
8751
+
F: drivers/clk/imgtec/clk-boston.c
8752
+
F: include/dt-bindings/clock/boston-clock.h
8749
8753
8750
8754
MIROSOUND PCM20 FM RADIO RECEIVER DRIVER
8751
8755
M: Hans Verkuil <hverkuil@xs4all.nl>
+65
-53
arch/mips/Kconfig
+65
-53
arch/mips/Kconfig
···
1
1
config MIPS
2
2
bool
3
3
default y
4
-
select ARCH_SUPPORTS_UPROBES
4
+
select ARCH_BINFMT_ELF_STATE
5
+
select ARCH_CLOCKSOURCE_DATA
6
+
select ARCH_DISCARD_MEMBLOCK
7
+
select ARCH_HAS_ELF_RANDOMIZE
8
+
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
5
9
select ARCH_MIGHT_HAVE_PC_PARPORT
6
10
select ARCH_MIGHT_HAVE_PC_SERIO
7
-
select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
11
+
select ARCH_SUPPORTS_UPROBES
8
12
select ARCH_USE_BUILTIN_BSWAP
9
-
select HAVE_CONTEXT_TRACKING
10
-
select HAVE_GENERIC_DMA_COHERENT
11
-
select HAVE_IDE
12
-
select HAVE_IRQ_EXIT_ON_IRQ_STACK
13
-
select HAVE_OPROFILE
14
-
select HAVE_PERF_EVENTS
15
-
select PERF_USE_VMALLOC
13
+
select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
14
+
select ARCH_USE_QUEUED_RWLOCKS
15
+
select ARCH_USE_QUEUED_SPINLOCKS
16
+
select ARCH_WANT_IPC_PARSE_VERSION
17
+
select BUILDTIME_EXTABLE_SORT
18
+
select CLONE_BACKWARDS
19
+
select CPU_PM if CPU_IDLE
20
+
select GENERIC_ATOMIC64 if !64BIT
21
+
select GENERIC_CLOCKEVENTS
22
+
select GENERIC_CMOS_UPDATE
23
+
select GENERIC_CPU_AUTOPROBE
24
+
select GENERIC_IRQ_PROBE
25
+
select GENERIC_IRQ_SHOW
26
+
select GENERIC_PCI_IOMAP
27
+
select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
28
+
select GENERIC_SMP_IDLE_THREAD
29
+
select GENERIC_TIME_VSYSCALL
30
+
select HANDLE_DOMAIN_IRQ
31
+
select HAVE_ARCH_JUMP_LABEL
16
32
select HAVE_ARCH_KGDB
17
33
select HAVE_ARCH_MMAP_RND_BITS if MMU
18
34
select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
19
35
select HAVE_ARCH_SECCOMP_FILTER
20
36
select HAVE_ARCH_TRACEHOOK
21
-
select HAVE_CBPF_JIT if !CPU_MICROMIPS
22
-
select HAVE_FUNCTION_TRACER
23
-
select HAVE_DYNAMIC_FTRACE
24
-
select HAVE_FTRACE_MCOUNT_RECORD
37
+
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
38
+
select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
39
+
select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
40
+
select HAVE_CC_STACKPROTECTOR
41
+
select HAVE_CONTEXT_TRACKING
42
+
select HAVE_COPY_THREAD_TLS
25
43
select HAVE_C_RECORDMCOUNT
44
+
select HAVE_DEBUG_KMEMLEAK
45
+
select HAVE_DEBUG_STACKOVERFLOW
46
+
select HAVE_DMA_API_DEBUG
47
+
select HAVE_DMA_CONTIGUOUS
48
+
select HAVE_DYNAMIC_FTRACE
49
+
select HAVE_EXIT_THREAD
50
+
select HAVE_FTRACE_MCOUNT_RECORD
26
51
select HAVE_FUNCTION_GRAPH_TRACER
52
+
select HAVE_FUNCTION_TRACER
53
+
select HAVE_GENERIC_DMA_COHERENT
54
+
select HAVE_IDE
55
+
select HAVE_IRQ_EXIT_ON_IRQ_STACK
56
+
select HAVE_IRQ_TIME_ACCOUNTING
27
57
select HAVE_KPROBES
28
58
select HAVE_KRETPROBES
29
-
select HAVE_SYSCALL_TRACEPOINTS
30
-
select HAVE_DEBUG_KMEMLEAK
31
-
select HAVE_SYSCALL_TRACEPOINTS
32
-
select ARCH_HAS_ELF_RANDOMIZE
33
-
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
34
-
select RTC_LIB if !MACH_LOONGSON64
35
-
select GENERIC_ATOMIC64 if !64BIT
36
-
select HAVE_DMA_CONTIGUOUS
37
-
select HAVE_DMA_API_DEBUG
38
-
select GENERIC_IRQ_PROBE
39
-
select GENERIC_IRQ_SHOW
40
-
select GENERIC_PCI_IOMAP
41
-
select HAVE_ARCH_JUMP_LABEL
42
-
select ARCH_WANT_IPC_PARSE_VERSION
43
-
select IRQ_FORCED_THREADING
44
59
select HAVE_MEMBLOCK
45
60
select HAVE_MEMBLOCK_NODE_MAP
46
-
select ARCH_DISCARD_MEMBLOCK
47
-
select GENERIC_SMP_IDLE_THREAD
48
-
select BUILDTIME_EXTABLE_SORT
49
-
select GENERIC_CPU_AUTOPROBE
50
-
select GENERIC_CLOCKEVENTS
51
-
select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
52
-
select GENERIC_CMOS_UPDATE
53
61
select HAVE_MOD_ARCH_SPECIFIC
54
62
select HAVE_NMI
55
-
select VIRT_TO_BUS
56
-
select MODULES_USE_ELF_REL if MODULES
57
-
select MODULES_USE_ELF_RELA if MODULES && 64BIT
58
-
select CLONE_BACKWARDS
59
-
select HAVE_DEBUG_STACKOVERFLOW
60
-
select HAVE_CC_STACKPROTECTOR
61
-
select CPU_PM if CPU_IDLE
62
-
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
63
-
select ARCH_BINFMT_ELF_STATE
64
-
select SYSCTL_EXCEPTION_TRACE
65
-
select HAVE_VIRT_CPU_ACCOUNTING_GEN
66
-
select HAVE_IRQ_TIME_ACCOUNTING
67
-
select GENERIC_TIME_VSYSCALL
68
-
select ARCH_CLOCKSOURCE_DATA
69
-
select HANDLE_DOMAIN_IRQ
70
-
select HAVE_EXIT_THREAD
63
+
select HAVE_OPROFILE
64
+
select HAVE_PERF_EVENTS
71
65
select HAVE_REGS_AND_STACK_ACCESS_API
72
-
select HAVE_COPY_THREAD_TLS
66
+
select HAVE_SYSCALL_TRACEPOINTS
67
+
select HAVE_VIRT_CPU_ACCOUNTING_GEN
68
+
select IRQ_FORCED_THREADING
69
+
select MODULES_USE_ELF_RELA if MODULES && 64BIT
70
+
select MODULES_USE_ELF_REL if MODULES
71
+
select PERF_USE_VMALLOC
72
+
select RTC_LIB if !MACH_LOONGSON64
73
+
select SYSCTL_EXCEPTION_TRACE
74
+
select VIRT_TO_BUS
73
75
74
76
menu "Machine selection"
75
77
···
1181
1179
The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
1182
1180
to allow access to command line and entropy sources.
1183
1181
1182
+
config MIPS_CBPF_JIT
1183
+
def_bool y
1184
+
depends on BPF_JIT && HAVE_CBPF_JIT
1185
+
1186
+
config MIPS_EBPF_JIT
1187
+
def_bool y
1188
+
depends on BPF_JIT && HAVE_EBPF_JIT
1189
+
1190
+
1184
1191
#
1185
1192
# Endianness selection. Sufficiently obscure so many users don't know what to
1186
1193
# answer,so we try hard to limit the available choices. Also the use of a
···
2073
2062
bool
2074
2063
config MIPS_PGD_C0_CONTEXT
2075
2064
bool
2076
-
default y if 64BIT && CPU_MIPSR2 && !CPU_XLP
2065
+
default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
2077
2066
2078
2067
#
2079
2068
# Set to y for ptrace access to watch registers.
···
2381
2370
select SMP
2382
2371
select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
2383
2372
select SYS_SUPPORTS_HOTPLUG_CPU
2373
+
select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
2384
2374
select SYS_SUPPORTS_SMP
2385
2375
select WEAK_ORDERING
2386
2376
help
+1
-1
arch/mips/Makefile
+1
-1
arch/mips/Makefile
···
160
160
-Wa,-mips32 -Wa,--trap
161
161
cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
162
162
-Wa,-mips32r2 -Wa,--trap
163
-
cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap
163
+
cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap -modd-spreg
164
164
cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
165
165
-Wa,-mips64 -Wa,--trap
166
166
cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
+3
-2
arch/mips/boot/dts/img/Makefile
+3
-2
arch/mips/boot/dts/img/Makefile
···
1
-
dtb-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb
1
+
dtb-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += boston.dtb
2
2
3
-
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
3
+
dtb-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb
4
+
obj-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb.o
4
5
5
6
# Force kbuild to make empty built-in.o if necessary
6
7
obj- += dummy.o
+224
arch/mips/boot/dts/img/boston.dts
+224
arch/mips/boot/dts/img/boston.dts
···
1
+
/dts-v1/;
2
+
3
+
#include <dt-bindings/clock/boston-clock.h>
4
+
#include <dt-bindings/gpio/gpio.h>
5
+
#include <dt-bindings/interrupt-controller/irq.h>
6
+
#include <dt-bindings/interrupt-controller/mips-gic.h>
7
+
8
+
/ {
9
+
#address-cells = <1>;
10
+
#size-cells = <1>;
11
+
compatible = "img,boston";
12
+
13
+
chosen {
14
+
stdout-path = "uart0:115200";
15
+
};
16
+
17
+
aliases {
18
+
uart0 = &uart0;
19
+
};
20
+
21
+
cpus {
22
+
#address-cells = <1>;
23
+
#size-cells = <0>;
24
+
25
+
cpu@0 {
26
+
device_type = "cpu";
27
+
compatible = "img,mips";
28
+
reg = <0>;
29
+
clocks = <&clk_boston BOSTON_CLK_CPU>;
30
+
};
31
+
};
32
+
33
+
memory@0 {
34
+
device_type = "memory";
35
+
reg = <0x00000000 0x10000000>;
36
+
};
37
+
38
+
pci0: pci@10000000 {
39
+
compatible = "xlnx,axi-pcie-host-1.00.a";
40
+
device_type = "pci";
41
+
reg = <0x10000000 0x2000000>;
42
+
43
+
#address-cells = <3>;
44
+
#size-cells = <2>;
45
+
#interrupt-cells = <1>;
46
+
47
+
interrupt-parent = <&gic>;
48
+
interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
49
+
50
+
ranges = <0x02000000 0 0x40000000
51
+
0x40000000 0 0x40000000>;
52
+
53
+
interrupt-map-mask = <0 0 0 7>;
54
+
interrupt-map = <0 0 0 1 &pci0_intc 1>,
55
+
<0 0 0 2 &pci0_intc 2>,
56
+
<0 0 0 3 &pci0_intc 3>,
57
+
<0 0 0 4 &pci0_intc 4>;
58
+
59
+
pci0_intc: interrupt-controller {
60
+
interrupt-controller;
61
+
#address-cells = <0>;
62
+
#interrupt-cells = <1>;
63
+
};
64
+
};
65
+
66
+
pci1: pci@12000000 {
67
+
compatible = "xlnx,axi-pcie-host-1.00.a";
68
+
device_type = "pci";
69
+
reg = <0x12000000 0x2000000>;
70
+
71
+
#address-cells = <3>;
72
+
#size-cells = <2>;
73
+
#interrupt-cells = <1>;
74
+
75
+
interrupt-parent = <&gic>;
76
+
interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
77
+
78
+
ranges = <0x02000000 0 0x20000000
79
+
0x20000000 0 0x20000000>;
80
+
81
+
interrupt-map-mask = <0 0 0 7>;
82
+
interrupt-map = <0 0 0 1 &pci1_intc 1>,
83
+
<0 0 0 2 &pci1_intc 2>,
84
+
<0 0 0 3 &pci1_intc 3>,
85
+
<0 0 0 4 &pci1_intc 4>;
86
+
87
+
pci1_intc: interrupt-controller {
88
+
interrupt-controller;
89
+
#address-cells = <0>;
90
+
#interrupt-cells = <1>;
91
+
};
92
+
};
93
+
94
+
pci2: pci@14000000 {
95
+
compatible = "xlnx,axi-pcie-host-1.00.a";
96
+
device_type = "pci";
97
+
reg = <0x14000000 0x2000000>;
98
+
99
+
#address-cells = <3>;
100
+
#size-cells = <2>;
101
+
#interrupt-cells = <1>;
102
+
103
+
interrupt-parent = <&gic>;
104
+
interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
105
+
106
+
ranges = <0x02000000 0 0x16000000
107
+
0x16000000 0 0x100000>;
108
+
109
+
interrupt-map-mask = <0 0 0 7>;
110
+
interrupt-map = <0 0 0 1 &pci2_intc 1>,
111
+
<0 0 0 2 &pci2_intc 2>,
112
+
<0 0 0 3 &pci2_intc 3>,
113
+
<0 0 0 4 &pci2_intc 4>;
114
+
115
+
pci2_intc: interrupt-controller {
116
+
interrupt-controller;
117
+
#address-cells = <0>;
118
+
#interrupt-cells = <1>;
119
+
};
120
+
121
+
pci2_root@0,0,0 {
122
+
compatible = "pci10ee,7021";
123
+
reg = <0x00000000 0 0 0 0>;
124
+
125
+
#address-cells = <3>;
126
+
#size-cells = <2>;
127
+
#interrupt-cells = <1>;
128
+
129
+
eg20t_bridge@1,0,0 {
130
+
compatible = "pci8086,8800";
131
+
reg = <0x00010000 0 0 0 0>;
132
+
133
+
#address-cells = <3>;
134
+
#size-cells = <2>;
135
+
#interrupt-cells = <1>;
136
+
137
+
eg20t_mac@2,0,1 {
138
+
compatible = "pci8086,8802";
139
+
reg = <0x00020100 0 0 0 0>;
140
+
phy-reset-gpios = <&eg20t_gpio 6
141
+
GPIO_ACTIVE_LOW>;
142
+
};
143
+
144
+
eg20t_gpio: eg20t_gpio@2,0,2 {
145
+
compatible = "pci8086,8803";
146
+
reg = <0x00020200 0 0 0 0>;
147
+
148
+
gpio-controller;
149
+
#gpio-cells = <2>;
150
+
};
151
+
152
+
eg20t_i2c@2,12,2 {
153
+
compatible = "pci8086,8817";
154
+
reg = <0x00026200 0 0 0 0>;
155
+
156
+
#address-cells = <1>;
157
+
#size-cells = <0>;
158
+
159
+
rtc@0x68 {
160
+
compatible = "st,m41t81s";
161
+
reg = <0x68>;
162
+
};
163
+
};
164
+
};
165
+
};
166
+
};
167
+
168
+
gic: interrupt-controller@16120000 {
169
+
compatible = "mti,gic";
170
+
reg = <0x16120000 0x20000>;
171
+
172
+
interrupt-controller;
173
+
#interrupt-cells = <3>;
174
+
175
+
timer {
176
+
compatible = "mti,gic-timer";
177
+
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
178
+
clocks = <&clk_boston BOSTON_CLK_CPU>;
179
+
};
180
+
};
181
+
182
+
cdmm@16140000 {
183
+
compatible = "mti,mips-cdmm";
184
+
reg = <0x16140000 0x8000>;
185
+
};
186
+
187
+
cpc@16200000 {
188
+
compatible = "mti,mips-cpc";
189
+
reg = <0x16200000 0x8000>;
190
+
};
191
+
192
+
plat_regs: system-controller@17ffd000 {
193
+
compatible = "img,boston-platform-regs", "syscon";
194
+
reg = <0x17ffd000 0x1000>;
195
+
196
+
clk_boston: clock {
197
+
compatible = "img,boston-clock";
198
+
#clock-cells = <1>;
199
+
};
200
+
};
201
+
202
+
reboot: syscon-reboot {
203
+
compatible = "syscon-reboot";
204
+
regmap = <&plat_regs>;
205
+
offset = <0x10>;
206
+
mask = <0x10>;
207
+
};
208
+
209
+
uart0: uart@17ffe000 {
210
+
compatible = "ns16550a";
211
+
reg = <0x17ffe000 0x1000>;
212
+
reg-shift = <2>;
213
+
214
+
interrupt-parent = <&gic>;
215
+
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
216
+
217
+
clocks = <&clk_boston BOSTON_CLK_SYS>;
218
+
};
219
+
220
+
lcd: lcd@17fff000 {
221
+
compatible = "img,boston-lcd";
222
+
reg = <0x17fff000 0x8>;
223
+
};
224
+
};
+11
-13
arch/mips/boot/dts/mti/sead3.dts
+11
-13
arch/mips/boot/dts/mti/sead3.dts
···
11
11
#size-cells = <1>;
12
12
compatible = "mti,sead-3";
13
13
model = "MIPS SEAD-3";
14
-
interrupt-parent = <&gic>;
15
14
16
15
chosen {
17
-
stdout-path = "uart1:115200";
16
+
stdout-path = "serial1:115200";
18
17
};
19
18
20
19
aliases {
21
-
uart0 = &uart0;
22
-
uart1 = &uart1;
20
+
serial0 = &uart0;
21
+
serial1 = &uart1;
23
22
};
24
23
25
24
cpus {
···
53
54
* controller & should be probed first.
54
55
*/
55
56
interrupt-parent = <&cpu_intc>;
56
-
57
-
timer {
58
-
compatible = "mti,gic-timer";
59
-
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
60
-
};
61
57
};
62
58
63
59
ehci@1b200000 {
64
60
compatible = "generic-ehci";
65
61
reg = <0x1b200000 0x1000>;
66
62
67
-
interrupts = <0>; /* GIC 0 or CPU 6 */
63
+
interrupt-parent = <&gic>;
64
+
interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
68
65
69
66
has-transaction-translator;
70
67
};
···
222
227
223
228
clock-frequency = <14745600>;
224
229
225
-
interrupts = <3>; /* GIC 3 or CPU 4 */
230
+
interrupt-parent = <&gic>;
231
+
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
226
232
227
233
no-loopback-test;
228
234
};
···
237
241
238
242
clock-frequency = <14745600>;
239
243
240
-
interrupts = <2>; /* GIC 2 or CPU 4 */
244
+
interrupt-parent = <&gic>;
245
+
interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
241
246
242
247
no-loopback-test;
243
248
};
···
248
251
reg = <0x1f010000 0x10000>;
249
252
reg-io-width = <4>;
250
253
251
-
interrupts = <0>; /* GIC 0 or CPU 6 */
254
+
interrupt-parent = <&gic>;
255
+
interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
252
256
253
257
phy-mode = "mii";
254
258
smsc,irq-push-pull;
-6
arch/mips/configs/ar7_defconfig
-6
arch/mips/configs/ar7_defconfig
···
3
3
CONFIG_HZ_100=y
4
4
CONFIG_KEXEC=y
5
5
# CONFIG_SECCOMP is not set
6
-
CONFIG_EXPERIMENTAL=y
7
6
# CONFIG_LOCALVERSION_AUTO is not set
8
7
CONFIG_KERNEL_LZMA=y
9
8
CONFIG_SYSVIPC=y
···
40
41
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
41
42
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
42
43
# CONFIG_INET_XFRM_MODE_BEET is not set
43
-
# CONFIG_INET_LRO is not set
44
44
# CONFIG_INET_DIAG is not set
45
45
CONFIG_TCP_CONG_ADVANCED=y
46
46
# CONFIG_TCP_CONG_BIC is not set
···
84
86
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
85
87
# CONFIG_FIRMWARE_IN_KERNEL is not set
86
88
CONFIG_MTD=y
87
-
CONFIG_MTD_CHAR=y
88
89
CONFIG_MTD_BLOCK=y
89
90
CONFIG_MTD_CFI=y
90
91
CONFIG_MTD_CFI_INTELEXT=y
···
96
99
CONFIG_NET_ETHERNET=y
97
100
CONFIG_MII=y
98
101
CONFIG_CPMAC=y
99
-
# CONFIG_NETDEV_1000 is not set
100
-
# CONFIG_NETDEV_10000 is not set
101
102
CONFIG_PPP=m
102
103
CONFIG_PPP_MULTILINK=y
103
104
CONFIG_PPP_FILTER=y
···
137
142
# CONFIG_ENABLE_MUST_CHECK is not set
138
143
CONFIG_STRIP_ASM_SYMS=y
139
144
CONFIG_DEBUG_FS=y
140
-
CONFIG_SYSCTL_SYSCALL_CHECK=y
141
145
CONFIG_CMDLINE_BOOL=y
142
146
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
143
147
CONFIG_CRYPTO=y
-2
arch/mips/configs/ath79_defconfig
-2
arch/mips/configs/ath79_defconfig
···
7
7
CONFIG_ATH79_MACH_UBNT_XM=y
8
8
CONFIG_HZ_100=y
9
9
# CONFIG_SECCOMP is not set
10
-
CONFIG_EXPERIMENTAL=y
11
10
# CONFIG_LOCALVERSION_AUTO is not set
12
11
CONFIG_SYSVIPC=y
13
12
CONFIG_HIGH_RES_TIMERS=y
···
34
35
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
35
36
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
36
37
# CONFIG_INET_XFRM_MODE_BEET is not set
37
-
# CONFIG_INET_LRO is not set
38
38
# CONFIG_IPV6 is not set
39
39
CONFIG_CFG80211=m
40
40
CONFIG_MAC80211=m
-7
arch/mips/configs/bcm63xx_defconfig
-7
arch/mips/configs/bcm63xx_defconfig
···
5
5
CONFIG_BCM63XX_CPU_6358=y
6
6
CONFIG_NO_HZ=y
7
7
# CONFIG_SECCOMP is not set
8
-
CONFIG_EXPERIMENTAL=y
9
8
# CONFIG_LOCALVERSION_AUTO is not set
10
9
# CONFIG_SWAP is not set
11
10
CONFIG_TINY_RCU=y
···
32
33
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
33
34
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
34
35
# CONFIG_INET_XFRM_MODE_BEET is not set
35
-
# CONFIG_INET_LRO is not set
36
36
# CONFIG_INET_DIAG is not set
37
37
# CONFIG_IPV6 is not set
38
38
CONFIG_CFG80211=y
···
48
50
CONFIG_MTD_CFI_AMDSTD=y
49
51
CONFIG_MTD_PHYSMAP=y
50
52
# CONFIG_BLK_DEV is not set
51
-
# CONFIG_MISC_DEVICES is not set
52
53
CONFIG_NETDEVICES=y
53
54
CONFIG_BCM63XX_PHY=y
54
55
CONFIG_NET_ETHERNET=y
55
56
CONFIG_BCM63XX_ENET=y
56
-
# CONFIG_NETDEV_1000 is not set
57
-
# CONFIG_NETDEV_10000 is not set
58
57
CONFIG_B43=y
59
58
# CONFIG_B43_PHY_LP is not set
60
59
# CONFIG_INPUT is not set
···
65
70
# CONFIG_HWMON is not set
66
71
# CONFIG_VGA_ARB is not set
67
72
CONFIG_USB=y
68
-
# CONFIG_USB_DEVICE_CLASS is not set
69
73
CONFIG_USB_EHCI_HCD=y
70
74
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
71
75
CONFIG_USB_OHCI_HCD=y
···
78
84
CONFIG_PROC_KCORE=y
79
85
# CONFIG_NETWORK_FILESYSTEMS is not set
80
86
CONFIG_MAGIC_SYSRQ=y
81
-
CONFIG_SYSCTL_SYSCALL_CHECK=y
82
87
CONFIG_CMDLINE_BOOL=y
83
88
CONFIG_CMDLINE="console=ttyS0,115200"
84
89
# CONFIG_CRYPTO_HW is not set
-4
arch/mips/configs/bigsur_defconfig
-4
arch/mips/configs/bigsur_defconfig
···
4
4
CONFIG_NO_HZ=y
5
5
CONFIG_HIGH_RES_TIMERS=y
6
6
CONFIG_HZ_1000=y
7
-
CONFIG_EXPERIMENTAL=y
8
7
CONFIG_SYSVIPC=y
9
8
CONFIG_POSIX_MQUEUE=y
10
9
CONFIG_BSD_PROCESS_ACCT=y
···
59
60
CONFIG_INET_IPCOMP=m
60
61
CONFIG_INET_XFRM_MODE_TRANSPORT=m
61
62
CONFIG_INET_XFRM_MODE_TUNNEL=m
62
-
# CONFIG_INET_LRO is not set
63
63
CONFIG_TCP_MD5SIG=y
64
64
CONFIG_IPV6_ROUTER_PREF=y
65
65
CONFIG_IPV6_ROUTE_INFO=y
···
180
182
CONFIG_QUOTA_NETLINK_INTERFACE=y
181
183
# CONFIG_PRINT_QUOTA_WARNING is not set
182
184
CONFIG_QFMT_V2=m
183
-
CONFIG_AUTOFS_FS=m
184
185
CONFIG_AUTOFS4_FS=m
185
186
CONFIG_FUSE_FS=m
186
187
CONFIG_ISO9660_FS=m
···
281
284
CONFIG_CRYPTO_SERPENT=m
282
285
CONFIG_CRYPTO_TEA=m
283
286
CONFIG_CRYPTO_TWOFISH=m
284
-
CONFIG_CRYPTO_ZLIB=m
285
287
CONFIG_CRYPTO_LZO=m
286
288
CONFIG_CRC_T10DIF=m
287
289
CONFIG_CRC7=m
-1
arch/mips/configs/bmips_be_defconfig
-1
arch/mips/configs/bmips_be_defconfig
-4
arch/mips/configs/capcella_defconfig
-4
arch/mips/configs/capcella_defconfig
···
1
1
CONFIG_MACH_VR41XX=y
2
2
CONFIG_ZAO_CAPCELLA=y
3
-
CONFIG_EXPERIMENTAL=y
4
3
CONFIG_SYSVIPC=y
5
4
CONFIG_LOG_BUF_SHIFT=14
6
5
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
···
45
46
CONFIG_NET_ETHERNET=y
46
47
CONFIG_NET_PCI=y
47
48
CONFIG_8139TOO=y
48
-
# CONFIG_NETDEV_1000 is not set
49
-
# CONFIG_NETDEV_10000 is not set
50
49
# CONFIG_INPUT_MOUSEDEV is not set
51
50
# CONFIG_INPUT_KEYBOARD is not set
52
51
# CONFIG_INPUT_MOUSE is not set
···
56
59
CONFIG_GPIO_VR41XX=y
57
60
# CONFIG_HWMON is not set
58
61
# CONFIG_VGA_CONSOLE is not set
59
-
# CONFIG_HID_SUPPORT is not set
60
62
# CONFIG_USB_SUPPORT is not set
61
63
CONFIG_RTC_CLASS=y
62
64
CONFIG_RTC_DRV_VR41XX=y
-1
arch/mips/configs/cavium_octeon_defconfig
-1
arch/mips/configs/cavium_octeon_defconfig
-1
arch/mips/configs/ci20_defconfig
-1
arch/mips/configs/ci20_defconfig
-8
arch/mips/configs/cobalt_defconfig
-8
arch/mips/configs/cobalt_defconfig
···
1
1
CONFIG_MIPS_COBALT=y
2
-
CONFIG_EXPERIMENTAL=y
3
2
CONFIG_SYSVIPC=y
4
3
CONFIG_LOG_BUF_SHIFT=14
5
4
CONFIG_RELAY=y
···
14
15
CONFIG_NET_KEY=y
15
16
CONFIG_NET_KEY_MIGRATE=y
16
17
CONFIG_INET=y
17
-
# CONFIG_INET_LRO is not set
18
18
# CONFIG_IPV6 is not set
19
19
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
20
20
CONFIG_MTD=y
21
-
CONFIG_MTD_CHAR=y
22
21
CONFIG_MTD_BLKDEVS=y
23
22
CONFIG_MTD_JEDECPROBE=y
24
23
CONFIG_MTD_CFI_AMDSTD=y
25
24
CONFIG_MTD_PHYSMAP=y
26
25
CONFIG_BLK_DEV_LOOP=y
27
-
# CONFIG_MISC_DEVICES is not set
28
26
CONFIG_RAID_ATTRS=y
29
27
CONFIG_BLK_DEV_SD=y
30
28
# CONFIG_SCSI_LOWLEVEL is not set
···
32
36
CONFIG_NET_TULIP=y
33
37
CONFIG_DE2104X=y
34
38
CONFIG_TULIP=y
35
-
# CONFIG_NETDEV_1000 is not set
36
-
# CONFIG_NETDEV_10000 is not set
37
39
# CONFIG_INPUT_MOUSEDEV is not set
38
40
CONFIG_INPUT_EVDEV=y
39
41
# CONFIG_INPUT_KEYBOARD is not set
···
50
56
# CONFIG_VGA_CONSOLE is not set
51
57
CONFIG_HID=m
52
58
CONFIG_USB=m
53
-
# CONFIG_USB_DEVICE_CLASS is not set
54
59
CONFIG_USB_EHCI_HCD=m
55
60
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
56
61
CONFIG_USB_OHCI_HCD=m
···
77
84
CONFIG_NFSD=y
78
85
CONFIG_NFSD_V3=y
79
86
CONFIG_NFSD_V3_ACL=y
80
-
CONFIG_SYSCTL_SYSCALL_CHECK=y
81
87
CONFIG_CRC16=y
82
88
CONFIG_LIBCRC32C=y
-1
arch/mips/configs/decstation_defconfig
-1
arch/mips/configs/decstation_defconfig
-2
arch/mips/configs/e55_defconfig
-2
arch/mips/configs/e55_defconfig
···
1
1
CONFIG_MACH_VR41XX=y
2
2
CONFIG_CASIO_E55=y
3
-
CONFIG_EXPERIMENTAL=y
4
3
CONFIG_SYSVIPC=y
5
4
CONFIG_LOG_BUF_SHIFT=14
6
5
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
···
27
28
CONFIG_GPIO_VR41XX=y
28
29
# CONFIG_HWMON is not set
29
30
# CONFIG_VGA_CONSOLE is not set
30
-
# CONFIG_HID_SUPPORT is not set
31
31
# CONFIG_USB_SUPPORT is not set
32
32
CONFIG_RTC_CLASS=y
33
33
CONFIG_RTC_DRV_VR41XX=y
-11
arch/mips/configs/fuloong2e_defconfig
-11
arch/mips/configs/fuloong2e_defconfig
···
3
3
CONFIG_NO_HZ=y
4
4
CONFIG_HIGH_RES_TIMERS=y
5
5
CONFIG_PREEMPT_VOLUNTARY=y
6
-
CONFIG_EXPERIMENTAL=y
7
6
CONFIG_LOCALVERSION="-fuloong2e"
8
7
# CONFIG_LOCALVERSION_AUTO is not set
9
8
CONFIG_SYSVIPC=y
···
46
47
CONFIG_NET_IPGRE_BROADCAST=y
47
48
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
48
49
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
49
-
# CONFIG_INET_LRO is not set
50
50
# CONFIG_INET_DIAG is not set
51
51
# CONFIG_IPV6 is not set
52
52
CONFIG_NETFILTER=y
···
77
79
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
78
80
CONFIG_NETFILTER_XT_MATCH_TIME=m
79
81
CONFIG_NETFILTER_XT_MATCH_U32=m
80
-
CONFIG_IP_NF_QUEUE=m
81
82
CONFIG_IP_NF_IPTABLES=m
82
83
CONFIG_IP_NF_MATCH_ADDRTYPE=m
83
84
CONFIG_IP_NF_MATCH_AH=m
···
85
88
CONFIG_IP_NF_FILTER=m
86
89
CONFIG_IP_NF_TARGET_REJECT=m
87
90
CONFIG_IP_NF_TARGET_LOG=m
88
-
CONFIG_IP_NF_TARGET_ULOG=m
89
91
CONFIG_IP_NF_MANGLE=m
90
92
CONFIG_IP_NF_TARGET_ECN=m
91
93
CONFIG_IP_NF_TARGET_TTL=m
···
97
101
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
98
102
CONFIG_FW_LOADER=m
99
103
CONFIG_MTD=m
100
-
CONFIG_MTD_CHAR=m
101
104
CONFIG_MTD_BLOCK=m
102
105
CONFIG_MTD_CFI=m
103
106
CONFIG_MTD_JEDECPROBE=m
···
158
163
CONFIG_I2C_CHARDEV=m
159
164
CONFIG_I2C_VIAPRO=m
160
165
# CONFIG_HWMON is not set
161
-
CONFIG_VIDEO_OUTPUT_CONTROL=m
162
166
CONFIG_FB=y
163
167
CONFIG_FB_RADEON=y
164
168
# CONFIG_FB_RADEON_I2C is not set
···
178
184
CONFIG_USB_MOUSE=y
179
185
CONFIG_USB=y
180
186
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
181
-
# CONFIG_USB_DEVICE_CLASS is not set
182
187
CONFIG_USB_OTG_WHITELIST=y
183
188
CONFIG_USB_WUSB_CBAF=m
184
189
CONFIG_USB_C67X00_HCD=m
···
194
201
CONFIG_USB_STORAGE=y
195
202
CONFIG_USB_STORAGE_ONETOUCH=y
196
203
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
197
-
CONFIG_USB_LIBUSUAL=y
198
204
CONFIG_USB_SEVSEG=m
199
205
CONFIG_USB_ISIGHTFW=m
200
206
CONFIG_UIO=m
···
207
215
CONFIG_EXT4_FS_POSIX_ACL=y
208
216
CONFIG_EXT4_FS_SECURITY=y
209
217
CONFIG_REISERFS_FS=m
210
-
CONFIG_AUTOFS_FS=y
211
218
CONFIG_AUTOFS4_FS=y
212
219
CONFIG_FUSE_FS=y
213
220
CONFIG_ISO9660_FS=m
···
247
256
CONFIG_NLS_UTF8=y
248
257
# CONFIG_ENABLE_MUST_CHECK is not set
249
258
CONFIG_DEBUG_FS=y
250
-
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
251
-
CONFIG_SYSCTL_SYSCALL_CHECK=y
252
259
CONFIG_CRYPTO_FIPS=y
253
260
CONFIG_CRYPTO_AUTHENC=m
254
261
CONFIG_CRYPTO_CCM=m
+48
arch/mips/configs/generic/board-boston.config
+48
arch/mips/configs/generic/board-boston.config
···
1
+
CONFIG_FIT_IMAGE_FDT_BOSTON=y
2
+
3
+
CONFIG_ATA=y
4
+
CONFIG_SATA_AHCI=y
5
+
CONFIG_SCSI=y
6
+
CONFIG_BLK_DEV_SD=y
7
+
8
+
CONFIG_AUXDISPLAY=y
9
+
CONFIG_IMG_ASCII_LCD=y
10
+
11
+
CONFIG_COMMON_CLK_BOSTON=y
12
+
13
+
CONFIG_DMADEVICES=y
14
+
CONFIG_PCH_DMA=y
15
+
16
+
CONFIG_GPIOLIB=y
17
+
CONFIG_GPIO_SYSFS=y
18
+
CONFIG_GPIO_PCH=y
19
+
20
+
CONFIG_I2C=y
21
+
CONFIG_I2C_EG20T=y
22
+
23
+
CONFIG_MMC=y
24
+
CONFIG_MMC_SDHCI=y
25
+
CONFIG_MMC_SDHCI_PCI=y
26
+
27
+
CONFIG_NETDEVICES=y
28
+
CONFIG_PCH_GBE=y
29
+
30
+
CONFIG_PCI=y
31
+
CONFIG_PCI_MSI=y
32
+
CONFIG_PCIE_XILINX=y
33
+
34
+
CONFIG_PCH_PHUB=y
35
+
36
+
CONFIG_RTC_CLASS=y
37
+
CONFIG_RTC_DRV_M41T80=y
38
+
39
+
CONFIG_SERIAL_8250=y
40
+
CONFIG_SERIAL_8250_CONSOLE=y
41
+
CONFIG_SERIAL_OF_PLATFORM=y
42
+
43
+
CONFIG_SPI=y
44
+
CONFIG_SPI_TOPCLIFF_PCH=y
45
+
46
+
CONFIG_USB=y
47
+
CONFIG_USB_EHCI_HCD=y
48
+
CONFIG_USB_OHCI_HCD=y
-8
arch/mips/configs/gpr_defconfig
-8
arch/mips/configs/gpr_defconfig
···
2
2
CONFIG_MIPS_GPR=y
3
3
CONFIG_HIGH_RES_TIMERS=y
4
4
CONFIG_PREEMPT_VOLUNTARY=y
5
-
CONFIG_EXPERIMENTAL=y
6
5
# CONFIG_LOCALVERSION_AUTO is not set
7
6
CONFIG_SYSVIPC=y
8
7
CONFIG_POSIX_MQUEUE=y
···
58
59
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
59
60
CONFIG_NETFILTER_XT_MATCH_STRING=m
60
61
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
61
-
CONFIG_IP_NF_QUEUE=m
62
62
CONFIG_IP_NF_IPTABLES=m
63
63
CONFIG_IP_NF_MATCH_ADDRTYPE=m
64
64
CONFIG_IP_NF_MATCH_AH=m
···
66
68
CONFIG_IP_NF_FILTER=m
67
69
CONFIG_IP_NF_TARGET_REJECT=m
68
70
CONFIG_IP_NF_TARGET_LOG=m
69
-
CONFIG_IP_NF_TARGET_ULOG=m
70
71
CONFIG_IP_NF_MANGLE=m
71
72
CONFIG_IP_NF_TARGET_ECN=m
72
73
CONFIG_IP_NF_TARGET_TTL=m
···
163
166
CONFIG_CFG80211=y
164
167
CONFIG_MAC80211=y
165
168
CONFIG_MTD=y
166
-
CONFIG_MTD_CHAR=y
167
169
CONFIG_MTD_BLOCK=y
168
170
CONFIG_MTD_CFI=y
169
171
CONFIG_MTD_CFI_INTELEXT=y
···
196
200
CONFIG_NET_ETHERNET=y
197
201
CONFIG_MII=y
198
202
CONFIG_MIPS_AU1X00_ENET=y
199
-
# CONFIG_NETDEV_1000 is not set
200
-
# CONFIG_NETDEV_10000 is not set
201
203
CONFIG_ATH_COMMON=y
202
204
CONFIG_ATH_DEBUG=y
203
205
CONFIG_ATH5K=y
···
280
286
CONFIG_USB_KBD=m
281
287
CONFIG_USB_MOUSE=m
282
288
CONFIG_USB=y
283
-
# CONFIG_USB_DEVICE_CLASS is not set
284
289
CONFIG_USB_MON=y
285
290
CONFIG_USB_EHCI_HCD=y
286
291
CONFIG_USB_EHCI_ROOT_HUB_TT=y
287
292
CONFIG_USB_OHCI_HCD=y
288
293
CONFIG_USB_OHCI_HCD_PLATFORM=y
289
294
CONFIG_USB_STORAGE=m
290
-
CONFIG_USB_LIBUSUAL=y
291
295
CONFIG_USB_SERIAL=y
292
296
CONFIG_USB_EZUSB=y
293
297
CONFIG_USB_SERIAL_GENERIC=y
-11
arch/mips/configs/ip22_defconfig
-11
arch/mips/configs/ip22_defconfig
···
4
4
CONFIG_HIGH_RES_TIMERS=y
5
5
CONFIG_HZ_1000=y
6
6
CONFIG_PREEMPT_VOLUNTARY=y
7
-
CONFIG_EXPERIMENTAL=y
8
7
CONFIG_SYSVIPC=y
9
8
CONFIG_IKCONFIG=y
10
9
CONFIG_IKCONFIG_PROC=y
···
45
46
CONFIG_INET_XFRM_MODE_TRANSPORT=m
46
47
CONFIG_INET_XFRM_MODE_TUNNEL=m
47
48
CONFIG_INET_XFRM_MODE_BEET=m
48
-
# CONFIG_INET_LRO is not set
49
49
CONFIG_TCP_MD5SIG=y
50
50
CONFIG_IPV6_ROUTER_PREF=y
51
51
CONFIG_IPV6_ROUTE_INFO=y
···
137
139
CONFIG_IP_VS_NQ=m
138
140
CONFIG_IP_VS_FTP=m
139
141
CONFIG_NF_CONNTRACK_IPV4=m
140
-
CONFIG_IP_NF_QUEUE=m
141
142
CONFIG_IP_NF_IPTABLES=m
142
143
CONFIG_IP_NF_MATCH_ADDRTYPE=m
143
144
CONFIG_IP_NF_MATCH_AH=m
···
145
148
CONFIG_IP_NF_FILTER=m
146
149
CONFIG_IP_NF_TARGET_REJECT=m
147
150
CONFIG_IP_NF_TARGET_LOG=m
148
-
CONFIG_IP_NF_TARGET_ULOG=m
149
151
CONFIG_NF_NAT=m
150
152
CONFIG_IP_NF_TARGET_MASQUERADE=m
151
153
CONFIG_IP_NF_TARGET_NETMAP=m
···
159
163
CONFIG_IP_NF_ARPFILTER=m
160
164
CONFIG_IP_NF_ARP_MANGLE=m
161
165
CONFIG_NF_CONNTRACK_IPV6=m
162
-
CONFIG_IP6_NF_QUEUE=m
163
166
CONFIG_IP6_NF_IPTABLES=m
164
167
CONFIG_IP6_NF_MATCH_AH=m
165
168
CONFIG_IP6_NF_MATCH_EUI64=m
···
169
174
CONFIG_IP6_NF_MATCH_MH=m
170
175
CONFIG_IP6_NF_MATCH_RT=m
171
176
CONFIG_IP6_NF_TARGET_HL=m
172
-
CONFIG_IP6_NF_TARGET_LOG=m
173
177
CONFIG_IP6_NF_FILTER=m
174
178
CONFIG_IP6_NF_TARGET_REJECT=m
175
179
CONFIG_IP6_NF_MANGLE=m
···
209
215
CONFIG_CONNECTOR=m
210
216
CONFIG_CDROM_PKTCDVD=m
211
217
CONFIG_ATA_OVER_ETH=m
212
-
# CONFIG_MISC_DEVICES is not set
213
218
CONFIG_RAID_ATTRS=m
214
219
CONFIG_SCSI=y
215
220
CONFIG_BLK_DEV_SD=y
···
238
245
CONFIG_NET_ETHERNET=y
239
246
CONFIG_SMC91X=m
240
247
CONFIG_SGISEEQ=y
241
-
# CONFIG_NETDEV_1000 is not set
242
-
# CONFIG_NETDEV_10000 is not set
243
248
CONFIG_HOSTAP=m
244
249
CONFIG_INPUT_MOUSEDEV=m
245
250
CONFIG_MOUSE_PS2=m
···
277
286
CONFIG_QUOTA_NETLINK_INTERFACE=y
278
287
# CONFIG_PRINT_QUOTA_WARNING is not set
279
288
CONFIG_QFMT_V2=m
280
-
CONFIG_AUTOFS_FS=m
281
289
CONFIG_AUTOFS4_FS=m
282
290
CONFIG_FUSE_FS=m
283
291
CONFIG_ISO9660_FS=m
···
345
355
CONFIG_NLS_UTF8=m
346
356
CONFIG_DLM=m
347
357
CONFIG_DEBUG_MEMORY_INIT=y
348
-
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
349
358
CONFIG_KEYS=y
350
359
CONFIG_CRYPTO_FIPS=y
351
360
CONFIG_CRYPTO_NULL=m
-5
arch/mips/configs/ip27_defconfig
-5
arch/mips/configs/ip27_defconfig
···
5
5
CONFIG_NO_HZ=y
6
6
CONFIG_HIGH_RES_TIMERS=y
7
7
CONFIG_HZ_1000=y
8
-
CONFIG_EXPERIMENTAL=y
9
8
CONFIG_SYSVIPC=y
10
9
CONFIG_POSIX_MQUEUE=y
11
10
CONFIG_IKCONFIG=y
···
103
104
CONFIG_BLK_DEV_OSD=m
104
105
CONFIG_CDROM_PKTCDVD=m
105
106
CONFIG_ATA_OVER_ETH=m
106
-
# CONFIG_MISC_DEVICES is not set
107
107
CONFIG_SCSI=y
108
108
CONFIG_BLK_DEV_SD=y
109
109
CONFIG_CHR_DEV_ST=y
···
323
325
CONFIG_BTRFS_FS=m
324
326
CONFIG_BTRFS_FS_POSIX_ACL=y
325
327
CONFIG_QUOTA_NETLINK_INTERFACE=y
326
-
CONFIG_AUTOFS_FS=m
327
328
CONFIG_FUSE_FS=m
328
329
CONFIG_CUSE=m
329
330
CONFIG_FSCACHE=m
···
339
342
CONFIG_RPCSEC_GSS_KRB5=y
340
343
CONFIG_PARTITION_ADVANCED=y
341
344
CONFIG_DLM=m
342
-
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
343
345
CONFIG_KEYS=y
344
346
CONFIG_SECURITYFS=y
345
347
CONFIG_CRYPTO_FIPS=y
···
374
378
CONFIG_CRYPTO_SERPENT=m
375
379
CONFIG_CRYPTO_TEA=m
376
380
CONFIG_CRYPTO_TWOFISH=m
377
-
CONFIG_CRYPTO_ZLIB=m
378
381
CONFIG_CRYPTO_LZO=m
379
382
CONFIG_CRYPTO_DEV_HIFN_795X=m
380
383
CONFIG_CRC_T10DIF=m
-5
arch/mips/configs/ip28_defconfig
-5
arch/mips/configs/ip28_defconfig
···
1
1
CONFIG_SGI_IP28=y
2
2
CONFIG_ARC_CONSOLE=y
3
3
CONFIG_PREEMPT_VOLUNTARY=y
4
-
CONFIG_EXPERIMENTAL=y
5
4
CONFIG_SYSVIPC=y
6
5
CONFIG_IKCONFIG=y
7
6
CONFIG_IKCONFIG_PROC=y
···
34
35
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
35
36
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
36
37
# CONFIG_INET_XFRM_MODE_BEET is not set
37
-
# CONFIG_INET_LRO is not set
38
38
CONFIG_TCP_MD5SIG=y
39
39
# CONFIG_IPV6 is not set
40
-
# CONFIG_MISC_DEVICES is not set
41
40
CONFIG_SCSI=y
42
41
CONFIG_BLK_DEV_SD=y
43
42
CONFIG_BLK_DEV_SR=y
···
45
48
CONFIG_DUMMY=m
46
49
CONFIG_NET_ETHERNET=y
47
50
CONFIG_SGISEEQ=y
48
-
# CONFIG_NETDEV_1000 is not set
49
-
# CONFIG_NETDEV_10000 is not set
50
51
# CONFIG_MOUSE_PS2_ALPS is not set
51
52
# CONFIG_MOUSE_PS2_SYNAPTICS is not set
52
53
CONFIG_VT_HW_CONSOLE_BINDING=y
-8
arch/mips/configs/ip32_defconfig
-8
arch/mips/configs/ip32_defconfig
···
1
1
CONFIG_SGI_IP32=y
2
2
# CONFIG_SECCOMP is not set
3
-
CONFIG_EXPERIMENTAL=y
4
3
CONFIG_SYSVIPC=y
5
4
CONFIG_POSIX_MQUEUE=y
6
5
CONFIG_BSD_PROCESS_ACCT=y
···
37
38
CONFIG_INET_AH=m
38
39
CONFIG_INET_ESP=m
39
40
CONFIG_INET_IPCOMP=m
40
-
# CONFIG_INET_LRO is not set
41
41
CONFIG_TCP_CONG_ADVANCED=y
42
42
CONFIG_TCP_MD5SIG=y
43
43
CONFIG_INET6_AH=m
···
74
76
CONFIG_DE2104X=m
75
77
CONFIG_TULIP=m
76
78
CONFIG_TULIP_MMIO=y
77
-
# CONFIG_NETDEV_1000 is not set
78
-
# CONFIG_NETDEV_10000 is not set
79
79
CONFIG_INPUT_EVDEV=m
80
80
# CONFIG_SERIO_I8042 is not set
81
81
CONFIG_SERIO_MACEPS2=y
···
83
87
CONFIG_SERIAL_8250_CONSOLE=y
84
88
CONFIG_HW_RANDOM=y
85
89
CONFIG_WATCHDOG=y
86
-
CONFIG_VIDEO_OUTPUT_CONTROL=y
87
90
CONFIG_FB=y
88
91
CONFIG_FIRMWARE_EDID=y
89
92
CONFIG_FB_GBE=y
···
112
117
CONFIG_QUOTA=y
113
118
CONFIG_QFMT_V1=m
114
119
CONFIG_QFMT_V2=m
115
-
CONFIG_AUTOFS_FS=m
116
120
CONFIG_AUTOFS4_FS=m
117
121
CONFIG_FUSE_FS=m
118
122
CONFIG_ISO9660_FS=m
···
172
178
CONFIG_NLS_KOI8_U=m
173
179
CONFIG_NLS_UTF8=m
174
180
CONFIG_MAGIC_SYSRQ=y
175
-
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
176
-
CONFIG_SYSCTL_SYSCALL_CHECK=y
177
181
CONFIG_KEYS=y
178
182
CONFIG_CRYPTO_NULL=y
179
183
CONFIG_CRYPTO_CBC=y
-6
arch/mips/configs/jazz_defconfig
-6
arch/mips/configs/jazz_defconfig
···
1
1
CONFIG_MACH_JAZZ=y
2
2
CONFIG_OLIVETTI_M700=y
3
3
CONFIG_PREEMPT_VOLUNTARY=y
4
-
CONFIG_EXPERIMENTAL=y
5
4
CONFIG_SYSVIPC=y
6
5
CONFIG_POSIX_MQUEUE=y
7
6
CONFIG_BSD_PROCESS_ACCT=y
···
84
85
CONFIG_NETFILTER_XT_MATCH_STRING=m
85
86
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
86
87
CONFIG_NF_CONNTRACK_IPV4=m
87
-
CONFIG_IP_NF_QUEUE=m
88
88
CONFIG_IP_NF_IPTABLES=m
89
89
CONFIG_IP_NF_MATCH_ADDRTYPE=m
90
90
CONFIG_IP_NF_MATCH_AH=m
···
92
94
CONFIG_IP_NF_FILTER=m
93
95
CONFIG_IP_NF_TARGET_REJECT=m
94
96
CONFIG_IP_NF_TARGET_LOG=m
95
-
CONFIG_IP_NF_TARGET_ULOG=m
96
97
CONFIG_NF_NAT=m
97
98
CONFIG_IP_NF_TARGET_MASQUERADE=m
98
99
CONFIG_IP_NF_TARGET_NETMAP=m
···
106
109
CONFIG_IP_NF_ARPFILTER=m
107
110
CONFIG_IP_NF_ARP_MANGLE=m
108
111
CONFIG_NF_CONNTRACK_IPV6=m
109
-
CONFIG_IP6_NF_QUEUE=m
110
112
CONFIG_IP6_NF_IPTABLES=m
111
113
CONFIG_IP6_NF_MATCH_AH=m
112
114
CONFIG_IP6_NF_MATCH_EUI64=m
···
116
120
CONFIG_IP6_NF_MATCH_MH=m
117
121
CONFIG_IP6_NF_MATCH_RT=m
118
122
CONFIG_IP6_NF_TARGET_HL=m
119
-
CONFIG_IP6_NF_TARGET_LOG=m
120
123
CONFIG_IP6_NF_FILTER=m
121
124
CONFIG_IP6_NF_TARGET_REJECT=m
122
125
CONFIG_IP6_NF_MANGLE=m
···
271
276
CONFIG_REISERFS_FS_SECURITY=y
272
277
CONFIG_XFS_FS=m
273
278
CONFIG_XFS_QUOTA=y
274
-
CONFIG_AUTOFS_FS=m
275
279
CONFIG_AUTOFS4_FS=m
276
280
CONFIG_FUSE_FS=m
277
281
CONFIG_ISO9660_FS=m
-7
arch/mips/configs/jmr3927_defconfig
-7
arch/mips/configs/jmr3927_defconfig
···
18
18
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
19
19
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
20
20
# CONFIG_INET_XFRM_MODE_BEET is not set
21
-
# CONFIG_INET_LRO is not set
22
21
# CONFIG_INET_DIAG is not set
23
22
# CONFIG_IPV6 is not set
24
23
CONFIG_MTD=y
25
24
CONFIG_MTD_CMDLINE_PARTS=y
26
-
CONFIG_MTD_CHAR=y
27
25
CONFIG_MTD_CFI=y
28
26
CONFIG_MTD_JEDECPROBE=y
29
27
CONFIG_MTD_CFI_AMDSTD=y
30
28
CONFIG_MTD_PHYSMAP=y
31
-
# CONFIG_MISC_DEVICES is not set
32
29
CONFIG_NETDEVICES=y
33
30
CONFIG_NET_ETHERNET=y
34
31
CONFIG_NET_PCI=y
35
32
CONFIG_TC35815=y
36
-
# CONFIG_NETDEV_1000 is not set
37
-
# CONFIG_NETDEV_10000 is not set
38
33
# CONFIG_INPUT is not set
39
34
# CONFIG_SERIO is not set
40
35
# CONFIG_VT is not set
···
53
58
# CONFIG_MISC_FILESYSTEMS is not set
54
59
CONFIG_NFS_FS=y
55
60
CONFIG_ROOT_NFS=y
56
-
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
57
-
CONFIG_SYSCTL_SYSCALL_CHECK=y
-5
arch/mips/configs/lasat_defconfig
-5
arch/mips/configs/lasat_defconfig
···
5
5
CONFIG_LASAT_SYSCTL=y
6
6
CONFIG_HZ_1000=y
7
7
# CONFIG_SECCOMP is not set
8
-
CONFIG_EXPERIMENTAL=y
9
8
CONFIG_SYSVIPC=y
10
9
CONFIG_LOG_BUF_SHIFT=14
11
10
CONFIG_EXPERT=y
···
30
31
# CONFIG_INET_DIAG is not set
31
32
# CONFIG_IPV6 is not set
32
33
CONFIG_MTD=y
33
-
CONFIG_MTD_CHAR=y
34
34
CONFIG_MTD_BLOCK=y
35
35
CONFIG_MTD_CFI=y
36
36
CONFIG_MTD_CFI_AMDSTD=y
···
42
44
CONFIG_NET_ETHERNET=y
43
45
CONFIG_NET_PCI=y
44
46
CONFIG_PCNET32=y
45
-
# CONFIG_NETDEV_1000 is not set
46
-
# CONFIG_NETDEV_10000 is not set
47
47
# CONFIG_INPUT_MOUSEDEV is not set
48
48
# CONFIG_INPUT_KEYBOARD is not set
49
49
# CONFIG_INPUT_MOUSE is not set
···
52
56
# CONFIG_SERIAL_8250_PCI is not set
53
57
# CONFIG_HW_RANDOM is not set
54
58
# CONFIG_HWMON is not set
55
-
# CONFIG_HID_SUPPORT is not set
56
59
# CONFIG_USB_SUPPORT is not set
57
60
CONFIG_EXT2_FS=y
58
61
CONFIG_EXT3_FS=y
-12
arch/mips/configs/lemote2f_defconfig
-12
arch/mips/configs/lemote2f_defconfig
···
7
7
CONFIG_PREEMPT=y
8
8
CONFIG_KEXEC=y
9
9
# CONFIG_SECCOMP is not set
10
-
CONFIG_EXPERIMENTAL=y
11
10
# CONFIG_LOCALVERSION_AUTO is not set
12
11
CONFIG_SYSVIPC=y
13
12
CONFIG_BSD_PROCESS_ACCT=y
···
82
83
CONFIG_NET_EMATCH=y
83
84
CONFIG_NET_CLS_ACT=y
84
85
CONFIG_BT=m
85
-
CONFIG_BT_L2CAP=y
86
-
CONFIG_BT_SCO=y
87
86
CONFIG_BT_RFCOMM=m
88
87
CONFIG_BT_RFCOMM_TTY=y
89
88
CONFIG_BT_BNEP=m
···
139
142
# CONFIG_8139TOO_PIO is not set
140
143
CONFIG_R8169=y
141
144
CONFIG_R8169_VLAN=y
142
-
# CONFIG_NETDEV_10000 is not set
143
145
CONFIG_USB_USBNET=m
144
146
CONFIG_USB_NET_CDC_EEM=m
145
147
CONFIG_NETCONSOLE=m
···
201
205
CONFIG_USB_STKWEBCAM=m
202
206
CONFIG_USB_S2255=m
203
207
# CONFIG_RADIO_ADAPTERS is not set
204
-
CONFIG_VIDEO_OUTPUT_CONTROL=y
205
208
CONFIG_FB=y
206
209
CONFIG_FIRMWARE_EDID=y
207
210
CONFIG_FB_MODE_HELPERS=y
···
285
290
CONFIG_HID_ZEROPLUS=m
286
291
CONFIG_ZEROPLUS_FF=y
287
292
CONFIG_USB=y
288
-
# CONFIG_USB_DEVICE_CLASS is not set
289
293
CONFIG_USB_DYNAMIC_MINORS=y
290
294
CONFIG_USB_OTG_WHITELIST=y
291
295
CONFIG_USB_MON=y
···
307
313
CONFIG_USB_STORAGE_SDDR55=m
308
314
CONFIG_USB_STORAGE_JUMPSHOT=m
309
315
CONFIG_USB_STORAGE_ALAUDA=m
310
-
CONFIG_USB_LIBUSUAL=y
311
316
CONFIG_USB_SERIAL=m
312
317
CONFIG_USB_SERIAL_GENERIC=y
313
-
CONFIG_USB_LED=m
314
318
CONFIG_USB_GADGET=m
315
319
CONFIG_USB_GADGET_M66592=y
316
320
CONFIG_MMC=m
···
333
341
CONFIG_BTRFS_FS=m
334
342
CONFIG_QUOTA=y
335
343
CONFIG_QFMT_V2=m
336
-
CONFIG_AUTOFS_FS=m
337
344
CONFIG_AUTOFS4_FS=m
338
345
CONFIG_FSCACHE=m
339
346
CONFIG_CACHEFILES=m
···
398
407
CONFIG_FRAME_WARN=1024
399
408
CONFIG_STRIP_ASM_SYMS=y
400
409
CONFIG_DEBUG_FS=y
401
-
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
402
-
CONFIG_SYSCTL_SYSCALL_CHECK=y
403
410
CONFIG_KEYS=y
404
411
CONFIG_CRYPTO_FIPS=y
405
412
CONFIG_CRYPTO_NULL=m
···
435
446
CONFIG_CRYPTO_TEA=m
436
447
CONFIG_CRYPTO_TWOFISH=m
437
448
CONFIG_CRYPTO_DEFLATE=m
438
-
CONFIG_CRYPTO_ZLIB=m
439
449
CONFIG_CRYPTO_LZO=m
440
450
CONFIG_CRC_T10DIF=y
-3
arch/mips/configs/loongson3_defconfig
-3
arch/mips/configs/loongson3_defconfig
···
95
95
CONFIG_IP_NF_MATCH_TTL=m
96
96
CONFIG_IP_NF_FILTER=m
97
97
CONFIG_IP_NF_TARGET_REJECT=m
98
-
CONFIG_IP_NF_TARGET_ULOG=m
99
98
CONFIG_IP_NF_MANGLE=m
100
99
CONFIG_IP_NF_TARGET_ECN=m
101
100
CONFIG_IP_NF_TARGET_TTL=m
···
251
252
CONFIG_USB_VIDEO_CLASS=m
252
253
CONFIG_DRM=y
253
254
CONFIG_DRM_RADEON=y
254
-
CONFIG_VIDEO_OUTPUT_CONTROL=y
255
255
CONFIG_FB_RADEON=y
256
256
CONFIG_LCD_CLASS_DEVICE=y
257
257
CONFIG_LCD_PLATFORM=m
···
333
335
CONFIG_MAGIC_SYSRQ=y
334
336
# CONFIG_SCHED_DEBUG is not set
335
337
# CONFIG_DEBUG_PREEMPT is not set
336
-
# CONFIG_RCU_CPU_STALL_VERBOSE is not set
337
338
# CONFIG_FTRACE is not set
338
339
CONFIG_SECURITY=y
339
340
CONFIG_SECURITYFS=y
-1
arch/mips/configs/malta_kvm_defconfig
-1
arch/mips/configs/malta_kvm_defconfig
-1
arch/mips/configs/malta_kvm_guest_defconfig
-1
arch/mips/configs/malta_kvm_guest_defconfig
-1
arch/mips/configs/malta_qemu_32r6_defconfig
-1
arch/mips/configs/malta_qemu_32r6_defconfig
-2
arch/mips/configs/maltaaprp_defconfig
-2
arch/mips/configs/maltaaprp_defconfig
···
43
43
CONFIG_INET_AH=m
44
44
CONFIG_INET_ESP=m
45
45
CONFIG_INET_IPCOMP=m
46
-
# CONFIG_INET_LRO is not set
47
46
CONFIG_INET6_AH=m
48
47
CONFIG_INET6_ESP=m
49
48
CONFIG_INET6_IPCOMP=m
···
134
135
CONFIG_POWER_RESET=y
135
136
CONFIG_POWER_RESET_SYSCON=y
136
137
# CONFIG_HWMON is not set
137
-
CONFIG_VIDEO_OUTPUT_CONTROL=m
138
138
CONFIG_FB=y
139
139
CONFIG_FIRMWARE_EDID=y
140
140
CONFIG_FB_MATROX=y
-1
arch/mips/configs/maltasmvp_defconfig
-1
arch/mips/configs/maltasmvp_defconfig
-2
arch/mips/configs/maltasmvp_eva_defconfig
-2
arch/mips/configs/maltasmvp_eva_defconfig
···
47
47
CONFIG_INET_AH=m
48
48
CONFIG_INET_ESP=m
49
49
CONFIG_INET_IPCOMP=m
50
-
# CONFIG_INET_LRO is not set
51
50
CONFIG_INET6_AH=m
52
51
CONFIG_INET6_ESP=m
53
52
CONFIG_INET6_IPCOMP=m
···
139
140
CONFIG_POWER_RESET=y
140
141
CONFIG_POWER_RESET_SYSCON=y
141
142
# CONFIG_HWMON is not set
142
-
CONFIG_VIDEO_OUTPUT_CONTROL=m
143
143
CONFIG_FB=y
144
144
CONFIG_FIRMWARE_EDID=y
145
145
CONFIG_FB_MATROX=y
-2
arch/mips/configs/maltaup_defconfig
-2
arch/mips/configs/maltaup_defconfig
···
42
42
CONFIG_INET_AH=m
43
43
CONFIG_INET_ESP=m
44
44
CONFIG_INET_IPCOMP=m
45
-
# CONFIG_INET_LRO is not set
46
45
CONFIG_INET6_AH=m
47
46
CONFIG_INET6_ESP=m
48
47
CONFIG_INET6_IPCOMP=m
···
133
134
CONFIG_POWER_RESET=y
134
135
CONFIG_POWER_RESET_SYSCON=y
135
136
# CONFIG_HWMON is not set
136
-
CONFIG_VIDEO_OUTPUT_CONTROL=m
137
137
CONFIG_FB=y
138
138
CONFIG_FIRMWARE_EDID=y
139
139
CONFIG_FB_MATROX=y
-4
arch/mips/configs/markeins_defconfig
-4
arch/mips/configs/markeins_defconfig
···
1
1
CONFIG_NEC_MARKEINS=y
2
2
CONFIG_HZ_1000=y
3
3
CONFIG_PREEMPT=y
4
-
CONFIG_EXPERIMENTAL=y
5
4
CONFIG_SYSVIPC=y
6
5
CONFIG_POSIX_MQUEUE=y
7
6
CONFIG_BSD_PROCESS_ACCT=y
···
91
92
CONFIG_IP_NF_FILTER=m
92
93
CONFIG_IP_NF_TARGET_REJECT=m
93
94
CONFIG_IP_NF_TARGET_LOG=m
94
-
CONFIG_IP_NF_TARGET_ULOG=m
95
95
CONFIG_NF_NAT=m
96
96
CONFIG_IP_NF_TARGET_MASQUERADE=m
97
97
CONFIG_IP_NF_TARGET_NETMAP=m
···
115
117
CONFIG_IP6_NF_MATCH_MH=m
116
118
CONFIG_IP6_NF_MATCH_RT=m
117
119
CONFIG_IP6_NF_TARGET_HL=m
118
-
CONFIG_IP6_NF_TARGET_LOG=m
119
120
CONFIG_IP6_NF_FILTER=m
120
121
CONFIG_IP6_NF_TARGET_REJECT=m
121
122
CONFIG_IP6_NF_MANGLE=m
···
122
125
CONFIG_FW_LOADER=m
123
126
CONFIG_MTD=y
124
127
CONFIG_MTD_CMDLINE_PARTS=y
125
-
CONFIG_MTD_CHAR=y
126
128
CONFIG_MTD_BLOCK=y
127
129
CONFIG_MTD_CFI=y
128
130
CONFIG_MTD_CFI_AMDSTD=y
-1
arch/mips/configs/mips_paravirt_defconfig
-1
arch/mips/configs/mips_paravirt_defconfig
-5
arch/mips/configs/mpc30x_defconfig
-5
arch/mips/configs/mpc30x_defconfig
···
1
1
CONFIG_MACH_VR41XX=y
2
2
CONFIG_VICTOR_MPC30X=y
3
-
CONFIG_EXPERIMENTAL=y
4
3
CONFIG_SYSVIPC=y
5
4
CONFIG_LOG_BUF_SHIFT=14
6
5
CONFIG_RELAY=y
···
30
31
CONFIG_ATA=y
31
32
CONFIG_PATA_LEGACY=y
32
33
CONFIG_NETDEVICES=y
33
-
# CONFIG_NETDEV_1000 is not set
34
-
# CONFIG_NETDEV_10000 is not set
35
34
CONFIG_USB_PEGASUS=m
36
35
# CONFIG_INPUT_MOUSEDEV is not set
37
36
# CONFIG_INPUT_KEYBOARD is not set
···
42
45
CONFIG_GPIO_VR41XX=y
43
46
# CONFIG_HWMON is not set
44
47
# CONFIG_VGA_CONSOLE is not set
45
-
# CONFIG_HID_SUPPORT is not set
46
48
CONFIG_USB=m
47
49
CONFIG_USB_OHCI_HCD=m
48
50
CONFIG_RTC_CLASS=y
49
51
CONFIG_RTC_DRV_VR41XX=y
50
52
CONFIG_EXT2_FS=y
51
-
CONFIG_AUTOFS_FS=y
52
53
CONFIG_AUTOFS4_FS=y
53
54
CONFIG_PROC_KCORE=y
54
55
CONFIG_CONFIGFS_FS=m
-2
arch/mips/configs/msp71xx_defconfig
-2
arch/mips/configs/msp71xx_defconfig
···
2
2
CONFIG_PMC_MSP7120_GW=y
3
3
CONFIG_CPU_MIPS32_R2=y
4
4
CONFIG_PREEMPT=y
5
-
CONFIG_EXPERIMENTAL=y
6
5
CONFIG_LOCALVERSION="-pmc"
7
6
# CONFIG_SWAP is not set
8
7
CONFIG_SYSVIPC=y
···
37
38
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
38
39
# CONFIG_FW_LOADER is not set
39
40
CONFIG_MTD=y
40
-
CONFIG_MTD_CHAR=y
41
41
CONFIG_MTD_BLOCK=y
42
42
CONFIG_MTD_CFI=y
43
43
CONFIG_MTD_CFI_AMDSTD=y
-11
arch/mips/configs/mtx1_defconfig
-11
arch/mips/configs/mtx1_defconfig
···
1
1
CONFIG_MIPS_ALCHEMY=y
2
2
CONFIG_MIPS_MTX1=y
3
3
CONFIG_PREEMPT_VOLUNTARY=y
4
-
CONFIG_EXPERIMENTAL=y
5
4
# CONFIG_LOCALVERSION_AUTO is not set
6
5
CONFIG_SYSVIPC=y
7
6
CONFIG_POSIX_MQUEUE=y
···
80
81
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
81
82
CONFIG_NETFILTER_XT_MATCH_STRING=m
82
83
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
83
-
CONFIG_IP_NF_QUEUE=m
84
84
CONFIG_IP_NF_IPTABLES=m
85
85
CONFIG_IP_NF_MATCH_ADDRTYPE=m
86
86
CONFIG_IP_NF_MATCH_AH=m
···
88
90
CONFIG_IP_NF_FILTER=m
89
91
CONFIG_IP_NF_TARGET_REJECT=m
90
92
CONFIG_IP_NF_TARGET_LOG=m
91
-
CONFIG_IP_NF_TARGET_ULOG=m
92
93
CONFIG_IP_NF_MANGLE=m
93
94
CONFIG_IP_NF_TARGET_ECN=m
94
95
CONFIG_IP_NF_TARGET_TTL=m
···
95
98
CONFIG_IP_NF_ARPTABLES=m
96
99
CONFIG_IP_NF_ARPFILTER=m
97
100
CONFIG_IP_NF_ARP_MANGLE=m
98
-
CONFIG_IP6_NF_QUEUE=m
99
101
CONFIG_IP6_NF_IPTABLES=m
100
102
CONFIG_IP6_NF_MATCH_AH=m
101
103
CONFIG_IP6_NF_MATCH_EUI64=m
···
104
108
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
105
109
CONFIG_IP6_NF_MATCH_RT=m
106
110
CONFIG_IP6_NF_TARGET_HL=m
107
-
CONFIG_IP6_NF_TARGET_LOG=m
108
111
CONFIG_IP6_NF_FILTER=m
109
112
CONFIG_IP6_NF_TARGET_REJECT=m
110
113
CONFIG_IP6_NF_MANGLE=m
···
220
225
CONFIG_VLSI_FIR=m
221
226
CONFIG_MCS_FIR=m
222
227
CONFIG_BT=m
223
-
CONFIG_BT_L2CAP=y
224
-
CONFIG_BT_SCO=y
225
228
CONFIG_BT_RFCOMM=m
226
229
CONFIG_BT_RFCOMM_TTY=y
227
230
CONFIG_BT_BNEP=m
···
239
246
CONFIG_BT_HCIVHCI=m
240
247
CONFIG_CONNECTOR=m
241
248
CONFIG_MTD=y
242
-
CONFIG_MTD_CHAR=y
243
249
CONFIG_MTD_BLOCK=y
244
250
CONFIG_MTD_CFI=y
245
251
CONFIG_MTD_CFI_INTELEXT=y
···
249
257
CONFIG_BLK_DEV_NBD=m
250
258
CONFIG_BLK_DEV_RAM=y
251
259
CONFIG_BLK_DEV_RAM_SIZE=65536
252
-
# CONFIG_MISC_DEVICES is not set
253
260
CONFIG_SCSI=m
254
261
CONFIG_BLK_DEV_SD=m
255
262
CONFIG_CHR_DEV_SG=m
···
587
596
CONFIG_USB_STORAGE_JUMPSHOT=m
588
597
CONFIG_USB_STORAGE_ALAUDA=m
589
598
CONFIG_USB_STORAGE_KARMA=m
590
-
CONFIG_USB_LIBUSUAL=y
591
599
CONFIG_USB_MDC800=m
592
600
CONFIG_USB_MICROTEK=m
593
601
CONFIG_USB_SERIAL=m
···
630
640
CONFIG_USB_RIO500=m
631
641
CONFIG_USB_LEGOTOWER=m
632
642
CONFIG_USB_LCD=m
633
-
CONFIG_USB_LED=m
634
643
CONFIG_USB_CYPRESS_CY7C63=m
635
644
CONFIG_USB_CYTHERM=m
636
645
CONFIG_USB_IDMOUSE=m
-5
arch/mips/configs/nlm_xlp_defconfig
-5
arch/mips/configs/nlm_xlp_defconfig
···
6
6
CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
7
7
CONFIG_SMP=y
8
8
# CONFIG_SECCOMP is not set
9
-
CONFIG_EXPERIMENTAL=y
10
9
# CONFIG_LOCALVERSION_AUTO is not set
11
10
CONFIG_SYSVIPC=y
12
11
CONFIG_POSIX_MQUEUE=y
···
182
183
CONFIG_IP_VS_NQ=m
183
184
CONFIG_IP_VS_FTP=m
184
185
CONFIG_NF_CONNTRACK_IPV4=m
185
-
CONFIG_IP_NF_QUEUE=m
186
186
CONFIG_IP_NF_IPTABLES=m
187
187
CONFIG_IP_NF_MATCH_AH=m
188
188
CONFIG_IP_NF_MATCH_ECN=m
189
189
CONFIG_IP_NF_MATCH_TTL=m
190
190
CONFIG_IP_NF_FILTER=m
191
191
CONFIG_IP_NF_TARGET_REJECT=m
192
-
CONFIG_IP_NF_TARGET_ULOG=m
193
192
CONFIG_NF_NAT=m
194
193
CONFIG_IP_NF_TARGET_MASQUERADE=m
195
194
CONFIG_IP_NF_TARGET_NETMAP=m
···
314
317
CONFIG_CONNECTOR=y
315
318
CONFIG_MTD=y
316
319
CONFIG_MTD_CMDLINE_PARTS=y
317
-
CONFIG_MTD_CHAR=y
318
320
CONFIG_MTD_BLOCK=y
319
321
CONFIG_MTD_CFI=y
320
322
CONFIG_MTD_CFI_ADV_OPTIONS=y
···
603
607
CONFIG_CRYPTO_SERPENT=m
604
608
CONFIG_CRYPTO_TEA=m
605
609
CONFIG_CRYPTO_TWOFISH=m
606
-
CONFIG_CRYPTO_ZLIB=m
607
610
CONFIG_CRYPTO_LZO=m
608
611
CONFIG_CRC_CCITT=m
609
612
CONFIG_CRC7=m
-9
arch/mips/configs/nlm_xlr_defconfig
-9
arch/mips/configs/nlm_xlr_defconfig
···
7
7
CONFIG_HIGH_RES_TIMERS=y
8
8
CONFIG_PREEMPT_VOLUNTARY=y
9
9
CONFIG_KEXEC=y
10
-
CONFIG_EXPERIMENTAL=y
11
10
CONFIG_CROSS_COMPILE=""
12
11
# CONFIG_LOCALVERSION_AUTO is not set
13
12
CONFIG_SYSVIPC=y
···
162
163
CONFIG_IP_VS_NQ=m
163
164
CONFIG_IP_VS_FTP=m
164
165
CONFIG_NF_CONNTRACK_IPV4=m
165
-
CONFIG_IP_NF_QUEUE=m
166
166
CONFIG_IP_NF_IPTABLES=m
167
167
CONFIG_IP_NF_MATCH_AH=m
168
168
CONFIG_IP_NF_MATCH_ECN=m
···
169
171
CONFIG_IP_NF_FILTER=m
170
172
CONFIG_IP_NF_TARGET_REJECT=m
171
173
CONFIG_IP_NF_TARGET_LOG=m
172
-
CONFIG_IP_NF_TARGET_ULOG=m
173
174
CONFIG_NF_NAT=m
174
175
CONFIG_IP_NF_TARGET_MASQUERADE=m
175
176
CONFIG_IP_NF_TARGET_NETMAP=m
···
183
186
CONFIG_IP_NF_ARPFILTER=m
184
187
CONFIG_IP_NF_ARP_MANGLE=m
185
188
CONFIG_NF_CONNTRACK_IPV6=m
186
-
CONFIG_IP6_NF_QUEUE=m
187
189
CONFIG_IP6_NF_IPTABLES=m
188
190
CONFIG_IP6_NF_MATCH_AH=m
189
191
CONFIG_IP6_NF_MATCH_EUI64=m
···
193
197
CONFIG_IP6_NF_MATCH_MH=m
194
198
CONFIG_IP6_NF_MATCH_RT=m
195
199
CONFIG_IP6_NF_TARGET_HL=m
196
-
CONFIG_IP6_NF_TARGET_LOG=m
197
200
CONFIG_IP6_NF_FILTER=m
198
201
CONFIG_IP6_NF_TARGET_REJECT=m
199
202
CONFIG_IP6_NF_MANGLE=m
···
303
308
CONFIG_BLK_DEV_RAM=y
304
309
CONFIG_BLK_DEV_RAM_SIZE=65536
305
310
CONFIG_CDROM_PKTCDVD=y
306
-
CONFIG_MISC_DEVICES=y
307
311
CONFIG_RAID_ATTRS=m
308
312
CONFIG_SCSI=y
309
313
CONFIG_BLK_DEV_SD=y
···
363
369
CONFIG_RTC_DRV_DS1374=y
364
370
# CONFIG_HWMON is not set
365
371
# CONFIG_VGA_CONSOLE is not set
366
-
# CONFIG_HID_SUPPORT is not set
367
372
# CONFIG_USB_SUPPORT is not set
368
373
CONFIG_UIO=y
369
374
CONFIG_UIO_PDRV=m
···
515
522
CONFIG_TIMER_STATS=y
516
523
CONFIG_DEBUG_INFO=y
517
524
CONFIG_DEBUG_MEMORY_INIT=y
518
-
CONFIG_SYSCTL_SYSCALL_CHECK=y
519
525
CONFIG_SCHED_TRACER=y
520
526
CONFIG_BLK_DEV_IO_TRACE=y
521
527
CONFIG_KGDB=y
···
560
568
CONFIG_CRYPTO_SERPENT=m
561
569
CONFIG_CRYPTO_TEA=m
562
570
CONFIG_CRYPTO_TWOFISH=m
563
-
CONFIG_CRYPTO_ZLIB=m
564
571
CONFIG_CRYPTO_LZO=m
565
572
CONFIG_CRC_CCITT=m
566
573
CONFIG_CRC7=m
-7
arch/mips/configs/pnx8335_stb225_defconfig
-7
arch/mips/configs/pnx8335_stb225_defconfig
···
5
5
CONFIG_HZ_128=y
6
6
CONFIG_PREEMPT_VOLUNTARY=y
7
7
# CONFIG_SECCOMP is not set
8
-
CONFIG_EXPERIMENTAL=y
9
8
# CONFIG_LOCALVERSION_AUTO is not set
10
9
# CONFIG_SWAP is not set
11
10
CONFIG_SYSVIPC=y
···
26
27
CONFIG_IP_PNP=y
27
28
CONFIG_IP_PNP_DHCP=y
28
29
CONFIG_INET_AH=y
29
-
# CONFIG_INET_LRO is not set
30
30
# CONFIG_IPV6 is not set
31
31
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
32
32
CONFIG_MTD=y
33
33
CONFIG_MTD_CMDLINE_PARTS=y
34
-
CONFIG_MTD_CHAR=y
35
34
CONFIG_MTD_BLOCK=y
36
35
CONFIG_MTD_CFI=y
37
36
CONFIG_MTD_CFI_ADV_OPTIONS=y
···
38
41
CONFIG_MTD_CFI_AMDSTD=y
39
42
CONFIG_MTD_PHYSMAP=y
40
43
CONFIG_BLK_DEV_LOOP=y
41
-
# CONFIG_MISC_DEVICES is not set
42
44
CONFIG_BLK_DEV_SD=y
43
45
# CONFIG_SCSI_LOWLEVEL is not set
44
46
CONFIG_ATA=y
45
47
CONFIG_NETDEVICES=y
46
48
CONFIG_NET_ETHERNET=y
47
49
CONFIG_MII=y
48
-
# CONFIG_NETDEV_1000 is not set
49
-
# CONFIG_NETDEV_10000 is not set
50
50
# CONFIG_INPUT_MOUSEDEV is not set
51
51
CONFIG_INPUT_EVDEV=m
52
52
CONFIG_INPUT_EVBUG=m
···
88
94
CONFIG_NLS_ISO8859_1=m
89
95
CONFIG_NLS_ISO8859_15=m
90
96
CONFIG_NLS_UTF8=m
91
-
CONFIG_SYSCTL_SYSCALL_CHECK=y
-3
arch/mips/configs/qi_lb60_defconfig
-3
arch/mips/configs/qi_lb60_defconfig
···
34
34
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
35
35
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
36
36
# CONFIG_INET_XFRM_MODE_BEET is not set
37
-
# CONFIG_INET_LRO is not set
38
37
# CONFIG_INET_DIAG is not set
39
38
CONFIG_TCP_CONG_ADVANCED=y
40
39
# CONFIG_TCP_CONG_BIC is not set
···
108
109
CONFIG_USB_ETH=y
109
110
# CONFIG_USB_ETH_RNDIS is not set
110
111
CONFIG_MMC=y
111
-
CONFIG_MMC_UNSAFE_RESUME=y
112
112
# CONFIG_MMC_BLOCK_BOUNCE is not set
113
113
CONFIG_MMC_JZ4740=y
114
114
CONFIG_RTC_CLASS=y
···
181
183
# CONFIG_FTRACE is not set
182
184
CONFIG_KGDB=y
183
185
CONFIG_RUNTIME_DEBUG=y
184
-
CONFIG_CRYPTO_ZLIB=y
185
186
# CONFIG_CRYPTO_ANSI_CPRNG is not set
186
187
CONFIG_FONTS=y
187
188
CONFIG_FONT_SUN8x16=y
-6
arch/mips/configs/rb532_defconfig
-6
arch/mips/configs/rb532_defconfig
···
3
3
CONFIG_HIGH_RES_TIMERS=y
4
4
CONFIG_HZ_100=y
5
5
# CONFIG_SECCOMP is not set
6
-
CONFIG_EXPERIMENTAL=y
7
6
# CONFIG_LOCALVERSION_AUTO is not set
8
7
CONFIG_SYSVIPC=y
9
8
CONFIG_BSD_PROCESS_ACCT=y
···
38
39
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
39
40
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
40
41
# CONFIG_INET_XFRM_MODE_BEET is not set
41
-
# CONFIG_INET_LRO is not set
42
42
CONFIG_INET_DIAG=m
43
43
CONFIG_TCP_CONG_ADVANCED=y
44
44
CONFIG_TCP_CONG_CUBIC=m
···
112
114
CONFIG_HAMRADIO=y
113
115
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
114
116
CONFIG_MTD=y
115
-
CONFIG_MTD_CHAR=y
116
117
CONFIG_MTD_BLOCK=y
117
118
CONFIG_MTD_BLOCK2MTD=y
118
119
CONFIG_MTD_NAND=y
···
126
129
CONFIG_KORINA=y
127
130
CONFIG_NET_PCI=y
128
131
CONFIG_VIA_RHINE=y
129
-
# CONFIG_NETDEV_1000 is not set
130
-
# CONFIG_NETDEV_10000 is not set
131
132
CONFIG_ATMEL=m
132
133
CONFIG_PPP=m
133
134
CONFIG_PPP_MULTILINK=y
···
178
183
CONFIG_STRIP_ASM_SYMS=y
179
184
CONFIG_CRYPTO=y
180
185
CONFIG_CRYPTO_TEST=m
181
-
CONFIG_CRYPTO_ZLIB=y
182
186
# CONFIG_CRYPTO_HW is not set
183
187
CONFIG_CRC16=m
184
188
CONFIG_LIBCRC32C=m
-7
arch/mips/configs/rbtx49xx_defconfig
-7
arch/mips/configs/rbtx49xx_defconfig
···
31
31
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
32
32
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
33
33
# CONFIG_INET_XFRM_MODE_BEET is not set
34
-
# CONFIG_INET_LRO is not set
35
34
# CONFIG_IPV6 is not set
36
35
# CONFIG_WIRELESS is not set
37
36
CONFIG_MTD=y
38
37
CONFIG_MTD_CMDLINE_PARTS=y
39
-
CONFIG_MTD_CHAR=y
40
38
CONFIG_MTD_BLOCK=m
41
39
CONFIG_MTD_BLOCK_RO=m
42
40
CONFIG_MTD_CFI=y
···
48
50
CONFIG_BLK_DEV_LOOP=y
49
51
CONFIG_BLK_DEV_RAM=y
50
52
CONFIG_BLK_DEV_RAM_SIZE=8192
51
-
# CONFIG_MISC_DEVICES is not set
52
53
CONFIG_IDE=y
53
54
CONFIG_BLK_DEV_IDE_TX4938=y
54
55
CONFIG_BLK_DEV_IDE_TX4939=y
···
57
60
CONFIG_NE2000=y
58
61
CONFIG_NET_PCI=y
59
62
CONFIG_TC35815=y
60
-
# CONFIG_NETDEV_1000 is not set
61
-
# CONFIG_NETDEV_10000 is not set
62
63
# CONFIG_WLAN is not set
63
64
# CONFIG_INPUT is not set
64
65
# CONFIG_SERIO is not set
···
103
108
CONFIG_ROOT_NFS=y
104
109
CONFIG_STRIP_ASM_SYMS=y
105
110
CONFIG_DEBUG_FS=y
106
-
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
107
-
CONFIG_SYSCTL_SYSCALL_CHECK=y
-8
arch/mips/configs/rm200_defconfig
-8
arch/mips/configs/rm200_defconfig
···
3
3
CONFIG_ARC_CONSOLE=y
4
4
CONFIG_HZ_1000=y
5
5
CONFIG_PREEMPT_VOLUNTARY=y
6
-
CONFIG_EXPERIMENTAL=y
7
6
CONFIG_SYSVIPC=y
8
7
CONFIG_POSIX_MQUEUE=y
9
8
CONFIG_BSD_PROCESS_ACCT=y
···
93
94
CONFIG_NETFILTER_XT_MATCH_STRING=m
94
95
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
95
96
CONFIG_NF_CONNTRACK_IPV4=m
96
-
CONFIG_IP_NF_QUEUE=m
97
97
CONFIG_IP_NF_IPTABLES=m
98
98
CONFIG_IP_NF_MATCH_ADDRTYPE=m
99
99
CONFIG_IP_NF_MATCH_AH=m
···
101
103
CONFIG_IP_NF_FILTER=m
102
104
CONFIG_IP_NF_TARGET_REJECT=m
103
105
CONFIG_IP_NF_TARGET_LOG=m
104
-
CONFIG_IP_NF_TARGET_ULOG=m
105
106
CONFIG_NF_NAT=m
106
107
CONFIG_IP_NF_TARGET_MASQUERADE=m
107
108
CONFIG_IP_NF_TARGET_NETMAP=m
···
115
118
CONFIG_IP_NF_ARPFILTER=m
116
119
CONFIG_IP_NF_ARP_MANGLE=m
117
120
CONFIG_NF_CONNTRACK_IPV6=m
118
-
CONFIG_IP6_NF_QUEUE=m
119
121
CONFIG_IP6_NF_IPTABLES=m
120
122
CONFIG_IP6_NF_MATCH_AH=m
121
123
CONFIG_IP6_NF_MATCH_EUI64=m
···
125
129
CONFIG_IP6_NF_MATCH_MH=m
126
130
CONFIG_IP6_NF_MATCH_RT=m
127
131
CONFIG_IP6_NF_TARGET_HL=m
128
-
CONFIG_IP6_NF_TARGET_LOG=m
129
132
CONFIG_IP6_NF_FILTER=m
130
133
CONFIG_IP6_NF_TARGET_REJECT=m
131
134
CONFIG_IP6_NF_MANGLE=m
···
209
214
CONFIG_BLK_DEV_CRYPTOLOOP=m
210
215
CONFIG_BLK_DEV_NBD=m
211
216
CONFIG_BLK_DEV_SX8=m
212
-
CONFIG_BLK_DEV_UB=m
213
217
CONFIG_BLK_DEV_RAM=m
214
218
CONFIG_CDROM_PKTCDVD=m
215
219
CONFIG_ATA_OVER_ETH=m
···
347
353
CONFIG_USB_RIO500=m
348
354
CONFIG_USB_LEGOTOWER=m
349
355
CONFIG_USB_LCD=m
350
-
CONFIG_USB_LED=m
351
356
CONFIG_USB_CYTHERM=m
352
357
CONFIG_USB_SISUSBVGA=m
353
358
CONFIG_USB_LD=m
···
359
366
CONFIG_REISERFS_FS_SECURITY=y
360
367
CONFIG_XFS_FS=m
361
368
CONFIG_XFS_QUOTA=y
362
-
CONFIG_AUTOFS_FS=m
363
369
CONFIG_AUTOFS4_FS=m
364
370
CONFIG_FUSE_FS=m
365
371
CONFIG_ISO9660_FS=m
-2
arch/mips/configs/rt305x_defconfig
-2
arch/mips/configs/rt305x_defconfig
···
5
5
# CONFIG_CROSS_MEMORY_ATTACH is not set
6
6
CONFIG_HZ_100=y
7
7
# CONFIG_SECCOMP is not set
8
-
CONFIG_EXPERIMENTAL=y
9
8
# CONFIG_LOCALVERSION_AUTO is not set
10
9
CONFIG_SYSVIPC=y
11
10
CONFIG_HIGH_RES_TIMERS=y
···
43
44
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
44
45
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
45
46
# CONFIG_INET_XFRM_MODE_BEET is not set
46
-
# CONFIG_INET_LRO is not set
47
47
# CONFIG_INET_DIAG is not set
48
48
CONFIG_TCP_CONG_ADVANCED=y
49
49
# CONFIG_TCP_CONG_BIC is not set
-1
arch/mips/configs/sb1250_swarm_defconfig
-1
arch/mips/configs/sb1250_swarm_defconfig
-6
arch/mips/configs/tb0219_defconfig
-6
arch/mips/configs/tb0219_defconfig
···
1
1
CONFIG_MACH_VR41XX=y
2
2
CONFIG_TANBAC_TB0219=y
3
-
CONFIG_EXPERIMENTAL=y
4
3
CONFIG_SYSVIPC=y
5
4
CONFIG_LOG_BUF_SHIFT=14
6
5
CONFIG_SYSFS_DEPRECATED_V2=y
···
30
31
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
31
32
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
32
33
# CONFIG_INET_XFRM_MODE_BEET is not set
33
-
# CONFIG_INET_LRO is not set
34
34
# CONFIG_IPV6 is not set
35
35
CONFIG_NETWORK_SECMARK=y
36
36
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
···
38
40
CONFIG_BLK_DEV_NBD=m
39
41
CONFIG_BLK_DEV_RAM=y
40
42
CONFIG_BLK_DEV_XIP=y
41
-
# CONFIG_MISC_DEVICES is not set
42
43
CONFIG_NETDEVICES=y
43
44
CONFIG_PHYLIB=m
44
45
CONFIG_MARVELL_PHY=m
···
54
57
CONFIG_VIA_RHINE_MMIO=y
55
58
CONFIG_R8169=y
56
59
CONFIG_VIA_VELOCITY=y
57
-
# CONFIG_NETDEV_10000 is not set
58
60
# CONFIG_INPUT_MOUSEDEV is not set
59
61
# CONFIG_INPUT_KEYBOARD is not set
60
62
# CONFIG_INPUT_MOUSE is not set
···
66
70
CONFIG_GPIO_TB0219=y
67
71
# CONFIG_HWMON is not set
68
72
# CONFIG_VGA_CONSOLE is not set
69
-
# CONFIG_HID_SUPPORT is not set
70
73
CONFIG_USB=m
71
74
CONFIG_USB_MON=m
72
75
CONFIG_USB_EHCI_HCD=m
···
86
91
CONFIG_ROOT_NFS=y
87
92
CONFIG_NFSD=y
88
93
CONFIG_NFSD_V3=y
89
-
CONFIG_SYSCTL_SYSCALL_CHECK=y
90
94
CONFIG_CMDLINE_BOOL=y
91
95
CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
-7
arch/mips/configs/tb0226_defconfig
-7
arch/mips/configs/tb0226_defconfig
···
1
1
CONFIG_MACH_VR41XX=y
2
2
CONFIG_TANBAC_TB0226=y
3
-
CONFIG_EXPERIMENTAL=y
4
3
CONFIG_SYSVIPC=y
5
4
CONFIG_LOG_BUF_SHIFT=14
6
5
CONFIG_SYSFS_DEPRECATED_V2=y
···
28
29
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
29
30
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
30
31
# CONFIG_INET_XFRM_MODE_BEET is not set
31
-
# CONFIG_INET_LRO is not set
32
32
# CONFIG_IPV6 is not set
33
33
CONFIG_NETWORK_SECMARK=y
34
34
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
···
35
37
CONFIG_BLK_DEV_NBD=m
36
38
CONFIG_BLK_DEV_RAM=y
37
39
CONFIG_BLK_DEV_XIP=y
38
-
# CONFIG_MISC_DEVICES is not set
39
40
CONFIG_SCSI=y
40
41
CONFIG_BLK_DEV_SD=y
41
42
CONFIG_SCSI_MULTI_LUN=y
···
46
49
CONFIG_NET_ETHERNET=y
47
50
CONFIG_NET_PCI=y
48
51
CONFIG_E100=y
49
-
# CONFIG_NETDEV_1000 is not set
50
-
# CONFIG_NETDEV_10000 is not set
51
52
CONFIG_USB_CATC=m
52
53
CONFIG_USB_KAWETH=m
53
54
CONFIG_USB_PEGASUS=m
···
61
66
# CONFIG_HW_RANDOM is not set
62
67
# CONFIG_HWMON is not set
63
68
# CONFIG_VGA_CONSOLE is not set
64
-
# CONFIG_HID_SUPPORT is not set
65
69
CONFIG_USB=y
66
70
CONFIG_USB_EHCI_HCD=y
67
71
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
···
81
87
CONFIG_ROOT_NFS=y
82
88
CONFIG_NFSD=m
83
89
CONFIG_NFSD_V3=y
84
-
CONFIG_SYSCTL_SYSCALL_CHECK=y
85
90
CONFIG_CMDLINE_BOOL=y
86
91
CONFIG_CMDLINE="cca=3 mem=32M console=ttyVR0,115200"
87
92
CONFIG_CRC32=m
-5
arch/mips/configs/tb0287_defconfig
-5
arch/mips/configs/tb0287_defconfig
···
1
1
CONFIG_MACH_VR41XX=y
2
-
CONFIG_EXPERIMENTAL=y
3
2
CONFIG_SYSVIPC=y
4
3
CONFIG_LOG_BUF_SHIFT=14
5
4
CONFIG_SYSFS_DEPRECATED_V2=y
···
30
31
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
31
32
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
32
33
# CONFIG_INET_XFRM_MODE_BEET is not set
33
-
# CONFIG_INET_LRO is not set
34
34
CONFIG_TCP_CONG_ADVANCED=y
35
35
CONFIG_TCP_CONG_BIC=y
36
36
CONFIG_TCP_CONG_CUBIC=m
···
41
43
CONFIG_BLK_DEV_NBD=m
42
44
CONFIG_BLK_DEV_RAM=y
43
45
CONFIG_BLK_DEV_XIP=y
44
-
# CONFIG_MISC_DEVICES is not set
45
46
CONFIG_BLK_DEV_SD=y
46
47
CONFIG_SCSI_SCAN_ASYNC=y
47
48
# CONFIG_SCSI_LOWLEVEL is not set
···
61
64
CONFIG_VIA_RHINE_MMIO=y
62
65
CONFIG_R8169=y
63
66
CONFIG_VIA_VELOCITY=y
64
-
# CONFIG_NETDEV_10000 is not set
65
67
# CONFIG_INPUT_KEYBOARD is not set
66
68
# CONFIG_INPUT_MOUSE is not set
67
69
# CONFIG_SERIO is not set
···
72
76
CONFIG_GPIO_VR41XX=y
73
77
# CONFIG_HWMON is not set
74
78
CONFIG_MFD_SM501=y
75
-
CONFIG_VIDEO_OUTPUT_CONTROL=m
76
79
CONFIG_FB=y
77
80
CONFIG_FB_SM501=y
78
81
# CONFIG_VGA_CONSOLE is not set
-4
arch/mips/configs/workpad_defconfig
-4
arch/mips/configs/workpad_defconfig
···
1
1
CONFIG_MACH_VR41XX=y
2
2
CONFIG_IBM_WORKPAD=y
3
-
CONFIG_EXPERIMENTAL=y
4
3
CONFIG_SYSVIPC=y
5
4
CONFIG_LOG_BUF_SHIFT=14
6
5
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
···
27
28
# CONFIG_IPV6 is not set
28
29
CONFIG_NETWORK_SECMARK=y
29
30
CONFIG_BLK_DEV_RAM=m
30
-
# CONFIG_MISC_DEVICES is not set
31
31
CONFIG_IDE=y
32
32
CONFIG_BLK_DEV_IDECS=m
33
33
CONFIG_IDE_GENERIC=y
34
34
CONFIG_NETDEVICES=y
35
-
# CONFIG_NETDEV_1000 is not set
36
-
# CONFIG_NETDEV_10000 is not set
37
35
CONFIG_NET_PCMCIA=y
38
36
CONFIG_PCMCIA_3C589=m
39
37
CONFIG_PCMCIA_3C574=m
+20
arch/mips/generic/Kconfig
+20
arch/mips/generic/Kconfig
···
9
9
kernel is booted without being provided with an FDT via the UHI
10
10
boot protocol.
11
11
12
+
config YAMON_DT_SHIM
13
+
bool
14
+
help
15
+
Select this from your board if the board uses the YAMON bootloader
16
+
and you wish to include code which helps translate various
17
+
YAMON-provided environment variables into a device tree properties.
18
+
19
+
comment "Legacy (non-UHI/non-FIT) Boards"
20
+
12
21
config LEGACY_BOARD_SEAD3
13
22
bool "Support MIPS SEAD-3 boards"
14
23
select LEGACY_BOARDS
24
+
select YAMON_DT_SHIM
15
25
help
16
26
Enable this to include support for booting on MIPS SEAD-3 FPGA-based
17
27
development boards, which boot using a legacy boot protocol.
28
+
29
+
comment "FIT/UHI Boards"
30
+
31
+
config FIT_IMAGE_FDT_BOSTON
32
+
bool "Include FDT for MIPS Boston boards"
33
+
help
34
+
Enable this to include the FDT for the MIPS Boston development board
35
+
from Imagination Technologies in the FIT kernel image. You should
36
+
enable this if you wish to boot on a MIPS Boston board, as it is
37
+
expected by the bootloader.
18
38
19
39
endif
+1
arch/mips/generic/Makefile
+1
arch/mips/generic/Makefile
+42
-194
arch/mips/generic/board-sead3.c
+42
-194
arch/mips/generic/board-sead3.c
···
13
13
#include <linux/errno.h>
14
14
#include <linux/libfdt.h>
15
15
#include <linux/printk.h>
16
+
#include <linux/sizes.h>
16
17
17
18
#include <asm/fw/fw.h>
18
19
#include <asm/io.h>
19
20
#include <asm/machine.h>
21
+
#include <asm/yamon-dt.h>
20
22
21
23
#define SEAD_CONFIG CKSEG1ADDR(0x1b100110)
22
24
#define SEAD_CONFIG_GIC_PRESENT BIT(1)
···
26
24
#define MIPS_REVISION CKSEG1ADDR(0x1fc00010)
27
25
#define MIPS_REVISION_MACHINE (0xf << 4)
28
26
#define MIPS_REVISION_MACHINE_SEAD3 (0x4 << 4)
27
+
28
+
/*
29
+
* Maximum 384MB RAM at physical address 0, preceding any I/O.
30
+
*/
31
+
static struct yamon_mem_region mem_regions[] __initdata = {
32
+
/* start size */
33
+
{ 0, SZ_256M + SZ_128M },
34
+
{}
35
+
};
29
36
30
37
static __init bool sead3_detect(void)
31
38
{
···
44
33
return (rev & MIPS_REVISION_MACHINE) == MIPS_REVISION_MACHINE_SEAD3;
45
34
}
46
35
47
-
static __init int append_cmdline(void *fdt)
48
-
{
49
-
int err, chosen_off;
50
-
51
-
/* find or add chosen node */
52
-
chosen_off = fdt_path_offset(fdt, "/chosen");
53
-
if (chosen_off == -FDT_ERR_NOTFOUND)
54
-
chosen_off = fdt_path_offset(fdt, "/chosen@0");
55
-
if (chosen_off == -FDT_ERR_NOTFOUND)
56
-
chosen_off = fdt_add_subnode(fdt, 0, "chosen");
57
-
if (chosen_off < 0) {
58
-
pr_err("Unable to find or add DT chosen node: %d\n",
59
-
chosen_off);
60
-
return chosen_off;
61
-
}
62
-
63
-
err = fdt_setprop_string(fdt, chosen_off, "bootargs", fw_getcmdline());
64
-
if (err) {
65
-
pr_err("Unable to set bootargs property: %d\n", err);
66
-
return err;
67
-
}
68
-
69
-
return 0;
70
-
}
71
-
72
36
static __init int append_memory(void *fdt)
73
37
{
74
-
unsigned long phys_memsize, memsize;
75
-
__be32 mem_array[2];
76
-
int err, mem_off;
77
-
char *var;
78
-
79
-
/* find memory size from the bootloader environment */
80
-
var = fw_getenv("memsize");
81
-
if (var) {
82
-
err = kstrtoul(var, 0, &phys_memsize);
83
-
if (err) {
84
-
pr_err("Failed to read memsize env variable '%s'\n",
85
-
var);
86
-
return -EINVAL;
87
-
}
88
-
} else {
89
-
pr_warn("The bootloader didn't provide memsize: defaulting to 32MB\n");
90
-
phys_memsize = 32 << 20;
91
-
}
92
-
93
-
/* default to using all available RAM */
94
-
memsize = phys_memsize;
95
-
96
-
/* allow the user to override the usable memory */
97
-
var = strstr(arcs_cmdline, "memsize=");
98
-
if (var)
99
-
memsize = memparse(var + strlen("memsize="), NULL);
100
-
101
-
/* if the user says there's more RAM than we thought, believe them */
102
-
phys_memsize = max_t(unsigned long, phys_memsize, memsize);
103
-
104
-
/* find or add a memory node */
105
-
mem_off = fdt_path_offset(fdt, "/memory");
106
-
if (mem_off == -FDT_ERR_NOTFOUND)
107
-
mem_off = fdt_add_subnode(fdt, 0, "memory");
108
-
if (mem_off < 0) {
109
-
pr_err("Unable to find or add memory DT node: %d\n", mem_off);
110
-
return mem_off;
111
-
}
112
-
113
-
err = fdt_setprop_string(fdt, mem_off, "device_type", "memory");
114
-
if (err) {
115
-
pr_err("Unable to set memory node device_type: %d\n", err);
116
-
return err;
117
-
}
118
-
119
-
mem_array[0] = 0;
120
-
mem_array[1] = cpu_to_be32(phys_memsize);
121
-
err = fdt_setprop(fdt, mem_off, "reg", mem_array, sizeof(mem_array));
122
-
if (err) {
123
-
pr_err("Unable to set memory regs property: %d\n", err);
124
-
return err;
125
-
}
126
-
127
-
mem_array[0] = 0;
128
-
mem_array[1] = cpu_to_be32(memsize);
129
-
err = fdt_setprop(fdt, mem_off, "linux,usable-memory",
130
-
mem_array, sizeof(mem_array));
131
-
if (err) {
132
-
pr_err("Unable to set linux,usable-memory property: %d\n", err);
133
-
return err;
134
-
}
135
-
136
-
return 0;
38
+
return yamon_dt_append_memory(fdt, mem_regions);
137
39
}
138
40
139
41
static __init int remove_gic(void *fdt)
···
87
163
return -EINVAL;
88
164
}
89
165
90
-
err = fdt_setprop_u32(fdt, 0, "interrupt-parent", cpu_phandle);
91
-
if (err) {
92
-
pr_err("unable to set root interrupt-parent: %d\n", err);
93
-
return err;
94
-
}
95
-
96
166
uart_off = fdt_node_offset_by_compatible(fdt, -1, "ns16550a");
97
167
while (uart_off >= 0) {
168
+
err = fdt_setprop_u32(fdt, uart_off, "interrupt-parent",
169
+
cpu_phandle);
170
+
if (err) {
171
+
pr_warn("unable to set UART interrupt-parent: %d\n",
172
+
err);
173
+
return err;
174
+
}
175
+
98
176
err = fdt_setprop_u32(fdt, uart_off, "interrupts",
99
177
cpu_uart_int);
100
178
if (err) {
···
119
193
return eth_off;
120
194
}
121
195
196
+
err = fdt_setprop_u32(fdt, eth_off, "interrupt-parent", cpu_phandle);
197
+
if (err) {
198
+
pr_err("unable to set ethernet interrupt-parent: %d\n", err);
199
+
return err;
200
+
}
201
+
122
202
err = fdt_setprop_u32(fdt, eth_off, "interrupts", cpu_eth_int);
123
203
if (err) {
124
204
pr_err("unable to set ethernet interrupts property: %d\n", err);
···
137
205
return ehci_off;
138
206
}
139
207
208
+
err = fdt_setprop_u32(fdt, ehci_off, "interrupt-parent", cpu_phandle);
209
+
if (err) {
210
+
pr_err("unable to set EHCI interrupt-parent: %d\n", err);
211
+
return err;
212
+
}
213
+
140
214
err = fdt_setprop_u32(fdt, ehci_off, "interrupts", cpu_ehci_int);
141
215
if (err) {
142
216
pr_err("unable to set EHCI interrupts property: %d\n", err);
···
152
214
return 0;
153
215
}
154
216
155
-
static __init int serial_config(void *fdt)
156
-
{
157
-
const char *yamontty, *mode_var;
158
-
char mode_var_name[9], path[18], parity;
159
-
unsigned int uart, baud, stop_bits;
160
-
bool hw_flow;
161
-
int chosen_off, err;
162
-
163
-
yamontty = fw_getenv("yamontty");
164
-
if (!yamontty || !strcmp(yamontty, "tty0")) {
165
-
uart = 0;
166
-
} else if (!strcmp(yamontty, "tty1")) {
167
-
uart = 1;
168
-
} else {
169
-
pr_warn("yamontty environment variable '%s' invalid\n",
170
-
yamontty);
171
-
uart = 0;
172
-
}
173
-
174
-
baud = stop_bits = 0;
175
-
parity = 0;
176
-
hw_flow = false;
177
-
178
-
snprintf(mode_var_name, sizeof(mode_var_name), "modetty%u", uart);
179
-
mode_var = fw_getenv(mode_var_name);
180
-
if (mode_var) {
181
-
while (mode_var[0] >= '0' && mode_var[0] <= '9') {
182
-
baud *= 10;
183
-
baud += mode_var[0] - '0';
184
-
mode_var++;
185
-
}
186
-
if (mode_var[0] == ',')
187
-
mode_var++;
188
-
if (mode_var[0])
189
-
parity = mode_var[0];
190
-
if (mode_var[0] == ',')
191
-
mode_var++;
192
-
if (mode_var[0])
193
-
stop_bits = mode_var[0] - '0';
194
-
if (mode_var[0] == ',')
195
-
mode_var++;
196
-
if (!strcmp(mode_var, "hw"))
197
-
hw_flow = true;
198
-
}
199
-
200
-
if (!baud)
201
-
baud = 38400;
202
-
203
-
if (parity != 'e' && parity != 'n' && parity != 'o')
204
-
parity = 'n';
205
-
206
-
if (stop_bits != 7 && stop_bits != 8)
207
-
stop_bits = 8;
208
-
209
-
WARN_ON(snprintf(path, sizeof(path), "uart%u:%u%c%u%s",
210
-
uart, baud, parity, stop_bits,
211
-
hw_flow ? "r" : "") >= sizeof(path));
212
-
213
-
/* find or add chosen node */
214
-
chosen_off = fdt_path_offset(fdt, "/chosen");
215
-
if (chosen_off == -FDT_ERR_NOTFOUND)
216
-
chosen_off = fdt_path_offset(fdt, "/chosen@0");
217
-
if (chosen_off == -FDT_ERR_NOTFOUND)
218
-
chosen_off = fdt_add_subnode(fdt, 0, "chosen");
219
-
if (chosen_off < 0) {
220
-
pr_err("Unable to find or add DT chosen node: %d\n",
221
-
chosen_off);
222
-
return chosen_off;
223
-
}
224
-
225
-
err = fdt_setprop_string(fdt, chosen_off, "stdout-path", path);
226
-
if (err) {
227
-
pr_err("Unable to set stdout-path property: %d\n", err);
228
-
return err;
229
-
}
230
-
231
-
return 0;
232
-
}
217
+
static const struct mips_fdt_fixup sead3_fdt_fixups[] __initconst = {
218
+
{ yamon_dt_append_cmdline, "append command line" },
219
+
{ append_memory, "append memory" },
220
+
{ remove_gic, "remove GIC when not present" },
221
+
{ yamon_dt_serial_config, "append serial configuration" },
222
+
{ },
223
+
};
233
224
234
225
static __init const void *sead3_fixup_fdt(const void *fdt,
235
226
const void *match_data)
···
174
307
175
308
fw_init_cmdline();
176
309
177
-
err = fdt_open_into(fdt, fdt_buf, sizeof(fdt_buf));
310
+
err = apply_mips_fdt_fixups(fdt_buf, sizeof(fdt_buf),
311
+
fdt, sead3_fdt_fixups);
178
312
if (err)
179
-
panic("Unable to open FDT: %d", err);
180
-
181
-
err = append_cmdline(fdt_buf);
182
-
if (err)
183
-
panic("Unable to patch FDT: %d", err);
184
-
185
-
err = append_memory(fdt_buf);
186
-
if (err)
187
-
panic("Unable to patch FDT: %d", err);
188
-
189
-
err = remove_gic(fdt_buf);
190
-
if (err)
191
-
panic("Unable to patch FDT: %d", err);
192
-
193
-
err = serial_config(fdt_buf);
194
-
if (err)
195
-
panic("Unable to patch FDT: %d", err);
196
-
197
-
err = fdt_pack(fdt_buf);
198
-
if (err)
199
-
panic("Unable to pack FDT: %d\n", err);
313
+
panic("Unable to fixup FDT: %d", err);
200
314
201
315
return fdt_buf;
202
316
}
+27
arch/mips/generic/init.c
+27
arch/mips/generic/init.c
···
122
122
err = register_up_smp_ops();
123
123
}
124
124
125
+
int __init apply_mips_fdt_fixups(void *fdt_out, size_t fdt_out_size,
126
+
const void *fdt_in,
127
+
const struct mips_fdt_fixup *fixups)
128
+
{
129
+
int err;
130
+
131
+
err = fdt_open_into(fdt_in, fdt_out, fdt_out_size);
132
+
if (err) {
133
+
pr_err("Failed to open FDT\n");
134
+
return err;
135
+
}
136
+
137
+
for (; fixups->apply; fixups++) {
138
+
err = fixups->apply(fdt_out);
139
+
if (err) {
140
+
pr_err("Failed to apply FDT fixup \"%s\"\n",
141
+
fixups->description);
142
+
return err;
143
+
}
144
+
}
145
+
146
+
err = fdt_pack(fdt_out);
147
+
if (err)
148
+
pr_err("Failed to pack FDT\n");
149
+
return err;
150
+
}
151
+
125
152
void __init plat_time_init(void)
126
153
{
127
154
struct device_node *np;
+25
arch/mips/generic/vmlinux.its.S
+25
arch/mips/generic/vmlinux.its.S
···
29
29
};
30
30
};
31
31
};
32
+
33
+
#ifdef CONFIG_FIT_IMAGE_FDT_BOSTON
34
+
/ {
35
+
images {
36
+
fdt@boston {
37
+
description = "img,boston Device Tree";
38
+
data = /incbin/("boot/dts/img/boston.dtb");
39
+
type = "flat_dt";
40
+
arch = "mips";
41
+
compression = "none";
42
+
hash@0 {
43
+
algo = "sha1";
44
+
};
45
+
};
46
+
};
47
+
48
+
configurations {
49
+
conf@boston {
50
+
description = "Boston Linux kernel";
51
+
kernel = "kernel@0";
52
+
fdt = "fdt@boston";
53
+
};
54
+
};
55
+
};
56
+
#endif /* CONFIG_FIT_IMAGE_FDT_BOSTON */
+240
arch/mips/generic/yamon-dt.c
+240
arch/mips/generic/yamon-dt.c
···
1
+
/*
2
+
* Copyright (C) 2016 Imagination Technologies
3
+
* Author: Paul Burton <paul.burton@imgtec.com>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify it
6
+
* under the terms of the GNU General Public License as published by the
7
+
* Free Software Foundation; either version 2 of the License, or (at your
8
+
* option) any later version.
9
+
*/
10
+
11
+
#define pr_fmt(fmt) "yamon-dt: " fmt
12
+
13
+
#include <linux/bug.h>
14
+
#include <linux/errno.h>
15
+
#include <linux/kernel.h>
16
+
#include <linux/libfdt.h>
17
+
#include <linux/printk.h>
18
+
19
+
#include <asm/fw/fw.h>
20
+
#include <asm/yamon-dt.h>
21
+
22
+
#define MAX_MEM_ARRAY_ENTRIES 2
23
+
24
+
__init int yamon_dt_append_cmdline(void *fdt)
25
+
{
26
+
int err, chosen_off;
27
+
28
+
/* find or add chosen node */
29
+
chosen_off = fdt_path_offset(fdt, "/chosen");
30
+
if (chosen_off == -FDT_ERR_NOTFOUND)
31
+
chosen_off = fdt_path_offset(fdt, "/chosen@0");
32
+
if (chosen_off == -FDT_ERR_NOTFOUND)
33
+
chosen_off = fdt_add_subnode(fdt, 0, "chosen");
34
+
if (chosen_off < 0) {
35
+
pr_err("Unable to find or add DT chosen node: %d\n",
36
+
chosen_off);
37
+
return chosen_off;
38
+
}
39
+
40
+
err = fdt_setprop_string(fdt, chosen_off, "bootargs", fw_getcmdline());
41
+
if (err) {
42
+
pr_err("Unable to set bootargs property: %d\n", err);
43
+
return err;
44
+
}
45
+
46
+
return 0;
47
+
}
48
+
49
+
static unsigned int __init gen_fdt_mem_array(
50
+
const struct yamon_mem_region *regions,
51
+
__be32 *mem_array,
52
+
unsigned int max_entries,
53
+
unsigned long memsize)
54
+
{
55
+
const struct yamon_mem_region *mr;
56
+
unsigned long size;
57
+
unsigned int entries = 0;
58
+
59
+
for (mr = regions; mr->size && memsize; ++mr) {
60
+
if (entries >= max_entries) {
61
+
pr_warn("Number of regions exceeds max %u\n",
62
+
max_entries);
63
+
break;
64
+
}
65
+
66
+
/* How much of the remaining RAM fits in the next region? */
67
+
size = min_t(unsigned long, memsize, mr->size);
68
+
memsize -= size;
69
+
70
+
/* Emit a memory region */
71
+
*(mem_array++) = cpu_to_be32(mr->start);
72
+
*(mem_array++) = cpu_to_be32(size);
73
+
++entries;
74
+
75
+
/* Discard the next mr->discard bytes */
76
+
memsize -= min_t(unsigned long, memsize, mr->discard);
77
+
}
78
+
return entries;
79
+
}
80
+
81
+
__init int yamon_dt_append_memory(void *fdt,
82
+
const struct yamon_mem_region *regions)
83
+
{
84
+
unsigned long phys_memsize, memsize;
85
+
__be32 mem_array[2 * MAX_MEM_ARRAY_ENTRIES];
86
+
unsigned int mem_entries;
87
+
int i, err, mem_off;
88
+
char *var, param_name[10], *var_names[] = {
89
+
"ememsize", "memsize",
90
+
};
91
+
92
+
/* find memory size from the bootloader environment */
93
+
for (i = 0; i < ARRAY_SIZE(var_names); i++) {
94
+
var = fw_getenv(var_names[i]);
95
+
if (!var)
96
+
continue;
97
+
98
+
err = kstrtoul(var, 0, &phys_memsize);
99
+
if (!err)
100
+
break;
101
+
102
+
pr_warn("Failed to read the '%s' env variable '%s'\n",
103
+
var_names[i], var);
104
+
}
105
+
106
+
if (!phys_memsize) {
107
+
pr_warn("The bootloader didn't provide memsize: defaulting to 32MB\n");
108
+
phys_memsize = 32 << 20;
109
+
}
110
+
111
+
/* default to using all available RAM */
112
+
memsize = phys_memsize;
113
+
114
+
/* allow the user to override the usable memory */
115
+
for (i = 0; i < ARRAY_SIZE(var_names); i++) {
116
+
snprintf(param_name, sizeof(param_name), "%s=", var_names[i]);
117
+
var = strstr(arcs_cmdline, param_name);
118
+
if (!var)
119
+
continue;
120
+
121
+
memsize = memparse(var + strlen(param_name), NULL);
122
+
}
123
+
124
+
/* if the user says there's more RAM than we thought, believe them */
125
+
phys_memsize = max_t(unsigned long, phys_memsize, memsize);
126
+
127
+
/* find or add a memory node */
128
+
mem_off = fdt_path_offset(fdt, "/memory");
129
+
if (mem_off == -FDT_ERR_NOTFOUND)
130
+
mem_off = fdt_add_subnode(fdt, 0, "memory");
131
+
if (mem_off < 0) {
132
+
pr_err("Unable to find or add memory DT node: %d\n", mem_off);
133
+
return mem_off;
134
+
}
135
+
136
+
err = fdt_setprop_string(fdt, mem_off, "device_type", "memory");
137
+
if (err) {
138
+
pr_err("Unable to set memory node device_type: %d\n", err);
139
+
return err;
140
+
}
141
+
142
+
mem_entries = gen_fdt_mem_array(regions, mem_array,
143
+
MAX_MEM_ARRAY_ENTRIES, phys_memsize);
144
+
err = fdt_setprop(fdt, mem_off, "reg",
145
+
mem_array, mem_entries * 2 * sizeof(mem_array[0]));
146
+
if (err) {
147
+
pr_err("Unable to set memory regs property: %d\n", err);
148
+
return err;
149
+
}
150
+
151
+
mem_entries = gen_fdt_mem_array(regions, mem_array,
152
+
MAX_MEM_ARRAY_ENTRIES, memsize);
153
+
err = fdt_setprop(fdt, mem_off, "linux,usable-memory",
154
+
mem_array, mem_entries * 2 * sizeof(mem_array[0]));
155
+
if (err) {
156
+
pr_err("Unable to set linux,usable-memory property: %d\n", err);
157
+
return err;
158
+
}
159
+
160
+
return 0;
161
+
}
162
+
163
+
__init int yamon_dt_serial_config(void *fdt)
164
+
{
165
+
const char *yamontty, *mode_var;
166
+
char mode_var_name[9], path[20], parity;
167
+
unsigned int uart, baud, stop_bits;
168
+
bool hw_flow;
169
+
int chosen_off, err;
170
+
171
+
yamontty = fw_getenv("yamontty");
172
+
if (!yamontty || !strcmp(yamontty, "tty0")) {
173
+
uart = 0;
174
+
} else if (!strcmp(yamontty, "tty1")) {
175
+
uart = 1;
176
+
} else {
177
+
pr_warn("yamontty environment variable '%s' invalid\n",
178
+
yamontty);
179
+
uart = 0;
180
+
}
181
+
182
+
baud = stop_bits = 0;
183
+
parity = 0;
184
+
hw_flow = false;
185
+
186
+
snprintf(mode_var_name, sizeof(mode_var_name), "modetty%u", uart);
187
+
mode_var = fw_getenv(mode_var_name);
188
+
if (mode_var) {
189
+
while (mode_var[0] >= '0' && mode_var[0] <= '9') {
190
+
baud *= 10;
191
+
baud += mode_var[0] - '0';
192
+
mode_var++;
193
+
}
194
+
if (mode_var[0] == ',')
195
+
mode_var++;
196
+
if (mode_var[0])
197
+
parity = mode_var[0];
198
+
if (mode_var[0] == ',')
199
+
mode_var++;
200
+
if (mode_var[0])
201
+
stop_bits = mode_var[0] - '0';
202
+
if (mode_var[0] == ',')
203
+
mode_var++;
204
+
if (!strcmp(mode_var, "hw"))
205
+
hw_flow = true;
206
+
}
207
+
208
+
if (!baud)
209
+
baud = 38400;
210
+
211
+
if (parity != 'e' && parity != 'n' && parity != 'o')
212
+
parity = 'n';
213
+
214
+
if (stop_bits != 7 && stop_bits != 8)
215
+
stop_bits = 8;
216
+
217
+
WARN_ON(snprintf(path, sizeof(path), "serial%u:%u%c%u%s",
218
+
uart, baud, parity, stop_bits,
219
+
hw_flow ? "r" : "") >= sizeof(path));
220
+
221
+
/* find or add chosen node */
222
+
chosen_off = fdt_path_offset(fdt, "/chosen");
223
+
if (chosen_off == -FDT_ERR_NOTFOUND)
224
+
chosen_off = fdt_path_offset(fdt, "/chosen@0");
225
+
if (chosen_off == -FDT_ERR_NOTFOUND)
226
+
chosen_off = fdt_add_subnode(fdt, 0, "chosen");
227
+
if (chosen_off < 0) {
228
+
pr_err("Unable to find or add DT chosen node: %d\n",
229
+
chosen_off);
230
+
return chosen_off;
231
+
}
232
+
233
+
err = fdt_setprop_string(fdt, chosen_off, "stdout-path", path);
234
+
if (err) {
235
+
pr_err("Unable to set stdout-path property: %d\n", err);
236
+
return err;
237
+
}
238
+
239
+
return 0;
240
+
}
+2
arch/mips/include/asm/Kbuild
+2
arch/mips/include/asm/Kbuild
+1
-4
arch/mips/include/asm/branch.h
+1
-4
arch/mips/include/asm/branch.h
+124
-162
arch/mips/include/asm/cmpxchg.h
+124
-162
arch/mips/include/asm/cmpxchg.h
···
13
13
#include <asm/compiler.h>
14
14
#include <asm/war.h>
15
15
16
-
static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
17
-
{
18
-
__u32 retval;
19
-
20
-
smp_mb__before_llsc();
21
-
22
-
if (kernel_uses_llsc && R10000_LLSC_WAR) {
23
-
unsigned long dummy;
24
-
25
-
__asm__ __volatile__(
26
-
" .set arch=r4000 \n"
27
-
"1: ll %0, %3 # xchg_u32 \n"
28
-
" .set mips0 \n"
29
-
" move %2, %z4 \n"
30
-
" .set arch=r4000 \n"
31
-
" sc %2, %1 \n"
32
-
" beqzl %2, 1b \n"
33
-
" .set mips0 \n"
34
-
: "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)
35
-
: GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
36
-
: "memory");
37
-
} else if (kernel_uses_llsc) {
38
-
unsigned long dummy;
39
-
40
-
do {
41
-
__asm__ __volatile__(
42
-
" .set "MIPS_ISA_ARCH_LEVEL" \n"
43
-
" ll %0, %3 # xchg_u32 \n"
44
-
" .set mips0 \n"
45
-
" move %2, %z4 \n"
46
-
" .set "MIPS_ISA_ARCH_LEVEL" \n"
47
-
" sc %2, %1 \n"
48
-
" .set mips0 \n"
49
-
: "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),
50
-
"=&r" (dummy)
51
-
: GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
52
-
: "memory");
53
-
} while (unlikely(!dummy));
54
-
} else {
55
-
unsigned long flags;
56
-
57
-
raw_local_irq_save(flags);
58
-
retval = *m;
59
-
*m = val;
60
-
raw_local_irq_restore(flags); /* implies memory barrier */
61
-
}
62
-
63
-
smp_llsc_mb();
64
-
65
-
return retval;
66
-
}
67
-
68
-
#ifdef CONFIG_64BIT
69
-
static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
70
-
{
71
-
__u64 retval;
72
-
73
-
smp_mb__before_llsc();
74
-
75
-
if (kernel_uses_llsc && R10000_LLSC_WAR) {
76
-
unsigned long dummy;
77
-
78
-
__asm__ __volatile__(
79
-
" .set arch=r4000 \n"
80
-
"1: lld %0, %3 # xchg_u64 \n"
81
-
" move %2, %z4 \n"
82
-
" scd %2, %1 \n"
83
-
" beqzl %2, 1b \n"
84
-
" .set mips0 \n"
85
-
: "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)
86
-
: GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
87
-
: "memory");
88
-
} else if (kernel_uses_llsc) {
89
-
unsigned long dummy;
90
-
91
-
do {
92
-
__asm__ __volatile__(
93
-
" .set "MIPS_ISA_ARCH_LEVEL" \n"
94
-
" lld %0, %3 # xchg_u64 \n"
95
-
" move %2, %z4 \n"
96
-
" scd %2, %1 \n"
97
-
" .set mips0 \n"
98
-
: "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),
99
-
"=&r" (dummy)
100
-
: GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
101
-
: "memory");
102
-
} while (unlikely(!dummy));
103
-
} else {
104
-
unsigned long flags;
105
-
106
-
raw_local_irq_save(flags);
107
-
retval = *m;
108
-
*m = val;
109
-
raw_local_irq_restore(flags); /* implies memory barrier */
110
-
}
111
-
112
-
smp_llsc_mb();
113
-
114
-
return retval;
115
-
}
16
+
/*
17
+
* Using a branch-likely instruction to check the result of an sc instruction
18
+
* works around a bug present in R10000 CPUs prior to revision 3.0 that could
19
+
* cause ll-sc sequences to execute non-atomically.
20
+
*/
21
+
#if R10000_LLSC_WAR
22
+
# define __scbeqz "beqzl"
116
23
#else
117
-
extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
118
-
#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
24
+
# define __scbeqz "beqz"
119
25
#endif
120
26
121
-
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
27
+
/*
28
+
* These functions doesn't exist, so if they are called you'll either:
29
+
*
30
+
* - Get an error at compile-time due to __compiletime_error, if supported by
31
+
* your compiler.
32
+
*
33
+
* or:
34
+
*
35
+
* - Get an error at link-time due to the call to the missing function.
36
+
*/
37
+
extern unsigned long __cmpxchg_called_with_bad_pointer(void)
38
+
__compiletime_error("Bad argument size for cmpxchg");
39
+
extern unsigned long __xchg_called_with_bad_pointer(void)
40
+
__compiletime_error("Bad argument size for xchg");
41
+
42
+
#define __xchg_asm(ld, st, m, val) \
43
+
({ \
44
+
__typeof(*(m)) __ret; \
45
+
\
46
+
if (kernel_uses_llsc) { \
47
+
__asm__ __volatile__( \
48
+
" .set push \n" \
49
+
" .set noat \n" \
50
+
" .set " MIPS_ISA_ARCH_LEVEL " \n" \
51
+
"1: " ld " %0, %2 # __xchg_asm \n" \
52
+
" .set mips0 \n" \
53
+
" move $1, %z3 \n" \
54
+
" .set " MIPS_ISA_ARCH_LEVEL " \n" \
55
+
" " st " $1, %1 \n" \
56
+
"\t" __scbeqz " $1, 1b \n" \
57
+
" .set pop \n" \
58
+
: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
59
+
: GCC_OFF_SMALL_ASM() (*m), "Jr" (val) \
60
+
: "memory"); \
61
+
} else { \
62
+
unsigned long __flags; \
63
+
\
64
+
raw_local_irq_save(__flags); \
65
+
__ret = *m; \
66
+
*m = val; \
67
+
raw_local_irq_restore(__flags); \
68
+
} \
69
+
\
70
+
__ret; \
71
+
})
72
+
73
+
extern unsigned long __xchg_small(volatile void *ptr, unsigned long val,
74
+
unsigned int size);
75
+
76
+
static inline unsigned long __xchg(volatile void *ptr, unsigned long x,
77
+
int size)
122
78
{
123
79
switch (size) {
124
-
case 4:
125
-
return __xchg_u32(ptr, x);
126
-
case 8:
127
-
return __xchg_u64(ptr, x);
128
-
}
80
+
case 1:
81
+
case 2:
82
+
return __xchg_small(ptr, x, size);
129
83
130
-
return x;
84
+
case 4:
85
+
return __xchg_asm("ll", "sc", (volatile u32 *)ptr, x);
86
+
87
+
case 8:
88
+
if (!IS_ENABLED(CONFIG_64BIT))
89
+
return __xchg_called_with_bad_pointer();
90
+
91
+
return __xchg_asm("lld", "scd", (volatile u64 *)ptr, x);
92
+
93
+
default:
94
+
return __xchg_called_with_bad_pointer();
95
+
}
131
96
}
132
97
133
98
#define xchg(ptr, x) \
134
99
({ \
135
-
BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
100
+
__typeof__(*(ptr)) __res; \
136
101
\
137
-
((__typeof__(*(ptr))) \
138
-
__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
102
+
smp_mb__before_llsc(); \
103
+
\
104
+
__res = (__typeof__(*(ptr))) \
105
+
__xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \
106
+
\
107
+
smp_llsc_mb(); \
108
+
\
109
+
__res; \
139
110
})
140
111
141
112
#define __cmpxchg_asm(ld, st, m, old, new) \
142
113
({ \
143
114
__typeof(*(m)) __ret; \
144
115
\
145
-
if (kernel_uses_llsc && R10000_LLSC_WAR) { \
146
-
__asm__ __volatile__( \
147
-
" .set push \n" \
148
-
" .set noat \n" \
149
-
" .set arch=r4000 \n" \
150
-
"1: " ld " %0, %2 # __cmpxchg_asm \n" \
151
-
" bne %0, %z3, 2f \n" \
152
-
" .set mips0 \n" \
153
-
" move $1, %z4 \n" \
154
-
" .set arch=r4000 \n" \
155
-
" " st " $1, %1 \n" \
156
-
" beqzl $1, 1b \n" \
157
-
"2: \n" \
158
-
" .set pop \n" \
159
-
: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
160
-
: GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
161
-
: "memory"); \
162
-
} else if (kernel_uses_llsc) { \
116
+
if (kernel_uses_llsc) { \
163
117
__asm__ __volatile__( \
164
118
" .set push \n" \
165
119
" .set noat \n" \
···
124
170
" move $1, %z4 \n" \
125
171
" .set "MIPS_ISA_ARCH_LEVEL" \n" \
126
172
" " st " $1, %1 \n" \
127
-
" beqz $1, 1b \n" \
173
+
"\t" __scbeqz " $1, 1b \n" \
128
174
" .set pop \n" \
129
175
"2: \n" \
130
176
: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
···
143
189
__ret; \
144
190
})
145
191
146
-
/*
147
-
* This function doesn't exist, so you'll get a linker error
148
-
* if something tries to do an invalid cmpxchg().
149
-
*/
150
-
extern void __cmpxchg_called_with_bad_pointer(void);
192
+
extern unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old,
193
+
unsigned long new, unsigned int size);
151
194
152
-
#define __cmpxchg(ptr, old, new, pre_barrier, post_barrier) \
195
+
static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
196
+
unsigned long new, unsigned int size)
197
+
{
198
+
switch (size) {
199
+
case 1:
200
+
case 2:
201
+
return __cmpxchg_small(ptr, old, new, size);
202
+
203
+
case 4:
204
+
return __cmpxchg_asm("ll", "sc", (volatile u32 *)ptr, old, new);
205
+
206
+
case 8:
207
+
/* lld/scd are only available for MIPS64 */
208
+
if (!IS_ENABLED(CONFIG_64BIT))
209
+
return __cmpxchg_called_with_bad_pointer();
210
+
211
+
return __cmpxchg_asm("lld", "scd", (volatile u64 *)ptr, old, new);
212
+
213
+
default:
214
+
return __cmpxchg_called_with_bad_pointer();
215
+
}
216
+
}
217
+
218
+
#define cmpxchg_local(ptr, old, new) \
219
+
((__typeof__(*(ptr))) \
220
+
__cmpxchg((ptr), \
221
+
(unsigned long)(__typeof__(*(ptr)))(old), \
222
+
(unsigned long)(__typeof__(*(ptr)))(new), \
223
+
sizeof(*(ptr))))
224
+
225
+
#define cmpxchg(ptr, old, new) \
153
226
({ \
154
-
__typeof__(ptr) __ptr = (ptr); \
155
-
__typeof__(*(ptr)) __old = (old); \
156
-
__typeof__(*(ptr)) __new = (new); \
157
-
__typeof__(*(ptr)) __res = 0; \
227
+
__typeof__(*(ptr)) __res; \
158
228
\
159
-
pre_barrier; \
160
-
\
161
-
switch (sizeof(*(__ptr))) { \
162
-
case 4: \
163
-
__res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \
164
-
break; \
165
-
case 8: \
166
-
if (sizeof(long) == 8) { \
167
-
__res = __cmpxchg_asm("lld", "scd", __ptr, \
168
-
__old, __new); \
169
-
break; \
170
-
} \
171
-
default: \
172
-
__cmpxchg_called_with_bad_pointer(); \
173
-
break; \
174
-
} \
175
-
\
176
-
post_barrier; \
229
+
smp_mb__before_llsc(); \
230
+
__res = cmpxchg_local((ptr), (old), (new)); \
231
+
smp_llsc_mb(); \
177
232
\
178
233
__res; \
179
234
})
180
-
181
-
#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb())
182
-
#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, , )
183
235
184
236
#ifdef CONFIG_64BIT
185
237
#define cmpxchg64_local(ptr, o, n) \
···
204
244
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
205
245
#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
206
246
#endif
247
+
248
+
#undef __scbeqz
207
249
208
250
#endif /* __ASM_CMPXCHG_H */
+44
arch/mips/include/asm/cpu-features.h
+44
arch/mips/include/asm/cpu-features.h
···
138
138
#ifndef cpu_has_mips16
139
139
#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
140
140
#endif
141
+
#ifndef cpu_has_mips16e2
142
+
#define cpu_has_mips16e2 (cpu_data[0].ases & MIPS_ASE_MIPS16E2)
143
+
#endif
141
144
#ifndef cpu_has_mdmx
142
145
#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
143
146
#endif
···
488
485
489
486
#ifndef cpu_has_perf
490
487
# define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF)
488
+
#endif
489
+
490
+
#if defined(CONFIG_SMP) && defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
491
+
/*
492
+
* Some systems share FTLB RAMs between threads within a core (siblings in
493
+
* kernel parlance). This means that FTLB entries may become invalid at almost
494
+
* any point when an entry is evicted due to a sibling thread writing an entry
495
+
* to the shared FTLB RAM.
496
+
*
497
+
* This is only relevant to SMP systems, and the only systems that exhibit this
498
+
* property implement MIPSr6 or higher so we constrain support for this to
499
+
* kernels that will run on such systems.
500
+
*/
501
+
# ifndef cpu_has_shared_ftlb_ram
502
+
# define cpu_has_shared_ftlb_ram \
503
+
(current_cpu_data.options & MIPS_CPU_SHARED_FTLB_RAM)
504
+
# endif
505
+
506
+
/*
507
+
* Some systems take this a step further & share FTLB entries between siblings.
508
+
* This is implemented as TLB writes happening as usual, but if an entry
509
+
* written by a sibling exists in the shared FTLB for a translation which would
510
+
* otherwise cause a TLB refill exception then the CPU will use the entry
511
+
* written by its sibling rather than triggering a refill & writing a matching
512
+
* TLB entry for itself.
513
+
*
514
+
* This is naturally only valid if a TLB entry is known to be suitable for use
515
+
* on all siblings in a CPU, and so it only takes effect when MMIDs are in use
516
+
* rather than ASIDs or when a TLB entry is marked global.
517
+
*/
518
+
# ifndef cpu_has_shared_ftlb_entries
519
+
# define cpu_has_shared_ftlb_entries \
520
+
(current_cpu_data.options & MIPS_CPU_SHARED_FTLB_ENTRIES)
521
+
# endif
522
+
#endif /* SMP && __mips_isa_rev >= 6 */
523
+
524
+
#ifndef cpu_has_shared_ftlb_ram
525
+
# define cpu_has_shared_ftlb_ram 0
526
+
#endif
527
+
#ifndef cpu_has_shared_ftlb_entries
528
+
# define cpu_has_shared_ftlb_entries 0
491
529
#endif
492
530
493
531
/*
+1
arch/mips/include/asm/cpu-type.h
+1
arch/mips/include/asm/cpu-type.h
+8
-1
arch/mips/include/asm/cpu.h
+8
-1
arch/mips/include/asm/cpu.h
···
124
124
#define PRID_IMP_P5600 0xa800
125
125
#define PRID_IMP_I6400 0xa900
126
126
#define PRID_IMP_M6250 0xab00
127
+
#define PRID_IMP_I6500 0xb000
127
128
128
129
/*
129
130
* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
···
248
247
#define PRID_REV_LOONGSON3B_R1 0x0006
249
248
#define PRID_REV_LOONGSON3B_R2 0x0007
250
249
#define PRID_REV_LOONGSON3A_R2 0x0008
250
+
#define PRID_REV_LOONGSON3A_R3 0x0009
251
251
252
252
/*
253
253
* Older processors used to encode processor version and revision in two
···
324
322
*/
325
323
CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
326
324
CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
327
-
CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
325
+
CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,
328
326
329
327
CPU_QEMU_GENERIC,
330
328
···
418
416
#define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
419
417
#define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
420
418
#define MIPS_CPU_UFR MBIT_ULL(53) /* CPU supports User mode FR switching */
419
+
#define MIPS_CPU_SHARED_FTLB_RAM \
420
+
MBIT_ULL(54) /* CPU shares FTLB RAM with another */
421
+
#define MIPS_CPU_SHARED_FTLB_ENTRIES \
422
+
MBIT_ULL(55) /* CPU shares FTLB entries with another */
421
423
422
424
/*
423
425
* CPU ASE encodings
···
436
430
#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
437
431
#define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */
438
432
#define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/
433
+
#define MIPS_ASE_MIPS16E2 0x00000400 /* MIPS16e2 */
439
434
440
435
#endif /* _ASM_CPU_H */
+1
-1
arch/mips/include/asm/irq.h
+1
-1
arch/mips/include/asm/irq.h
+1
arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
+1
-1
arch/mips/include/asm/mach-generic/mc146818rtc.h
+1
-1
arch/mips/include/asm/mach-generic/mc146818rtc.h
+1
arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
+16
-6
arch/mips/include/asm/mach-loongson64/boot_param.h
+16
-6
arch/mips/include/asm/mach-loongson64/boot_param.h
···
27
27
} __packed;
28
28
29
29
enum loongson_cpu_type {
30
-
Loongson_2E = 0,
31
-
Loongson_2F = 1,
32
-
Loongson_3A = 2,
33
-
Loongson_3B = 3,
34
-
Loongson_1A = 4,
35
-
Loongson_1B = 5
30
+
Legacy_2E = 0x0,
31
+
Legacy_2F = 0x1,
32
+
Legacy_3A = 0x2,
33
+
Legacy_3B = 0x3,
34
+
Legacy_1A = 0x4,
35
+
Legacy_1B = 0x5,
36
+
Legacy_2G = 0x6,
37
+
Legacy_2H = 0x7,
38
+
Loongson_1A = 0x100,
39
+
Loongson_1B = 0x101,
40
+
Loongson_2E = 0x200,
41
+
Loongson_2F = 0x201,
42
+
Loongson_2G = 0x202,
43
+
Loongson_2H = 0x203,
44
+
Loongson_3A = 0x300,
45
+
Loongson_3B = 0x301
36
46
};
37
47
38
48
/*
+1
arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
+1
arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
+31
arch/mips/include/asm/machine.h
+31
arch/mips/include/asm/machine.h
···
60
60
return NULL;
61
61
}
62
62
63
+
/**
64
+
* struct mips_fdt_fixup - Describe a fixup to apply to an FDT
65
+
* @apply: applies the fixup to @fdt, returns zero on success else -errno
66
+
* @description: a short description of the fixup
67
+
*
68
+
* Describes a fixup applied to an FDT blob by the @apply function. The
69
+
* @description field provides a short description of the fixup intended for
70
+
* use in error messages if the @apply function returns non-zero.
71
+
*/
72
+
struct mips_fdt_fixup {
73
+
int (*apply)(void *fdt);
74
+
const char *description;
75
+
};
76
+
77
+
/**
78
+
* apply_mips_fdt_fixups() - apply fixups to an FDT blob
79
+
* @fdt_out: buffer in which to place the fixed-up FDT
80
+
* @fdt_out_size: the size of the @fdt_out buffer
81
+
* @fdt_in: the FDT blob
82
+
* @fixups: pointer to an array of fixups to be applied
83
+
*
84
+
* Loop through the array of fixups pointed to by @fixups, calling the apply
85
+
* function on each until either one returns an error or we reach the end of
86
+
* the list as indicated by an entry with a NULL apply field.
87
+
*
88
+
* Return: zero on success, else -errno
89
+
*/
90
+
extern int __init apply_mips_fdt_fixups(void *fdt_out, size_t fdt_out_size,
91
+
const void *fdt_in,
92
+
const struct mips_fdt_fixup *fixups);
93
+
63
94
#endif /* __MIPS_ASM_MACHINE_H__ */
+1
arch/mips/include/asm/mipsregs.h
+1
arch/mips/include/asm/mipsregs.h
···
652
652
#define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
653
653
#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
654
654
#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
655
+
#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
655
656
#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
656
657
#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
657
658
#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
+4
-4
arch/mips/include/asm/module.h
+4
-4
arch/mips/include/asm/module.h
···
47
47
#define Elf_Mips_Rel Elf32_Rel
48
48
#define Elf_Mips_Rela Elf32_Rela
49
49
50
-
#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM(rel.r_info)
51
-
#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE(rel.r_info)
50
+
#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM((rel).r_info)
51
+
#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE((rel).r_info)
52
52
53
53
#endif
54
54
···
65
65
#define Elf_Mips_Rel Elf64_Mips_Rel
66
66
#define Elf_Mips_Rela Elf64_Mips_Rela
67
67
68
-
#define ELF_MIPS_R_SYM(rel) (rel.r_sym)
69
-
#define ELF_MIPS_R_TYPE(rel) (rel.r_type)
68
+
#define ELF_MIPS_R_SYM(rel) ((rel).r_sym)
69
+
#define ELF_MIPS_R_TYPE(rel) ((rel).r_type)
70
70
71
71
#endif
72
72
+2
-424
arch/mips/include/asm/spinlock.h
+2
-424
arch/mips/include/asm/spinlock.h
···
9
9
#ifndef _ASM_SPINLOCK_H
10
10
#define _ASM_SPINLOCK_H
11
11
12
-
#include <linux/compiler.h>
13
-
14
-
#include <asm/barrier.h>
15
12
#include <asm/processor.h>
16
-
#include <asm/compiler.h>
17
-
#include <asm/war.h>
18
-
19
-
/*
20
-
* Your basic SMP spinlocks, allowing only a single CPU anywhere
21
-
*
22
-
* Simple spin lock operations. There are two variants, one clears IRQ's
23
-
* on the local processor, one does not.
24
-
*
25
-
* These are fair FIFO ticket locks
26
-
*
27
-
* (the type definitions are in asm/spinlock_types.h)
28
-
*/
29
-
30
-
31
-
/*
32
-
* Ticket locks are conceptually two parts, one indicating the current head of
33
-
* the queue, and the other indicating the current tail. The lock is acquired
34
-
* by atomically noting the tail and incrementing it by one (thus adding
35
-
* ourself to the queue and noting our position), then waiting until the head
36
-
* becomes equal to the the initial value of the tail.
37
-
*/
38
-
39
-
static inline int arch_spin_is_locked(arch_spinlock_t *lock)
40
-
{
41
-
u32 counters = ACCESS_ONCE(lock->lock);
42
-
43
-
return ((counters >> 16) ^ counters) & 0xffff;
44
-
}
45
-
46
-
static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
47
-
{
48
-
return lock.h.serving_now == lock.h.ticket;
49
-
}
50
-
51
-
#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
52
-
53
-
static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
54
-
{
55
-
u16 owner = READ_ONCE(lock->h.serving_now);
56
-
smp_rmb();
57
-
for (;;) {
58
-
arch_spinlock_t tmp = READ_ONCE(*lock);
59
-
60
-
if (tmp.h.serving_now == tmp.h.ticket ||
61
-
tmp.h.serving_now != owner)
62
-
break;
63
-
64
-
cpu_relax();
65
-
}
66
-
smp_acquire__after_ctrl_dep();
67
-
}
68
-
69
-
static inline int arch_spin_is_contended(arch_spinlock_t *lock)
70
-
{
71
-
u32 counters = ACCESS_ONCE(lock->lock);
72
-
73
-
return (((counters >> 16) - counters) & 0xffff) > 1;
74
-
}
75
-
#define arch_spin_is_contended arch_spin_is_contended
76
-
77
-
static inline void arch_spin_lock(arch_spinlock_t *lock)
78
-
{
79
-
int my_ticket;
80
-
int tmp;
81
-
int inc = 0x10000;
82
-
83
-
if (R10000_LLSC_WAR) {
84
-
__asm__ __volatile__ (
85
-
" .set push # arch_spin_lock \n"
86
-
" .set noreorder \n"
87
-
" \n"
88
-
"1: ll %[ticket], %[ticket_ptr] \n"
89
-
" addu %[my_ticket], %[ticket], %[inc] \n"
90
-
" sc %[my_ticket], %[ticket_ptr] \n"
91
-
" beqzl %[my_ticket], 1b \n"
92
-
" nop \n"
93
-
" srl %[my_ticket], %[ticket], 16 \n"
94
-
" andi %[ticket], %[ticket], 0xffff \n"
95
-
" bne %[ticket], %[my_ticket], 4f \n"
96
-
" subu %[ticket], %[my_ticket], %[ticket] \n"
97
-
"2: \n"
98
-
" .subsection 2 \n"
99
-
"4: andi %[ticket], %[ticket], 0xffff \n"
100
-
" sll %[ticket], 5 \n"
101
-
" \n"
102
-
"6: bnez %[ticket], 6b \n"
103
-
" subu %[ticket], 1 \n"
104
-
" \n"
105
-
" lhu %[ticket], %[serving_now_ptr] \n"
106
-
" beq %[ticket], %[my_ticket], 2b \n"
107
-
" subu %[ticket], %[my_ticket], %[ticket] \n"
108
-
" b 4b \n"
109
-
" subu %[ticket], %[ticket], 1 \n"
110
-
" .previous \n"
111
-
" .set pop \n"
112
-
: [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
113
-
[serving_now_ptr] "+m" (lock->h.serving_now),
114
-
[ticket] "=&r" (tmp),
115
-
[my_ticket] "=&r" (my_ticket)
116
-
: [inc] "r" (inc));
117
-
} else {
118
-
__asm__ __volatile__ (
119
-
" .set push # arch_spin_lock \n"
120
-
" .set noreorder \n"
121
-
" \n"
122
-
"1: ll %[ticket], %[ticket_ptr] \n"
123
-
" addu %[my_ticket], %[ticket], %[inc] \n"
124
-
" sc %[my_ticket], %[ticket_ptr] \n"
125
-
" beqz %[my_ticket], 1b \n"
126
-
" srl %[my_ticket], %[ticket], 16 \n"
127
-
" andi %[ticket], %[ticket], 0xffff \n"
128
-
" bne %[ticket], %[my_ticket], 4f \n"
129
-
" subu %[ticket], %[my_ticket], %[ticket] \n"
130
-
"2: .insn \n"
131
-
" .subsection 2 \n"
132
-
"4: andi %[ticket], %[ticket], 0xffff \n"
133
-
" sll %[ticket], 5 \n"
134
-
" \n"
135
-
"6: bnez %[ticket], 6b \n"
136
-
" subu %[ticket], 1 \n"
137
-
" \n"
138
-
" lhu %[ticket], %[serving_now_ptr] \n"
139
-
" beq %[ticket], %[my_ticket], 2b \n"
140
-
" subu %[ticket], %[my_ticket], %[ticket] \n"
141
-
" b 4b \n"
142
-
" subu %[ticket], %[ticket], 1 \n"
143
-
" .previous \n"
144
-
" .set pop \n"
145
-
: [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
146
-
[serving_now_ptr] "+m" (lock->h.serving_now),
147
-
[ticket] "=&r" (tmp),
148
-
[my_ticket] "=&r" (my_ticket)
149
-
: [inc] "r" (inc));
150
-
}
151
-
152
-
smp_llsc_mb();
153
-
}
154
-
155
-
static inline void arch_spin_unlock(arch_spinlock_t *lock)
156
-
{
157
-
unsigned int serving_now = lock->h.serving_now + 1;
158
-
wmb();
159
-
lock->h.serving_now = (u16)serving_now;
160
-
nudge_writes();
161
-
}
162
-
163
-
static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
164
-
{
165
-
int tmp, tmp2, tmp3;
166
-
int inc = 0x10000;
167
-
168
-
if (R10000_LLSC_WAR) {
169
-
__asm__ __volatile__ (
170
-
" .set push # arch_spin_trylock \n"
171
-
" .set noreorder \n"
172
-
" \n"
173
-
"1: ll %[ticket], %[ticket_ptr] \n"
174
-
" srl %[my_ticket], %[ticket], 16 \n"
175
-
" andi %[now_serving], %[ticket], 0xffff \n"
176
-
" bne %[my_ticket], %[now_serving], 3f \n"
177
-
" addu %[ticket], %[ticket], %[inc] \n"
178
-
" sc %[ticket], %[ticket_ptr] \n"
179
-
" beqzl %[ticket], 1b \n"
180
-
" li %[ticket], 1 \n"
181
-
"2: \n"
182
-
" .subsection 2 \n"
183
-
"3: b 2b \n"
184
-
" li %[ticket], 0 \n"
185
-
" .previous \n"
186
-
" .set pop \n"
187
-
: [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
188
-
[ticket] "=&r" (tmp),
189
-
[my_ticket] "=&r" (tmp2),
190
-
[now_serving] "=&r" (tmp3)
191
-
: [inc] "r" (inc));
192
-
} else {
193
-
__asm__ __volatile__ (
194
-
" .set push # arch_spin_trylock \n"
195
-
" .set noreorder \n"
196
-
" \n"
197
-
"1: ll %[ticket], %[ticket_ptr] \n"
198
-
" srl %[my_ticket], %[ticket], 16 \n"
199
-
" andi %[now_serving], %[ticket], 0xffff \n"
200
-
" bne %[my_ticket], %[now_serving], 3f \n"
201
-
" addu %[ticket], %[ticket], %[inc] \n"
202
-
" sc %[ticket], %[ticket_ptr] \n"
203
-
" beqz %[ticket], 1b \n"
204
-
" li %[ticket], 1 \n"
205
-
"2: .insn \n"
206
-
" .subsection 2 \n"
207
-
"3: b 2b \n"
208
-
" li %[ticket], 0 \n"
209
-
" .previous \n"
210
-
" .set pop \n"
211
-
: [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
212
-
[ticket] "=&r" (tmp),
213
-
[my_ticket] "=&r" (tmp2),
214
-
[now_serving] "=&r" (tmp3)
215
-
: [inc] "r" (inc));
216
-
}
217
-
218
-
smp_llsc_mb();
219
-
220
-
return tmp;
221
-
}
222
-
223
-
/*
224
-
* Read-write spinlocks, allowing multiple readers but only one writer.
225
-
*
226
-
* NOTE! it is quite common to have readers in interrupts but no interrupt
227
-
* writers. For those circumstances we can "mix" irq-safe locks - any writer
228
-
* needs to get a irq-safe write-lock, but readers can get non-irqsafe
229
-
* read-locks.
230
-
*/
231
-
232
-
/*
233
-
* read_can_lock - would read_trylock() succeed?
234
-
* @lock: the rwlock in question.
235
-
*/
236
-
#define arch_read_can_lock(rw) ((rw)->lock >= 0)
237
-
238
-
/*
239
-
* write_can_lock - would write_trylock() succeed?
240
-
* @lock: the rwlock in question.
241
-
*/
242
-
#define arch_write_can_lock(rw) (!(rw)->lock)
243
-
244
-
static inline void arch_read_lock(arch_rwlock_t *rw)
245
-
{
246
-
unsigned int tmp;
247
-
248
-
if (R10000_LLSC_WAR) {
249
-
__asm__ __volatile__(
250
-
" .set noreorder # arch_read_lock \n"
251
-
"1: ll %1, %2 \n"
252
-
" bltz %1, 1b \n"
253
-
" addu %1, 1 \n"
254
-
" sc %1, %0 \n"
255
-
" beqzl %1, 1b \n"
256
-
" nop \n"
257
-
" .set reorder \n"
258
-
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
259
-
: GCC_OFF_SMALL_ASM() (rw->lock)
260
-
: "memory");
261
-
} else {
262
-
do {
263
-
__asm__ __volatile__(
264
-
"1: ll %1, %2 # arch_read_lock \n"
265
-
" bltz %1, 1b \n"
266
-
" addu %1, 1 \n"
267
-
"2: sc %1, %0 \n"
268
-
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
269
-
: GCC_OFF_SMALL_ASM() (rw->lock)
270
-
: "memory");
271
-
} while (unlikely(!tmp));
272
-
}
273
-
274
-
smp_llsc_mb();
275
-
}
276
-
277
-
static inline void arch_read_unlock(arch_rwlock_t *rw)
278
-
{
279
-
unsigned int tmp;
280
-
281
-
smp_mb__before_llsc();
282
-
283
-
if (R10000_LLSC_WAR) {
284
-
__asm__ __volatile__(
285
-
"1: ll %1, %2 # arch_read_unlock \n"
286
-
" addiu %1, -1 \n"
287
-
" sc %1, %0 \n"
288
-
" beqzl %1, 1b \n"
289
-
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
290
-
: GCC_OFF_SMALL_ASM() (rw->lock)
291
-
: "memory");
292
-
} else {
293
-
do {
294
-
__asm__ __volatile__(
295
-
"1: ll %1, %2 # arch_read_unlock \n"
296
-
" addiu %1, -1 \n"
297
-
" sc %1, %0 \n"
298
-
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
299
-
: GCC_OFF_SMALL_ASM() (rw->lock)
300
-
: "memory");
301
-
} while (unlikely(!tmp));
302
-
}
303
-
}
304
-
305
-
static inline void arch_write_lock(arch_rwlock_t *rw)
306
-
{
307
-
unsigned int tmp;
308
-
309
-
if (R10000_LLSC_WAR) {
310
-
__asm__ __volatile__(
311
-
" .set noreorder # arch_write_lock \n"
312
-
"1: ll %1, %2 \n"
313
-
" bnez %1, 1b \n"
314
-
" lui %1, 0x8000 \n"
315
-
" sc %1, %0 \n"
316
-
" beqzl %1, 1b \n"
317
-
" nop \n"
318
-
" .set reorder \n"
319
-
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
320
-
: GCC_OFF_SMALL_ASM() (rw->lock)
321
-
: "memory");
322
-
} else {
323
-
do {
324
-
__asm__ __volatile__(
325
-
"1: ll %1, %2 # arch_write_lock \n"
326
-
" bnez %1, 1b \n"
327
-
" lui %1, 0x8000 \n"
328
-
"2: sc %1, %0 \n"
329
-
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
330
-
: GCC_OFF_SMALL_ASM() (rw->lock)
331
-
: "memory");
332
-
} while (unlikely(!tmp));
333
-
}
334
-
335
-
smp_llsc_mb();
336
-
}
337
-
338
-
static inline void arch_write_unlock(arch_rwlock_t *rw)
339
-
{
340
-
smp_mb__before_llsc();
341
-
342
-
__asm__ __volatile__(
343
-
" # arch_write_unlock \n"
344
-
" sw $0, %0 \n"
345
-
: "=m" (rw->lock)
346
-
: "m" (rw->lock)
347
-
: "memory");
348
-
}
349
-
350
-
static inline int arch_read_trylock(arch_rwlock_t *rw)
351
-
{
352
-
unsigned int tmp;
353
-
int ret;
354
-
355
-
if (R10000_LLSC_WAR) {
356
-
__asm__ __volatile__(
357
-
" .set noreorder # arch_read_trylock \n"
358
-
" li %2, 0 \n"
359
-
"1: ll %1, %3 \n"
360
-
" bltz %1, 2f \n"
361
-
" addu %1, 1 \n"
362
-
" sc %1, %0 \n"
363
-
" .set reorder \n"
364
-
" beqzl %1, 1b \n"
365
-
" nop \n"
366
-
__WEAK_LLSC_MB
367
-
" li %2, 1 \n"
368
-
"2: \n"
369
-
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
370
-
: GCC_OFF_SMALL_ASM() (rw->lock)
371
-
: "memory");
372
-
} else {
373
-
__asm__ __volatile__(
374
-
" .set noreorder # arch_read_trylock \n"
375
-
" li %2, 0 \n"
376
-
"1: ll %1, %3 \n"
377
-
" bltz %1, 2f \n"
378
-
" addu %1, 1 \n"
379
-
" sc %1, %0 \n"
380
-
" beqz %1, 1b \n"
381
-
" nop \n"
382
-
" .set reorder \n"
383
-
__WEAK_LLSC_MB
384
-
" li %2, 1 \n"
385
-
"2: .insn \n"
386
-
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
387
-
: GCC_OFF_SMALL_ASM() (rw->lock)
388
-
: "memory");
389
-
}
390
-
391
-
return ret;
392
-
}
393
-
394
-
static inline int arch_write_trylock(arch_rwlock_t *rw)
395
-
{
396
-
unsigned int tmp;
397
-
int ret;
398
-
399
-
if (R10000_LLSC_WAR) {
400
-
__asm__ __volatile__(
401
-
" .set noreorder # arch_write_trylock \n"
402
-
" li %2, 0 \n"
403
-
"1: ll %1, %3 \n"
404
-
" bnez %1, 2f \n"
405
-
" lui %1, 0x8000 \n"
406
-
" sc %1, %0 \n"
407
-
" beqzl %1, 1b \n"
408
-
" nop \n"
409
-
__WEAK_LLSC_MB
410
-
" li %2, 1 \n"
411
-
" .set reorder \n"
412
-
"2: \n"
413
-
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
414
-
: GCC_OFF_SMALL_ASM() (rw->lock)
415
-
: "memory");
416
-
} else {
417
-
do {
418
-
__asm__ __volatile__(
419
-
" ll %1, %3 # arch_write_trylock \n"
420
-
" li %2, 0 \n"
421
-
" bnez %1, 2f \n"
422
-
" lui %1, 0x8000 \n"
423
-
" sc %1, %0 \n"
424
-
" li %2, 1 \n"
425
-
"2: .insn \n"
426
-
: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp),
427
-
"=&r" (ret)
428
-
: GCC_OFF_SMALL_ASM() (rw->lock)
429
-
: "memory");
430
-
} while (unlikely(!tmp));
431
-
432
-
smp_llsc_mb();
433
-
}
434
-
435
-
return ret;
436
-
}
13
+
#include <asm/qrwlock.h>
14
+
#include <asm/qspinlock.h>
437
15
438
16
#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
439
17
#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+2
-32
arch/mips/include/asm/spinlock_types.h
+2
-32
arch/mips/include/asm/spinlock_types.h
···
1
1
#ifndef _ASM_SPINLOCK_TYPES_H
2
2
#define _ASM_SPINLOCK_TYPES_H
3
3
4
-
#ifndef __LINUX_SPINLOCK_TYPES_H
5
-
# error "please don't include this file directly"
6
-
#endif
7
-
8
-
#include <linux/types.h>
9
-
10
-
#include <asm/byteorder.h>
11
-
12
-
typedef union {
13
-
/*
14
-
* bits 0..15 : serving_now
15
-
* bits 16..31 : ticket
16
-
*/
17
-
u32 lock;
18
-
struct {
19
-
#ifdef __BIG_ENDIAN
20
-
u16 ticket;
21
-
u16 serving_now;
22
-
#else
23
-
u16 serving_now;
24
-
u16 ticket;
25
-
#endif
26
-
} h;
27
-
} arch_spinlock_t;
28
-
29
-
#define __ARCH_SPIN_LOCK_UNLOCKED { .lock = 0 }
30
-
31
-
typedef struct {
32
-
volatile unsigned int lock;
33
-
} arch_rwlock_t;
34
-
35
-
#define __ARCH_RW_LOCK_UNLOCKED { 0 }
4
+
#include <asm-generic/qspinlock_types.h>
5
+
#include <asm-generic/qrwlock_types.h>
36
6
37
7
#endif
+1
-1
arch/mips/include/asm/syscall.h
+1
-1
arch/mips/include/asm/syscall.h
+30
arch/mips/include/asm/uasm.h
+30
arch/mips/include/asm/uasm.h
···
72
72
Ip_u1u2s3(_beql);
73
73
Ip_u1s2(_bgez);
74
74
Ip_u1s2(_bgezl);
75
+
Ip_u1s2(_bgtz);
76
+
Ip_u1s2(_blez);
75
77
Ip_u1s2(_bltz);
76
78
Ip_u1s2(_bltzl);
77
79
Ip_u1u2s3(_bne);
80
+
Ip_u1(_break);
78
81
Ip_u2s3u1(_cache);
79
82
Ip_u1u2(_cfc1);
80
83
Ip_u2u1(_cfcmsa);
···
85
82
Ip_u2u1(_ctcmsa);
86
83
Ip_u2u1s3(_daddiu);
87
84
Ip_u3u1u2(_daddu);
85
+
Ip_u1u2(_ddivu);
88
86
Ip_u1(_di);
89
87
Ip_u2u1msbu3(_dins);
90
88
Ip_u2u1msbu3(_dinsm);
89
+
Ip_u2u1msbu3(_dinsu);
91
90
Ip_u1u2(_divu);
92
91
Ip_u1u2u3(_dmfc0);
93
92
Ip_u1u2u3(_dmtc0);
93
+
Ip_u1u2(_dmultu);
94
94
Ip_u2u1u3(_drotr);
95
95
Ip_u2u1u3(_drotr32);
96
+
Ip_u2u1(_dsbh);
97
+
Ip_u2u1(_dshd);
96
98
Ip_u2u1u3(_dsll);
97
99
Ip_u2u1u3(_dsll32);
100
+
Ip_u3u2u1(_dsllv);
98
101
Ip_u2u1u3(_dsra);
102
+
Ip_u2u1u3(_dsra32);
103
+
Ip_u3u2u1(_dsrav);
99
104
Ip_u2u1u3(_dsrl);
100
105
Ip_u2u1u3(_dsrl32);
106
+
Ip_u3u2u1(_dsrlv);
101
107
Ip_u3u1u2(_dsubu);
102
108
Ip_0(_eret);
103
109
Ip_u2u1msbu3(_ext);
···
116
104
Ip_u2u1(_jalr);
117
105
Ip_u1(_jr);
118
106
Ip_u2s3u1(_lb);
107
+
Ip_u2s3u1(_lbu);
119
108
Ip_u2s3u1(_ld);
120
109
Ip_u3u1u2(_ldx);
121
110
Ip_u2s3u1(_lh);
···
125
112
Ip_u2s3u1(_lld);
126
113
Ip_u1s2(_lui);
127
114
Ip_u2s3u1(_lw);
115
+
Ip_u2s3u1(_lwu);
128
116
Ip_u3u1u2(_lwx);
129
117
Ip_u1u2u3(_mfc0);
130
118
Ip_u1u2u3(_mfhc0);
131
119
Ip_u1(_mfhi);
132
120
Ip_u1(_mflo);
121
+
Ip_u3u1u2(_movn);
122
+
Ip_u3u1u2(_movz);
133
123
Ip_u1u2u3(_mtc0);
134
124
Ip_u1u2u3(_mthc0);
135
125
Ip_u1(_mthi);
136
126
Ip_u1(_mtlo);
137
127
Ip_u3u1u2(_mul);
128
+
Ip_u1u2(_multu);
129
+
Ip_u3u1u2(_nor);
138
130
Ip_u3u1u2(_or);
139
131
Ip_u2u1u3(_ori);
140
132
Ip_u2s3u1(_pref);
141
133
Ip_0(_rfe);
142
134
Ip_u2u1u3(_rotr);
135
+
Ip_u2s3u1(_sb);
143
136
Ip_u2s3u1(_sc);
144
137
Ip_u2s3u1(_scd);
145
138
Ip_u2s3u1(_sd);
139
+
Ip_u2s3u1(_sh);
146
140
Ip_u2u1u3(_sll);
147
141
Ip_u3u2u1(_sllv);
148
142
Ip_s3s1s2(_slt);
143
+
Ip_u2u1s3(_slti);
149
144
Ip_u2u1s3(_sltiu);
150
145
Ip_u3u1u2(_sltu);
151
146
Ip_u2u1u3(_sra);
···
267
246
uasm_i_dsrl(p, a1, a2, a3);
268
247
else
269
248
uasm_i_dsrl32(p, a1, a2, a3 - 32);
249
+
}
250
+
251
+
static inline void uasm_i_dsra_safe(u32 **p, unsigned int a1,
252
+
unsigned int a2, unsigned int a3)
253
+
{
254
+
if (a3 < 32)
255
+
uasm_i_dsra(p, a1, a2, a3);
256
+
else
257
+
uasm_i_dsra32(p, a1, a2, a3 - 32);
270
258
}
271
259
272
260
/* Handle relocations. */
+2
-2
arch/mips/include/asm/vdso.h
+2
-2
arch/mips/include/asm/vdso.h
+64
arch/mips/include/asm/yamon-dt.h
+64
arch/mips/include/asm/yamon-dt.h
···
1
+
/*
2
+
* Copyright (C) 2016 Imagination Technologies
3
+
* Author: Paul Burton <paul.burton@imgtec.com>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify it
6
+
* under the terms of the GNU General Public License as published by the
7
+
* Free Software Foundation; either version 2 of the License, or (at your
8
+
* option) any later version.
9
+
*/
10
+
11
+
#ifndef __MIPS_ASM_YAMON_DT_H__
12
+
#define __MIPS_ASM_YAMON_DT_H__
13
+
14
+
#include <linux/types.h>
15
+
16
+
/**
17
+
* struct yamon_mem_region - Represents a contiguous range of physical RAM.
18
+
* @start: Start physical address.
19
+
* @size: Maximum size of region.
20
+
* @discard: Length of additional memory to discard after the region.
21
+
*/
22
+
struct yamon_mem_region {
23
+
phys_addr_t start;
24
+
phys_addr_t size;
25
+
phys_addr_t discard;
26
+
};
27
+
28
+
/**
29
+
* yamon_dt_append_cmdline() - Append YAMON-provided command line to /chosen
30
+
* @fdt: the FDT blob
31
+
*
32
+
* Write the YAMON-provided command line to the bootargs property of the
33
+
* /chosen node in @fdt.
34
+
*
35
+
* Return: 0 on success, else -errno
36
+
*/
37
+
extern __init int yamon_dt_append_cmdline(void *fdt);
38
+
39
+
/**
40
+
* yamon_dt_append_memory() - Append YAMON-provided memory info to /memory
41
+
* @fdt: the FDT blob
42
+
* @regions: zero size terminated array of physical memory regions
43
+
*
44
+
* Generate a /memory node in @fdt based upon memory size information provided
45
+
* by YAMON in its environment and the @regions array.
46
+
*
47
+
* Return: 0 on success, else -errno
48
+
*/
49
+
extern __init int yamon_dt_append_memory(void *fdt,
50
+
const struct yamon_mem_region *regions);
51
+
52
+
/**
53
+
* yamon_dt_serial_config() - Append YAMON-provided serial config to /chosen
54
+
* @fdt: the FDT blob
55
+
*
56
+
* Generate a stdout-path property in the /chosen node of @fdt, based upon
57
+
* information provided in the YAMON environment about the UART configuration
58
+
* of the system.
59
+
*
60
+
* Return: 0 on success, else -errno
61
+
*/
62
+
extern __init int yamon_dt_serial_config(void *fdt);
63
+
64
+
#endif /* __MIPS_ASM_YAMON_DT_H__ */
+19
-1
arch/mips/include/uapi/asm/inst.h
+19
-1
arch/mips/include/uapi/asm/inst.h
···
276
276
*/
277
277
enum bshfl_func {
278
278
wsbh_op = 0x2,
279
-
dshd_op = 0x5,
280
279
seb_op = 0x10,
281
280
seh_op = 0x18,
281
+
};
282
+
283
+
/*
284
+
* DBSHFL opcodes
285
+
*/
286
+
enum dbshfl_func {
287
+
dsbh_op = 0x2,
288
+
dshd_op = 0x5,
282
289
};
283
290
284
291
/*
···
762
755
;))))))
763
756
};
764
757
758
+
struct dsp_format { /* SPEC3 DSP format instructions */
759
+
__BITFIELD_FIELD(unsigned int opcode : 6,
760
+
__BITFIELD_FIELD(unsigned int base : 5,
761
+
__BITFIELD_FIELD(unsigned int index : 5,
762
+
__BITFIELD_FIELD(unsigned int rd : 5,
763
+
__BITFIELD_FIELD(unsigned int op : 5,
764
+
__BITFIELD_FIELD(unsigned int func : 6,
765
+
;))))))
766
+
};
767
+
765
768
struct spec3_format { /* SPEC3 */
766
769
__BITFIELD_FIELD(unsigned int opcode:6,
767
770
__BITFIELD_FIELD(unsigned int rs:5,
···
1063
1046
struct b_format b_format;
1064
1047
struct ps_format ps_format;
1065
1048
struct v_format v_format;
1049
+
struct dsp_format dsp_format;
1066
1050
struct spec3_format spec3_format;
1067
1051
struct fb_format fb_format;
1068
1052
struct fp0_format fp0_format;
+1
-2
arch/mips/kernel/Makefile
+1
-2
arch/mips/kernel/Makefile
···
4
4
5
5
extra-y := head.o vmlinux.lds
6
6
7
-
obj-y += cpu-probe.o branch.o elf.o entry.o genex.o idle.o irq.o \
7
+
obj-y += cmpxchg.o cpu-probe.o branch.o elf.o entry.o genex.o idle.o irq.o \
8
8
process.o prom.o ptrace.o reset.o setup.o signal.o \
9
9
syscall.o time.o topology.o traps.o unaligned.o watch.o \
10
10
vdso.o cacheinfo.o
···
31
31
obj-$(CONFIG_DEBUG_FS) += segment.o
32
32
obj-$(CONFIG_STACKTRACE) += stacktrace.o
33
33
obj-$(CONFIG_MODULES) += module.o
34
-
obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o
35
34
36
35
obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o
37
36
obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
+33
-40
arch/mips/kernel/branch.c
+33
-40
arch/mips/kernel/branch.c
···
399
399
*
400
400
* @regs: Pointer to pt_regs
401
401
* @insn: branch instruction to decode
402
-
* @returns: -EFAULT on error and forces SIGBUS, and on success
402
+
* @returns: -EFAULT on error and forces SIGILL, and on success
403
403
* returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
404
404
* evaluating the branch.
405
405
*
···
431
431
/* Fall through */
432
432
case jr_op:
433
433
if (NO_R6EMU && insn.r_format.func == jr_op)
434
-
goto sigill_r6;
434
+
goto sigill_r2r6;
435
435
regs->cp0_epc = regs->regs[insn.r_format.rs];
436
436
break;
437
437
}
···
446
446
switch (insn.i_format.rt) {
447
447
case bltzl_op:
448
448
if (NO_R6EMU)
449
-
goto sigill_r6;
449
+
goto sigill_r2r6;
450
450
case bltz_op:
451
451
if ((long)regs->regs[insn.i_format.rs] < 0) {
452
452
epc = epc + 4 + (insn.i_format.simmediate << 2);
···
459
459
460
460
case bgezl_op:
461
461
if (NO_R6EMU)
462
-
goto sigill_r6;
462
+
goto sigill_r2r6;
463
463
case bgez_op:
464
464
if ((long)regs->regs[insn.i_format.rs] >= 0) {
465
465
epc = epc + 4 + (insn.i_format.simmediate << 2);
···
473
473
case bltzal_op:
474
474
case bltzall_op:
475
475
if (NO_R6EMU && (insn.i_format.rs ||
476
-
insn.i_format.rt == bltzall_op)) {
477
-
ret = -SIGILL;
478
-
break;
479
-
}
476
+
insn.i_format.rt == bltzall_op))
477
+
goto sigill_r2r6;
480
478
regs->regs[31] = epc + 8;
481
479
/*
482
480
* OK we are here either because we hit a NAL
···
505
507
case bgezal_op:
506
508
case bgezall_op:
507
509
if (NO_R6EMU && (insn.i_format.rs ||
508
-
insn.i_format.rt == bgezall_op)) {
509
-
ret = -SIGILL;
510
-
break;
511
-
}
510
+
insn.i_format.rt == bgezall_op))
511
+
goto sigill_r2r6;
512
512
regs->regs[31] = epc + 8;
513
513
/*
514
514
* OK we are here either because we hit a BAL
···
552
556
/*
553
557
* These are unconditional and in j_format.
554
558
*/
559
+
case jalx_op:
555
560
case jal_op:
556
561
regs->regs[31] = regs->cp0_epc + 8;
557
562
case j_op:
···
570
573
*/
571
574
case beql_op:
572
575
if (NO_R6EMU)
573
-
goto sigill_r6;
576
+
goto sigill_r2r6;
574
577
case beq_op:
575
578
if (regs->regs[insn.i_format.rs] ==
576
579
regs->regs[insn.i_format.rt]) {
···
584
587
585
588
case bnel_op:
586
589
if (NO_R6EMU)
587
-
goto sigill_r6;
590
+
goto sigill_r2r6;
588
591
case bne_op:
589
592
if (regs->regs[insn.i_format.rs] !=
590
593
regs->regs[insn.i_format.rt]) {
···
598
601
599
602
case blezl_op: /* not really i_format */
600
603
if (!insn.i_format.rt && NO_R6EMU)
601
-
goto sigill_r6;
604
+
goto sigill_r2r6;
602
605
case blez_op:
603
606
/*
604
607
* Compact branches for R6 for the
···
633
636
634
637
case bgtzl_op:
635
638
if (!insn.i_format.rt && NO_R6EMU)
636
-
goto sigill_r6;
639
+
goto sigill_r2r6;
637
640
case bgtz_op:
638
641
/*
639
642
* Compact branches for R6 for the
···
771
774
#else
772
775
case bc6_op:
773
776
/* Only valid for MIPS R6 */
774
-
if (!cpu_has_mips_r6) {
775
-
ret = -SIGILL;
776
-
break;
777
-
}
777
+
if (!cpu_has_mips_r6)
778
+
goto sigill_r6;
778
779
regs->cp0_epc += 8;
779
780
break;
780
781
case balc6_op:
781
-
if (!cpu_has_mips_r6) {
782
-
ret = -SIGILL;
783
-
break;
784
-
}
782
+
if (!cpu_has_mips_r6)
783
+
goto sigill_r6;
785
784
/* Compact branch: BALC */
786
785
regs->regs[31] = epc + 4;
787
786
epc += 4 + (insn.i_format.simmediate << 2);
788
787
regs->cp0_epc = epc;
789
788
break;
790
789
case pop66_op:
791
-
if (!cpu_has_mips_r6) {
792
-
ret = -SIGILL;
793
-
break;
794
-
}
790
+
if (!cpu_has_mips_r6)
791
+
goto sigill_r6;
795
792
/* Compact branch: BEQZC || JIC */
796
793
regs->cp0_epc += 8;
797
794
break;
798
795
case pop76_op:
799
-
if (!cpu_has_mips_r6) {
800
-
ret = -SIGILL;
801
-
break;
802
-
}
796
+
if (!cpu_has_mips_r6)
797
+
goto sigill_r6;
803
798
/* Compact branch: BNEZC || JIALC */
804
799
if (!insn.i_format.rs) {
805
800
/* JIALC: set $31/ra */
···
803
814
case pop10_op:
804
815
case pop30_op:
805
816
/* Only valid for MIPS R6 */
806
-
if (!cpu_has_mips_r6) {
807
-
ret = -SIGILL;
808
-
break;
809
-
}
817
+
if (!cpu_has_mips_r6)
818
+
goto sigill_r6;
810
819
/*
811
820
* Compact branches:
812
821
* bovc, beqc, beqzalc, bnvc, bnec, bnezlac
···
818
831
return ret;
819
832
820
833
sigill_dsp:
821
-
printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
822
-
force_sig(SIGBUS, current);
834
+
pr_debug("%s: DSP branch but not DSP ASE - sending SIGILL.\n",
835
+
current->comm);
836
+
force_sig(SIGILL, current);
837
+
return -EFAULT;
838
+
sigill_r2r6:
839
+
pr_debug("%s: R2 branch but r2-to-r6 emulator is not present - sending SIGILL.\n",
840
+
current->comm);
841
+
force_sig(SIGILL, current);
823
842
return -EFAULT;
824
843
sigill_r6:
825
-
pr_info("%s: R2 branch but r2-to-r6 emulator is not preset - sending SIGILL.\n",
826
-
current->comm);
844
+
pr_debug("%s: R6 branch but no MIPSr6 ISA support - sending SIGILL.\n",
845
+
current->comm);
827
846
force_sig(SIGILL, current);
828
847
return -EFAULT;
829
848
}
+109
arch/mips/kernel/cmpxchg.c
+109
arch/mips/kernel/cmpxchg.c
···
1
+
/*
2
+
* Copyright (C) 2017 Imagination Technologies
3
+
* Author: Paul Burton <paul.burton@imgtec.com>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify it
6
+
* under the terms of the GNU General Public License as published by the
7
+
* Free Software Foundation; either version 2 of the License, or (at your
8
+
* option) any later version.
9
+
*/
10
+
11
+
#include <linux/bitops.h>
12
+
#include <asm/cmpxchg.h>
13
+
14
+
unsigned long __xchg_small(volatile void *ptr, unsigned long val, unsigned int size)
15
+
{
16
+
u32 old32, new32, load32, mask;
17
+
volatile u32 *ptr32;
18
+
unsigned int shift;
19
+
20
+
/* Check that ptr is naturally aligned */
21
+
WARN_ON((unsigned long)ptr & (size - 1));
22
+
23
+
/* Mask value to the correct size. */
24
+
mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);
25
+
val &= mask;
26
+
27
+
/*
28
+
* Calculate a shift & mask that correspond to the value we wish to
29
+
* exchange within the naturally aligned 4 byte integerthat includes
30
+
* it.
31
+
*/
32
+
shift = (unsigned long)ptr & 0x3;
33
+
if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
34
+
shift ^= sizeof(u32) - size;
35
+
shift *= BITS_PER_BYTE;
36
+
mask <<= shift;
37
+
38
+
/*
39
+
* Calculate a pointer to the naturally aligned 4 byte integer that
40
+
* includes our byte of interest, and load its value.
41
+
*/
42
+
ptr32 = (volatile u32 *)((unsigned long)ptr & ~0x3);
43
+
load32 = *ptr32;
44
+
45
+
do {
46
+
old32 = load32;
47
+
new32 = (load32 & ~mask) | (val << shift);
48
+
load32 = cmpxchg(ptr32, old32, new32);
49
+
} while (load32 != old32);
50
+
51
+
return (load32 & mask) >> shift;
52
+
}
53
+
54
+
unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old,
55
+
unsigned long new, unsigned int size)
56
+
{
57
+
u32 mask, old32, new32, load32;
58
+
volatile u32 *ptr32;
59
+
unsigned int shift;
60
+
u8 load;
61
+
62
+
/* Check that ptr is naturally aligned */
63
+
WARN_ON((unsigned long)ptr & (size - 1));
64
+
65
+
/* Mask inputs to the correct size. */
66
+
mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);
67
+
old &= mask;
68
+
new &= mask;
69
+
70
+
/*
71
+
* Calculate a shift & mask that correspond to the value we wish to
72
+
* compare & exchange within the naturally aligned 4 byte integer
73
+
* that includes it.
74
+
*/
75
+
shift = (unsigned long)ptr & 0x3;
76
+
if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
77
+
shift ^= sizeof(u32) - size;
78
+
shift *= BITS_PER_BYTE;
79
+
mask <<= shift;
80
+
81
+
/*
82
+
* Calculate a pointer to the naturally aligned 4 byte integer that
83
+
* includes our byte of interest, and load its value.
84
+
*/
85
+
ptr32 = (volatile u32 *)((unsigned long)ptr & ~0x3);
86
+
load32 = *ptr32;
87
+
88
+
while (true) {
89
+
/*
90
+
* Ensure the byte we want to exchange matches the expected
91
+
* old value, and if not then bail.
92
+
*/
93
+
load = (load32 & mask) >> shift;
94
+
if (load != old)
95
+
return load;
96
+
97
+
/*
98
+
* Calculate the old & new values of the naturally aligned
99
+
* 4 byte integer that include the byte we want to exchange.
100
+
* Attempt to exchange the old value for the new value, and
101
+
* return if we succeed.
102
+
*/
103
+
old32 = (load32 & ~mask) | (old << shift);
104
+
new32 = (load32 & ~mask) | (new << shift);
105
+
load32 = cmpxchg(ptr32, old32, new32);
106
+
if (load32 == old32)
107
+
return old;
108
+
}
109
+
}
+6
-1
arch/mips/kernel/cps-vec.S
+6
-1
arch/mips/kernel/cps-vec.S
···
22
22
#define GCR_CL_COHERENCE_OFS 0x2008
23
23
#define GCR_CL_ID_OFS 0x2028
24
24
25
+
#define CPC_CL_VC_STOP_OFS 0x2020
25
26
#define CPC_CL_VC_RUN_OFS 0x2028
26
27
27
28
.extern mips_cm_base
···
377
376
PTR_LI t2, UNCAC_BASE
378
377
PTR_ADD t1, t1, t2
379
378
380
-
/* Set VC_RUN to the VPE mask */
379
+
/* Start any other VPs that ought to be running */
381
380
PTR_S ta2, CPC_CL_VC_RUN_OFS(t1)
381
+
382
+
/* Ensure this VP stops running if it shouldn't be */
383
+
not ta2
384
+
PTR_S ta2, CPC_CL_VC_STOP_OFS(t1)
382
385
ehb
383
386
384
387
#elif defined(CONFIG_MIPS_MT)
+24
arch/mips/kernel/cpu-probe.c
+24
arch/mips/kernel/cpu-probe.c
···
564
564
back_to_back_c0_hazard();
565
565
break;
566
566
case CPU_I6400:
567
+
case CPU_I6500:
567
568
/* There's no way to disable the FTLB */
568
569
if (!(flags & FTLB_EN))
569
570
return 1;
···
845
844
c->options |= MIPS_CPU_MVH;
846
845
if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
847
846
c->options |= MIPS_CPU_VP;
847
+
if (config5 & MIPS_CONF5_CA2)
848
+
c->ases |= MIPS_ASE_MIPS16E2;
848
849
849
850
return config5 & MIPS_CONF_M;
850
851
}
···
1638
1635
c->cputype = CPU_I6400;
1639
1636
__cpu_name[cpu] = "MIPS I6400";
1640
1637
break;
1638
+
case PRID_IMP_I6500:
1639
+
c->cputype = CPU_I6500;
1640
+
__cpu_name[cpu] = "MIPS I6500";
1641
+
break;
1641
1642
case PRID_IMP_M5150:
1642
1643
c->cputype = CPU_M5150;
1643
1644
__cpu_name[cpu] = "MIPS M5150";
···
1655
1648
decode_configs(c);
1656
1649
1657
1650
spram_config();
1651
+
1652
+
switch (__get_cpu_type(c->cputype)) {
1653
+
case CPU_I6500:
1654
+
c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1655
+
/* fall-through */
1656
+
case CPU_I6400:
1657
+
c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1658
+
/* fall-through */
1659
+
default:
1660
+
break;
1661
+
}
1658
1662
}
1659
1663
1660
1664
static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
···
1844
1826
case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1845
1827
switch (c->processor_id & PRID_REV_MASK) {
1846
1828
case PRID_REV_LOONGSON3A_R2:
1829
+
c->cputype = CPU_LOONGSON3;
1830
+
__cpu_name[cpu] = "ICT Loongson-3";
1831
+
set_elf_platform(cpu, "loongson3a");
1832
+
set_isa(c, MIPS_CPU_ISA_M64R2);
1833
+
break;
1834
+
case PRID_REV_LOONGSON3A_R3:
1847
1835
c->cputype = CPU_LOONGSON3;
1848
1836
__cpu_name[cpu] = "ICT Loongson-3";
1849
1837
set_elf_platform(cpu, "loongson3a");
+33
-7
arch/mips/kernel/mips-cm.c
+33
-7
arch/mips/kernel/mips-cm.c
···
265
265
u32 val;
266
266
267
267
preempt_disable();
268
-
curr_core = current_cpu_data.core;
269
-
spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
270
-
per_cpu(cm_core_lock_flags, curr_core));
271
268
272
269
if (mips_cm_revision() >= CM_REV_CM3) {
273
270
val = core << CM3_GCR_Cx_OTHER_CORE_SHF;
274
271
val |= vp << CM3_GCR_Cx_OTHER_VP_SHF;
272
+
273
+
/*
274
+
* We need to disable interrupts in SMP systems in order to
275
+
* ensure that we don't interrupt the caller with code which
276
+
* may modify the redirect register. We do so here in a
277
+
* slightly obscure way by using a spin lock, since this has
278
+
* the neat property of also catching any nested uses of
279
+
* mips_cm_lock_other() leading to a deadlock or a nice warning
280
+
* with lockdep enabled.
281
+
*/
282
+
spin_lock_irqsave(this_cpu_ptr(&cm_core_lock),
283
+
*this_cpu_ptr(&cm_core_lock_flags));
275
284
} else {
276
-
BUG_ON(vp != 0);
285
+
WARN_ON(vp != 0);
286
+
287
+
/*
288
+
* We only have a GCR_CL_OTHER per core in systems with
289
+
* CM 2.5 & older, so have to ensure other VP(E)s don't
290
+
* race with us.
291
+
*/
292
+
curr_core = current_cpu_data.core;
293
+
spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
294
+
per_cpu(cm_core_lock_flags, curr_core));
295
+
277
296
val = core << CM_GCR_Cx_OTHER_CORENUM_SHF;
278
297
}
279
298
···
307
288
308
289
void mips_cm_unlock_other(void)
309
290
{
310
-
unsigned curr_core = current_cpu_data.core;
291
+
unsigned int curr_core;
311
292
312
-
spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
313
-
per_cpu(cm_core_lock_flags, curr_core));
293
+
if (mips_cm_revision() < CM_REV_CM3) {
294
+
curr_core = current_cpu_data.core;
295
+
spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
296
+
per_cpu(cm_core_lock_flags, curr_core));
297
+
} else {
298
+
spin_unlock_irqrestore(this_cpu_ptr(&cm_core_lock),
299
+
*this_cpu_ptr(&cm_core_lock_flags));
300
+
}
301
+
314
302
preempt_enable();
315
303
}
316
304
-202
arch/mips/kernel/module-rela.c
-202
arch/mips/kernel/module-rela.c
···
1
-
/*
2
-
* This program is free software; you can redistribute it and/or modify
3
-
* it under the terms of the GNU General Public License as published by
4
-
* the Free Software Foundation; either version 2 of the License, or
5
-
* (at your option) any later version.
6
-
*
7
-
* This program is distributed in the hope that it will be useful,
8
-
* but WITHOUT ANY WARRANTY; without even the implied warranty of
9
-
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10
-
* GNU General Public License for more details.
11
-
*
12
-
* You should have received a copy of the GNU General Public License
13
-
* along with this program; if not, write to the Free Software
14
-
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15
-
*
16
-
* Copyright (C) 2001 Rusty Russell.
17
-
* Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
18
-
* Copyright (C) 2005 Thiemo Seufer
19
-
* Copyright (C) 2015 Imagination Technologies Ltd.
20
-
*/
21
-
22
-
#include <linux/elf.h>
23
-
#include <linux/err.h>
24
-
#include <linux/errno.h>
25
-
#include <linux/moduleloader.h>
26
-
27
-
extern int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v);
28
-
29
-
static int apply_r_mips_32_rela(struct module *me, u32 *location, Elf_Addr v)
30
-
{
31
-
*location = v;
32
-
33
-
return 0;
34
-
}
35
-
36
-
static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v)
37
-
{
38
-
if (v % 4) {
39
-
pr_err("module %s: dangerous R_MIPS_26 RELA relocation\n",
40
-
me->name);
41
-
return -ENOEXEC;
42
-
}
43
-
44
-
if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
45
-
pr_err("module %s: relocation overflow\n", me->name);
46
-
return -ENOEXEC;
47
-
}
48
-
49
-
*location = (*location & ~0x03ffffff) | ((v >> 2) & 0x03ffffff);
50
-
51
-
return 0;
52
-
}
53
-
54
-
static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v)
55
-
{
56
-
*location = (*location & 0xffff0000) |
57
-
((((long long) v + 0x8000LL) >> 16) & 0xffff);
58
-
59
-
return 0;
60
-
}
61
-
62
-
static int apply_r_mips_lo16_rela(struct module *me, u32 *location, Elf_Addr v)
63
-
{
64
-
*location = (*location & 0xffff0000) | (v & 0xffff);
65
-
66
-
return 0;
67
-
}
68
-
69
-
static int apply_r_mips_pc_rela(struct module *me, u32 *location, Elf_Addr v,
70
-
unsigned bits)
71
-
{
72
-
unsigned long mask = GENMASK(bits - 1, 0);
73
-
unsigned long se_bits;
74
-
long offset;
75
-
76
-
if (v % 4) {
77
-
pr_err("module %s: dangerous R_MIPS_PC%u RELA relocation\n",
78
-
me->name, bits);
79
-
return -ENOEXEC;
80
-
}
81
-
82
-
offset = ((long)v - (long)location) >> 2;
83
-
84
-
/* check the sign bit onwards are identical - ie. we didn't overflow */
85
-
se_bits = (offset & BIT(bits - 1)) ? ~0ul : 0;
86
-
if ((offset & ~mask) != (se_bits & ~mask)) {
87
-
pr_err("module %s: relocation overflow\n", me->name);
88
-
return -ENOEXEC;
89
-
}
90
-
91
-
*location = (*location & ~mask) | (offset & mask);
92
-
93
-
return 0;
94
-
}
95
-
96
-
static int apply_r_mips_pc16_rela(struct module *me, u32 *location, Elf_Addr v)
97
-
{
98
-
return apply_r_mips_pc_rela(me, location, v, 16);
99
-
}
100
-
101
-
static int apply_r_mips_pc21_rela(struct module *me, u32 *location, Elf_Addr v)
102
-
{
103
-
return apply_r_mips_pc_rela(me, location, v, 21);
104
-
}
105
-
106
-
static int apply_r_mips_pc26_rela(struct module *me, u32 *location, Elf_Addr v)
107
-
{
108
-
return apply_r_mips_pc_rela(me, location, v, 26);
109
-
}
110
-
111
-
static int apply_r_mips_64_rela(struct module *me, u32 *location, Elf_Addr v)
112
-
{
113
-
*(Elf_Addr *)location = v;
114
-
115
-
return 0;
116
-
}
117
-
118
-
static int apply_r_mips_higher_rela(struct module *me, u32 *location,
119
-
Elf_Addr v)
120
-
{
121
-
*location = (*location & 0xffff0000) |
122
-
((((long long) v + 0x80008000LL) >> 32) & 0xffff);
123
-
124
-
return 0;
125
-
}
126
-
127
-
static int apply_r_mips_highest_rela(struct module *me, u32 *location,
128
-
Elf_Addr v)
129
-
{
130
-
*location = (*location & 0xffff0000) |
131
-
((((long long) v + 0x800080008000LL) >> 48) & 0xffff);
132
-
133
-
return 0;
134
-
}
135
-
136
-
static int (*reloc_handlers_rela[]) (struct module *me, u32 *location,
137
-
Elf_Addr v) = {
138
-
[R_MIPS_NONE] = apply_r_mips_none,
139
-
[R_MIPS_32] = apply_r_mips_32_rela,
140
-
[R_MIPS_26] = apply_r_mips_26_rela,
141
-
[R_MIPS_HI16] = apply_r_mips_hi16_rela,
142
-
[R_MIPS_LO16] = apply_r_mips_lo16_rela,
143
-
[R_MIPS_PC16] = apply_r_mips_pc16_rela,
144
-
[R_MIPS_64] = apply_r_mips_64_rela,
145
-
[R_MIPS_HIGHER] = apply_r_mips_higher_rela,
146
-
[R_MIPS_HIGHEST] = apply_r_mips_highest_rela,
147
-
[R_MIPS_PC21_S2] = apply_r_mips_pc21_rela,
148
-
[R_MIPS_PC26_S2] = apply_r_mips_pc26_rela,
149
-
};
150
-
151
-
int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
152
-
unsigned int symindex, unsigned int relsec,
153
-
struct module *me)
154
-
{
155
-
Elf_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr;
156
-
int (*handler)(struct module *me, u32 *location, Elf_Addr v);
157
-
Elf_Sym *sym;
158
-
u32 *location;
159
-
unsigned int i, type;
160
-
Elf_Addr v;
161
-
int res;
162
-
163
-
pr_debug("Applying relocate section %u to %u\n", relsec,
164
-
sechdrs[relsec].sh_info);
165
-
166
-
for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
167
-
/* This is where to make the change */
168
-
location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
169
-
+ rel[i].r_offset;
170
-
/* This is the symbol it is referring to */
171
-
sym = (Elf_Sym *)sechdrs[symindex].sh_addr
172
-
+ ELF_MIPS_R_SYM(rel[i]);
173
-
if (sym->st_value >= -MAX_ERRNO) {
174
-
/* Ignore unresolved weak symbol */
175
-
if (ELF_ST_BIND(sym->st_info) == STB_WEAK)
176
-
continue;
177
-
pr_warn("%s: Unknown symbol %s\n",
178
-
me->name, strtab + sym->st_name);
179
-
return -ENOENT;
180
-
}
181
-
182
-
type = ELF_MIPS_R_TYPE(rel[i]);
183
-
184
-
if (type < ARRAY_SIZE(reloc_handlers_rela))
185
-
handler = reloc_handlers_rela[type];
186
-
else
187
-
handler = NULL;
188
-
189
-
if (!handler) {
190
-
pr_err("%s: Unknown relocation type %u\n",
191
-
me->name, type);
192
-
return -EINVAL;
193
-
}
194
-
195
-
v = sym->st_value + rel[i].r_addend;
196
-
res = handler(me, location, v);
197
-
if (res)
198
-
return res;
199
-
}
200
-
201
-
return 0;
202
-
}
+165
-56
arch/mips/kernel/module.c
+165
-56
arch/mips/kernel/module.c
···
53
53
}
54
54
#endif
55
55
56
-
int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v)
56
+
static int apply_r_mips_none(struct module *me, u32 *location,
57
+
u32 base, Elf_Addr v, bool rela)
57
58
{
58
59
return 0;
59
60
}
60
61
61
-
static int apply_r_mips_32_rel(struct module *me, u32 *location, Elf_Addr v)
62
+
static int apply_r_mips_32(struct module *me, u32 *location,
63
+
u32 base, Elf_Addr v, bool rela)
62
64
{
63
-
*location += v;
65
+
*location = base + v;
64
66
65
67
return 0;
66
68
}
67
69
68
-
static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v)
70
+
static int apply_r_mips_26(struct module *me, u32 *location,
71
+
u32 base, Elf_Addr v, bool rela)
69
72
{
70
73
if (v % 4) {
71
-
pr_err("module %s: dangerous R_MIPS_26 REL relocation\n",
74
+
pr_err("module %s: dangerous R_MIPS_26 relocation\n",
72
75
me->name);
73
76
return -ENOEXEC;
74
77
}
···
83
80
}
84
81
85
82
*location = (*location & ~0x03ffffff) |
86
-
((*location + (v >> 2)) & 0x03ffffff);
83
+
((base + (v >> 2)) & 0x03ffffff);
87
84
88
85
return 0;
89
86
}
90
87
91
-
static int apply_r_mips_hi16_rel(struct module *me, u32 *location, Elf_Addr v)
88
+
static int apply_r_mips_hi16(struct module *me, u32 *location,
89
+
u32 base, Elf_Addr v, bool rela)
92
90
{
93
91
struct mips_hi16 *n;
92
+
93
+
if (rela) {
94
+
*location = (*location & 0xffff0000) |
95
+
((((long long) v + 0x8000LL) >> 16) & 0xffff);
96
+
return 0;
97
+
}
94
98
95
99
/*
96
100
* We cannot relocate this one now because we don't know the value of
···
127
117
}
128
118
}
129
119
130
-
static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
120
+
static int apply_r_mips_lo16(struct module *me, u32 *location,
121
+
u32 base, Elf_Addr v, bool rela)
131
122
{
132
-
unsigned long insnlo = *location;
123
+
unsigned long insnlo = base;
133
124
struct mips_hi16 *l;
134
125
Elf_Addr val, vallo;
126
+
127
+
if (rela) {
128
+
*location = (*location & 0xffff0000) | (v & 0xffff);
129
+
return 0;
130
+
}
135
131
136
132
/* Sign extend the addend we extract from the lo insn. */
137
133
vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
···
194
178
free_relocation_chain(l);
195
179
me->arch.r_mips_hi16_list = NULL;
196
180
197
-
pr_err("module %s: dangerous R_MIPS_LO16 REL relocation\n", me->name);
181
+
pr_err("module %s: dangerous R_MIPS_LO16 relocation\n", me->name);
198
182
199
183
return -ENOEXEC;
200
184
}
201
185
202
-
static int apply_r_mips_pc_rel(struct module *me, u32 *location, Elf_Addr v,
203
-
unsigned bits)
186
+
static int apply_r_mips_pc(struct module *me, u32 *location, u32 base,
187
+
Elf_Addr v, unsigned int bits)
204
188
{
205
189
unsigned long mask = GENMASK(bits - 1, 0);
206
190
unsigned long se_bits;
207
191
long offset;
208
192
209
193
if (v % 4) {
210
-
pr_err("module %s: dangerous R_MIPS_PC%u REL relocation\n",
194
+
pr_err("module %s: dangerous R_MIPS_PC%u relocation\n",
211
195
me->name, bits);
212
196
return -ENOEXEC;
213
197
}
214
198
215
-
/* retrieve & sign extend implicit addend */
216
-
offset = *location & mask;
199
+
/* retrieve & sign extend implicit addend if any */
200
+
offset = base & mask;
217
201
offset |= (offset & BIT(bits - 1)) ? ~mask : 0;
218
202
219
203
offset += ((long)v - (long)location) >> 2;
···
230
214
return 0;
231
215
}
232
216
233
-
static int apply_r_mips_pc16_rel(struct module *me, u32 *location, Elf_Addr v)
217
+
static int apply_r_mips_pc16(struct module *me, u32 *location,
218
+
u32 base, Elf_Addr v, bool rela)
234
219
{
235
-
return apply_r_mips_pc_rel(me, location, v, 16);
220
+
return apply_r_mips_pc(me, location, base, v, 16);
236
221
}
237
222
238
-
static int apply_r_mips_pc21_rel(struct module *me, u32 *location, Elf_Addr v)
223
+
static int apply_r_mips_pc21(struct module *me, u32 *location,
224
+
u32 base, Elf_Addr v, bool rela)
239
225
{
240
-
return apply_r_mips_pc_rel(me, location, v, 21);
226
+
return apply_r_mips_pc(me, location, base, v, 21);
241
227
}
242
228
243
-
static int apply_r_mips_pc26_rel(struct module *me, u32 *location, Elf_Addr v)
229
+
static int apply_r_mips_pc26(struct module *me, u32 *location,
230
+
u32 base, Elf_Addr v, bool rela)
244
231
{
245
-
return apply_r_mips_pc_rel(me, location, v, 26);
232
+
return apply_r_mips_pc(me, location, base, v, 26);
246
233
}
247
234
248
-
static int (*reloc_handlers_rel[]) (struct module *me, u32 *location,
249
-
Elf_Addr v) = {
235
+
static int apply_r_mips_64(struct module *me, u32 *location,
236
+
u32 base, Elf_Addr v, bool rela)
237
+
{
238
+
if (WARN_ON(!rela))
239
+
return -EINVAL;
240
+
241
+
*(Elf_Addr *)location = v;
242
+
243
+
return 0;
244
+
}
245
+
246
+
static int apply_r_mips_higher(struct module *me, u32 *location,
247
+
u32 base, Elf_Addr v, bool rela)
248
+
{
249
+
if (WARN_ON(!rela))
250
+
return -EINVAL;
251
+
252
+
*location = (*location & 0xffff0000) |
253
+
((((long long)v + 0x80008000LL) >> 32) & 0xffff);
254
+
255
+
return 0;
256
+
}
257
+
258
+
static int apply_r_mips_highest(struct module *me, u32 *location,
259
+
u32 base, Elf_Addr v, bool rela)
260
+
{
261
+
if (WARN_ON(!rela))
262
+
return -EINVAL;
263
+
264
+
*location = (*location & 0xffff0000) |
265
+
((((long long)v + 0x800080008000LL) >> 48) & 0xffff);
266
+
267
+
return 0;
268
+
}
269
+
270
+
/**
271
+
* reloc_handler() - Apply a particular relocation to a module
272
+
* @me: the module to apply the reloc to
273
+
* @location: the address at which the reloc is to be applied
274
+
* @base: the existing value at location for REL-style; 0 for RELA-style
275
+
* @v: the value of the reloc, with addend for RELA-style
276
+
*
277
+
* Each implemented reloc_handler function applies a particular type of
278
+
* relocation to the module @me. Relocs that may be found in either REL or RELA
279
+
* variants can be handled by making use of the @base & @v parameters which are
280
+
* set to values which abstract the difference away from the particular reloc
281
+
* implementations.
282
+
*
283
+
* Return: 0 upon success, else -ERRNO
284
+
*/
285
+
typedef int (*reloc_handler)(struct module *me, u32 *location,
286
+
u32 base, Elf_Addr v, bool rela);
287
+
288
+
/* The handlers for known reloc types */
289
+
static reloc_handler reloc_handlers[] = {
250
290
[R_MIPS_NONE] = apply_r_mips_none,
251
-
[R_MIPS_32] = apply_r_mips_32_rel,
252
-
[R_MIPS_26] = apply_r_mips_26_rel,
253
-
[R_MIPS_HI16] = apply_r_mips_hi16_rel,
254
-
[R_MIPS_LO16] = apply_r_mips_lo16_rel,
255
-
[R_MIPS_PC16] = apply_r_mips_pc16_rel,
256
-
[R_MIPS_PC21_S2] = apply_r_mips_pc21_rel,
257
-
[R_MIPS_PC26_S2] = apply_r_mips_pc26_rel,
291
+
[R_MIPS_32] = apply_r_mips_32,
292
+
[R_MIPS_26] = apply_r_mips_26,
293
+
[R_MIPS_HI16] = apply_r_mips_hi16,
294
+
[R_MIPS_LO16] = apply_r_mips_lo16,
295
+
[R_MIPS_PC16] = apply_r_mips_pc16,
296
+
[R_MIPS_64] = apply_r_mips_64,
297
+
[R_MIPS_HIGHER] = apply_r_mips_higher,
298
+
[R_MIPS_HIGHEST] = apply_r_mips_highest,
299
+
[R_MIPS_PC21_S2] = apply_r_mips_pc21,
300
+
[R_MIPS_PC26_S2] = apply_r_mips_pc26,
258
301
};
259
302
260
-
int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
261
-
unsigned int symindex, unsigned int relsec,
262
-
struct module *me)
303
+
static int __apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
304
+
unsigned int symindex, unsigned int relsec,
305
+
struct module *me, bool rela)
263
306
{
264
-
Elf_Mips_Rel *rel = (void *) sechdrs[relsec].sh_addr;
265
-
int (*handler)(struct module *me, u32 *location, Elf_Addr v);
307
+
union {
308
+
Elf_Mips_Rel *rel;
309
+
Elf_Mips_Rela *rela;
310
+
} r;
311
+
reloc_handler handler;
266
312
Elf_Sym *sym;
267
-
u32 *location;
313
+
u32 *location, base;
268
314
unsigned int i, type;
269
315
Elf_Addr v;
270
-
int res;
316
+
int err = 0;
317
+
size_t reloc_sz;
271
318
272
319
pr_debug("Applying relocate section %u to %u\n", relsec,
273
320
sechdrs[relsec].sh_info);
274
321
322
+
r.rel = (void *)sechdrs[relsec].sh_addr;
323
+
reloc_sz = rela ? sizeof(*r.rela) : sizeof(*r.rel);
275
324
me->arch.r_mips_hi16_list = NULL;
276
-
for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
325
+
for (i = 0; i < sechdrs[relsec].sh_size / reloc_sz; i++) {
277
326
/* This is where to make the change */
278
327
location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
279
-
+ rel[i].r_offset;
328
+
+ r.rel->r_offset;
280
329
/* This is the symbol it is referring to */
281
330
sym = (Elf_Sym *)sechdrs[symindex].sh_addr
282
-
+ ELF_MIPS_R_SYM(rel[i]);
331
+
+ ELF_MIPS_R_SYM(*r.rel);
283
332
if (sym->st_value >= -MAX_ERRNO) {
284
333
/* Ignore unresolved weak symbol */
285
334
if (ELF_ST_BIND(sym->st_info) == STB_WEAK)
286
335
continue;
287
336
pr_warn("%s: Unknown symbol %s\n",
288
337
me->name, strtab + sym->st_name);
289
-
return -ENOENT;
338
+
err = -ENOENT;
339
+
goto out;
290
340
}
291
341
292
-
type = ELF_MIPS_R_TYPE(rel[i]);
293
-
294
-
if (type < ARRAY_SIZE(reloc_handlers_rel))
295
-
handler = reloc_handlers_rel[type];
342
+
type = ELF_MIPS_R_TYPE(*r.rel);
343
+
if (type < ARRAY_SIZE(reloc_handlers))
344
+
handler = reloc_handlers[type];
296
345
else
297
346
handler = NULL;
298
347
299
348
if (!handler) {
300
349
pr_err("%s: Unknown relocation type %u\n",
301
350
me->name, type);
302
-
return -EINVAL;
351
+
err = -EINVAL;
352
+
goto out;
303
353
}
304
354
305
-
v = sym->st_value;
306
-
res = handler(me, location, v);
307
-
if (res)
308
-
return res;
355
+
if (rela) {
356
+
v = sym->st_value + r.rela->r_addend;
357
+
base = 0;
358
+
r.rela = &r.rela[1];
359
+
} else {
360
+
v = sym->st_value;
361
+
base = *location;
362
+
r.rel = &r.rel[1];
363
+
}
364
+
365
+
err = handler(me, location, base, v, rela);
366
+
if (err)
367
+
goto out;
309
368
}
310
369
370
+
out:
311
371
/*
312
-
* Normally the hi16 list should be deallocated at this point. A
372
+
* Normally the hi16 list should be deallocated at this point. A
313
373
* malformed binary however could contain a series of R_MIPS_HI16
314
-
* relocations not followed by a R_MIPS_LO16 relocation. In that
315
-
* case, free up the list and return an error.
374
+
* relocations not followed by a R_MIPS_LO16 relocation, or if we hit
375
+
* an error processing a reloc we might have gotten here before
376
+
* reaching the R_MIPS_LO16. In either case, free up the list and
377
+
* return an error.
316
378
*/
317
379
if (me->arch.r_mips_hi16_list) {
318
380
free_relocation_chain(me->arch.r_mips_hi16_list);
319
381
me->arch.r_mips_hi16_list = NULL;
320
-
321
-
return -ENOEXEC;
382
+
err = err ?: -ENOEXEC;
322
383
}
323
384
324
-
return 0;
385
+
return err;
325
386
}
387
+
388
+
int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
389
+
unsigned int symindex, unsigned int relsec,
390
+
struct module *me)
391
+
{
392
+
return __apply_relocate(sechdrs, strtab, symindex, relsec, me, false);
393
+
}
394
+
395
+
#ifdef CONFIG_MODULES_USE_ELF_RELA
396
+
int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
397
+
unsigned int symindex, unsigned int relsec,
398
+
struct module *me)
399
+
{
400
+
return __apply_relocate(sechdrs, strtab, symindex, relsec, me, true);
401
+
}
402
+
#endif /* CONFIG_MODULES_USE_ELF_RELA */
326
403
327
404
/* Given an address, look for it in the module exception tables. */
328
405
const struct exception_table_entry *search_module_dbetables(unsigned long addr)
+10
-4
arch/mips/kernel/perf_event_mipsxx.c
+10
-4
arch/mips/kernel/perf_event_mipsxx.c
···
814
814
[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
815
815
};
816
816
817
-
static const struct mips_perf_event i6400_event_map[PERF_COUNT_HW_MAX] = {
817
+
static const struct mips_perf_event i6x00_event_map[PERF_COUNT_HW_MAX] = {
818
818
[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD },
819
819
[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD },
820
820
/* These only count dcache, not icache */
···
1014
1014
},
1015
1015
};
1016
1016
1017
-
static const struct mips_perf_event i6400_cache_map
1017
+
static const struct mips_perf_event i6x00_cache_map
1018
1018
[PERF_COUNT_HW_CACHE_MAX]
1019
1019
[PERF_COUNT_HW_CACHE_OP_MAX]
1020
1020
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
···
1610
1610
#endif
1611
1611
break;
1612
1612
case CPU_I6400:
1613
+
case CPU_I6500:
1613
1614
/* 8-bit event numbers */
1614
1615
base_id = config & 0xff;
1615
1616
raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
···
1771
1770
break;
1772
1771
case CPU_I6400:
1773
1772
mipspmu.name = "mips/I6400";
1774
-
mipspmu.general_event_map = &i6400_event_map;
1775
-
mipspmu.cache_event_map = &i6400_cache_map;
1773
+
mipspmu.general_event_map = &i6x00_event_map;
1774
+
mipspmu.cache_event_map = &i6x00_cache_map;
1775
+
break;
1776
+
case CPU_I6500:
1777
+
mipspmu.name = "mips/I6500";
1778
+
mipspmu.general_event_map = &i6x00_event_map;
1779
+
mipspmu.cache_event_map = &i6x00_cache_map;
1776
1780
break;
1777
1781
case CPU_1004K:
1778
1782
mipspmu.name = "mips/1004K";
+2
-1
arch/mips/kernel/proc.c
+2
-1
arch/mips/kernel/proc.c
···
83
83
}
84
84
85
85
seq_printf(m, "isa\t\t\t:");
86
-
if (cpu_has_mips_r1)
86
+
if (cpu_has_mips_1)
87
87
seq_printf(m, " mips1");
88
88
if (cpu_has_mips_2)
89
89
seq_printf(m, "%s", " mips2");
···
109
109
110
110
seq_printf(m, "ASEs implemented\t:");
111
111
if (cpu_has_mips16) seq_printf(m, "%s", " mips16");
112
+
if (cpu_has_mips16e2) seq_printf(m, "%s", " mips16e2");
112
113
if (cpu_has_mdmx) seq_printf(m, "%s", " mdmx");
113
114
if (cpu_has_mips3d) seq_printf(m, "%s", " mips3d");
114
115
if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips");
+28
-3
arch/mips/kernel/ptrace.c
+28
-3
arch/mips/kernel/ptrace.c
···
868
868
tracehook_report_syscall_entry(regs))
869
869
return -1;
870
870
871
-
if (secure_computing(NULL) == -1)
872
-
return -1;
871
+
#ifdef CONFIG_SECCOMP
872
+
if (unlikely(test_thread_flag(TIF_SECCOMP))) {
873
+
int ret, i;
874
+
struct seccomp_data sd;
875
+
876
+
sd.nr = syscall;
877
+
sd.arch = syscall_get_arch();
878
+
for (i = 0; i < 6; i++) {
879
+
unsigned long v, r;
880
+
881
+
r = mips_get_syscall_arg(&v, current, regs, i);
882
+
sd.args[i] = r ? 0 : v;
883
+
}
884
+
sd.instruction_pointer = KSTK_EIP(current);
885
+
886
+
ret = __secure_computing(&sd);
887
+
if (ret == -1)
888
+
return ret;
889
+
}
890
+
#endif
873
891
874
892
if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
875
893
trace_sys_enter(regs, regs->regs[2]);
876
894
877
895
audit_syscall_entry(syscall, regs->regs[4], regs->regs[5],
878
896
regs->regs[6], regs->regs[7]);
897
+
898
+
/*
899
+
* Negative syscall numbers are mistaken for rejected syscalls, but
900
+
* won't have had the return value set appropriately, so we do so now.
901
+
*/
902
+
if (syscall < 0)
903
+
syscall_set_return_value(current, regs, -ENOSYS, 0);
879
904
return syscall;
880
905
}
881
906
···
920
895
audit_syscall_exit(regs);
921
896
922
897
if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
923
-
trace_sys_exit(regs, regs->regs[2]);
898
+
trace_sys_exit(regs, regs_return_value(regs));
924
899
925
900
if (test_thread_flag(TIF_SYSCALL_TRACE))
926
901
tracehook_report_syscall_exit(regs, 0);
+1
-1
arch/mips/kernel/scall32-o32.S
+1
-1
arch/mips/kernel/scall32-o32.S
+1
-1
arch/mips/kernel/scall64-64.S
+1
-1
arch/mips/kernel/scall64-64.S
+1
-1
arch/mips/kernel/scall64-n32.S
+1
-1
arch/mips/kernel/scall64-n32.S
+1
-1
arch/mips/kernel/scall64-o32.S
+1
-1
arch/mips/kernel/scall64-o32.S
+40
arch/mips/kernel/setup.c
+40
arch/mips/kernel/setup.c
···
670
670
}
671
671
early_param("mem", early_parse_mem);
672
672
673
+
static int __init early_parse_memmap(char *p)
674
+
{
675
+
char *oldp;
676
+
u64 start_at, mem_size;
677
+
678
+
if (!p)
679
+
return -EINVAL;
680
+
681
+
if (!strncmp(p, "exactmap", 8)) {
682
+
pr_err("\"memmap=exactmap\" invalid on MIPS\n");
683
+
return 0;
684
+
}
685
+
686
+
oldp = p;
687
+
mem_size = memparse(p, &p);
688
+
if (p == oldp)
689
+
return -EINVAL;
690
+
691
+
if (*p == '@') {
692
+
start_at = memparse(p+1, &p);
693
+
add_memory_region(start_at, mem_size, BOOT_MEM_RAM);
694
+
} else if (*p == '#') {
695
+
pr_err("\"memmap=nn#ss\" (force ACPI data) invalid on MIPS\n");
696
+
return -EINVAL;
697
+
} else if (*p == '$') {
698
+
start_at = memparse(p+1, &p);
699
+
add_memory_region(start_at, mem_size, BOOT_MEM_RESERVED);
700
+
} else {
701
+
pr_err("\"memmap\" invalid format!\n");
702
+
return -EINVAL;
703
+
}
704
+
705
+
if (*p == '\0') {
706
+
usermem = 1;
707
+
return 0;
708
+
} else
709
+
return -EINVAL;
710
+
}
711
+
early_param("memmap", early_parse_memmap);
712
+
673
713
#ifdef CONFIG_PROC_VMCORE
674
714
unsigned long setup_elfcorehdr, setup_elfcorehdr_size;
675
715
static int __init early_parse_elfcorehdr(char *p)
+29
-6
arch/mips/kernel/smp-cps.c
+29
-6
arch/mips/kernel/smp-cps.c
···
142
142
143
143
/* Warn the user if the CCA prevents multi-core */
144
144
ncores = mips_cm_numcores();
145
-
if (cca_unsuitable && ncores > 1) {
146
-
pr_warn("Using only one core due to unsuitable CCA 0x%x\n",
147
-
cca);
145
+
if ((cca_unsuitable || cpu_has_dc_aliases) && ncores > 1) {
146
+
pr_warn("Using only one core due to %s%s%s\n",
147
+
cca_unsuitable ? "unsuitable CCA" : "",
148
+
(cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
149
+
cpu_has_dc_aliases ? "dcache aliasing" : "");
148
150
149
151
for_each_present_cpu(c) {
150
152
if (cpu_data[c].core)
···
490
488
{
491
489
unsigned core = cpu_data[cpu].core;
492
490
unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
491
+
ktime_t fail_time;
493
492
unsigned stat;
494
493
int err;
495
494
···
517
514
* state, the latter happening when a JTAG probe is connected
518
515
* in which case the CPC will refuse to power down the core.
519
516
*/
517
+
fail_time = ktime_add_ms(ktime_get(), 2000);
520
518
do {
521
519
mips_cm_lock_other(core, 0);
522
520
mips_cpc_lock_other(core);
···
525
521
stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
526
522
mips_cpc_unlock_other();
527
523
mips_cm_unlock_other();
528
-
} while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 &&
529
-
stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 &&
530
-
stat != CPC_Cx_STAT_CONF_SEQSTATE_U2);
524
+
525
+
if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
526
+
stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
527
+
stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
528
+
break;
529
+
530
+
/*
531
+
* The core ought to have powered down, but didn't &
532
+
* now we don't really know what state it's in. It's
533
+
* likely that its _pwr_up pin has been wired to logic
534
+
* 1 & it powered back up as soon as we powered it
535
+
* down...
536
+
*
537
+
* The best we can do is warn the user & continue in
538
+
* the hope that the core is doing nothing harmful &
539
+
* might behave properly if we online it later.
540
+
*/
541
+
if (WARN(ktime_after(ktime_get(), fail_time),
542
+
"CPU%u hasn't powered down, seq. state %u\n",
543
+
cpu, stat >> CPC_Cx_STAT_CONF_SEQSTATE_SHF))
544
+
break;
545
+
} while (1);
531
546
532
547
/* Indicate the core is powered off */
533
548
bitmap_clear(core_power, core, 1);
+3
arch/mips/kernel/smp.c
+3
arch/mips/kernel/smp.c
+12
-7
arch/mips/kernel/syscall.c
+12
-7
arch/mips/kernel/syscall.c
···
29
29
#include <linux/sched/task_stack.h>
30
30
31
31
#include <asm/asm.h>
32
+
#include <asm/asm-eva.h>
32
33
#include <asm/branch.h>
33
34
#include <asm/cachectl.h>
34
35
#include <asm/cacheflush.h>
···
132
131
__asm__ __volatile__ (
133
132
" .set "MIPS_ISA_ARCH_LEVEL" \n"
134
133
" li %[err], 0 \n"
135
-
"1: ll %[old], (%[addr]) \n"
134
+
"1: \n"
135
+
user_ll("%[old]", "(%[addr])")
136
136
" move %[tmp], %[new] \n"
137
-
"2: sc %[tmp], (%[addr]) \n"
138
-
" bnez %[tmp], 4f \n"
137
+
"2: \n"
138
+
user_sc("%[tmp]", "(%[addr])")
139
+
" beqz %[tmp], 1b \n"
139
140
"3: \n"
140
141
" .insn \n"
141
-
" .subsection 2 \n"
142
-
"4: b 1b \n"
143
-
" .previous \n"
144
-
" \n"
145
142
" .section .fixup,\"ax\" \n"
146
143
"5: li %[err], %[efault] \n"
147
144
" j 3b \n"
···
190
191
/* unreached. Honestly. */
191
192
unreachable();
192
193
}
194
+
195
+
/*
196
+
* mips_atomic_set() normally returns directly via syscall_exit potentially
197
+
* clobbering static registers, so be sure to preserve them.
198
+
*/
199
+
save_static_function(sys_sysmips);
193
200
194
201
SYSCALL_DEFINE3(sysmips, long, cmd, long, arg1, long, arg2)
195
202
{
+141
-80
arch/mips/kernel/unaligned.c
+141
-80
arch/mips/kernel/unaligned.c
···
939
939
* The remaining opcodes are the ones that are really of
940
940
* interest.
941
941
*/
942
-
#ifdef CONFIG_EVA
943
942
case spec3_op:
944
-
/*
945
-
* we can land here only from kernel accessing user memory,
946
-
* so we need to "switch" the address limit to user space, so
947
-
* address check can work properly.
948
-
*/
949
-
seg = get_fs();
950
-
set_fs(USER_DS);
951
-
switch (insn.spec3_format.func) {
952
-
case lhe_op:
953
-
if (!access_ok(VERIFY_READ, addr, 2)) {
954
-
set_fs(seg);
955
-
goto sigbus;
943
+
if (insn.dsp_format.func == lx_op) {
944
+
switch (insn.dsp_format.op) {
945
+
case lwx_op:
946
+
if (!access_ok(VERIFY_READ, addr, 4))
947
+
goto sigbus;
948
+
LoadW(addr, value, res);
949
+
if (res)
950
+
goto fault;
951
+
compute_return_epc(regs);
952
+
regs->regs[insn.dsp_format.rd] = value;
953
+
break;
954
+
case lhx_op:
955
+
if (!access_ok(VERIFY_READ, addr, 2))
956
+
goto sigbus;
957
+
LoadHW(addr, value, res);
958
+
if (res)
959
+
goto fault;
960
+
compute_return_epc(regs);
961
+
regs->regs[insn.dsp_format.rd] = value;
962
+
break;
963
+
default:
964
+
goto sigill;
956
965
}
957
-
LoadHWE(addr, value, res);
958
-
if (res) {
959
-
set_fs(seg);
960
-
goto fault;
961
-
}
962
-
compute_return_epc(regs);
963
-
regs->regs[insn.spec3_format.rt] = value;
964
-
break;
965
-
case lwe_op:
966
-
if (!access_ok(VERIFY_READ, addr, 4)) {
967
-
set_fs(seg);
968
-
goto sigbus;
969
-
}
970
-
LoadWE(addr, value, res);
971
-
if (res) {
972
-
set_fs(seg);
973
-
goto fault;
974
-
}
975
-
compute_return_epc(regs);
976
-
regs->regs[insn.spec3_format.rt] = value;
977
-
break;
978
-
case lhue_op:
979
-
if (!access_ok(VERIFY_READ, addr, 2)) {
980
-
set_fs(seg);
981
-
goto sigbus;
982
-
}
983
-
LoadHWUE(addr, value, res);
984
-
if (res) {
985
-
set_fs(seg);
986
-
goto fault;
987
-
}
988
-
compute_return_epc(regs);
989
-
regs->regs[insn.spec3_format.rt] = value;
990
-
break;
991
-
case she_op:
992
-
if (!access_ok(VERIFY_WRITE, addr, 2)) {
993
-
set_fs(seg);
994
-
goto sigbus;
995
-
}
996
-
compute_return_epc(regs);
997
-
value = regs->regs[insn.spec3_format.rt];
998
-
StoreHWE(addr, value, res);
999
-
if (res) {
1000
-
set_fs(seg);
1001
-
goto fault;
1002
-
}
1003
-
break;
1004
-
case swe_op:
1005
-
if (!access_ok(VERIFY_WRITE, addr, 4)) {
1006
-
set_fs(seg);
1007
-
goto sigbus;
1008
-
}
1009
-
compute_return_epc(regs);
1010
-
value = regs->regs[insn.spec3_format.rt];
1011
-
StoreWE(addr, value, res);
1012
-
if (res) {
1013
-
set_fs(seg);
1014
-
goto fault;
1015
-
}
1016
-
break;
1017
-
default:
1018
-
set_fs(seg);
1019
-
goto sigill;
1020
966
}
1021
-
set_fs(seg);
1022
-
break;
967
+
#ifdef CONFIG_EVA
968
+
else {
969
+
/*
970
+
* we can land here only from kernel accessing user
971
+
* memory, so we need to "switch" the address limit to
972
+
* user space, so that address check can work properly.
973
+
*/
974
+
seg = get_fs();
975
+
set_fs(USER_DS);
976
+
switch (insn.spec3_format.func) {
977
+
case lhe_op:
978
+
if (!access_ok(VERIFY_READ, addr, 2)) {
979
+
set_fs(seg);
980
+
goto sigbus;
981
+
}
982
+
LoadHWE(addr, value, res);
983
+
if (res) {
984
+
set_fs(seg);
985
+
goto fault;
986
+
}
987
+
compute_return_epc(regs);
988
+
regs->regs[insn.spec3_format.rt] = value;
989
+
break;
990
+
case lwe_op:
991
+
if (!access_ok(VERIFY_READ, addr, 4)) {
992
+
set_fs(seg);
993
+
goto sigbus;
994
+
}
995
+
LoadWE(addr, value, res);
996
+
if (res) {
997
+
set_fs(seg);
998
+
goto fault;
999
+
}
1000
+
compute_return_epc(regs);
1001
+
regs->regs[insn.spec3_format.rt] = value;
1002
+
break;
1003
+
case lhue_op:
1004
+
if (!access_ok(VERIFY_READ, addr, 2)) {
1005
+
set_fs(seg);
1006
+
goto sigbus;
1007
+
}
1008
+
LoadHWUE(addr, value, res);
1009
+
if (res) {
1010
+
set_fs(seg);
1011
+
goto fault;
1012
+
}
1013
+
compute_return_epc(regs);
1014
+
regs->regs[insn.spec3_format.rt] = value;
1015
+
break;
1016
+
case she_op:
1017
+
if (!access_ok(VERIFY_WRITE, addr, 2)) {
1018
+
set_fs(seg);
1019
+
goto sigbus;
1020
+
}
1021
+
compute_return_epc(regs);
1022
+
value = regs->regs[insn.spec3_format.rt];
1023
+
StoreHWE(addr, value, res);
1024
+
if (res) {
1025
+
set_fs(seg);
1026
+
goto fault;
1027
+
}
1028
+
break;
1029
+
case swe_op:
1030
+
if (!access_ok(VERIFY_WRITE, addr, 4)) {
1031
+
set_fs(seg);
1032
+
goto sigbus;
1033
+
}
1034
+
compute_return_epc(regs);
1035
+
value = regs->regs[insn.spec3_format.rt];
1036
+
StoreWE(addr, value, res);
1037
+
if (res) {
1038
+
set_fs(seg);
1039
+
goto fault;
1040
+
}
1041
+
break;
1042
+
default:
1043
+
set_fs(seg);
1044
+
goto sigill;
1045
+
}
1046
+
set_fs(seg);
1047
+
}
1023
1048
#endif
1049
+
break;
1024
1050
case lh_op:
1025
1051
if (!access_ok(VERIFY_READ, addr, 2))
1026
1052
goto sigbus;
···
2010
1984
u16 __user *pc16;
2011
1985
unsigned long origpc;
2012
1986
union mips16e_instruction mips16inst, oldinst;
1987
+
unsigned int opcode;
1988
+
int extended = 0;
2013
1989
2014
1990
origpc = regs->cp0_epc;
2015
1991
orig31 = regs->regs[31];
···
2024
1996
2025
1997
/* skip EXTEND instruction */
2026
1998
if (mips16inst.ri.opcode == MIPS16e_extend_op) {
1999
+
extended = 1;
2027
2000
pc16++;
2028
2001
__get_user(mips16inst.full, pc16);
2029
2002
} else if (delay_slot(regs)) {
···
2037
2008
goto sigbus;
2038
2009
}
2039
2010
2040
-
switch (mips16inst.ri.opcode) {
2011
+
opcode = mips16inst.ri.opcode;
2012
+
switch (opcode) {
2041
2013
case MIPS16e_i64_op: /* I64 or RI64 instruction */
2042
2014
switch (mips16inst.i64.func) { /* I64/RI64 func field check */
2043
2015
case MIPS16e_ldpc_func:
···
2058
2028
goto sigbus;
2059
2029
2060
2030
case MIPS16e_swsp_op:
2031
+
reg = reg16to32[mips16inst.ri.rx];
2032
+
if (extended && cpu_has_mips16e2)
2033
+
switch (mips16inst.ri.imm >> 5) {
2034
+
case 0: /* SWSP */
2035
+
case 1: /* SWGP */
2036
+
break;
2037
+
case 2: /* SHGP */
2038
+
opcode = MIPS16e_sh_op;
2039
+
break;
2040
+
default:
2041
+
goto sigbus;
2042
+
}
2043
+
break;
2044
+
2061
2045
case MIPS16e_lwpc_op:
2046
+
reg = reg16to32[mips16inst.ri.rx];
2047
+
break;
2048
+
2062
2049
case MIPS16e_lwsp_op:
2063
2050
reg = reg16to32[mips16inst.ri.rx];
2051
+
if (extended && cpu_has_mips16e2)
2052
+
switch (mips16inst.ri.imm >> 5) {
2053
+
case 0: /* LWSP */
2054
+
case 1: /* LWGP */
2055
+
break;
2056
+
case 2: /* LHGP */
2057
+
opcode = MIPS16e_lh_op;
2058
+
break;
2059
+
case 4: /* LHUGP */
2060
+
opcode = MIPS16e_lhu_op;
2061
+
break;
2062
+
default:
2063
+
goto sigbus;
2064
+
}
2064
2065
break;
2065
2066
2066
2067
case MIPS16e_i8_op:
···
2105
2044
break;
2106
2045
}
2107
2046
2108
-
switch (mips16inst.ri.opcode) {
2047
+
switch (opcode) {
2109
2048
2110
2049
case MIPS16e_lb_op:
2111
2050
case MIPS16e_lbu_op:
+3
arch/mips/lib/memcpy.S
+3
arch/mips/lib/memcpy.S
+9
-3
arch/mips/loongson64/common/env.c
+9
-3
arch/mips/loongson64/common/env.c
···
90
90
91
91
cpu_clock_freq = ecpu->cpu_clock_freq;
92
92
loongson_sysconf.cputype = ecpu->cputype;
93
-
if (ecpu->cputype == Loongson_3A) {
93
+
switch (ecpu->cputype) {
94
+
case Legacy_3A:
95
+
case Loongson_3A:
94
96
loongson_sysconf.cores_per_node = 4;
95
97
loongson_sysconf.cores_per_package = 4;
96
98
smp_group[0] = 0x900000003ff01000;
···
113
111
loongson_freqctrl[3] = 0x900030001fe001d0;
114
112
loongson_sysconf.ht_control_base = 0x90000EFDFB000000;
115
113
loongson_sysconf.workarounds = WORKAROUND_CPUFREQ;
116
-
} else if (ecpu->cputype == Loongson_3B) {
114
+
break;
115
+
case Legacy_3B:
116
+
case Loongson_3B:
117
117
loongson_sysconf.cores_per_node = 4; /* One chip has 2 nodes */
118
118
loongson_sysconf.cores_per_package = 8;
119
119
smp_group[0] = 0x900000003ff01000;
···
136
132
loongson_freqctrl[3] = 0x900060001fe001d0;
137
133
loongson_sysconf.ht_control_base = 0x90001EFDFB000000;
138
134
loongson_sysconf.workarounds = WORKAROUND_CPUHOTPLUG;
139
-
} else {
135
+
break;
136
+
default:
140
137
loongson_sysconf.cores_per_node = 1;
141
138
loongson_sysconf.cores_per_package = 1;
142
139
loongson_chipcfg[0] = 0x900000001fe00180;
···
198
193
break;
199
194
case PRID_REV_LOONGSON3A_R1:
200
195
case PRID_REV_LOONGSON3A_R2:
196
+
case PRID_REV_LOONGSON3A_R3:
201
197
cpu_clock_freq = 900000000;
202
198
break;
203
199
case PRID_REV_LOONGSON3B_R1:
+13
arch/mips/loongson64/common/init.c
+13
arch/mips/loongson64/common/init.c
···
10
10
11
11
#include <linux/bootmem.h>
12
12
#include <asm/bootinfo.h>
13
+
#include <asm/traps.h>
13
14
#include <asm/smp-ops.h>
15
+
#include <asm/cacheflush.h>
14
16
15
17
#include <loongson.h>
16
18
17
19
/* Loongson CPU address windows config space base address */
18
20
unsigned long __maybe_unused _loongson_addrwincfg_base;
21
+
22
+
static void __init mips_nmi_setup(void)
23
+
{
24
+
void *base;
25
+
extern char except_vec_nmi;
26
+
27
+
base = (void *)(CAC_BASE + 0x380);
28
+
memcpy(base, &except_vec_nmi, 0x80);
29
+
flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
30
+
}
19
31
20
32
void __init prom_init(void)
21
33
{
···
52
40
/*init the uart base address */
53
41
prom_init_uart_base();
54
42
register_smp_ops(&loongson3_smp_ops);
43
+
board_nmi_handler_setup = mips_nmi_setup;
55
44
}
56
45
57
46
void __init prom_free_prom_memory(void)
+57
-1
arch/mips/loongson64/loongson-3/irq.c
+57
-1
arch/mips/loongson64/loongson-3/irq.c
···
9
9
10
10
#include "smp.h"
11
11
12
+
extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
13
+
14
+
unsigned int irq_cpu[16] = {[0 ... 15] = -1};
12
15
unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
16
+
unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12;
17
+
18
+
int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
19
+
bool force)
20
+
{
21
+
unsigned int cpu;
22
+
struct cpumask new_affinity;
23
+
24
+
/* I/O devices are connected on package-0 */
25
+
cpumask_copy(&new_affinity, affinity);
26
+
for_each_cpu(cpu, affinity)
27
+
if (cpu_data[cpu].package > 0)
28
+
cpumask_clear_cpu(cpu, &new_affinity);
29
+
30
+
if (cpumask_empty(&new_affinity))
31
+
return -EINVAL;
32
+
33
+
cpumask_copy(d->common->affinity, &new_affinity);
34
+
35
+
return IRQ_SET_MASK_OK_NOCOPY;
36
+
}
13
37
14
38
static void ht_irqdispatch(void)
15
39
{
16
40
unsigned int i, irq;
41
+
struct irq_data *irqd;
42
+
struct cpumask affinity;
17
43
18
44
irq = LOONGSON_HT1_INT_VECTOR(0);
19
45
LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
20
46
21
47
for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
22
-
if (irq & (0x1 << ht_irq[i]))
48
+
if (!(irq & (0x1 << ht_irq[i])))
49
+
continue;
50
+
51
+
/* handled by local core */
52
+
if (local_irq & (0x1 << ht_irq[i])) {
23
53
do_IRQ(ht_irq[i]);
54
+
continue;
55
+
}
56
+
57
+
irqd = irq_get_irq_data(ht_irq[i]);
58
+
cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
59
+
if (cpumask_empty(&affinity)) {
60
+
do_IRQ(ht_irq[i]);
61
+
continue;
62
+
}
63
+
64
+
irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
65
+
if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
66
+
irq_cpu[ht_irq[i]] = cpumask_first(&affinity);
67
+
68
+
if (irq_cpu[ht_irq[i]] == 0) {
69
+
do_IRQ(ht_irq[i]);
70
+
continue;
71
+
}
72
+
73
+
/* balanced by other cores */
74
+
loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
24
75
}
25
76
}
26
77
···
171
120
172
121
void __init mach_init_irq(void)
173
122
{
123
+
struct irq_chip *chip;
124
+
174
125
clear_c0_status(ST0_IM | ST0_BEV);
175
126
176
127
irq_router_init();
177
128
mips_cpu_irq_init();
178
129
init_i8259_irqs();
130
+
chip = irq_get_chip(I8259A_IRQ_BASE);
131
+
chip->irq_set_affinity = plat_set_irq_affinity;
132
+
179
133
irq_set_chip_and_handler(LOONGSON_UART_IRQ,
180
134
&loongson_irq_chip, handle_level_irq);
181
135
+20
-3
arch/mips/loongson64/loongson-3/smp.c
+20
-3
arch/mips/loongson64/loongson-3/smp.c
···
254
254
loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(i)]);
255
255
}
256
256
257
+
#define IPI_IRQ_OFFSET 6
258
+
259
+
void loongson3_send_irq_by_ipi(int cpu, int irqs)
260
+
{
261
+
loongson3_ipi_write32(irqs << IPI_IRQ_OFFSET, ipi_set0_regs[cpu_logical_map(cpu)]);
262
+
}
263
+
257
264
void loongson3_ipi_interrupt(struct pt_regs *regs)
258
265
{
259
266
int i, cpu = smp_processor_id();
260
-
unsigned int action, c0count;
267
+
unsigned int action, c0count, irqs;
261
268
262
269
/* Load the ipi register to figure out what we're supposed to do */
263
270
action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]);
271
+
irqs = action >> IPI_IRQ_OFFSET;
264
272
265
273
/* Clear the ipi register to clear the interrupt */
266
274
loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu_logical_map(cpu)]);
···
289
281
for (i = 1; i < nr_cpu_ids; i++)
290
282
core0_c0count[i] = c0count;
291
283
__wbflush(); /* Let others see the result ASAP */
284
+
}
285
+
286
+
if (irqs) {
287
+
int irq;
288
+
while ((irq = ffs(irqs))) {
289
+
do_IRQ(irq-1);
290
+
irqs &= ~(1<<(irq-1));
291
+
}
292
292
}
293
293
}
294
294
···
519
503
: "a1");
520
504
}
521
505
522
-
static void loongson3a_r2_play_dead(int *state_addr)
506
+
static void loongson3a_r2r3_play_dead(int *state_addr)
523
507
{
524
508
register int val;
525
509
register long cpuid, core, node, count;
···
680
664
(void *)CKSEG1ADDR((unsigned long)loongson3a_r1_play_dead);
681
665
break;
682
666
case PRID_REV_LOONGSON3A_R2:
667
+
case PRID_REV_LOONGSON3A_R3:
683
668
play_dead_at_ckseg1 =
684
-
(void *)CKSEG1ADDR((unsigned long)loongson3a_r2_play_dead);
669
+
(void *)CKSEG1ADDR((unsigned long)loongson3a_r2r3_play_dead);
685
670
break;
686
671
case PRID_REV_LOONGSON3B_R1:
687
672
case PRID_REV_LOONGSON3B_R2:
+40
-3
arch/mips/math-emu/cp1emu.c
+40
-3
arch/mips/math-emu/cp1emu.c
···
1142
1142
1143
1143
case mfhc_op:
1144
1144
if (!cpu_has_mips_r2_r6)
1145
-
goto sigill;
1145
+
return SIGILL;
1146
1146
1147
1147
/* copregister rd -> gpr[rt] */
1148
1148
if (MIPSInst_RT(ir) != 0) {
···
1153
1153
1154
1154
case mthc_op:
1155
1155
if (!cpu_has_mips_r2_r6)
1156
-
goto sigill;
1156
+
return SIGILL;
1157
1157
1158
1158
/* copregister rd <- gpr[rt] */
1159
1159
SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
···
1376
1376
xcp->regs[MIPSInst_RS(ir)];
1377
1377
break;
1378
1378
default:
1379
-
sigill:
1380
1379
return SIGILL;
1381
1380
}
1382
1381
···
2523
2524
return 0;
2524
2525
}
2525
2526
2527
+
/*
2528
+
* Emulate FPU instructions.
2529
+
*
2530
+
* If we use FPU hardware, then we have been typically called to handle
2531
+
* an unimplemented operation, such as where an operand is a NaN or
2532
+
* denormalized. In that case exit the emulation loop after a single
2533
+
* iteration so as to let hardware execute any subsequent instructions.
2534
+
*
2535
+
* If we have no FPU hardware or it has been disabled, then continue
2536
+
* emulating floating-point instructions until one of these conditions
2537
+
* has occurred:
2538
+
*
2539
+
* - a non-FPU instruction has been encountered,
2540
+
*
2541
+
* - an attempt to emulate has ended with a signal,
2542
+
*
2543
+
* - the ISA mode has been switched.
2544
+
*
2545
+
* We need to terminate the emulation loop if we got switched to the
2546
+
* MIPS16 mode, whether supported or not, so that we do not attempt
2547
+
* to emulate a MIPS16 instruction as a regular MIPS FPU instruction.
2548
+
* Similarly if we got switched to the microMIPS mode and only the
2549
+
* regular MIPS mode is supported, so that we do not attempt to emulate
2550
+
* a microMIPS instruction as a regular MIPS FPU instruction. Or if
2551
+
* we got switched to the regular MIPS mode and only the microMIPS mode
2552
+
* is supported, so that we do not attempt to emulate a regular MIPS
2553
+
* instruction that should cause an Address Error exception instead.
2554
+
* For simplicity we always terminate upon an ISA mode switch.
2555
+
*/
2526
2556
int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2527
2557
int has_fpu, void *__user *fault_addr)
2528
2558
{
···
2636
2608
if (has_fpu)
2637
2609
break;
2638
2610
if (sig)
2611
+
break;
2612
+
/*
2613
+
* We have to check for the ISA bit explicitly here,
2614
+
* because `get_isa16_mode' may return 0 if support
2615
+
* for code compression has been globally disabled,
2616
+
* or otherwise we may produce the wrong signal or
2617
+
* even proceed successfully where we must not.
2618
+
*/
2619
+
if ((xcp->cp0_epc ^ prevepc) & 0x1)
2639
2620
break;
2640
2621
2641
2622
cond_resched();
+2
arch/mips/mm/c-r4k.c
+2
arch/mips/mm/c-r4k.c
···
1453
1453
case CPU_20KC:
1454
1454
case CPU_25KF:
1455
1455
case CPU_I6400:
1456
+
case CPU_I6500:
1456
1457
case CPU_SB1:
1457
1458
case CPU_SB1A:
1458
1459
case CPU_XLR:
···
1513
1512
1514
1513
case CPU_ALCHEMY:
1515
1514
case CPU_I6400:
1515
+
case CPU_I6500:
1516
1516
c->icache.flags |= MIPS_CACHE_IC_F_DC;
1517
1517
break;
1518
1518
+38
-3
arch/mips/mm/tlbex.c
+38
-3
arch/mips/mm/tlbex.c
···
153
153
*/
154
154
static int m4kc_tlbp_war(void)
155
155
{
156
-
return (current_cpu_data.processor_id & 0xffff00) ==
157
-
(PRID_COMP_MIPS | PRID_IMP_4KC);
156
+
return current_cpu_type() == CPU_4KC;
158
157
}
159
158
160
159
/* Handle labels (which must be positive integers). */
···
2014
2015
}
2015
2016
#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
2016
2017
2018
+
static bool cpu_has_tlbex_tlbp_race(void)
2019
+
{
2020
+
/*
2021
+
* When a Hardware Table Walker is running it can replace TLB entries
2022
+
* at any time, leading to a race between it & the CPU.
2023
+
*/
2024
+
if (cpu_has_htw)
2025
+
return true;
2026
+
2027
+
/*
2028
+
* If the CPU shares FTLB RAM with its siblings then our entry may be
2029
+
* replaced at any time by a sibling performing a write to the FTLB.
2030
+
*/
2031
+
if (cpu_has_shared_ftlb_ram)
2032
+
return true;
2033
+
2034
+
/* In all other cases there ought to be no race condition to handle */
2035
+
return false;
2036
+
}
2037
+
2017
2038
/*
2018
2039
* R4000 style TLB load/store/modify handlers.
2019
2040
*/
···
2070
2051
iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
2071
2052
if (!m4kc_tlbp_war()) {
2072
2053
build_tlb_probe_entry(p);
2073
-
if (cpu_has_htw) {
2054
+
if (cpu_has_tlbex_tlbp_race()) {
2074
2055
/* race condition happens, leaving */
2075
2056
uasm_i_ehb(p);
2076
2057
uasm_i_mfc0(p, wr.r3, C0_INDEX);
···
2144
2125
}
2145
2126
uasm_i_nop(&p);
2146
2127
2128
+
/*
2129
+
* Warn if something may race with us & replace the TLB entry
2130
+
* before we read it here. Everything with such races should
2131
+
* also have dedicated RiXi exception handlers, so this
2132
+
* shouldn't be hit.
2133
+
*/
2134
+
WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
2135
+
2147
2136
uasm_i_tlbr(&p);
2148
2137
2149
2138
switch (current_cpu_type()) {
···
2218
2191
uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2219
2192
}
2220
2193
uasm_i_nop(&p);
2194
+
2195
+
/*
2196
+
* Warn if something may race with us & replace the TLB entry
2197
+
* before we read it here. Everything with such races should
2198
+
* also have dedicated RiXi exception handlers, so this
2199
+
* shouldn't be hit.
2200
+
*/
2201
+
WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
2221
2202
2222
2203
uasm_i_tlbr(&p);
2223
2204
+92
-96
arch/mips/mm/uasm-micromips.c
+92
-96
arch/mips/mm/uasm-micromips.c
···
40
40
41
41
#include "uasm.c"
42
42
43
-
static struct insn insn_table_MM[] = {
44
-
{ insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD },
45
-
{ insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
46
-
{ insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD },
47
-
{ insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
48
-
{ insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
49
-
{ insn_beql, 0, 0 },
50
-
{ insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM },
51
-
{ insn_bgezl, 0, 0 },
52
-
{ insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM },
53
-
{ insn_bltzl, 0, 0 },
54
-
{ insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM },
55
-
{ insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM },
56
-
{ insn_cfc1, M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS },
57
-
{ insn_cfcmsa, M(mm_pool32s_op, 0, msa_cfc_op, 0, 0, mm_32s_elm_op), RD | RE },
58
-
{ insn_ctc1, M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS },
59
-
{ insn_ctcmsa, M(mm_pool32s_op, 0, msa_ctc_op, 0, 0, mm_32s_elm_op), RD | RE },
60
-
{ insn_daddu, 0, 0 },
61
-
{ insn_daddiu, 0, 0 },
62
-
{ insn_di, M(mm_pool32a_op, 0, 0, 0, mm_di_op, mm_pool32axf_op), RS },
63
-
{ insn_divu, M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS },
64
-
{ insn_dmfc0, 0, 0 },
65
-
{ insn_dmtc0, 0, 0 },
66
-
{ insn_dsll, 0, 0 },
67
-
{ insn_dsll32, 0, 0 },
68
-
{ insn_dsra, 0, 0 },
69
-
{ insn_dsrl, 0, 0 },
70
-
{ insn_dsrl32, 0, 0 },
71
-
{ insn_drotr, 0, 0 },
72
-
{ insn_drotr32, 0, 0 },
73
-
{ insn_dsubu, 0, 0 },
74
-
{ insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 },
75
-
{ insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE },
76
-
{ insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE },
77
-
{ insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM },
78
-
{ insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM },
79
-
{ insn_jalr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS },
80
-
{ insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS },
81
-
{ insn_lb, M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
82
-
{ insn_ld, 0, 0 },
83
-
{ insn_lh, M(mm_lh32_op, 0, 0, 0, 0, 0), RS | RS | SIMM },
84
-
{ insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM },
85
-
{ insn_lld, 0, 0 },
86
-
{ insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM },
87
-
{ insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
88
-
{ insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD },
89
-
{ insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS },
90
-
{ insn_mflo, M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS },
91
-
{ insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },
92
-
{ insn_mthi, M(mm_pool32a_op, 0, 0, 0, mm_mthi32_op, mm_pool32axf_op), RS },
93
-
{ insn_mtlo, M(mm_pool32a_op, 0, 0, 0, mm_mtlo32_op, mm_pool32axf_op), RS },
94
-
{ insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD },
95
-
{ insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },
96
-
{ insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
97
-
{ insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM },
98
-
{ insn_rfe, 0, 0 },
99
-
{ insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM },
100
-
{ insn_scd, 0, 0 },
101
-
{ insn_sd, 0, 0 },
102
-
{ insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD },
103
-
{ insn_sllv, M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD },
104
-
{ insn_slt, M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD },
105
-
{ insn_sltiu, M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
106
-
{ insn_sltu, M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD },
107
-
{ insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD },
108
-
{ insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD },
109
-
{ insn_srlv, M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD },
110
-
{ insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD },
111
-
{ insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD },
112
-
{ insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
113
-
{ insn_sync, M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS },
114
-
{ insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 },
115
-
{ insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 },
116
-
{ insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 },
117
-
{ insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 },
118
-
{ insn_wait, M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM },
119
-
{ insn_wsbh, M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS },
120
-
{ insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD },
121
-
{ insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
122
-
{ insn_dins, 0, 0 },
123
-
{ insn_dinsm, 0, 0 },
124
-
{ insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM},
125
-
{ insn_bbit0, 0, 0 },
126
-
{ insn_bbit1, 0, 0 },
127
-
{ insn_lwx, 0, 0 },
128
-
{ insn_ldx, 0, 0 },
129
-
{ insn_invalid, 0, 0 }
43
+
static const struct insn const insn_table_MM[insn_invalid] = {
44
+
[insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
45
+
[insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
46
+
[insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
47
+
[insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
48
+
[insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
49
+
[insn_beql] = {0, 0},
50
+
[insn_bgez] = {M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM},
51
+
[insn_bgezl] = {0, 0},
52
+
[insn_bltz] = {M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM},
53
+
[insn_bltzl] = {0, 0},
54
+
[insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM},
55
+
[insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM},
56
+
[insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS},
57
+
[insn_cfcmsa] = {M(mm_pool32s_op, 0, msa_cfc_op, 0, 0, mm_32s_elm_op), RD | RE},
58
+
[insn_ctc1] = {M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS},
59
+
[insn_ctcmsa] = {M(mm_pool32s_op, 0, msa_ctc_op, 0, 0, mm_32s_elm_op), RD | RE},
60
+
[insn_daddu] = {0, 0},
61
+
[insn_daddiu] = {0, 0},
62
+
[insn_di] = {M(mm_pool32a_op, 0, 0, 0, mm_di_op, mm_pool32axf_op), RS},
63
+
[insn_divu] = {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS},
64
+
[insn_dmfc0] = {0, 0},
65
+
[insn_dmtc0] = {0, 0},
66
+
[insn_dsll] = {0, 0},
67
+
[insn_dsll32] = {0, 0},
68
+
[insn_dsra] = {0, 0},
69
+
[insn_dsrl] = {0, 0},
70
+
[insn_dsrl32] = {0, 0},
71
+
[insn_drotr] = {0, 0},
72
+
[insn_drotr32] = {0, 0},
73
+
[insn_dsubu] = {0, 0},
74
+
[insn_eret] = {M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0},
75
+
[insn_ins] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE},
76
+
[insn_ext] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE},
77
+
[insn_j] = {M(mm_j32_op, 0, 0, 0, 0, 0), JIMM},
78
+
[insn_jal] = {M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM},
79
+
[insn_jalr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS},
80
+
[insn_jr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS},
81
+
[insn_lb] = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
82
+
[insn_ld] = {0, 0},
83
+
[insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RS | RS | SIMM},
84
+
[insn_ll] = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM},
85
+
[insn_lld] = {0, 0},
86
+
[insn_lui] = {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM},
87
+
[insn_lw] = {M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
88
+
[insn_mfc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD},
89
+
[insn_mfhi] = {M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS},
90
+
[insn_mflo] = {M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS},
91
+
[insn_mtc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD},
92
+
[insn_mthi] = {M(mm_pool32a_op, 0, 0, 0, mm_mthi32_op, mm_pool32axf_op), RS},
93
+
[insn_mtlo] = {M(mm_pool32a_op, 0, 0, 0, mm_mtlo32_op, mm_pool32axf_op), RS},
94
+
[insn_mul] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD},
95
+
[insn_or] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD},
96
+
[insn_ori] = {M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
97
+
[insn_pref] = {M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM},
98
+
[insn_rfe] = {0, 0},
99
+
[insn_sc] = {M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM},
100
+
[insn_scd] = {0, 0},
101
+
[insn_sd] = {0, 0},
102
+
[insn_sll] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD},
103
+
[insn_sllv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD},
104
+
[insn_slt] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD},
105
+
[insn_sltiu] = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
106
+
[insn_sltu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD},
107
+
[insn_sra] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD},
108
+
[insn_srl] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD},
109
+
[insn_srlv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD},
110
+
[insn_rotr] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD},
111
+
[insn_subu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD},
112
+
[insn_sw] = {M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
113
+
[insn_sync] = {M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS},
114
+
[insn_tlbp] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0},
115
+
[insn_tlbr] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0},
116
+
[insn_tlbwi] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0},
117
+
[insn_tlbwr] = {M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0},
118
+
[insn_wait] = {M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM},
119
+
[insn_wsbh] = {M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS},
120
+
[insn_xor] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD},
121
+
[insn_xori] = {M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
122
+
[insn_dins] = {0, 0},
123
+
[insn_dinsm] = {0, 0},
124
+
[insn_syscall] = {M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM},
125
+
[insn_bbit0] = {0, 0},
126
+
[insn_bbit1] = {0, 0},
127
+
[insn_lwx] = {0, 0},
128
+
[insn_ldx] = {0, 0},
130
129
};
131
130
132
131
#undef M
···
155
156
*/
156
157
static void build_insn(u32 **buf, enum opcode opc, ...)
157
158
{
158
-
struct insn *ip = NULL;
159
-
unsigned int i;
159
+
const struct insn *ip;
160
160
va_list ap;
161
161
u32 op;
162
162
163
-
for (i = 0; insn_table_MM[i].opcode != insn_invalid; i++)
164
-
if (insn_table_MM[i].opcode == opc) {
165
-
ip = &insn_table_MM[i];
166
-
break;
167
-
}
168
-
169
-
if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
163
+
if (opc < 0 || opc >= insn_invalid ||
164
+
(opc == insn_daddiu && r4k_daddiu_bug()) ||
165
+
(insn_table_MM[opc].match == 0 && insn_table_MM[opc].fields == 0))
170
166
panic("Unsupported Micro-assembler instruction %d", opc);
167
+
168
+
ip = &insn_table_MM[opc];
171
169
172
170
op = ip->match;
173
171
va_start(ap, opc);
+127
-111
arch/mips/mm/uasm-mips.c
+127
-111
arch/mips/mm/uasm-mips.c
···
48
48
49
49
#include "uasm.c"
50
50
51
-
static struct insn insn_table[] = {
52
-
{ insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
53
-
{ insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
54
-
{ insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
55
-
{ insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
56
-
{ insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
57
-
{ insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
58
-
{ insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
59
-
{ insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
60
-
{ insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
61
-
{ insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
62
-
{ insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
63
-
{ insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
64
-
{ insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
51
+
static const struct insn const insn_table[insn_invalid] = {
52
+
[insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
53
+
[insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
54
+
[insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
55
+
[insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
56
+
[insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
57
+
[insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
58
+
[insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
59
+
[insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
60
+
[insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM},
61
+
[insn_bgezl] = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM},
62
+
[insn_bgtz] = {M(bgtz_op, 0, 0, 0, 0, 0), RS | BIMM},
63
+
[insn_blez] = {M(blez_op, 0, 0, 0, 0, 0), RS | BIMM},
64
+
[insn_bltz] = {M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM},
65
+
[insn_bltzl] = {M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM},
66
+
[insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
67
+
[insn_break] = {M(spec_op, 0, 0, 0, 0, break_op), SCIMM},
65
68
#ifndef CONFIG_CPU_MIPSR6
66
-
{ insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
69
+
[insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
67
70
#else
68
-
{ insn_cache, M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 },
71
+
[insn_cache] = {M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9},
69
72
#endif
70
-
{ insn_cfc1, M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD },
71
-
{ insn_cfcmsa, M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE },
72
-
{ insn_ctc1, M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD },
73
-
{ insn_ctcmsa, M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE },
74
-
{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
75
-
{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
76
-
{ insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
77
-
{ insn_di, M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT },
78
-
{ insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
79
-
{ insn_divu, M(spec_op, 0, 0, 0, 0, divu_op), RS | RT },
80
-
{ insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
81
-
{ insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
82
-
{ insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
83
-
{ insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
84
-
{ insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
85
-
{ insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
86
-
{ insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
87
-
{ insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
88
-
{ insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
89
-
{ insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
90
-
{ insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
91
-
{ insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE },
92
-
{ insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
93
-
{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
94
-
{ insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
95
-
{ insn_jalr, M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD },
96
-
{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
73
+
[insn_cfc1] = {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD},
74
+
[insn_cfcmsa] = {M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE},
75
+
[insn_ctc1] = {M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD},
76
+
[insn_ctcmsa] = {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE},
77
+
[insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
78
+
[insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD},
79
+
[insn_ddivu] = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT},
80
+
[insn_di] = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT},
81
+
[insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
82
+
[insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},
83
+
[insn_dinsu] = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE},
84
+
[insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT},
85
+
[insn_dmfc0] = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
86
+
[insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
87
+
[insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
88
+
[insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
89
+
[insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
90
+
[insn_dsbh] = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD},
91
+
[insn_dshd] = {M(spec3_op, 0, 0, 0, dshd_op, dbshfl_op), RT | RD},
92
+
[insn_dsll] = {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE},
93
+
[insn_dsll32] = {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE},
94
+
[insn_dsllv] = {M(spec_op, 0, 0, 0, 0, dsllv_op), RS | RT | RD},
95
+
[insn_dsra] = {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE},
96
+
[insn_dsra32] = {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE},
97
+
[insn_dsrav] = {M(spec_op, 0, 0, 0, 0, dsrav_op), RS | RT | RD},
98
+
[insn_dsrl] = {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE},
99
+
[insn_dsrl32] = {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE},
100
+
[insn_dsrlv] = {M(spec_op, 0, 0, 0, 0, dsrlv_op), RS | RT | RD},
101
+
[insn_dsubu] = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD},
102
+
[insn_eret] = {M(cop0_op, cop_op, 0, 0, 0, eret_op), 0},
103
+
[insn_ext] = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE},
104
+
[insn_ins] = {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE},
105
+
[insn_j] = {M(j_op, 0, 0, 0, 0, 0), JIMM},
106
+
[insn_jal] = {M(jal_op, 0, 0, 0, 0, 0), JIMM},
107
+
[insn_jalr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD},
97
108
#ifndef CONFIG_CPU_MIPSR6
98
-
{ insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
109
+
[insn_jr] = {M(spec_op, 0, 0, 0, 0, jr_op), RS},
99
110
#else
100
-
{ insn_jr, M(spec_op, 0, 0, 0, 0, jalr_op), RS },
111
+
[insn_jr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS},
101
112
#endif
102
-
{ insn_lb, M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
103
-
{ insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
104
-
{ insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
105
-
{ insn_lh, M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
106
-
{ insn_lhu, M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
113
+
[insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
114
+
[insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
115
+
[insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
116
+
[insn_lddir] = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD},
117
+
[insn_ldpte] = {M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD},
118
+
[insn_ldx] = {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD},
119
+
[insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
120
+
[insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
107
121
#ifndef CONFIG_CPU_MIPSR6
108
-
{ insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
109
-
{ insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
122
+
[insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
123
+
[insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
110
124
#else
111
-
{ insn_lld, M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9 },
112
-
{ insn_ll, M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9 },
125
+
[insn_ll] = {M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9},
126
+
[insn_lld] = {M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9},
113
127
#endif
114
-
{ insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
115
-
{ insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
116
-
{ insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
117
-
{ insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
118
-
{ insn_mfhc0, M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET},
119
-
{ insn_mfhi, M(spec_op, 0, 0, 0, 0, mfhi_op), RD },
120
-
{ insn_mflo, M(spec_op, 0, 0, 0, 0, mflo_op), RD },
121
-
{ insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
122
-
{ insn_mthc0, M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET},
123
-
{ insn_mthi, M(spec_op, 0, 0, 0, 0, mthi_op), RS },
124
-
{ insn_mtlo, M(spec_op, 0, 0, 0, 0, mtlo_op), RS },
128
+
[insn_lui] = {M(lui_op, 0, 0, 0, 0, 0), RT | SIMM},
129
+
[insn_lw] = {M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
130
+
[insn_lwu] = {M(lwu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
131
+
[insn_lwx] = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD},
132
+
[insn_mfc0] = {M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
133
+
[insn_mfhc0] = {M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET},
134
+
[insn_mfhi] = {M(spec_op, 0, 0, 0, 0, mfhi_op), RD},
135
+
[insn_mflo] = {M(spec_op, 0, 0, 0, 0, mflo_op), RD},
136
+
[insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD},
137
+
[insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD},
138
+
[insn_mtc0] = {M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
139
+
[insn_mthc0] = {M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET},
140
+
[insn_mthi] = {M(spec_op, 0, 0, 0, 0, mthi_op), RS},
141
+
[insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},
125
142
#ifndef CONFIG_CPU_MIPSR6
126
-
{ insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
143
+
[insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
127
144
#else
128
-
{ insn_mul, M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD},
145
+
[insn_mul] = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD},
129
146
#endif
130
-
{ insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
131
-
{ insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
147
+
[insn_multu] = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT},
148
+
[insn_nor] = {M(spec_op, 0, 0, 0, 0, nor_op), RS | RT | RD},
149
+
[insn_or] = {M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD},
150
+
[insn_ori] = {M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
132
151
#ifndef CONFIG_CPU_MIPSR6
133
-
{ insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
152
+
[insn_pref] = {M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
134
153
#else
135
-
{ insn_pref, M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9 },
154
+
[insn_pref] = {M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9},
136
155
#endif
137
-
{ insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
138
-
{ insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
156
+
[insn_rfe] = {M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0},
157
+
[insn_rotr] = {M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE},
158
+
[insn_sb] = {M(sb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
139
159
#ifndef CONFIG_CPU_MIPSR6
140
-
{ insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
141
-
{ insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
160
+
[insn_sc] = {M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
161
+
[insn_scd] = {M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
142
162
#else
143
-
{ insn_scd, M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9 },
144
-
{ insn_sc, M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9 },
163
+
[insn_sc] = {M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9},
164
+
[insn_scd] = {M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9},
145
165
#endif
146
-
{ insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
147
-
{ insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
148
-
{ insn_sllv, M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD },
149
-
{ insn_slt, M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD },
150
-
{ insn_sltiu, M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
151
-
{ insn_sltu, M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD },
152
-
{ insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
153
-
{ insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
154
-
{ insn_srlv, M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD },
155
-
{ insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
156
-
{ insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
157
-
{ insn_sync, M(spec_op, 0, 0, 0, 0, sync_op), RE },
158
-
{ insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
159
-
{ insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
160
-
{ insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
161
-
{ insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
162
-
{ insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
163
-
{ insn_wait, M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM },
164
-
{ insn_wsbh, M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD },
165
-
{ insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
166
-
{ insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
167
-
{ insn_yield, M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD },
168
-
{ insn_ldpte, M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD },
169
-
{ insn_lddir, M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD },
170
-
{ insn_invalid, 0, 0 }
166
+
[insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
167
+
[insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
168
+
[insn_sll] = {M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE},
169
+
[insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD},
170
+
[insn_slt] = {M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD},
171
+
[insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
172
+
[insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
173
+
[insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD},
174
+
[insn_sra] = {M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE},
175
+
[insn_srl] = {M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE},
176
+
[insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD},
177
+
[insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD},
178
+
[insn_sw] = {M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
179
+
[insn_sync] = {M(spec_op, 0, 0, 0, 0, sync_op), RE},
180
+
[insn_syscall] = {M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
181
+
[insn_tlbp] = {M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0},
182
+
[insn_tlbr] = {M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0},
183
+
[insn_tlbwi] = {M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0},
184
+
[insn_tlbwr] = {M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0},
185
+
[insn_wait] = {M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM},
186
+
[insn_wsbh] = {M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD},
187
+
[insn_xor] = {M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD},
188
+
[insn_xori] = {M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
189
+
[insn_yield] = {M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD},
171
190
};
172
191
173
192
#undef M
···
215
196
*/
216
197
static void build_insn(u32 **buf, enum opcode opc, ...)
217
198
{
218
-
struct insn *ip = NULL;
219
-
unsigned int i;
199
+
const struct insn *ip;
220
200
va_list ap;
221
201
u32 op;
222
202
223
-
for (i = 0; insn_table[i].opcode != insn_invalid; i++)
224
-
if (insn_table[i].opcode == opc) {
225
-
ip = &insn_table[i];
226
-
break;
227
-
}
228
-
229
-
if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
203
+
if (opc < 0 || opc >= insn_invalid ||
204
+
(opc == insn_daddiu && r4k_daddiu_bug()) ||
205
+
(insn_table[opc].match == 0 && insn_table[opc].fields == 0))
230
206
panic("Unsupported Micro-assembler instruction %d", opc);
207
+
208
+
ip = &insn_table[opc];
231
209
232
210
op = ip->match;
233
211
va_start(ap, opc);
+46
-15
arch/mips/mm/uasm.c
+46
-15
arch/mips/mm/uasm.c
···
46
46
#define SIMM9_MASK 0x1ff
47
47
48
48
enum opcode {
49
-
insn_invalid,
50
49
insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
51
-
insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
52
-
insn_bne, insn_cache, insn_cfc1, insn_cfcmsa, insn_ctc1, insn_ctcmsa,
53
-
insn_daddiu, insn_daddu, insn_di, insn_dins, insn_dinsm, insn_divu,
54
-
insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
55
-
insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
56
-
insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb,
57
-
insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,
58
-
insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0,
59
-
insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_or, insn_ori,
60
-
insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll,
61
-
insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra, insn_srl,
50
+
insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez,
51
+
insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1,
52
+
insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu,
53
+
insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, insn_dmfc0,
54
+
insn_dmtc0, insn_dmultu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd,
55
+
insn_dsll, insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav,
56
+
insn_dsrl, insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext,
57
+
insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu,
58
+
insn_ld, insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu,
59
+
insn_ll, insn_lld, insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0,
60
+
insn_mfhc0, insn_mfhi, insn_mflo, insn_movn, insn_movz, insn_mtc0,
61
+
insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor,
62
+
insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb,
63
+
insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv,
64
+
insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srl,
62
65
insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,
63
66
insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,
64
-
insn_xori, insn_yield, insn_lddir, insn_ldpte, insn_lhu,
67
+
insn_xori, insn_yield,
68
+
insn_invalid /* insn_invalid must be last */
65
69
};
66
70
67
71
struct insn {
68
-
enum opcode opcode;
69
72
u32 match;
70
73
enum fields fields;
71
74
};
···
218
215
} \
219
216
UASM_EXPORT_SYMBOL(uasm_i##op);
220
217
218
+
#define I_u2u1msb32msb3(op) \
219
+
Ip_u2u1msbu3(op) \
220
+
{ \
221
+
build_insn(buf, insn##op, b, a, c+d-33, c-32); \
222
+
} \
223
+
UASM_EXPORT_SYMBOL(uasm_i##op);
224
+
221
225
#define I_u2u1msbdu3(op) \
222
226
Ip_u2u1msbu3(op) \
223
227
{ \
···
275
265
I_u1u2s3(_beql)
276
266
I_u1s2(_bgez)
277
267
I_u1s2(_bgezl)
268
+
I_u1s2(_bgtz)
269
+
I_u1s2(_blez)
278
270
I_u1s2(_bltz)
279
271
I_u1s2(_bltzl)
280
272
I_u1u2s3(_bne)
273
+
I_u1(_break)
281
274
I_u2s3u1(_cache)
282
275
I_u1u2(_cfc1)
283
276
I_u2u1(_cfcmsa)
284
277
I_u1u2(_ctc1)
285
278
I_u2u1(_ctcmsa)
279
+
I_u1u2(_ddivu)
286
280
I_u1u2u3(_dmfc0)
287
281
I_u1u2u3(_dmtc0)
282
+
I_u1u2(_dmultu)
288
283
I_u2u1s3(_daddiu)
289
284
I_u3u1u2(_daddu)
290
285
I_u1(_di);
291
286
I_u1u2(_divu)
287
+
I_u2u1(_dsbh);
288
+
I_u2u1(_dshd);
292
289
I_u2u1u3(_dsll)
293
290
I_u2u1u3(_dsll32)
291
+
I_u3u2u1(_dsllv)
294
292
I_u2u1u3(_dsra)
293
+
I_u2u1u3(_dsra32)
294
+
I_u3u2u1(_dsrav)
295
295
I_u2u1u3(_dsrl)
296
296
I_u2u1u3(_dsrl32)
297
+
I_u3u2u1(_dsrlv)
297
298
I_u2u1u3(_drotr)
298
299
I_u2u1u3(_drotr32)
299
300
I_u3u1u2(_dsubu)
···
316
295
I_u2u1(_jalr)
317
296
I_u1(_jr)
318
297
I_u2s3u1(_lb)
298
+
I_u2s3u1(_lbu)
319
299
I_u2s3u1(_ld)
320
300
I_u2s3u1(_lh)
321
301
I_u2s3u1(_lhu)
···
324
302
I_u2s3u1(_lld)
325
303
I_u1s2(_lui)
326
304
I_u2s3u1(_lw)
305
+
I_u2s3u1(_lwu)
327
306
I_u1u2u3(_mfc0)
328
307
I_u1u2u3(_mfhc0)
308
+
I_u3u1u2(_movn)
309
+
I_u3u1u2(_movz)
329
310
I_u1(_mfhi)
330
311
I_u1(_mflo)
331
312
I_u1u2u3(_mtc0)
···
336
311
I_u1(_mthi)
337
312
I_u1(_mtlo)
338
313
I_u3u1u2(_mul)
339
-
I_u2u1u3(_ori)
314
+
I_u1u2(_multu)
315
+
I_u3u1u2(_nor)
340
316
I_u3u1u2(_or)
317
+
I_u2u1u3(_ori)
341
318
I_0(_rfe)
319
+
I_u2s3u1(_sb)
342
320
I_u2s3u1(_sc)
343
321
I_u2s3u1(_scd)
344
322
I_u2s3u1(_sd)
323
+
I_u2s3u1(_sh)
345
324
I_u2u1u3(_sll)
346
325
I_u3u2u1(_sllv)
347
326
I_s3s1s2(_slt)
327
+
I_u2u1s3(_slti)
348
328
I_u2u1s3(_sltiu)
349
329
I_u3u1u2(_sltu)
350
330
I_u2u1u3(_sra)
···
370
340
I_u2u1(_yield)
371
341
I_u2u1msbu3(_dins);
372
342
I_u2u1msb32u3(_dinsm);
343
+
I_u2u1msb32msb3(_dinsu);
373
344
I_u1(_syscall);
374
345
I_u1u2s3(_bbit0);
375
346
I_u1u2s3(_bbit1);
+2
-1
arch/mips/net/Makefile
+2
-1
arch/mips/net/Makefile
+50
-9
arch/mips/vdso/gettimeofday.c
+50
-9
arch/mips/vdso/gettimeofday.c
···
20
20
#include <asm/unistd.h>
21
21
#include <asm/vdso.h>
22
22
23
+
#ifdef CONFIG_MIPS_CLOCK_VSYSCALL
24
+
25
+
static __always_inline long gettimeofday_fallback(struct timeval *_tv,
26
+
struct timezone *_tz)
27
+
{
28
+
register struct timezone *tz asm("a1") = _tz;
29
+
register struct timeval *tv asm("a0") = _tv;
30
+
register long ret asm("v0");
31
+
register long nr asm("v0") = __NR_gettimeofday;
32
+
register long error asm("a3");
33
+
34
+
asm volatile(
35
+
" syscall\n"
36
+
: "=r" (ret), "=r" (error)
37
+
: "r" (tv), "r" (tz), "r" (nr)
38
+
: "memory");
39
+
40
+
return error ? -ret : ret;
41
+
}
42
+
43
+
#endif
44
+
45
+
static __always_inline long clock_gettime_fallback(clockid_t _clkid,
46
+
struct timespec *_ts)
47
+
{
48
+
register struct timespec *ts asm("a1") = _ts;
49
+
register clockid_t clkid asm("a0") = _clkid;
50
+
register long ret asm("v0");
51
+
register long nr asm("v0") = __NR_clock_gettime;
52
+
register long error asm("a3");
53
+
54
+
asm volatile(
55
+
" syscall\n"
56
+
: "=r" (ret), "=r" (error)
57
+
: "r" (clkid), "r" (ts), "r" (nr)
58
+
: "memory");
59
+
60
+
return error ? -ret : ret;
61
+
}
62
+
23
63
static __always_inline int do_realtime_coarse(struct timespec *ts,
24
64
const union mips_vdso_data *data)
25
65
{
···
79
39
const union mips_vdso_data *data)
80
40
{
81
41
u32 start_seq;
82
-
u32 to_mono_sec;
83
-
u32 to_mono_nsec;
42
+
u64 to_mono_sec;
43
+
u64 to_mono_nsec;
84
44
85
45
do {
86
46
start_seq = vdso_data_read_begin(data);
···
188
148
{
189
149
u32 start_seq;
190
150
u64 ns;
191
-
u32 to_mono_sec;
192
-
u32 to_mono_nsec;
151
+
u64 to_mono_sec;
152
+
u64 to_mono_nsec;
193
153
194
154
do {
195
155
start_seq = vdso_data_read_begin(data);
···
227
187
228
188
ret = do_realtime(&ts, data);
229
189
if (ret)
230
-
return ret;
190
+
return gettimeofday_fallback(tv, tz);
231
191
232
192
if (tv) {
233
193
tv->tv_sec = ts.tv_sec;
···
242
202
return 0;
243
203
}
244
204
245
-
#endif /* CONFIG_CLKSRC_MIPS_GIC */
205
+
#endif /* CONFIG_MIPS_CLOCK_VSYSCALL */
246
206
247
207
int __vdso_clock_gettime(clockid_t clkid, struct timespec *ts)
248
208
{
249
209
const union mips_vdso_data *data = get_vdso_data();
250
-
int ret;
210
+
int ret = -1;
251
211
252
212
switch (clkid) {
253
213
case CLOCK_REALTIME_COARSE:
···
263
223
ret = do_monotonic(ts, data);
264
224
break;
265
225
default:
266
-
ret = -ENOSYS;
267
226
break;
268
227
}
269
228
270
-
/* If we return -ENOSYS libc should fall back to a syscall. */
229
+
if (ret)
230
+
ret = clock_gettime_fallback(clkid, ts);
231
+
271
232
return ret;
272
233
}
+1
drivers/clk/Kconfig
+1
drivers/clk/Kconfig
+1
drivers/clk/Makefile
+1
drivers/clk/Makefile
+9
drivers/clk/imgtec/Kconfig
+9
drivers/clk/imgtec/Kconfig
···
1
+
config COMMON_CLK_BOSTON
2
+
bool "Clock driver for MIPS Boston boards"
3
+
depends on MIPS || COMPILE_TEST
4
+
select MFD_SYSCON
5
+
---help---
6
+
Enable this to support the system & CPU clocks on the MIPS Boston
7
+
development board from Imagination Technologies. These are simple
8
+
fixed rate clocks whose rate is determined by reading a platform
9
+
provided register.
+1
drivers/clk/imgtec/Makefile
+1
drivers/clk/imgtec/Makefile
···
1
+
obj-$(CONFIG_COMMON_CLK_BOSTON) += clk-boston.o
+103
drivers/clk/imgtec/clk-boston.c
+103
drivers/clk/imgtec/clk-boston.c
···
1
+
/*
2
+
* Copyright (C) 2016-2017 Imagination Technologies
3
+
* Author: Paul Burton <paul.burton@imgtec.com>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify it
6
+
* under the terms of the GNU General Public License as published by the
7
+
* Free Software Foundation; either version 2 of the License, or (at your
8
+
* option) any later version.
9
+
*/
10
+
11
+
#define pr_fmt(fmt) "clk-boston: " fmt
12
+
13
+
#include <linux/clk-provider.h>
14
+
#include <linux/kernel.h>
15
+
#include <linux/of.h>
16
+
#include <linux/regmap.h>
17
+
#include <linux/slab.h>
18
+
#include <linux/mfd/syscon.h>
19
+
20
+
#include <dt-bindings/clock/boston-clock.h>
21
+
22
+
#define BOSTON_PLAT_MMCMDIV 0x30
23
+
# define BOSTON_PLAT_MMCMDIV_CLK0DIV (0xff << 0)
24
+
# define BOSTON_PLAT_MMCMDIV_INPUT (0xff << 8)
25
+
# define BOSTON_PLAT_MMCMDIV_MUL (0xff << 16)
26
+
# define BOSTON_PLAT_MMCMDIV_CLK1DIV (0xff << 24)
27
+
28
+
#define BOSTON_CLK_COUNT 3
29
+
30
+
static u32 ext_field(u32 val, u32 mask)
31
+
{
32
+
return (val & mask) >> (ffs(mask) - 1);
33
+
}
34
+
35
+
static void __init clk_boston_setup(struct device_node *np)
36
+
{
37
+
unsigned long in_freq, cpu_freq, sys_freq;
38
+
uint mmcmdiv, mul, cpu_div, sys_div;
39
+
struct clk_hw_onecell_data *onecell;
40
+
struct regmap *regmap;
41
+
struct clk_hw *hw;
42
+
int err;
43
+
44
+
regmap = syscon_node_to_regmap(np->parent);
45
+
if (IS_ERR(regmap)) {
46
+
pr_err("failed to find regmap\n");
47
+
return;
48
+
}
49
+
50
+
err = regmap_read(regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv);
51
+
if (err) {
52
+
pr_err("failed to read mmcm_div register: %d\n", err);
53
+
return;
54
+
}
55
+
56
+
in_freq = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_INPUT) * 1000000;
57
+
mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL);
58
+
59
+
sys_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK0DIV);
60
+
sys_freq = mult_frac(in_freq, mul, sys_div);
61
+
62
+
cpu_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK1DIV);
63
+
cpu_freq = mult_frac(in_freq, mul, cpu_div);
64
+
65
+
onecell = kzalloc(sizeof(*onecell) +
66
+
(BOSTON_CLK_COUNT * sizeof(struct clk_hw *)),
67
+
GFP_KERNEL);
68
+
if (!onecell)
69
+
return;
70
+
71
+
onecell->num = BOSTON_CLK_COUNT;
72
+
73
+
hw = clk_hw_register_fixed_rate(NULL, "input", NULL, 0, in_freq);
74
+
if (IS_ERR(hw)) {
75
+
pr_err("failed to register input clock: %ld\n", PTR_ERR(hw));
76
+
return;
77
+
}
78
+
onecell->hws[BOSTON_CLK_INPUT] = hw;
79
+
80
+
hw = clk_hw_register_fixed_rate(NULL, "sys", "input", 0, sys_freq);
81
+
if (IS_ERR(hw)) {
82
+
pr_err("failed to register sys clock: %ld\n", PTR_ERR(hw));
83
+
return;
84
+
}
85
+
onecell->hws[BOSTON_CLK_SYS] = hw;
86
+
87
+
hw = clk_hw_register_fixed_rate(NULL, "cpu", "input", 0, cpu_freq);
88
+
if (IS_ERR(hw)) {
89
+
pr_err("failed to register cpu clock: %ld\n", PTR_ERR(hw));
90
+
return;
91
+
}
92
+
onecell->hws[BOSTON_CLK_CPU] = hw;
93
+
94
+
err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, onecell);
95
+
if (err)
96
+
pr_err("failed to add DT provider: %d\n", err);
97
+
}
98
+
99
+
/*
100
+
* Use CLK_OF_DECLARE so that this driver is probed early enough to provide the
101
+
* CPU frequency for use with the GIC or cop0 counters/timers.
102
+
*/
103
+
CLK_OF_DECLARE(clk_boston, "img,boston-clock", clk_boston_setup);
+70
-64
drivers/platform/mips/cpu_hwmon.c
+70
-64
drivers/platform/mips/cpu_hwmon.c
···
17
17
*/
18
18
int loongson3_cpu_temp(int cpu)
19
19
{
20
-
u32 reg;
20
+
u32 reg, prid_rev;
21
21
22
22
reg = LOONGSON_CHIPTEMP(cpu);
23
-
if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1)
23
+
prid_rev = read_c0_prid() & PRID_REV_MASK;
24
+
switch (prid_rev) {
25
+
case PRID_REV_LOONGSON3A_R1:
24
26
reg = (reg >> 8) & 0xff;
25
-
else
27
+
break;
28
+
case PRID_REV_LOONGSON3A_R2:
29
+
case PRID_REV_LOONGSON3B_R1:
30
+
case PRID_REV_LOONGSON3B_R2:
26
31
reg = ((reg >> 8) & 0xff) - 100;
27
-
32
+
break;
33
+
case PRID_REV_LOONGSON3A_R3:
34
+
reg = (reg & 0xffff)*731/0x4000 - 273;
35
+
break;
36
+
}
28
37
return (int)reg * 1000;
29
38
}
30
39
40
+
static int nr_packages;
31
41
static struct device *cpu_hwmon_dev;
32
42
33
43
static ssize_t get_hwmon_name(struct device *dev,
···
61
51
return sprintf(buf, "cpu-hwmon\n");
62
52
}
63
53
64
-
static ssize_t get_cpu0_temp(struct device *dev,
54
+
static ssize_t get_cpu_temp(struct device *dev,
65
55
struct device_attribute *attr, char *buf);
66
-
static ssize_t get_cpu1_temp(struct device *dev,
67
-
struct device_attribute *attr, char *buf);
68
-
static ssize_t cpu0_temp_label(struct device *dev,
69
-
struct device_attribute *attr, char *buf);
70
-
static ssize_t cpu1_temp_label(struct device *dev,
56
+
static ssize_t cpu_temp_label(struct device *dev,
71
57
struct device_attribute *attr, char *buf);
72
58
73
-
static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu0_temp, NULL, 1);
74
-
static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu0_temp_label, NULL, 1);
75
-
static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu1_temp, NULL, 2);
76
-
static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu1_temp_label, NULL, 2);
59
+
static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL, 1);
60
+
static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu_temp_label, NULL, 1);
61
+
static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu_temp, NULL, 2);
62
+
static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu_temp_label, NULL, 2);
63
+
static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, get_cpu_temp, NULL, 3);
64
+
static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, cpu_temp_label, NULL, 3);
65
+
static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, get_cpu_temp, NULL, 4);
66
+
static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, cpu_temp_label, NULL, 4);
77
67
78
-
static const struct attribute *hwmon_cputemp1[] = {
79
-
&sensor_dev_attr_temp1_input.dev_attr.attr,
80
-
&sensor_dev_attr_temp1_label.dev_attr.attr,
81
-
NULL
68
+
static const struct attribute *hwmon_cputemp[4][3] = {
69
+
{
70
+
&sensor_dev_attr_temp1_input.dev_attr.attr,
71
+
&sensor_dev_attr_temp1_label.dev_attr.attr,
72
+
NULL
73
+
},
74
+
{
75
+
&sensor_dev_attr_temp2_input.dev_attr.attr,
76
+
&sensor_dev_attr_temp2_label.dev_attr.attr,
77
+
NULL
78
+
},
79
+
{
80
+
&sensor_dev_attr_temp3_input.dev_attr.attr,
81
+
&sensor_dev_attr_temp3_label.dev_attr.attr,
82
+
NULL
83
+
},
84
+
{
85
+
&sensor_dev_attr_temp4_input.dev_attr.attr,
86
+
&sensor_dev_attr_temp4_label.dev_attr.attr,
87
+
NULL
88
+
}
82
89
};
83
90
84
-
static const struct attribute *hwmon_cputemp2[] = {
85
-
&sensor_dev_attr_temp2_input.dev_attr.attr,
86
-
&sensor_dev_attr_temp2_label.dev_attr.attr,
87
-
NULL
88
-
};
89
-
90
-
static ssize_t cpu0_temp_label(struct device *dev,
91
+
static ssize_t cpu_temp_label(struct device *dev,
91
92
struct device_attribute *attr, char *buf)
92
93
{
93
-
return sprintf(buf, "CPU 0 Temperature\n");
94
+
int id = (to_sensor_dev_attr(attr))->index - 1;
95
+
return sprintf(buf, "CPU %d Temperature\n", id);
94
96
}
95
97
96
-
static ssize_t cpu1_temp_label(struct device *dev,
98
+
static ssize_t get_cpu_temp(struct device *dev,
97
99
struct device_attribute *attr, char *buf)
98
100
{
99
-
return sprintf(buf, "CPU 1 Temperature\n");
100
-
}
101
-
102
-
static ssize_t get_cpu0_temp(struct device *dev,
103
-
struct device_attribute *attr, char *buf)
104
-
{
105
-
int value = loongson3_cpu_temp(0);
106
-
return sprintf(buf, "%d\n", value);
107
-
}
108
-
109
-
static ssize_t get_cpu1_temp(struct device *dev,
110
-
struct device_attribute *attr, char *buf)
111
-
{
112
-
int value = loongson3_cpu_temp(1);
101
+
int id = (to_sensor_dev_attr(attr))->index - 1;
102
+
int value = loongson3_cpu_temp(id);
113
103
return sprintf(buf, "%d\n", value);
114
104
}
115
105
116
106
static int create_sysfs_cputemp_files(struct kobject *kobj)
117
107
{
118
-
int ret;
108
+
int i, ret = 0;
119
109
120
-
ret = sysfs_create_files(kobj, hwmon_cputemp1);
121
-
if (ret)
122
-
goto sysfs_create_temp1_fail;
110
+
for (i=0; i<nr_packages; i++)
111
+
ret = sysfs_create_files(kobj, hwmon_cputemp[i]);
123
112
124
-
if (loongson_sysconf.nr_cpus <= loongson_sysconf.cores_per_package)
125
-
return 0;
126
-
127
-
ret = sysfs_create_files(kobj, hwmon_cputemp2);
128
-
if (ret)
129
-
goto sysfs_create_temp2_fail;
130
-
131
-
return 0;
132
-
133
-
sysfs_create_temp2_fail:
134
-
sysfs_remove_files(kobj, hwmon_cputemp1);
135
-
136
-
sysfs_create_temp1_fail:
137
-
return -1;
113
+
return ret;
138
114
}
139
115
140
116
static void remove_sysfs_cputemp_files(struct kobject *kobj)
141
117
{
142
-
sysfs_remove_files(&cpu_hwmon_dev->kobj, hwmon_cputemp1);
118
+
int i;
143
119
144
-
if (loongson_sysconf.nr_cpus > loongson_sysconf.cores_per_package)
145
-
sysfs_remove_files(&cpu_hwmon_dev->kobj, hwmon_cputemp2);
120
+
for (i=0; i<nr_packages; i++)
121
+
sysfs_remove_files(kobj, hwmon_cputemp[i]);
146
122
}
147
123
148
124
#define CPU_THERMAL_THRESHOLD 90000
···
136
140
137
141
static void do_thermal_timer(struct work_struct *work)
138
142
{
139
-
int value = loongson3_cpu_temp(0);
140
-
if (value <= CPU_THERMAL_THRESHOLD)
143
+
int i, value, temp_max = 0;
144
+
145
+
for (i=0; i<nr_packages; i++) {
146
+
value = loongson3_cpu_temp(i);
147
+
if (value > temp_max)
148
+
temp_max = value;
149
+
}
150
+
151
+
if (temp_max <= CPU_THERMAL_THRESHOLD)
141
152
schedule_delayed_work(&thermal_work, msecs_to_jiffies(5000));
142
153
else
143
154
orderly_poweroff(true);
···
162
159
pr_err("hwmon_device_register fail!\n");
163
160
goto fail_hwmon_device_register;
164
161
}
162
+
163
+
nr_packages = loongson_sysconf.nr_cpus /
164
+
loongson_sysconf.cores_per_package;
165
165
166
166
ret = sysfs_create_group(&cpu_hwmon_dev->kobj,
167
167
&cpu_hwmon_attribute_group);
+14
include/dt-bindings/clock/boston-clock.h
+14
include/dt-bindings/clock/boston-clock.h
···
1
+
/*
2
+
* Copyright (C) 2016 Imagination Technologies
3
+
*
4
+
* SPDX-License-Identifier: GPL-2.0
5
+
*/
6
+
7
+
#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
8
+
#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
9
+
10
+
#define BOSTON_CLK_INPUT 0
11
+
#define BOSTON_CLK_SYS 1
12
+
#define BOSTON_CLK_CPU 2
13
+
14
+
#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */