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ice: fix missing SMA pin initialization in DPLL subsystem

The DPLL SMA/U.FL pin redesign introduced ice_dpll_sw_pin_frequency_get()
which gates frequency reporting on the pin's active flag. This flag is
determined by ice_dpll_sw_pins_update() from the PCA9575 GPIO expander
state. Before the redesign, SMA pins were exposed as direct HW
input/output pins and ice_dpll_frequency_get() returned the CGU
frequency unconditionally — the PCA9575 state was never consulted.

The PCA9575 powers on with all outputs high, setting ICE_SMA1_DIR_EN,
ICE_SMA1_TX_EN, ICE_SMA2_DIR_EN and ICE_SMA2_TX_EN. Nothing in the
driver writes the register during initialization, so
ice_dpll_sw_pins_update() sees all pins as inactive and
ice_dpll_sw_pin_frequency_get() permanently returns 0 Hz for every
SW pin.

Fix this by writing a default SMA configuration in
ice_dpll_init_info_sw_pins(): clear all SMA bits, then set SMA1 and
SMA2 as active inputs (DIR_EN=0) with U.FL1 output and U.FL2 input
disabled. Each SMA/U.FL pair shares a physical signal path so only
one pin per pair can be active at a time. U.FL pins still report
frequency 0 after this fix: U.FL1 (output-only) is disabled by
ICE_SMA1_TX_EN which keeps the TX output buffer off, and U.FL2
(input-only) is disabled by ICE_SMA2_UFL2_RX_DIS. They can be
activated by changing the corresponding SMA pin direction via dpll
netlink.

Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
Signed-off-by: Petr Oros <poros@redhat.com>
Reviewed-by: Ivan Vecera <ivecera@redhat.com>
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Tested-by: Alexander Nowlin <alexander.nowlin@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://patch.msgid.link/20260427-jk-iwl-net-petr-oros-fixes-v1-7-cdcb48303fd8@intel.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

authored by

Petr Oros and committed by
Paolo Abeni 56a643ae 70ad2164

+17
+17
drivers/net/ethernet/intel/ice/ice_dpll.c
··· 4014 4014 struct ice_dpll_pin *pin; 4015 4015 u32 phase_adj_max, caps; 4016 4016 int i, ret; 4017 + u8 data; 4017 4018 4018 4019 if (pf->hw.device_id == ICE_DEV_ID_E810C_QSFP) 4019 4020 input_idx_offset = ICE_E810_RCLK_PINS_NUM; ··· 4074 4073 } 4075 4074 ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); 4076 4075 } 4076 + 4077 + /* Initialize the SMA control register to a known-good default state. 4078 + * Without this write the PCA9575 GPIO expander retains its power-on 4079 + * default (all outputs high) which makes all SW pins appear inactive. 4080 + * Set SMA1 and SMA2 as active inputs, disable U.FL1 output and 4081 + * U.FL2 input. 4082 + */ 4083 + ret = ice_read_sma_ctrl(&pf->hw, &data); 4084 + if (ret) 4085 + return ret; 4086 + data &= ~ICE_ALL_SMA_MASK; 4087 + data |= ICE_SMA1_TX_EN | ICE_SMA2_TX_EN | ICE_SMA2_UFL2_RX_DIS; 4088 + ret = ice_write_sma_ctrl(&pf->hw, data); 4089 + if (ret) 4090 + return ret; 4091 + 4077 4092 ret = ice_dpll_pin_state_update(pf, pin, ICE_DPLL_PIN_TYPE_SOFTWARE, 4078 4093 NULL); 4079 4094 if (ret)