Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pmdomain: mediatek: Add support for MT8196 HFRPSYS power domains
Add support for the HFRPSYS Multimedia power domains found in the
MediaTek MT8196 Chromebook SoC.
Those power domains are all managed by the Hardware Voter MCU.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
authored by
AngeloGioacchino Del Regno
and committed by
Ulf Hansson
56b0d230
5437b281
+243
+239
drivers/pmdomain/mediatek/mt8196-pm-domains.h
+239
drivers/pmdomain/mediatek/mt8196-pm-domains.h
···
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},
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};
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+
static const struct scpsys_hwv_domain_data hfrpsys_hwv_domain_data_mt8196[] = {
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[MT8196_POWER_DOMAIN_VDE0] = {
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.name = "vde0",
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.set = 0x0218,
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+
.clr = 0x021C,
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+
.done = 0x141C,
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+
.en = 0x1410,
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.set_sta = 0x146C,
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.clr_sta = 0x1470,
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.setclr_bit = 7,
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},
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[MT8196_POWER_DOMAIN_VDE1] = {
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.name = "vde1",
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.set = 0x0218,
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.clr = 0x021C,
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.done = 0x141C,
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.en = 0x1410,
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.set_sta = 0x146C,
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.clr_sta = 0x1470,
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.setclr_bit = 8,
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},
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[MT8196_POWER_DOMAIN_VDE_VCORE0] = {
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.name = "vde-vcore0",
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.set = 0x0218,
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.clr = 0x021C,
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.done = 0x141C,
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.en = 0x1410,
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.set_sta = 0x146C,
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.clr_sta = 0x1470,
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.setclr_bit = 9,
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},
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[MT8196_POWER_DOMAIN_VEN0] = {
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.name = "ven0",
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.set = 0x0218,
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.clr = 0x021C,
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.done = 0x141C,
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.en = 0x1410,
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.set_sta = 0x146C,
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.clr_sta = 0x1470,
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.setclr_bit = 10,
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},
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[MT8196_POWER_DOMAIN_VEN1] = {
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.name = "ven1",
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.set = 0x0218,
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.clr = 0x021C,
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.done = 0x141C,
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.en = 0x1410,
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.set_sta = 0x146C,
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.clr_sta = 0x1470,
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.setclr_bit = 11,
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},
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[MT8196_POWER_DOMAIN_VEN2] = {
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.name = "ven2",
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.set = 0x0218,
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.clr = 0x021C,
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.done = 0x141C,
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.en = 0x1410,
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.set_sta = 0x146C,
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.clr_sta = 0x1470,
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.setclr_bit = 12,
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+
},
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[MT8196_POWER_DOMAIN_DISP_VCORE] = {
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.name = "disp-vcore",
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.set = 0x0218,
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.clr = 0x021C,
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.done = 0x141C,
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.en = 0x1410,
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.set_sta = 0x146C,
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.clr_sta = 0x1470,
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.setclr_bit = 24,
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},
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[MT8196_POWER_DOMAIN_DIS0_DORMANT] = {
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.name = "dis0-dormant",
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.set = 0x0218,
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.clr = 0x021C,
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.done = 0x141C,
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.en = 0x1410,
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+
.set_sta = 0x146C,
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.clr_sta = 0x1470,
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.setclr_bit = 25,
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},
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[MT8196_POWER_DOMAIN_DIS1_DORMANT] = {
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.name = "dis1-dormant",
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.set = 0x0218,
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.clr = 0x021C,
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.done = 0x141C,
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.en = 0x1410,
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.set_sta = 0x146C,
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.clr_sta = 0x1470,
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.setclr_bit = 26,
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+
},
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[MT8196_POWER_DOMAIN_OVL0_DORMANT] = {
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.name = "ovl0-dormant",
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.set = 0x0218,
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+
.clr = 0x021C,
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+
.done = 0x141C,
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+
.en = 0x1410,
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.set_sta = 0x146C,
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.clr_sta = 0x1470,
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.setclr_bit = 27,
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},
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[MT8196_POWER_DOMAIN_OVL1_DORMANT] = {
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.name = "ovl1-dormant",
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.set = 0x0218,
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+
.clr = 0x021C,
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+
.done = 0x141C,
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+
.en = 0x1410,
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+
.set_sta = 0x146C,
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+
.clr_sta = 0x1470,
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+
.setclr_bit = 28,
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+
},
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[MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT] = {
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.name = "disp-edptx-dormant",
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+
.set = 0x0218,
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+
.clr = 0x021C,
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.done = 0x141C,
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.en = 0x1410,
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+
.set_sta = 0x146C,
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.clr_sta = 0x1470,
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+
.setclr_bit = 29,
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},
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[MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT] = {
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.name = "disp-dptx-dormant",
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.set = 0x0218,
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.clr = 0x021C,
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.done = 0x141C,
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.en = 0x1410,
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.set_sta = 0x146C,
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.clr_sta = 0x1470,
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.setclr_bit = 30,
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},
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[MT8196_POWER_DOMAIN_MML0_SHUTDOWN] = {
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.name = "mml0-shutdown",
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+
.set = 0x0218,
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+
.clr = 0x021C,
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+
.done = 0x141C,
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.en = 0x1410,
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+
.set_sta = 0x146C,
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.clr_sta = 0x1470,
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+
.setclr_bit = 31,
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},
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[MT8196_POWER_DOMAIN_MML1_SHUTDOWN] = {
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.name = "mml1-shutdown",
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.set = 0x0220,
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.clr = 0x0224,
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.done = 0x142C,
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.en = 0x1420,
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.set_sta = 0x1474,
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.clr_sta = 0x1478,
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.setclr_bit = 0,
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},
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[MT8196_POWER_DOMAIN_MM_INFRA0] = {
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.name = "mm-infra0",
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.set = 0x0220,
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.clr = 0x0224,
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.done = 0x142C,
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.en = 0x1420,
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.set_sta = 0x1474,
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.clr_sta = 0x1478,
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.setclr_bit = 1,
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},
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[MT8196_POWER_DOMAIN_MM_INFRA1] = {
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.name = "mm-infra1",
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.set = 0x0220,
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.clr = 0x0224,
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.done = 0x142C,
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.en = 0x1420,
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.set_sta = 0x1474,
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.clr_sta = 0x1478,
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.setclr_bit = 2,
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},
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[MT8196_POWER_DOMAIN_MM_INFRA_AO] = {
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.name = "mm-infra-ao",
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.set = 0x0220,
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.clr = 0x0224,
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.done = 0x142C,
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.en = 0x1420,
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.set_sta = 0x1474,
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.clr_sta = 0x1478,
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.setclr_bit = 3,
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},
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[MT8196_POWER_DOMAIN_CSI_BS_RX] = {
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.name = "csi-bs-rx",
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.set = 0x0220,
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.clr = 0x0224,
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.done = 0x142C,
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.en = 0x1420,
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.set_sta = 0x1474,
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.clr_sta = 0x1478,
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.setclr_bit = 5,
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},
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[MT8196_POWER_DOMAIN_CSI_LS_RX] = {
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.name = "csi-ls-rx",
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.set = 0x0220,
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.clr = 0x0224,
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.done = 0x142C,
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.en = 0x1420,
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.set_sta = 0x1474,
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.clr_sta = 0x1478,
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.setclr_bit = 6,
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},
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[MT8196_POWER_DOMAIN_DSI_PHY0] = {
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.name = "dsi-phy0",
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+
.set = 0x0220,
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+
.clr = 0x0224,
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+
.done = 0x142C,
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.en = 0x1420,
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.set_sta = 0x1474,
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+
.clr_sta = 0x1478,
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.setclr_bit = 7,
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+
},
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[MT8196_POWER_DOMAIN_DSI_PHY1] = {
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.name = "dsi-phy1",
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.set = 0x0220,
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.clr = 0x0224,
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.done = 0x142C,
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.en = 0x1420,
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+
.set_sta = 0x1474,
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+
.clr_sta = 0x1478,
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.setclr_bit = 8,
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},
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[MT8196_POWER_DOMAIN_DSI_PHY2] = {
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.name = "dsi-phy2",
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+
.set = 0x0220,
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+
.clr = 0x0224,
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+
.done = 0x142C,
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+
.en = 0x1420,
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+
.set_sta = 0x1474,
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+
.clr_sta = 0x1478,
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+
.setclr_bit = 9,
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},
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+
};
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+
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static const struct scpsys_soc_data mt8196_scpsys_data = {
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.domains_data = scpsys_domain_data_mt8196,
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.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8196),
···
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static const struct scpsys_soc_data mt8196_scpsys_hwv_data = {
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.hwv_domains_data = scpsys_hwv_domain_data_mt8196,
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.num_hwv_domains = ARRAY_SIZE(scpsys_hwv_domain_data_mt8196),
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.type = SCPSYS_MTCMOS_TYPE_HW_VOTER,
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};
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+
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static const struct scpsys_soc_data mt8196_hfrpsys_hwv_data = {
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.hwv_domains_data = hfrpsys_hwv_domain_data_mt8196,
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.num_hwv_domains = ARRAY_SIZE(hfrpsys_hwv_domain_data_mt8196),
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.type = SCPSYS_MTCMOS_TYPE_HW_VOTER,
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};
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+4
drivers/pmdomain/mediatek/mtk-pm-domains.c
+4
drivers/pmdomain/mediatek/mtk-pm-domains.c
···
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.data = &mt8196_scpsys_data,
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},
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{
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.compatible = "mediatek,mt8196-hwv-hfrp-power-controller",
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.data = &mt8196_hfrpsys_hwv_data,
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},
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{
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.compatible = "mediatek,mt8196-hwv-scp-power-controller",
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.data = &mt8196_scpsys_hwv_data,
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},