Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Kevin Hilman:
"Another round of fixes from arm-soc land, which are mostly DT fixes
for:
- OMAP: handful of DT fixes devices on newly supported hardware
- davinci: fix 2nd EDMA channel
- ux500: extend previous pinctrl fix to another board
- at91: clock registration fixes, compatibility string precision
And one more fix for event cleanup in drivers/bus/arm-ccn"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
bus: arm-ccn: Move event cleanup routine
ARM: at91/dt: rm9200: fix usb clock definition
ARM: at91: rm9200: fix clock registration
ARM: at91/dt: sam9g20: set at91sam9g20 pllb driver
ARM: dts: dra7-evm: Add vtt regulator support
ARM: dts: dra7-evm: Fix spi1 mux documentation
ARM: dts: am43x-epos-evm: Disable QSPI to prevent conflict with GPMC-NAND
ARM: OMAP2+: gpmc: Don't complain if wait pin is used without r/w monitoring
ARM: dts: am43xx-epos-evm: Don't use read/write wait monitoring
ARM: dts: am437x-gp-evm: Don't use read/write wait monitoring
ARM: dts: am437x-gp-evm: Use BCH16 ECC scheme instead of BCH8
ARM: dts: am43x-epos-evm: Use BCH16 ECC scheme instead of BCH8
ARM: dts: am4372: fix USB regs size
ARM: dts: am437x-gp: switch i2c0 to 100KHz
ARM: dts: dra7-evm: Fix 8th NAND partition's name
ARM: dts: dra7-evm: Fix i2c3 pinmux and frequency
ARM: ux500: disable msp2 node on Snowball
ARM: edma: Fix configuration parsing for SoCs with multiple eDMA3 CC
ARM: dts: set 'ti,set-rate-parent' for dpll4_m5x2 clock
+90
-59
+2
-2
arch/arm/boot/dts/am4372.dtsi
+2
-2
arch/arm/boot/dts/am4372.dtsi
···
804
804
805
805
usb1: usb@48390000 {
806
806
compatible = "synopsys,dwc3";
807
-
reg = <0x48390000 0x17000>;
807
+
reg = <0x48390000 0x10000>;
808
808
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
809
809
phys = <&usb2_phy1>;
810
810
phy-names = "usb2-phy";
···
826
826
827
827
usb2: usb@483d0000 {
828
828
compatible = "synopsys,dwc3";
829
-
reg = <0x483d0000 0x17000>;
829
+
reg = <0x483d0000 0x10000>;
830
830
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
831
831
phys = <&usb2_phy2>;
832
832
phy-names = "usb2-phy";
+2
-4
arch/arm/boot/dts/am437x-gp-evm.dts
+2
-4
arch/arm/boot/dts/am437x-gp-evm.dts
···
260
260
status = "okay";
261
261
pinctrl-names = "default";
262
262
pinctrl-0 = <&i2c0_pins>;
263
-
clock-frequency = <400000>;
263
+
clock-frequency = <100000>;
264
264
265
265
tps65218: tps65218@24 {
266
266
reg = <0x24>;
···
424
424
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
425
425
nand@0,0 {
426
426
reg = <0 0 4>; /* device IO registers */
427
-
ti,nand-ecc-opt = "bch8";
427
+
ti,nand-ecc-opt = "bch16";
428
428
ti,elm-id = <&elm>;
429
429
nand-bus-width = <8>;
430
430
gpmc,device-width = <1>;
···
443
443
gpmc,rd-cycle-ns = <40>;
444
444
gpmc,wr-cycle-ns = <40>;
445
445
gpmc,wait-pin = <0>;
446
-
gpmc,wait-on-read;
447
-
gpmc,wait-on-write;
448
446
gpmc,bus-turnaround-ns = <0>;
449
447
gpmc,cycle2cycle-delay-ns = <0>;
450
448
gpmc,clk-activation-ns = <0>;
+4
-5
arch/arm/boot/dts/am43x-epos-evm.dts
+4
-5
arch/arm/boot/dts/am43x-epos-evm.dts
···
435
435
};
436
436
437
437
&gpmc {
438
-
status = "okay";
438
+
status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
439
439
pinctrl-names = "default";
440
440
pinctrl-0 = <&nand_flash_x8>;
441
441
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
442
442
nand@0,0 {
443
443
reg = <0 0 0>; /* CS0, offset 0 */
444
-
ti,nand-ecc-opt = "bch8";
444
+
ti,nand-ecc-opt = "bch16";
445
445
ti,elm-id = <&elm>;
446
446
nand-bus-width = <8>;
447
447
gpmc,device-width = <1>;
···
459
459
gpmc,access-ns = <30>; /* tCEA + 4*/
460
460
gpmc,rd-cycle-ns = <40>;
461
461
gpmc,wr-cycle-ns = <40>;
462
-
gpmc,wait-on-read = "true";
463
-
gpmc,wait-on-write = "true";
462
+
gpmc,wait-pin = <0>;
464
463
gpmc,bus-turnaround-ns = <0>;
465
464
gpmc,cycle2cycle-delay-ns = <0>;
466
465
gpmc,clk-activation-ns = <0>;
···
556
557
};
557
558
558
559
&qspi {
559
-
status = "okay";
560
+
status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */
560
561
pinctrl-names = "default";
561
562
pinctrl-0 = <&qspi1_default>;
562
563
+1
-1
arch/arm/boot/dts/at91rm9200.dtsi
+1
-1
arch/arm/boot/dts/at91rm9200.dtsi
+1
arch/arm/boot/dts/at91sam9g20.dtsi
+1
arch/arm/boot/dts/at91sam9g20.dtsi
+36
-11
arch/arm/boot/dts/dra7-evm.dts
+36
-11
arch/arm/boot/dts/dra7-evm.dts
···
8
8
/dts-v1/;
9
9
10
10
#include "dra74x.dtsi"
11
+
#include <dt-bindings/gpio/gpio.h>
11
12
12
13
/ {
13
14
model = "TI DRA742";
···
25
24
regulator-min-microvolt = <3300000>;
26
25
regulator-max-microvolt = <3300000>;
27
26
};
27
+
28
+
vtt_fixed: fixedregulator-vtt {
29
+
compatible = "regulator-fixed";
30
+
regulator-name = "vtt_fixed";
31
+
regulator-min-microvolt = <1350000>;
32
+
regulator-max-microvolt = <1350000>;
33
+
regulator-always-on;
34
+
regulator-boot-on;
35
+
enable-active-high;
36
+
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
37
+
};
28
38
};
29
39
30
40
&dra7_pmx_core {
41
+
pinctrl-names = "default";
42
+
pinctrl-0 = <&vtt_pin>;
43
+
44
+
vtt_pin: pinmux_vtt_pin {
45
+
pinctrl-single,pins = <
46
+
0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
47
+
>;
48
+
};
49
+
31
50
i2c1_pins: pinmux_i2c1_pins {
32
51
pinctrl-single,pins = <
33
52
0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
···
64
43
65
44
i2c3_pins: pinmux_i2c3_pins {
66
45
pinctrl-single,pins = <
67
-
0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
68
-
0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
46
+
0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
47
+
0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
69
48
>;
70
49
};
71
50
72
51
mcspi1_pins: pinmux_mcspi1_pins {
73
52
pinctrl-single,pins = <
74
-
0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */
75
-
0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */
76
-
0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */
77
-
0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
78
-
0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */
79
-
0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */
80
-
0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */
53
+
0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
54
+
0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
55
+
0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
56
+
0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
57
+
0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
58
+
0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
81
59
>;
82
60
};
83
61
···
304
284
status = "okay";
305
285
pinctrl-names = "default";
306
286
pinctrl-0 = <&i2c3_pins>;
307
-
clock-frequency = <3400000>;
287
+
clock-frequency = <400000>;
308
288
};
309
289
310
290
&mcspi1 {
···
503
483
reg = <0x001c0000 0x00020000>;
504
484
};
505
485
partition@7 {
506
-
label = "NAND.u-boot-env";
486
+
label = "NAND.u-boot-env.backup1";
507
487
reg = <0x001e0000 0x00020000>;
508
488
};
509
489
partition@8 {
···
523
503
524
504
&usb2_phy2 {
525
505
phy-supply = <&ldousb_reg>;
506
+
};
507
+
508
+
&gpio7 {
509
+
ti,no-reset-on-init;
510
+
ti,no-idle-on-init;
526
511
};
+1
arch/arm/boot/dts/omap3xxx-clocks.dtsi
+1
arch/arm/boot/dts/omap3xxx-clocks.dtsi
-1
arch/arm/boot/dts/ste-snowball.dts
-1
arch/arm/boot/dts/ste-snowball.dts
+5
-4
arch/arm/common/edma.c
+5
-4
arch/arm/common/edma.c
···
1443
1443
EXPORT_SYMBOL(edma_assign_channel_eventq);
1444
1444
1445
1445
static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1446
-
struct edma *edma_cc)
1446
+
struct edma *edma_cc, int cc_id)
1447
1447
{
1448
1448
int i;
1449
1449
u32 value, cccfg;
1450
1450
s8 (*queue_priority_map)[2];
1451
1451
1452
1452
/* Decode the eDMA3 configuration from CCCFG register */
1453
-
cccfg = edma_read(0, EDMA_CCCFG);
1453
+
cccfg = edma_read(cc_id, EDMA_CCCFG);
1454
1454
1455
1455
value = GET_NUM_REGN(cccfg);
1456
1456
edma_cc->num_region = BIT(value);
···
1464
1464
value = GET_NUM_EVQUE(cccfg);
1465
1465
edma_cc->num_tc = value + 1;
1466
1466
1467
-
dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg);
1467
+
dev_dbg(dev, "eDMA3 CC%d HW configuration (cccfg: 0x%08x):\n", cc_id,
1468
+
cccfg);
1468
1469
dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
1469
1470
dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
1470
1471
dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
···
1685
1684
return -ENOMEM;
1686
1685
1687
1686
/* Get eDMA3 configuration from IP */
1688
-
ret = edma_setup_from_hw(dev, info[j], edma_cc[j]);
1687
+
ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j);
1689
1688
if (ret)
1690
1689
return ret;
1691
1690
+10
-1
arch/arm/mach-at91/board-dt-rm9200.c
+10
-1
arch/arm/mach-at91/board-dt-rm9200.c
···
14
14
#include <linux/gpio.h>
15
15
#include <linux/of.h>
16
16
#include <linux/of_irq.h>
17
+
#include <linux/clk-provider.h>
17
18
18
19
#include <asm/setup.h>
19
20
#include <asm/irq.h>
···
36
35
of_irq_init(irq_of_match);
37
36
}
38
37
38
+
static void __init at91rm9200_dt_timer_init(void)
39
+
{
40
+
#if defined(CONFIG_COMMON_CLK)
41
+
of_clk_init(NULL);
42
+
#endif
43
+
at91rm9200_timer_init();
44
+
}
45
+
39
46
static const char *at91rm9200_dt_board_compat[] __initdata = {
40
47
"atmel,at91rm9200",
41
48
NULL
42
49
};
43
50
44
51
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
45
-
.init_time = at91rm9200_timer_init,
52
+
.init_time = at91rm9200_dt_timer_init,
46
53
.map_io = at91_map_io,
47
54
.handle_irq = at91_aic_handle_irq,
48
55
.init_early = at91rm9200_dt_initialize,
+3
-4
arch/arm/mach-omap2/gpmc.c
+3
-4
arch/arm/mach-omap2/gpmc.c
···
1207
1207
}
1208
1208
}
1209
1209
1210
-
if ((p->wait_on_read || p->wait_on_write) &&
1211
-
(p->wait_pin > gpmc_nr_waitpins)) {
1210
+
if (p->wait_pin > gpmc_nr_waitpins) {
1212
1211
pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1213
1212
return -EINVAL;
1214
1213
}
···
1287
1288
p->wait_on_write = of_property_read_bool(np,
1288
1289
"gpmc,wait-on-write");
1289
1290
if (!p->wait_on_read && !p->wait_on_write)
1290
-
pr_warn("%s: read/write wait monitoring not enabled!\n",
1291
-
__func__);
1291
+
pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1292
+
__func__);
1292
1293
}
1293
1294
}
1294
1295
+25
-26
drivers/bus/arm-ccn.c
+25
-26
drivers/bus/arm-ccn.c
···
586
586
return 0;
587
587
}
588
588
589
+
static void arm_ccn_pmu_event_destroy(struct perf_event *event)
590
+
{
591
+
struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
592
+
struct hw_perf_event *hw = &event->hw;
593
+
594
+
if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
595
+
clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
596
+
} else {
597
+
struct arm_ccn_component *source =
598
+
ccn->dt.pmu_counters[hw->idx].source;
599
+
600
+
if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
601
+
CCN_CONFIG_EVENT(event->attr.config) ==
602
+
CCN_EVENT_WATCHPOINT)
603
+
clear_bit(hw->config_base, source->xp.dt_cmp_mask);
604
+
else
605
+
clear_bit(hw->config_base, source->pmu_events_mask);
606
+
clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
607
+
}
608
+
609
+
ccn->dt.pmu_counters[hw->idx].source = NULL;
610
+
ccn->dt.pmu_counters[hw->idx].event = NULL;
611
+
}
612
+
589
613
static int arm_ccn_pmu_event_init(struct perf_event *event)
590
614
{
591
615
struct arm_ccn *ccn;
···
623
599
return -ENOENT;
624
600
625
601
ccn = pmu_to_arm_ccn(event->pmu);
602
+
event->destroy = arm_ccn_pmu_event_destroy;
626
603
627
604
if (hw->sample_period) {
628
605
dev_warn(ccn->dev, "Sampling not supported!\n");
···
754
729
ccn->dt.pmu_counters[hw->idx].event = event;
755
730
756
731
return 0;
757
-
}
758
-
759
-
static void arm_ccn_pmu_event_free(struct perf_event *event)
760
-
{
761
-
struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
762
-
struct hw_perf_event *hw = &event->hw;
763
-
764
-
if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
765
-
clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
766
-
} else {
767
-
struct arm_ccn_component *source =
768
-
ccn->dt.pmu_counters[hw->idx].source;
769
-
770
-
if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
771
-
CCN_CONFIG_EVENT(event->attr.config) ==
772
-
CCN_EVENT_WATCHPOINT)
773
-
clear_bit(hw->config_base, source->xp.dt_cmp_mask);
774
-
else
775
-
clear_bit(hw->config_base, source->pmu_events_mask);
776
-
clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
777
-
}
778
-
779
-
ccn->dt.pmu_counters[hw->idx].source = NULL;
780
-
ccn->dt.pmu_counters[hw->idx].event = NULL;
781
732
}
782
733
783
734
static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
···
1028
1027
static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1029
1028
{
1030
1029
arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1031
-
1032
-
arm_ccn_pmu_event_free(event);
1033
1030
}
1034
1031
1035
1032
static void arm_ccn_pmu_event_read(struct perf_event *event)