tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/i915/gvt: always pass struct intel_display * to register macros

The long term goal is to remove the __to_intel_display() generics from
display macros, such as register macros. This requires that all such
macro usage passes struct intel_display * rather than struct
drm_i915_private * to the macros.

The short term goal is to hide the struct drm_i915_private access in
intel_display_conversions.h into a function. This is problematic with
gvt, because it's a separate module, and the conversion function would
need to be exported.

Make the conversion to always passing struct intel_display * in gvt to
unblock both of the above.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/266616e14db8d9a342fd93ec9752f561149a799b.1732104170.git.jani.nikula@intel.com

Jani Nikula 57442cfb 618f9e12

+89 -73
+10 -7
drivers/gpu/drm/i915/gvt/cmd_parser.c
··· 1286 1286 struct mi_display_flip_command_info *info) 1287 1287 { 1288 1288 struct drm_i915_private *dev_priv = s->engine->i915; 1289 + struct intel_display *display = &dev_priv->display; 1289 1290 struct plane_code_mapping gen8_plane_code[] = { 1290 1291 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE}, 1291 1292 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, ··· 1315 1314 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); 1316 1315 1317 1316 if (info->plane == PLANE_A) { 1318 - info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); 1319 - info->stride_reg = DSPSTRIDE(dev_priv, info->pipe); 1320 - info->surf_reg = DSPSURF(dev_priv, info->pipe); 1317 + info->ctrl_reg = DSPCNTR(display, info->pipe); 1318 + info->stride_reg = DSPSTRIDE(display, info->pipe); 1319 + info->surf_reg = DSPSURF(display, info->pipe); 1321 1320 } else if (info->plane == PLANE_B) { 1322 1321 info->ctrl_reg = SPRCTL(info->pipe); 1323 1322 info->stride_reg = SPRSTRIDE(info->pipe); ··· 1333 1332 struct mi_display_flip_command_info *info) 1334 1333 { 1335 1334 struct drm_i915_private *dev_priv = s->engine->i915; 1335 + struct intel_display *display = &dev_priv->display; 1336 1336 struct intel_vgpu *vgpu = s->vgpu; 1337 1337 u32 dword0 = cmd_val(s, 0); 1338 1338 u32 dword1 = cmd_val(s, 1); ··· 1382 1380 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; 1383 1381 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); 1384 1382 1385 - info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); 1386 - info->stride_reg = DSPSTRIDE(dev_priv, info->pipe); 1387 - info->surf_reg = DSPSURF(dev_priv, info->pipe); 1383 + info->ctrl_reg = DSPCNTR(display, info->pipe); 1384 + info->stride_reg = DSPSTRIDE(display, info->pipe); 1385 + info->surf_reg = DSPSURF(display, info->pipe); 1388 1386 1389 1387 return 0; 1390 1388 } ··· 1421 1419 struct mi_display_flip_command_info *info) 1422 1420 { 1423 1421 struct drm_i915_private *dev_priv = s->engine->i915; 1422 + struct intel_display *display = &dev_priv->display; 1424 1423 struct intel_vgpu *vgpu = s->vgpu; 1425 1424 1426 1425 set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12), ··· 1439 1436 } 1440 1437 1441 1438 if (info->plane == PLANE_PRIMARY) 1442 - vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, info->pipe))++; 1439 + vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++; 1443 1440 1444 1441 if (info->async_flip) 1445 1442 intel_vgpu_trigger_virtual_event(vgpu, info->event);
+43 -37
drivers/gpu/drm/i915/gvt/display.c
··· 69 69 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 70 70 { 71 71 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 72 + struct intel_display *display = &dev_priv->display; 72 73 73 - if (!(vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) 74 + if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) 74 75 return 0; 75 76 76 77 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) ··· 82 81 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 83 82 { 84 83 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 84 + struct intel_display *display = &dev_priv->display; 85 85 86 86 if (drm_WARN_ON(&dev_priv->drm, 87 87 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 88 88 return -EINVAL; 89 89 90 - if (vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) & TRANSCONF_ENABLE) 90 + if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE) 91 91 return 1; 92 92 93 93 if (edp_pipe_is_enabled(vgpu) && ··· 183 181 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 184 182 { 185 183 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 184 + struct intel_display *display = &dev_priv->display; 186 185 int pipe; 187 186 188 187 if (IS_BROXTON(dev_priv)) { ··· 196 193 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | 197 194 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); 198 195 199 - for_each_pipe(dev_priv, pipe) { 200 - vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) &= 196 + for_each_pipe(display, pipe) { 197 + vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &= 201 198 ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE); 202 - vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; 199 + vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; 203 200 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 204 - vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; 205 - vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; 201 + vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; 202 + vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; 206 203 } 207 204 208 205 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { 209 - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, trans)) &= 206 + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &= 210 207 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 211 208 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE); 212 209 } 213 - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= 210 + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 214 211 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 215 212 TRANS_DDI_PORT_MASK); 216 213 ··· 258 255 * TRANSCODER_A can be enabled. PORT_x depends on the input of 259 256 * setup_virtual_dp_monitor. 260 257 */ 261 - vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE; 262 - vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; 258 + vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; 259 + vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; 263 260 264 261 /* 265 262 * Golden M/N are calculated based on: ··· 267 264 * DP link clk 1620 MHz and non-constant_n. 268 265 * TODO: calculate DP link symbol clk and stream clk m/n. 269 266 */ 270 - vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); 271 - vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; 272 - vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; 273 - vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; 274 - vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000; 267 + vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); 268 + vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; 269 + vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; 270 + vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; 271 + vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; 275 272 276 273 /* Enable per-DDI/PORT vreg */ 277 274 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { ··· 294 291 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= 295 292 ~DDI_BUF_IS_IDLE; 296 293 vgpu_vreg_t(vgpu, 297 - TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)) |= 294 + TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)) |= 298 295 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 299 296 TRANS_DDI_FUNC_ENABLE); 300 297 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= ··· 324 321 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= 325 322 ~DDI_BUF_IS_IDLE; 326 323 vgpu_vreg_t(vgpu, 327 - TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= 324 + TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 328 325 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 329 326 (PORT_B << TRANS_DDI_PORT_SHIFT) | 330 327 TRANS_DDI_FUNC_ENABLE); ··· 355 352 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= 356 353 ~DDI_BUF_IS_IDLE; 357 354 vgpu_vreg_t(vgpu, 358 - TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= 355 + TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 359 356 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 360 357 (PORT_B << TRANS_DDI_PORT_SHIFT) | 361 358 TRANS_DDI_FUNC_ENABLE); ··· 404 401 * DP link clk 1620 MHz and non-constant_n. 405 402 * TODO: calculate DP link symbol clk and stream clk m/n. 406 403 */ 407 - vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); 408 - vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; 409 - vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; 410 - vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; 411 - vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000; 404 + vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); 405 + vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; 406 + vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; 407 + vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; 408 + vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; 412 409 } 413 410 414 411 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { ··· 419 416 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 420 417 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); 421 418 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 422 - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= 419 + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 423 420 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 424 421 TRANS_DDI_PORT_MASK); 425 - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= 422 + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 426 423 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 427 424 (PORT_B << TRANS_DDI_PORT_SHIFT) | 428 425 TRANS_DDI_FUNC_ENABLE); ··· 445 442 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 446 443 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); 447 444 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 448 - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= 445 + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 449 446 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 450 447 TRANS_DDI_PORT_MASK); 451 - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= 448 + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 452 449 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 453 450 (PORT_C << TRANS_DDI_PORT_SHIFT) | 454 451 TRANS_DDI_FUNC_ENABLE); ··· 471 468 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 472 469 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); 473 470 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 474 - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= 471 + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 475 472 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 476 473 TRANS_DDI_PORT_MASK); 477 - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= 474 + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 478 475 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 479 476 (PORT_D << TRANS_DDI_PORT_SHIFT) | 480 477 TRANS_DDI_FUNC_ENABLE); ··· 512 509 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 513 510 514 511 /* Disable Primary/Sprite/Cursor plane */ 515 - for_each_pipe(dev_priv, pipe) { 516 - vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; 512 + for_each_pipe(display, pipe) { 513 + vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; 517 514 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 518 - vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; 519 - vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; 515 + vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; 516 + vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; 520 517 } 521 518 522 - vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE; 519 + vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; 523 520 } 524 521 525 522 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) ··· 635 632 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 636 633 { 637 634 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 635 + struct intel_display *display = &dev_priv->display; 638 636 struct intel_vgpu_irq *irq = &vgpu->irq; 639 637 int vblank_event[] = { 640 638 [PIPE_A] = PIPE_A_VBLANK, ··· 657 653 } 658 654 659 655 if (pipe_is_enabled(vgpu, pipe)) { 660 - vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(dev_priv, pipe))++; 656 + vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++; 661 657 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 662 658 } 663 659 } 664 660 665 661 void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu) 666 662 { 663 + struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 664 + struct intel_display *display = &i915->display; 667 665 int pipe; 668 666 669 667 mutex_lock(&vgpu->vgpu_lock); 670 - for_each_pipe(vgpu->gvt->gt->i915, pipe) 668 + for_each_pipe(display, pipe) 671 669 emulate_vblank_on_pipe(vgpu, pipe); 672 670 mutex_unlock(&vgpu->vgpu_lock); 673 671 }
+12 -9
drivers/gpu/drm/i915/gvt/fb_decoder.c
··· 154 154 u32 tiled, int stride_mask, int bpp) 155 155 { 156 156 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 157 + struct intel_display *display = &dev_priv->display; 157 158 158 - u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(dev_priv, pipe)) & stride_mask; 159 + u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask; 159 160 u32 stride = stride_reg; 160 161 161 162 if (GRAPHICS_VER(dev_priv) >= 9) { ··· 211 210 struct intel_vgpu_primary_plane_format *plane) 212 211 { 213 212 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 213 + struct intel_display *display = &dev_priv->display; 214 214 u32 val, fmt; 215 215 int pipe; 216 216 ··· 219 217 if (pipe >= I915_MAX_PIPES) 220 218 return -ENODEV; 221 219 222 - val = vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)); 220 + val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)); 223 221 plane->enabled = !!(val & DISP_ENABLE); 224 222 if (!plane->enabled) 225 223 return -ENODEV; ··· 253 251 254 252 plane->hw_format = fmt; 255 253 256 - plane->base = vgpu_vreg_t(vgpu, DSPSURF(dev_priv, pipe)) & I915_GTT_PAGE_MASK; 254 + plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK; 257 255 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) 258 256 return -EINVAL; 259 257 ··· 269 267 (_PRI_PLANE_STRIDE_MASK >> 6) : 270 268 _PRI_PLANE_STRIDE_MASK, plane->bpp); 271 269 272 - plane->width = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) & _PIPE_H_SRCSZ_MASK) >> 270 + plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >> 273 271 _PIPE_H_SRCSZ_SHIFT; 274 272 plane->width += 1; 275 - plane->height = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) & 273 + plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & 276 274 _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT; 277 275 plane->height += 1; /* raw height is one minus the real value */ 278 276 279 - val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe)); 277 + val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe)); 280 278 plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >> 281 279 _PRI_PLANE_X_OFF_SHIFT; 282 280 plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >> ··· 342 340 struct intel_vgpu_cursor_plane_format *plane) 343 341 { 344 342 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 343 + struct intel_display *display = &dev_priv->display; 345 344 u32 val, mode, index; 346 345 u32 alpha_plane, alpha_force; 347 346 int pipe; ··· 351 348 if (pipe >= I915_MAX_PIPES) 352 349 return -ENODEV; 353 350 354 - val = vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)); 351 + val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe)); 355 352 mode = val & MCURSOR_MODE_MASK; 356 353 plane->enabled = (mode != MCURSOR_MODE_DISABLE); 357 354 if (!plane->enabled) ··· 377 374 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n", 378 375 alpha_plane, alpha_force); 379 376 380 - plane->base = vgpu_vreg_t(vgpu, CURBASE(dev_priv, pipe)) & I915_GTT_PAGE_MASK; 377 + plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK; 381 378 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) 382 379 return -EINVAL; 383 380 ··· 388 385 return -EINVAL; 389 386 } 390 387 391 - val = vgpu_vreg_t(vgpu, CURPOS(dev_priv, pipe)); 388 + val = vgpu_vreg_t(vgpu, CURPOS(display, pipe)); 392 389 plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT; 393 390 plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT; 394 391 plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
+24 -20
drivers/gpu/drm/i915/gvt/handlers.c
··· 656 656 static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) 657 657 { 658 658 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 659 + struct intel_display *display = &dev_priv->display; 659 660 enum port port; 660 661 u32 dp_br, link_m, link_n, htotal, vtotal; 661 662 662 663 /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */ 663 - port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) & 664 + port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) & 664 665 TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 665 666 if (port != PORT_B && port != PORT_D) { 666 667 gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port)); ··· 677 676 dp_br = skl_vgpu_get_dp_bitrate(vgpu, port); 678 677 679 678 /* Get DP link symbol clock M/N */ 680 - link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)); 681 - link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)); 679 + link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)); 680 + link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)); 682 681 683 682 /* Get H/V total from transcoder timing */ 684 - htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); 685 - vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); 683 + htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); 684 + vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); 686 685 687 686 if (dp_br && link_n && htotal && vtotal) { 688 687 u64 pixel_clk = 0; ··· 1013 1012 return 0; 1014 1013 } 1015 1014 1016 - #define DSPSURF_TO_PIPE(dev_priv, offset) \ 1017 - calc_index(offset, DSPSURF(dev_priv, PIPE_A), DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C)) 1015 + #define DSPSURF_TO_PIPE(display, offset) \ 1016 + calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C)) 1018 1017 1019 1018 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1020 1019 void *p_data, unsigned int bytes) 1021 1020 { 1022 1021 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1023 - u32 pipe = DSPSURF_TO_PIPE(dev_priv, offset); 1022 + struct intel_display *display = &dev_priv->display; 1023 + u32 pipe = DSPSURF_TO_PIPE(display, offset); 1024 1024 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); 1025 1025 1026 1026 write_vreg(vgpu, offset, p_data, bytes); 1027 - vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset); 1027 + vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset); 1028 1028 1029 - vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++; 1029 + vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++; 1030 1030 1031 - if (vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) & PLANE_CTL_ASYNC_FLIP) 1031 + if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP) 1032 1032 intel_vgpu_trigger_virtual_event(vgpu, event); 1033 1033 else 1034 1034 set_bit(event, vgpu->irq.flip_done_event[pipe]); ··· 1062 1060 unsigned int bytes) 1063 1061 { 1064 1062 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1063 + struct intel_display *display = &dev_priv->display; 1065 1064 enum pipe pipe = REG_50080_TO_PIPE(offset); 1066 1065 enum plane_id plane = REG_50080_TO_PLANE(offset); 1067 1066 int event = SKL_FLIP_EVENT(pipe, plane); 1068 1067 1069 1068 write_vreg(vgpu, offset, p_data, bytes); 1070 1069 if (plane == PLANE_PRIMARY) { 1071 - vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset); 1072 - vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++; 1070 + vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset); 1071 + vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++; 1073 1072 } else { 1074 1073 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1075 1074 } ··· 2196 2193 static int init_generic_mmio_info(struct intel_gvt *gvt) 2197 2194 { 2198 2195 struct drm_i915_private *dev_priv = gvt->gt->i915; 2196 + struct intel_display *display = &dev_priv->display; 2199 2197 int ret; 2200 2198 2201 2199 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, ··· 2285 2281 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2286 2282 2287 2283 /* display */ 2288 - MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_A), D_ALL, NULL, 2284 + MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL, 2289 2285 pipeconf_mmio_write); 2290 - MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_B), D_ALL, NULL, 2286 + MMIO_DH(TRANSCONF(display, TRANSCODER_B), D_ALL, NULL, 2291 2287 pipeconf_mmio_write); 2292 - MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_C), D_ALL, NULL, 2288 + MMIO_DH(TRANSCONF(display, TRANSCODER_C), D_ALL, NULL, 2293 2289 pipeconf_mmio_write); 2294 - MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_EDP), D_ALL, NULL, 2290 + MMIO_DH(TRANSCONF(display, TRANSCODER_EDP), D_ALL, NULL, 2295 2291 pipeconf_mmio_write); 2296 - MMIO_DH(DSPSURF(dev_priv, PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2292 + MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2297 2293 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, 2298 2294 reg50080_mmio_write); 2299 - MMIO_DH(DSPSURF(dev_priv, PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2295 + MMIO_DH(DSPSURF(display, PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2300 2296 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, 2301 2297 reg50080_mmio_write); 2302 - MMIO_DH(DSPSURF(dev_priv, PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2298 + MMIO_DH(DSPSURF(display, PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2303 2299 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, 2304 2300 reg50080_mmio_write); 2305 2301 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);