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drm/amdgpu: Use SMUIO 15.0.0 offsets for TSC upper and lower count.

Define and use regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0 and
regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0 for TSC upper and lower count.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Signed-off-by: Ramalingeswara Reddy, Kanala <Kanala.RamalingeswaraReddy@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

authored by

Ramalingeswara Reddy, Kanala and committed by
Alex Deucher 574b3b14 a094bcf2

+26 -5
+26 -5
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 64 64 #define regPC_CONFIG_CNTL_1 0x194d 65 65 #define regPC_CONFIG_CNTL_1_BASE_IDX 1 66 66 67 + #define regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0 0x0030 68 + #define regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0_BASE_IDX 1 69 + #define regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0 0x0031 70 + #define regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0_BASE_IDX 1 71 + 67 72 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 68 73 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 69 74 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 ··· 5239 5234 amdgpu_gfx_off_ctrl(adev, true); 5240 5235 } else { 5241 5236 preempt_disable(); 5242 - clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 5243 - clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 5244 - clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 5245 - if (clock_counter_hi_pre != clock_counter_hi_after) 5246 - clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 5237 + if (amdgpu_ip_version(adev, SMUIO_HWIP, 0) < IP_VERSION(15, 0, 0)) { 5238 + clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, 5239 + regGOLDEN_TSC_COUNT_UPPER); 5240 + clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, 5241 + regGOLDEN_TSC_COUNT_LOWER); 5242 + clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, 5243 + regGOLDEN_TSC_COUNT_UPPER); 5244 + if (clock_counter_hi_pre != clock_counter_hi_after) 5245 + clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, 5246 + regGOLDEN_TSC_COUNT_LOWER); 5247 + } else { 5248 + clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, 5249 + regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0); 5250 + clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, 5251 + regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0); 5252 + clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, 5253 + regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0); 5254 + if (clock_counter_hi_pre != clock_counter_hi_after) 5255 + clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, 5256 + regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0); 5257 + } 5247 5258 preempt_enable(); 5248 5259 } 5249 5260 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);