Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A handful of driver fixes.
The sunxi fixes are for an incorrect clk tree configuration and a bad
frequency calculation. The other two are fixes for passing the wrong
pointer in drivers recently converted to clk_hw style registration"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: efm32gg: Pass correct type to hw provider registration
clk: berlin: Pass correct type to hw provider registration
clk: sunxi: Fix M factor computation for APB1
clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent
+16
-4
+1
-1
drivers/clk/berlin/bg2.c
+1
-1
drivers/clk/berlin/bg2.c
+1
-1
drivers/clk/berlin/bg2q.c
+1
-1
drivers/clk/berlin/bg2q.c
+1
-1
drivers/clk/clk-efm32gg.c
+1
-1
drivers/clk/clk-efm32gg.c
···
82
82
hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0",
83
83
"HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);
84
84
85
-
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data);
85
+
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
86
86
}
87
87
CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
+12
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+12
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
···
191
191
static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
192
192
0x050, 0, 3, axi_div_table, 0);
193
193
194
+
#define SUN6I_A31_AHB1_REG 0x054
195
+
194
196
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
195
197
"axi", "pll-periph" };
196
198
···
1231
1229
val = readl(reg + SUN6I_A31_PLL_MIPI_REG);
1232
1230
val &= BIT(16);
1233
1231
writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
1232
+
1233
+
/* Force AHB1 to PLL6 / 3 */
1234
+
val = readl(reg + SUN6I_A31_AHB1_REG);
1235
+
/* set PLL6 pre-div = 3 */
1236
+
val &= ~GENMASK(7, 6);
1237
+
val |= 0x2 << 6;
1238
+
/* select PLL6 / pre-div */
1239
+
val &= ~GENMASK(13, 12);
1240
+
val |= 0x3 << 12;
1241
+
writel(val, reg + SUN6I_A31_AHB1_REG);
1234
1242
1235
1243
sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);
1236
1244