tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2022-09-16' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"This is the regular drm fixes pull.

The i915 and misc fixes are fairly regular, but the amdgpu contains
fixes for new hw blocks, the dcn314 specific path hookups and also has
a bunch of fixes for clang stack size warnings which are a bit churny
but fairly straightforward. This means it looks a little larger than
usual.

amdgpu:
- BACO fixes for some RDNA2 boards
- PCI AER fixes uncovered by a core PCI change
- Properly hook up dirtyfb helper
- RAS fixes for GC 11.x
- TMR fix
- DCN 3.2.x fixes
- DCN 3.1.4 fixes
- LLVM DML stack size fixes

i915:
- Revert a display patch around max DP source rate now that the
proper WaEdpLinkRateDataReload is in place
- Fix perf limit reasons bit position
- Fix unclaimmed mmio registers on suspend flow with GuC
- A vma_move_to_active fix for a regression with video decoding
- DP DSP fix

gma500:
- Locking and IRQ fixes

meson:
- OSD1 display fixes

panel-edp:
- Fix Innolux timings

rockchip:
- DP/HDMI fixes"

* tag 'drm-fixes-2022-09-16' of git://anongit.freedesktop.org/drm/drm: (42 commits)
drm/amdgpu: make sure to init common IP before gmc
drm/amdgpu: move nbio sdma_doorbell_range() into sdma code for vega
drm/amdgpu: move nbio ih_doorbell_range() into ih code for vega
drm/rockchip: Fix return type of cdn_dp_connector_mode_valid
drm/amd/display: Mark dml30's UseMinimumDCFCLK() as noinline for stack usage
drm/amd/display: Reduce number of arguments of dml31's CalculateFlipSchedule()
drm/amd/display: Reduce number of arguments of dml31's CalculateWatermarksAndDRAMSpeedChangeSupport()
drm/amd/display: Reduce number of arguments of dml32_CalculatePrefetchSchedule()
drm/amd/display: Reduce number of arguments of dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
drm/amd/display: Refactor SubVP calculation to remove FPU
drm/amd/display: Limit user regamma to a valid value
drm/amd/display: add workaround for subvp cursor corruption for DCN32/321
drm/amd/display: SW cursor fallback for SubVP
drm/amd/display: Round cursor width up for MALL allocation
drm/amd/display: Correct dram channel width for dcn314
drm/amd/display: Relax swizzle checks for video non-RGB formats on DCN314
drm/amd/display: Hook up DCN314 specific dml implementation
drm/amd/display: Enable dlg and vba compilation for dcn314
drm/amd/display: Fix compilation errors on DCN314
drm/amd/display: Fix divide by zero in DML
...

Linus Torvalds 5763d7f2 714820c6

+653 -906
+11 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 2365 2365 } 2366 2366 adev->ip_blocks[i].status.sw = true; 2367 2367 2368 - /* need to do gmc hw init early so we can allocate gpu mem */ 2369 - if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { 2368 + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { 2369 + /* need to do common hw init early so everything is set up for gmc */ 2370 + r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); 2371 + if (r) { 2372 + DRM_ERROR("hw_init %d failed %d\n", i, r); 2373 + goto init_failed; 2374 + } 2375 + adev->ip_blocks[i].status.hw = true; 2376 + } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { 2377 + /* need to do gmc hw init early so we can allocate gpu mem */ 2370 2378 /* Try to reserve bad pages early */ 2371 2379 if (amdgpu_sriov_vf(adev)) 2372 2380 amdgpu_virt_exchange_data(adev); ··· 3060 3052 int i, r; 3061 3053 3062 3054 static enum amd_ip_block_type ip_order[] = { 3063 - AMD_IP_BLOCK_TYPE_GMC, 3064 3055 AMD_IP_BLOCK_TYPE_COMMON, 3056 + AMD_IP_BLOCK_TYPE_GMC, 3065 3057 AMD_IP_BLOCK_TYPE_PSP, 3066 3058 AMD_IP_BLOCK_TYPE_IH, 3067 3059 };
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
··· 38 38 #include <linux/pci.h> 39 39 #include <linux/pm_runtime.h> 40 40 #include <drm/drm_crtc_helper.h> 41 + #include <drm/drm_damage_helper.h> 41 42 #include <drm/drm_edid.h> 42 43 #include <drm/drm_gem_framebuffer_helper.h> 43 44 #include <drm/drm_fb_helper.h> ··· 497 496 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 498 497 .destroy = drm_gem_fb_destroy, 499 498 .create_handle = drm_gem_fb_create_handle, 499 + .dirty = drm_atomic_helper_dirtyfb, 500 500 }; 501 501 502 502 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
··· 756 756 } 757 757 758 758 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 759 - ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 759 + ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT, 760 760 AMDGPU_GEM_DOMAIN_VRAM, 761 761 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 762 762
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
··· 36 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 37 #define PSP_1_MEG 0x100000 38 38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 39 + #define PSP_TMR_ALIGNMENT 0x100000 39 40 #define PSP_FW_NAME_LEN 0x24 40 41 41 42 enum psp_shared_mem_size {
+2 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
··· 1811 1811 amdgpu_ras_query_error_status(adev, &info); 1812 1812 1813 1813 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && 1814 - adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) { 1814 + adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) && 1815 + adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) { 1815 1816 if (amdgpu_ras_reset_error_status(adev, info.head.block)) 1816 1817 dev_warn(adev->dev, "Failed to reset error counter and error status"); 1817 1818 }
+8 -1
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
··· 380 380 WREG32_PCIE(smnPCIE_LC_CNTL, data); 381 381 } 382 382 383 + #ifdef CONFIG_PCIEASPM 383 384 static void nbio_v2_3_program_ltr(struct amdgpu_device *adev) 384 385 { 385 386 uint32_t def, data; ··· 402 401 if (def != data) 403 402 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 404 403 } 404 + #endif 405 405 406 406 static void nbio_v2_3_program_aspm(struct amdgpu_device *adev) 407 407 { 408 + #ifdef CONFIG_PCIEASPM 408 409 uint32_t def, data; 409 410 410 411 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); ··· 462 459 if (def != data) 463 460 WREG32_PCIE(smnPCIE_LC_CNTL6, data); 464 461 465 - nbio_v2_3_program_ltr(adev); 462 + /* Don't bother about LTR if LTR is not enabled 463 + * in the path */ 464 + if (adev->pdev->ltr_path) 465 + nbio_v2_3_program_ltr(adev); 466 466 467 467 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); 468 468 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; ··· 489 483 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 490 484 if (def != data) 491 485 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 486 + #endif 492 487 } 493 488 494 489 static void nbio_v2_3_apply_lc_spc_mode_wa(struct amdgpu_device *adev)
+8 -1
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
··· 282 282 mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 283 283 } 284 284 285 + #ifdef CONFIG_PCIEASPM 285 286 static void nbio_v6_1_program_ltr(struct amdgpu_device *adev) 286 287 { 287 288 uint32_t def, data; ··· 304 303 if (def != data) 305 304 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 306 305 } 306 + #endif 307 307 308 308 static void nbio_v6_1_program_aspm(struct amdgpu_device *adev) 309 309 { 310 + #ifdef CONFIG_PCIEASPM 310 311 uint32_t def, data; 311 312 312 313 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); ··· 364 361 if (def != data) 365 362 WREG32_PCIE(smnPCIE_LC_CNTL6, data); 366 363 367 - nbio_v6_1_program_ltr(adev); 364 + /* Don't bother about LTR if LTR is not enabled 365 + * in the path */ 366 + if (adev->pdev->ltr_path) 367 + nbio_v6_1_program_ltr(adev); 368 368 369 369 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 370 370 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; ··· 391 385 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 392 386 if (def != data) 393 387 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 388 + #endif 394 389 } 395 390 396 391 const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
+8 -1
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
··· 673 673 }; 674 674 675 675 676 + #ifdef CONFIG_PCIEASPM 676 677 static void nbio_v7_4_program_ltr(struct amdgpu_device *adev) 677 678 { 678 679 uint32_t def, data; ··· 695 694 if (def != data) 696 695 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 697 696 } 697 + #endif 698 698 699 699 static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) 700 700 { 701 + #ifdef CONFIG_PCIEASPM 701 702 uint32_t def, data; 702 703 703 704 if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(7, 4, 4)) ··· 758 755 if (def != data) 759 756 WREG32_PCIE(smnPCIE_LC_CNTL6, data); 760 757 761 - nbio_v7_4_program_ltr(adev); 758 + /* Don't bother about LTR if LTR is not enabled 759 + * in the path */ 760 + if (adev->pdev->ltr_path) 761 + nbio_v7_4_program_ltr(adev); 762 762 763 763 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 764 764 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; ··· 785 779 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 786 780 if (def != data) 787 781 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 782 + #endif 788 783 } 789 784 790 785 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+9
drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
··· 28 28 #include "nbio/nbio_7_7_0_sh_mask.h" 29 29 #include <uapi/linux/kfd_ioctl.h> 30 30 31 + static void nbio_v7_7_remap_hdp_registers(struct amdgpu_device *adev) 32 + { 33 + WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 34 + adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 35 + WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 36 + adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 37 + } 38 + 31 39 static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev) 32 40 { 33 41 u32 tmp; ··· 344 336 .get_clockgating_state = nbio_v7_7_get_clockgating_state, 345 337 .ih_control = nbio_v7_7_ih_control, 346 338 .init_registers = nbio_v7_7_init_registers, 339 + .remap_hdp_registers = nbio_v7_7_remap_hdp_registers, 347 340 };
+5
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
··· 1504 1504 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1505 1505 1506 1506 if (!amdgpu_sriov_vf(adev)) { 1507 + ring = &adev->sdma.instance[i].ring; 1508 + adev->nbio.funcs->sdma_doorbell_range(adev, i, 1509 + ring->use_doorbell, ring->doorbell_index, 1510 + adev->doorbell_index.sdma_doorbell_range); 1511 + 1507 1512 /* unhalt engine */ 1508 1513 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1509 1514 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
-25
drivers/gpu/drm/amd/amdgpu/soc15.c
··· 1211 1211 return 0; 1212 1212 } 1213 1213 1214 - static void soc15_doorbell_range_init(struct amdgpu_device *adev) 1215 - { 1216 - int i; 1217 - struct amdgpu_ring *ring; 1218 - 1219 - /* sdma/ih doorbell range are programed by hypervisor */ 1220 - if (!amdgpu_sriov_vf(adev)) { 1221 - for (i = 0; i < adev->sdma.num_instances; i++) { 1222 - ring = &adev->sdma.instance[i].ring; 1223 - adev->nbio.funcs->sdma_doorbell_range(adev, i, 1224 - ring->use_doorbell, ring->doorbell_index, 1225 - adev->doorbell_index.sdma_doorbell_range); 1226 - } 1227 - 1228 - adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 1229 - adev->irq.ih.doorbell_index); 1230 - } 1231 - } 1232 - 1233 1214 static int soc15_common_hw_init(void *handle) 1234 1215 { 1235 1216 struct amdgpu_device *adev = (struct amdgpu_device *)handle; ··· 1230 1249 1231 1250 /* enable the doorbell aperture */ 1232 1251 soc15_enable_doorbell_aperture(adev, true); 1233 - /* HW doorbell routing policy: doorbell writing not 1234 - * in SDMA/IH/MM/ACV range will be routed to CP. So 1235 - * we need to init SDMA/IH/MM/ACV doorbell range prior 1236 - * to CP ip block init and ring test. 1237 - */ 1238 - soc15_doorbell_range_init(adev); 1239 1252 1240 1253 return 0; 1241 1254 }
+1
drivers/gpu/drm/amd/amdgpu/soc21.c
··· 421 421 { 422 422 switch (adev->ip_versions[GC_HWIP][0]) { 423 423 case IP_VERSION(11, 0, 0): 424 + return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC); 424 425 case IP_VERSION(11, 0, 2): 425 426 return false; 426 427 default:
+4
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
··· 289 289 } 290 290 } 291 291 292 + if (!amdgpu_sriov_vf(adev)) 293 + adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 294 + adev->irq.ih.doorbell_index); 295 + 292 296 pci_set_master(adev->pdev); 293 297 294 298 /* enable interrupts */
+4
drivers/gpu/drm/amd/amdgpu/vega20_ih.c
··· 340 340 } 341 341 } 342 342 343 + if (!amdgpu_sriov_vf(adev)) 344 + adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 345 + adev->irq.ih.doorbell_index); 346 + 343 347 pci_set_master(adev->pdev); 344 348 345 349 /* enable interrupts */
+2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
··· 670 670 } 671 671 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); 672 672 bw_params->vram_type = bios_info->memory_type; 673 + 674 + bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; 673 675 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4; 674 676 675 677 for (i = 0; i < WM_SET_COUNT; i++) {
+1 -1
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
··· 329 329 330 330 dc = stream->ctx->dc; 331 331 332 - if (attributes->height * attributes->width * 4 > 16384) 332 + if (dc->debug.allow_sw_cursor_fallback && attributes->height * attributes->width * 4 > 16384) 333 333 if (stream->mall_stream_config.type == SUBVP_MAIN) 334 334 return false; 335 335
+1
drivers/gpu/drm/amd/display/dc/dc.h
··· 745 745 bool disable_fixed_vs_aux_timeout_wa; 746 746 bool force_disable_subvp; 747 747 bool force_subvp_mclk_switch; 748 + bool allow_sw_cursor_fallback; 748 749 bool force_usr_allow; 749 750 /* uses value at boot and disables switch */ 750 751 bool disable_dtb_ref_clk_switch;
+43 -44
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
··· 417 417 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 418 418 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; 419 419 struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; 420 - int16_t drr_frame_us = 0; 421 - int16_t min_drr_supported_us = 0; 422 - int16_t max_drr_supported_us = 0; 423 - int16_t max_drr_vblank_us = 0; 424 - int16_t max_drr_mallregion_us = 0; 425 - int16_t mall_region_us = 0; 426 - int16_t prefetch_us = 0; 427 - int16_t subvp_active_us = 0; 428 - int16_t drr_active_us = 0; 429 - int16_t min_vtotal_supported = 0; 430 - int16_t max_vtotal_supported = 0; 420 + uint16_t drr_frame_us = 0; 421 + uint16_t min_drr_supported_us = 0; 422 + uint16_t max_drr_supported_us = 0; 423 + uint16_t max_drr_vblank_us = 0; 424 + uint16_t max_drr_mallregion_us = 0; 425 + uint16_t mall_region_us = 0; 426 + uint16_t prefetch_us = 0; 427 + uint16_t subvp_active_us = 0; 428 + uint16_t drr_active_us = 0; 429 + uint16_t min_vtotal_supported = 0; 430 + uint16_t max_vtotal_supported = 0; 431 431 432 432 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; 433 433 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping 434 434 pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now 435 435 436 - drr_frame_us = div64_s64(drr_timing->v_total * drr_timing->h_total, 437 - (int64_t)(drr_timing->pix_clk_100hz * 100) * 1000000); 436 + drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000), 437 + (((uint64_t)drr_timing->pix_clk_100hz * 100))); 438 438 // P-State allow width and FW delays already included phantom_timing->v_addressable 439 - mall_region_us = div64_s64(phantom_timing->v_addressable * phantom_timing->h_total, 440 - (int64_t)(phantom_timing->pix_clk_100hz * 100) * 1000000); 439 + mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000), 440 + (((uint64_t)phantom_timing->pix_clk_100hz * 100))); 441 441 min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 442 - min_vtotal_supported = div64_s64(drr_timing->pix_clk_100hz * 100 * 443 - (div64_s64((int64_t)min_drr_supported_us, 1000000)), 444 - (int64_t)drr_timing->h_total); 442 + min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us), 443 + (((uint64_t)drr_timing->h_total * 1000000))); 445 444 446 - prefetch_us = div64_s64((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total, 447 - (int64_t)(phantom_timing->pix_clk_100hz * 100) * 1000000 + 448 - dc->caps.subvp_prefetch_end_to_mall_start_us); 449 - subvp_active_us = div64_s64(main_timing->v_addressable * main_timing->h_total, 450 - (int64_t)(main_timing->pix_clk_100hz * 100) * 1000000); 451 - drr_active_us = div64_s64(drr_timing->v_addressable * drr_timing->h_total, 452 - (int64_t)(drr_timing->pix_clk_100hz * 100) * 1000000); 453 - max_drr_vblank_us = div64_s64((int64_t)(subvp_active_us - prefetch_us - drr_active_us), 2) + drr_active_us; 445 + prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000), 446 + (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 447 + subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000), 448 + (((uint64_t)main_timing->pix_clk_100hz * 100))); 449 + drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000), 450 + (((uint64_t)drr_timing->pix_clk_100hz * 100))); 451 + max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us - drr_active_us), 2) + drr_active_us; 454 452 max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us; 455 453 max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us; 456 - max_vtotal_supported = div64_s64(drr_timing->pix_clk_100hz * 100 * (div64_s64((int64_t)max_drr_supported_us, 1000000)), 457 - (int64_t)drr_timing->h_total); 454 + max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us), 455 + (((uint64_t)drr_timing->h_total * 1000000))); 458 456 459 457 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; 460 458 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; ··· 546 548 struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing; 547 549 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL; 548 550 549 - subvp0_prefetch_us = div64_s64((phantom_timing0->v_total - phantom_timing0->v_front_porch) * phantom_timing0->h_total, 550 - (int64_t)(phantom_timing0->pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us); 551 - subvp1_prefetch_us = div64_s64((phantom_timing1->v_total - phantom_timing1->v_front_porch) * phantom_timing1->h_total, 552 - (int64_t)(phantom_timing1->pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us); 551 + subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * 552 + (uint64_t)phantom_timing0->h_total * 1000000), 553 + (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 554 + subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * 555 + (uint64_t)phantom_timing1->h_total * 1000000), 556 + (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 553 557 554 558 // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time) 555 559 // should increase it's prefetch time to match the other ··· 559 559 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; 560 560 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; 561 561 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 562 - div64_s64(((div64_s64((int64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us), 1000000)) * 563 - (phantom_timing1->pix_clk_100hz * 100) + phantom_timing1->h_total - 1), 564 - (int64_t)phantom_timing1->h_total); 562 + div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 563 + ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)), 564 + ((uint64_t)phantom_timing1->h_total * 1000000)); 565 + 565 566 } else if (subvp1_prefetch_us > subvp0_prefetch_us) { 566 567 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; 567 568 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; 568 569 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 569 - div64_s64(((div64_s64((int64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us), 1000000)) * 570 - (phantom_timing0->pix_clk_100hz * 100) + phantom_timing0->h_total - 1), 571 - (int64_t)phantom_timing0->h_total); 570 + div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 571 + ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)), 572 + ((uint64_t)phantom_timing0->h_total * 1000000)); 572 573 } 573 574 } 574 575 ··· 631 630 632 631 // Round up 633 632 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 634 - div64_s64(((div64_s64((int64_t)dc->caps.subvp_prefetch_end_to_mall_start_us, 1000000)) * 635 - (phantom_timing->pix_clk_100hz * 100) + phantom_timing->h_total - 1), 636 - (int64_t)phantom_timing->h_total); 633 + div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 634 + ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 637 635 pipe_data->pipe_config.subvp_data.processing_delay_lines = 638 - div64_s64(((div64_s64((int64_t)dc->caps.subvp_fw_processing_delay_us, 1000000)) * 639 - (phantom_timing->pix_clk_100hz * 100) + phantom_timing->h_total - 1), 640 - (int64_t)phantom_timing->h_total); 636 + div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 637 + ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 641 638 // Find phantom pipe index based on phantom stream 642 639 for (j = 0; j < dc->res_pool->pipe_count; j++) { 643 640 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
+1 -2
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
··· 67 67 { 68 68 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 69 69 70 - REG_UPDATE_2(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0, 71 - DIG_FIFO_READ_START_LEVEL, 0); 70 + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0); 72 71 } 73 72 74 73 static void enc314_dp_set_odm_combine(
+23 -1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
··· 103 103 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk( 104 104 attr->width, attr->color_format); 105 105 106 + //Round cursor width up to next multiple of 64 107 + uint32_t cursor_width = ((attr->width + 63) / 64) * 64; 108 + uint32_t cursor_height = attr->height; 109 + uint32_t cursor_size = cursor_width * cursor_height; 110 + 106 111 hubp->curs_attr = *attr; 107 112 108 113 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, ··· 131 126 /* used to shift the cursor chunk request deadline */ 132 127 CURSOR0_CHUNK_HDL_ADJUST, 3); 133 128 134 - if (attr->width * attr->height * 4 > 16384) 129 + switch (attr->color_format) { 130 + case CURSOR_MODE_MONO: 131 + cursor_size /= 2; 132 + break; 133 + case CURSOR_MODE_COLOR_1BIT_AND: 134 + case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 135 + case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 136 + cursor_size *= 4; 137 + break; 138 + 139 + case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 140 + case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 141 + default: 142 + cursor_size *= 8; 143 + break; 144 + } 145 + 146 + if (cursor_size > 16384) 135 147 REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, true); 136 148 else 137 149 REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, false);
+23 -1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
··· 741 741 struct hubp *hubp = pipe->plane_res.hubp; 742 742 743 743 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 744 - if (hubp->curs_attr.width * hubp->curs_attr.height * 4 > 16384) 744 + //Round cursor width up to next multiple of 64 745 + int cursor_width = ((hubp->curs_attr.width + 63) / 64) * 64; 746 + int cursor_height = hubp->curs_attr.height; 747 + int cursor_size = cursor_width * cursor_height; 748 + 749 + switch (hubp->curs_attr.color_format) { 750 + case CURSOR_MODE_MONO: 751 + cursor_size /= 2; 752 + break; 753 + case CURSOR_MODE_COLOR_1BIT_AND: 754 + case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 755 + case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 756 + cursor_size *= 4; 757 + break; 758 + 759 + case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 760 + case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 761 + default: 762 + cursor_size *= 8; 763 + break; 764 + } 765 + 766 + if (cursor_size > 16384) 745 767 cache_cursor = true; 746 768 747 769 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+3 -1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
··· 871 871 .exit_idle_opt_for_cursor_updates = true, 872 872 .enable_single_display_2to1_odm_policy = true, 873 873 .enable_dp_dig_pixel_rate_div_policy = 1, 874 + .allow_sw_cursor_fallback = false, 874 875 }; 875 876 876 877 static const struct dc_debug_options debug_defaults_diags = { ··· 2040 2039 dc->caps.max_downscale_ratio = 600; 2041 2040 dc->caps.i2c_speed_in_khz = 100; 2042 2041 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2043 - dc->caps.max_cursor_size = 256; 2042 + /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ 2043 + dc->caps.max_cursor_size = 64; 2044 2044 dc->caps.min_horizontal_blanking_period = 80; 2045 2045 dc->caps.dmdata_alloc_size = 2048; 2046 2046 dc->caps.mall_size_per_mem_channel = 0;
+3
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
··· 30 30 31 31 #define DCN3_2_DET_SEG_SIZE 64 32 32 #define DCN3_2_MALL_MBLK_SIZE_BYTES 65536 // 64 * 1024 33 + #define DCN3_2_MBLK_WIDTH 128 34 + #define DCN3_2_MBLK_HEIGHT_4BPE 128 35 + #define DCN3_2_MBLK_HEIGHT_8BPE 64 33 36 34 37 #define TO_DCN32_RES_POOL(pool)\ 35 38 container_of(pool, struct dcn32_resource_pool, base)
+51 -8
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
··· 46 46 uint32_t dcn32_helper_calculate_num_ways_for_subvp(struct dc *dc, struct dc_state *context) 47 47 { 48 48 uint32_t num_ways = 0; 49 - uint32_t mall_region_pixels = 0; 50 49 uint32_t bytes_per_pixel = 0; 51 50 uint32_t cache_lines_used = 0; 52 51 uint32_t lines_per_way = 0; ··· 53 54 uint32_t bytes_in_mall = 0; 54 55 uint32_t num_mblks = 0; 55 56 uint32_t cache_lines_per_plane = 0; 56 - uint32_t i = 0; 57 + uint32_t i = 0, j = 0; 58 + uint32_t mblk_width = 0; 59 + uint32_t mblk_height = 0; 60 + uint32_t full_vp_width_blk_aligned = 0; 61 + uint32_t full_vp_height_blk_aligned = 0; 62 + uint32_t mall_alloc_width_blk_aligned = 0; 63 + uint32_t mall_alloc_height_blk_aligned = 0; 64 + uint32_t full_vp_height = 0; 57 65 58 66 for (i = 0; i < dc->res_pool->pipe_count; i++) { 59 67 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 60 68 61 69 // Find the phantom pipes 62 - if (pipe->stream && pipe->plane_state && !pipe->top_pipe && 70 + if (pipe->stream && pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && 63 71 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 64 - bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4; 65 - mall_region_pixels = pipe->plane_state->plane_size.surface_pitch * pipe->stream->timing.v_addressable; 72 + struct pipe_ctx *main_pipe = NULL; 66 73 67 - // For bytes required in MALL, calculate based on number of MBlks required 68 - num_mblks = (mall_region_pixels * bytes_per_pixel + 69 - DCN3_2_MALL_MBLK_SIZE_BYTES - 1) / DCN3_2_MALL_MBLK_SIZE_BYTES; 74 + /* Get full viewport height from main pipe (required for MBLK calculation) */ 75 + for (j = 0; j < dc->res_pool->pipe_count; j++) { 76 + main_pipe = &context->res_ctx.pipe_ctx[j]; 77 + if (main_pipe->stream == pipe->stream->mall_stream_config.paired_stream) { 78 + full_vp_height = main_pipe->plane_res.scl_data.viewport.height; 79 + break; 80 + } 81 + } 82 + 83 + bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4; 84 + mblk_width = DCN3_2_MBLK_WIDTH; 85 + mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE; 86 + 87 + /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) - 88 + * FLOOR(vp_x_start, blk_width) 89 + */ 90 + full_vp_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + 91 + pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) + 92 + (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); 93 + 94 + /* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) - 95 + * FLOOR(vp_y_start, blk_height) 96 + */ 97 + full_vp_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y + 98 + full_vp_height + mblk_height - 1) / mblk_height * mblk_height) + 99 + (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height); 100 + 101 + /* mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c */ 102 + mall_alloc_width_blk_aligned = full_vp_width_blk_aligned; 103 + 104 + /* mall_alloc_height_blk_aligned_l/c = CEILING(sub_vp_height_l/c - 1, blk_height_l/c) + blk_height_l/c */ 105 + mall_alloc_height_blk_aligned = (pipe->stream->timing.v_addressable - 1 + mblk_height - 1) / 106 + mblk_height * mblk_height + mblk_height; 107 + 108 + /* full_mblk_width_ub_l/c = mall_alloc_width_blk_aligned_l/c; 109 + * full_mblk_height_ub_l/c = mall_alloc_height_blk_aligned_l/c; 110 + * num_mblk_l/c = (full_mblk_width_ub_l/c / mblk_width_l/c) * (full_mblk_height_ub_l/c / mblk_height_l/c); 111 + * (Should be divisible, but round up if not) 112 + */ 113 + num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) * 114 + ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height); 70 115 bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES; 71 116 // cache lines used is total bytes / cache_line size. Add +2 for worst case alignment 72 117 // (MALL is 64-byte aligned)
+3 -1
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
··· 872 872 .exit_idle_opt_for_cursor_updates = true, 873 873 .enable_single_display_2to1_odm_policy = true, 874 874 .enable_dp_dig_pixel_rate_div_policy = 1, 875 + .allow_sw_cursor_fallback = false, 875 876 }; 876 877 877 878 static const struct dc_debug_options debug_defaults_diags = { ··· 1652 1651 dc->caps.max_downscale_ratio = 600; 1653 1652 dc->caps.i2c_speed_in_khz = 100; 1654 1653 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 1655 - dc->caps.max_cursor_size = 256; 1654 + /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ 1655 + dc->caps.max_cursor_size = 64; 1656 1656 dc->caps.min_horizontal_blanking_period = 80; 1657 1657 dc->caps.dmdata_alloc_size = 2048; 1658 1658 dc->caps.mall_size_per_mem_channel = 0;
+3
drivers/gpu/drm/amd/display/dc/dml/Makefile
··· 70 70 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags) 71 71 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) $(frame_warn_flag) 72 72 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags) 73 + CFLAGS_$(AMDDALPATH)/dc/dml/dcn314/display_mode_vba_314.o := $(dml_ccflags) $(frame_warn_flag) 74 + CFLAGS_$(AMDDALPATH)/dc/dml/dcn314/display_rq_dlg_calc_314.o := $(dml_ccflags) 73 75 CFLAGS_$(AMDDALPATH)/dc/dml/dcn314/dcn314_fpu.o := $(dml_ccflags) 74 76 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags) 75 77 CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/dcn32_fpu.o := $(dml_ccflags) ··· 125 123 DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o 126 124 DML += dcn30/dcn30_fpu.o dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o 127 125 DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o 126 + DML += dcn314/display_mode_vba_314.o dcn314/display_rq_dlg_calc_314.o 128 127 DML += dcn32/display_mode_vba_32.o dcn32/display_rq_dlg_calc_32.o dcn32/display_mode_vba_util_32.o 129 128 DML += dcn31/dcn31_fpu.o 130 129 DML += dcn32/dcn32_fpu.o
+1 -2
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
··· 6610 6610 return ret; 6611 6611 } 6612 6612 6613 - 6614 - static void UseMinimumDCFCLK( 6613 + static noinline_for_stack void UseMinimumDCFCLK( 6615 6614 struct display_mode_lib *mode_lib, 6616 6615 int MaxInterDCNTileRepeaters, 6617 6616 int MaxPrefetchMode,
+99 -321
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
··· 251 251 252 252 static void CalculateFlipSchedule( 253 253 struct display_mode_lib *mode_lib, 254 + unsigned int k, 254 255 double HostVMInefficiencyFactor, 255 256 double UrgentExtraLatency, 256 257 double UrgentLatency, 257 - unsigned int GPUVMMaxPageTableLevels, 258 - bool HostVMEnable, 259 - unsigned int HostVMMaxNonCachedPageTableLevels, 260 - bool GPUVMEnable, 261 - double HostVMMinPageSize, 262 258 double PDEAndMetaPTEBytesPerFrame, 263 259 double MetaRowBytes, 264 - double DPTEBytesPerRow, 265 - double BandwidthAvailableForImmediateFlip, 266 - unsigned int TotImmediateFlipBytes, 267 - enum source_format_class SourcePixelFormat, 268 - double LineTime, 269 - double VRatio, 270 - double VRatioChroma, 271 - double Tno_bw, 272 - bool DCCEnable, 273 - unsigned int dpte_row_height, 274 - unsigned int meta_row_height, 275 - unsigned int dpte_row_height_chroma, 276 - unsigned int meta_row_height_chroma, 277 - double *DestinationLinesToRequestVMInImmediateFlip, 278 - double *DestinationLinesToRequestRowInImmediateFlip, 279 - double *final_flip_bw, 280 - bool *ImmediateFlipSupportedForPipe); 260 + double DPTEBytesPerRow); 281 261 static double CalculateWriteBackDelay( 282 262 enum source_format_class WritebackPixelFormat, 283 263 double WritebackHRatio, ··· 291 311 static void CalculateWatermarksAndDRAMSpeedChangeSupport( 292 312 struct display_mode_lib *mode_lib, 293 313 unsigned int PrefetchMode, 294 - unsigned int NumberOfActivePlanes, 295 - unsigned int MaxLineBufferLines, 296 - unsigned int LineBufferSize, 297 - unsigned int WritebackInterfaceBufferSize, 298 314 double DCFCLK, 299 315 double ReturnBW, 300 - bool SynchronizedVBlank, 301 - unsigned int dpte_group_bytes[], 302 - unsigned int MetaChunkSize, 303 316 double UrgentLatency, 304 317 double ExtraLatency, 305 - double WritebackLatency, 306 - double WritebackChunkSize, 307 318 double SOCCLK, 308 - double DRAMClockChangeLatency, 309 - double SRExitTime, 310 - double SREnterPlusExitTime, 311 - double SRExitZ8Time, 312 - double SREnterPlusExitZ8Time, 313 319 double DCFCLKDeepSleep, 314 320 unsigned int DETBufferSizeY[], 315 321 unsigned int DETBufferSizeC[], 316 322 unsigned int SwathHeightY[], 317 323 unsigned int SwathHeightC[], 318 - unsigned int LBBitPerPixel[], 319 324 double SwathWidthY[], 320 325 double SwathWidthC[], 321 - double HRatio[], 322 - double HRatioChroma[], 323 - unsigned int vtaps[], 324 - unsigned int VTAPsChroma[], 325 - double VRatio[], 326 - double VRatioChroma[], 327 - unsigned int HTotal[], 328 - double PixelClock[], 329 - unsigned int BlendingAndTiming[], 330 326 unsigned int DPPPerPlane[], 331 327 double BytePerPixelDETY[], 332 328 double BytePerPixelDETC[], 333 - double DSTXAfterScaler[], 334 - double DSTYAfterScaler[], 335 - bool WritebackEnable[], 336 - enum source_format_class WritebackPixelFormat[], 337 - double WritebackDestinationWidth[], 338 - double WritebackDestinationHeight[], 339 - double WritebackSourceHeight[], 340 329 bool UnboundedRequestEnabled, 341 330 int unsigned CompressedBufferSizeInkByte, 342 331 enum clock_change_support *DRAMClockChangeSupport, 343 - double *UrgentWatermark, 344 - double *WritebackUrgentWatermark, 345 - double *DRAMClockChangeWatermark, 346 - double *WritebackDRAMClockChangeWatermark, 347 332 double *StutterExitWatermark, 348 333 double *StutterEnterPlusExitWatermark, 349 334 double *Z8StutterExitWatermark, 350 - double *Z8StutterEnterPlusExitWatermark, 351 - double *MinActiveDRAMClockChangeLatencySupported); 335 + double *Z8StutterEnterPlusExitWatermark); 352 336 353 337 static void CalculateDCFCLKDeepSleep( 354 338 struct display_mode_lib *mode_lib, ··· 2848 2904 for (k = 0; k < v->NumberOfActivePlanes; ++k) { 2849 2905 CalculateFlipSchedule( 2850 2906 mode_lib, 2907 + k, 2851 2908 HostVMInefficiencyFactor, 2852 2909 v->UrgentExtraLatency, 2853 2910 v->UrgentLatency, 2854 - v->GPUVMMaxPageTableLevels, 2855 - v->HostVMEnable, 2856 - v->HostVMMaxNonCachedPageTableLevels, 2857 - v->GPUVMEnable, 2858 - v->HostVMMinPageSize, 2859 2911 v->PDEAndMetaPTEBytesFrame[k], 2860 2912 v->MetaRowByte[k], 2861 - v->PixelPTEBytesPerRow[k], 2862 - v->BandwidthAvailableForImmediateFlip, 2863 - v->TotImmediateFlipBytes, 2864 - v->SourcePixelFormat[k], 2865 - v->HTotal[k] / v->PixelClock[k], 2866 - v->VRatio[k], 2867 - v->VRatioChroma[k], 2868 - v->Tno_bw[k], 2869 - v->DCCEnable[k], 2870 - v->dpte_row_height[k], 2871 - v->meta_row_height[k], 2872 - v->dpte_row_height_chroma[k], 2873 - v->meta_row_height_chroma[k], 2874 - &v->DestinationLinesToRequestVMInImmediateFlip[k], 2875 - &v->DestinationLinesToRequestRowInImmediateFlip[k], 2876 - &v->final_flip_bw[k], 2877 - &v->ImmediateFlipSupportedForPipe[k]); 2913 + v->PixelPTEBytesPerRow[k]); 2878 2914 } 2879 2915 2880 2916 v->total_dcn_read_bw_with_flip = 0.0; ··· 2941 3017 CalculateWatermarksAndDRAMSpeedChangeSupport( 2942 3018 mode_lib, 2943 3019 PrefetchMode, 2944 - v->NumberOfActivePlanes, 2945 - v->MaxLineBufferLines, 2946 - v->LineBufferSize, 2947 - v->WritebackInterfaceBufferSize, 2948 3020 v->DCFCLK, 2949 3021 v->ReturnBW, 2950 - v->SynchronizedVBlank, 2951 - v->dpte_group_bytes, 2952 - v->MetaChunkSize, 2953 3022 v->UrgentLatency, 2954 3023 v->UrgentExtraLatency, 2955 - v->WritebackLatency, 2956 - v->WritebackChunkSize, 2957 3024 v->SOCCLK, 2958 - v->DRAMClockChangeLatency, 2959 - v->SRExitTime, 2960 - v->SREnterPlusExitTime, 2961 - v->SRExitZ8Time, 2962 - v->SREnterPlusExitZ8Time, 2963 3025 v->DCFCLKDeepSleep, 2964 3026 v->DETBufferSizeY, 2965 3027 v->DETBufferSizeC, 2966 3028 v->SwathHeightY, 2967 3029 v->SwathHeightC, 2968 - v->LBBitPerPixel, 2969 3030 v->SwathWidthY, 2970 3031 v->SwathWidthC, 2971 - v->HRatio, 2972 - v->HRatioChroma, 2973 - v->vtaps, 2974 - v->VTAPsChroma, 2975 - v->VRatio, 2976 - v->VRatioChroma, 2977 - v->HTotal, 2978 - v->PixelClock, 2979 - v->BlendingAndTiming, 2980 3032 v->DPPPerPlane, 2981 3033 v->BytePerPixelDETY, 2982 3034 v->BytePerPixelDETC, 2983 - v->DSTXAfterScaler, 2984 - v->DSTYAfterScaler, 2985 - v->WritebackEnable, 2986 - v->WritebackPixelFormat, 2987 - v->WritebackDestinationWidth, 2988 - v->WritebackDestinationHeight, 2989 - v->WritebackSourceHeight, 2990 3035 v->UnboundedRequestEnabled, 2991 3036 v->CompressedBufferSizeInkByte, 2992 3037 &DRAMClockChangeSupport, 2993 - &v->UrgentWatermark, 2994 - &v->WritebackUrgentWatermark, 2995 - &v->DRAMClockChangeWatermark, 2996 - &v->WritebackDRAMClockChangeWatermark, 2997 3038 &v->StutterExitWatermark, 2998 3039 &v->StutterEnterPlusExitWatermark, 2999 3040 &v->Z8StutterExitWatermark, 3000 - &v->Z8StutterEnterPlusExitWatermark, 3001 - &v->MinActiveDRAMClockChangeLatencySupported); 3041 + &v->Z8StutterEnterPlusExitWatermark); 3002 3042 3003 3043 for (k = 0; k < v->NumberOfActivePlanes; ++k) { 3004 3044 if (v->WritebackEnable[k] == true) { ··· 3486 3598 3487 3599 static void CalculateFlipSchedule( 3488 3600 struct display_mode_lib *mode_lib, 3601 + unsigned int k, 3489 3602 double HostVMInefficiencyFactor, 3490 3603 double UrgentExtraLatency, 3491 3604 double UrgentLatency, 3492 - unsigned int GPUVMMaxPageTableLevels, 3493 - bool HostVMEnable, 3494 - unsigned int HostVMMaxNonCachedPageTableLevels, 3495 - bool GPUVMEnable, 3496 - double HostVMMinPageSize, 3497 3605 double PDEAndMetaPTEBytesPerFrame, 3498 3606 double MetaRowBytes, 3499 - double DPTEBytesPerRow, 3500 - double BandwidthAvailableForImmediateFlip, 3501 - unsigned int TotImmediateFlipBytes, 3502 - enum source_format_class SourcePixelFormat, 3503 - double LineTime, 3504 - double VRatio, 3505 - double VRatioChroma, 3506 - double Tno_bw, 3507 - bool DCCEnable, 3508 - unsigned int dpte_row_height, 3509 - unsigned int meta_row_height, 3510 - unsigned int dpte_row_height_chroma, 3511 - unsigned int meta_row_height_chroma, 3512 - double *DestinationLinesToRequestVMInImmediateFlip, 3513 - double *DestinationLinesToRequestRowInImmediateFlip, 3514 - double *final_flip_bw, 3515 - bool *ImmediateFlipSupportedForPipe) 3607 + double DPTEBytesPerRow) 3516 3608 { 3609 + struct vba_vars_st *v = &mode_lib->vba; 3517 3610 double min_row_time = 0.0; 3518 3611 unsigned int HostVMDynamicLevelsTrips; 3519 3612 double TimeForFetchingMetaPTEImmediateFlip; 3520 3613 double TimeForFetchingRowInVBlankImmediateFlip; 3521 3614 double ImmediateFlipBW; 3615 + double LineTime = v->HTotal[k] / v->PixelClock[k]; 3522 3616 3523 - if (GPUVMEnable == true && HostVMEnable == true) { 3524 - HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels; 3617 + if (v->GPUVMEnable == true && v->HostVMEnable == true) { 3618 + HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels; 3525 3619 } else { 3526 3620 HostVMDynamicLevelsTrips = 0; 3527 3621 } 3528 3622 3529 - if (GPUVMEnable == true || DCCEnable == true) { 3530 - ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) * BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes; 3623 + if (v->GPUVMEnable == true || v->DCCEnable[k] == true) { 3624 + ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) * v->BandwidthAvailableForImmediateFlip / v->TotImmediateFlipBytes; 3531 3625 } 3532 3626 3533 - if (GPUVMEnable == true) { 3627 + if (v->GPUVMEnable == true) { 3534 3628 TimeForFetchingMetaPTEImmediateFlip = dml_max3( 3535 - Tno_bw + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW, 3536 - UrgentExtraLatency + UrgentLatency * (GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1), 3629 + v->Tno_bw[k] + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW, 3630 + UrgentExtraLatency + UrgentLatency * (v->GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1), 3537 3631 LineTime / 4.0); 3538 3632 } else { 3539 3633 TimeForFetchingMetaPTEImmediateFlip = 0; 3540 3634 } 3541 3635 3542 - *DestinationLinesToRequestVMInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0; 3543 - if ((GPUVMEnable == true || DCCEnable == true)) { 3636 + v->DestinationLinesToRequestVMInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0; 3637 + if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) { 3544 3638 TimeForFetchingRowInVBlankImmediateFlip = dml_max3( 3545 3639 (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / ImmediateFlipBW, 3546 3640 UrgentLatency * (HostVMDynamicLevelsTrips + 1), ··· 3531 3661 TimeForFetchingRowInVBlankImmediateFlip = 0; 3532 3662 } 3533 3663 3534 - *DestinationLinesToRequestRowInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0; 3664 + v->DestinationLinesToRequestRowInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0; 3535 3665 3536 - if (GPUVMEnable == true) { 3537 - *final_flip_bw = dml_max( 3538 - PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInImmediateFlip * LineTime), 3539 - (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInImmediateFlip * LineTime)); 3540 - } else if ((GPUVMEnable == true || DCCEnable == true)) { 3541 - *final_flip_bw = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInImmediateFlip * LineTime); 3666 + if (v->GPUVMEnable == true) { 3667 + v->final_flip_bw[k] = dml_max( 3668 + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (v->DestinationLinesToRequestVMInImmediateFlip[k] * LineTime), 3669 + (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime)); 3670 + } else if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) { 3671 + v->final_flip_bw[k] = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime); 3542 3672 } else { 3543 - *final_flip_bw = 0; 3673 + v->final_flip_bw[k] = 0; 3544 3674 } 3545 3675 3546 - if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_rgbe_alpha) { 3547 - if (GPUVMEnable == true && DCCEnable != true) { 3548 - min_row_time = dml_min(dpte_row_height * LineTime / VRatio, dpte_row_height_chroma * LineTime / VRatioChroma); 3549 - } else if (GPUVMEnable != true && DCCEnable == true) { 3550 - min_row_time = dml_min(meta_row_height * LineTime / VRatio, meta_row_height_chroma * LineTime / VRatioChroma); 3676 + if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_rgbe_alpha) { 3677 + if (v->GPUVMEnable == true && v->DCCEnable[k] != true) { 3678 + min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k]); 3679 + } else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) { 3680 + min_row_time = dml_min(v->meta_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]); 3551 3681 } else { 3552 3682 min_row_time = dml_min4( 3553 - dpte_row_height * LineTime / VRatio, 3554 - meta_row_height * LineTime / VRatio, 3555 - dpte_row_height_chroma * LineTime / VRatioChroma, 3556 - meta_row_height_chroma * LineTime / VRatioChroma); 3683 + v->dpte_row_height[k] * LineTime / v->VRatio[k], 3684 + v->meta_row_height[k] * LineTime / v->VRatio[k], 3685 + v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k], 3686 + v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]); 3557 3687 } 3558 3688 } else { 3559 - if (GPUVMEnable == true && DCCEnable != true) { 3560 - min_row_time = dpte_row_height * LineTime / VRatio; 3561 - } else if (GPUVMEnable != true && DCCEnable == true) { 3562 - min_row_time = meta_row_height * LineTime / VRatio; 3689 + if (v->GPUVMEnable == true && v->DCCEnable[k] != true) { 3690 + min_row_time = v->dpte_row_height[k] * LineTime / v->VRatio[k]; 3691 + } else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) { 3692 + min_row_time = v->meta_row_height[k] * LineTime / v->VRatio[k]; 3563 3693 } else { 3564 - min_row_time = dml_min(dpte_row_height * LineTime / VRatio, meta_row_height * LineTime / VRatio); 3694 + min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height[k] * LineTime / v->VRatio[k]); 3565 3695 } 3566 3696 } 3567 3697 3568 - if (*DestinationLinesToRequestVMInImmediateFlip >= 32 || *DestinationLinesToRequestRowInImmediateFlip >= 16 3698 + if (v->DestinationLinesToRequestVMInImmediateFlip[k] >= 32 || v->DestinationLinesToRequestRowInImmediateFlip[k] >= 16 3569 3699 || TimeForFetchingMetaPTEImmediateFlip + 2 * TimeForFetchingRowInVBlankImmediateFlip > min_row_time) { 3570 - *ImmediateFlipSupportedForPipe = false; 3700 + v->ImmediateFlipSupportedForPipe[k] = false; 3571 3701 } else { 3572 - *ImmediateFlipSupportedForPipe = true; 3702 + v->ImmediateFlipSupportedForPipe[k] = true; 3573 3703 } 3574 3704 3575 3705 #ifdef __DML_VBA_DEBUG__ 3576 - dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, *DestinationLinesToRequestVMInImmediateFlip); 3577 - dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, *DestinationLinesToRequestRowInImmediateFlip); 3706 + dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestVMInImmediateFlip[k]); 3707 + dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestRowInImmediateFlip[k]); 3578 3708 dml_print("DML::%s: TimeForFetchingMetaPTEImmediateFlip = %f\n", __func__, TimeForFetchingMetaPTEImmediateFlip); 3579 3709 dml_print("DML::%s: TimeForFetchingRowInVBlankImmediateFlip = %f\n", __func__, TimeForFetchingRowInVBlankImmediateFlip); 3580 3710 dml_print("DML::%s: min_row_time = %f\n", __func__, min_row_time); 3581 - dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, *ImmediateFlipSupportedForPipe); 3711 + dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, v->ImmediateFlipSupportedForPipe[k]); 3582 3712 #endif 3583 3713 3584 3714 } ··· 5170 5300 for (k = 0; k < v->NumberOfActivePlanes; k++) { 5171 5301 CalculateFlipSchedule( 5172 5302 mode_lib, 5303 + k, 5173 5304 HostVMInefficiencyFactor, 5174 5305 v->ExtraLatency, 5175 5306 v->UrgLatency[i], 5176 - v->GPUVMMaxPageTableLevels, 5177 - v->HostVMEnable, 5178 - v->HostVMMaxNonCachedPageTableLevels, 5179 - v->GPUVMEnable, 5180 - v->HostVMMinPageSize, 5181 5307 v->PDEAndMetaPTEBytesPerFrame[i][j][k], 5182 5308 v->MetaRowBytes[i][j][k], 5183 - v->DPTEBytesPerRow[i][j][k], 5184 - v->BandwidthAvailableForImmediateFlip, 5185 - v->TotImmediateFlipBytes, 5186 - v->SourcePixelFormat[k], 5187 - v->HTotal[k] / v->PixelClock[k], 5188 - v->VRatio[k], 5189 - v->VRatioChroma[k], 5190 - v->Tno_bw[k], 5191 - v->DCCEnable[k], 5192 - v->dpte_row_height[k], 5193 - v->meta_row_height[k], 5194 - v->dpte_row_height_chroma[k], 5195 - v->meta_row_height_chroma[k], 5196 - &v->DestinationLinesToRequestVMInImmediateFlip[k], 5197 - &v->DestinationLinesToRequestRowInImmediateFlip[k], 5198 - &v->final_flip_bw[k], 5199 - &v->ImmediateFlipSupportedForPipe[k]); 5309 + v->DPTEBytesPerRow[i][j][k]); 5200 5310 } 5201 5311 v->total_dcn_read_bw_with_flip = 0.0; 5202 5312 for (k = 0; k < v->NumberOfActivePlanes; k++) { ··· 5234 5384 CalculateWatermarksAndDRAMSpeedChangeSupport( 5235 5385 mode_lib, 5236 5386 v->PrefetchModePerState[i][j], 5237 - v->NumberOfActivePlanes, 5238 - v->MaxLineBufferLines, 5239 - v->LineBufferSize, 5240 - v->WritebackInterfaceBufferSize, 5241 5387 v->DCFCLKState[i][j], 5242 5388 v->ReturnBWPerState[i][j], 5243 - v->SynchronizedVBlank, 5244 - v->dpte_group_bytes, 5245 - v->MetaChunkSize, 5246 5389 v->UrgLatency[i], 5247 5390 v->ExtraLatency, 5248 - v->WritebackLatency, 5249 - v->WritebackChunkSize, 5250 5391 v->SOCCLKPerState[i], 5251 - v->DRAMClockChangeLatency, 5252 - v->SRExitTime, 5253 - v->SREnterPlusExitTime, 5254 - v->SRExitZ8Time, 5255 - v->SREnterPlusExitZ8Time, 5256 5392 v->ProjectedDCFCLKDeepSleep[i][j], 5257 5393 v->DETBufferSizeYThisState, 5258 5394 v->DETBufferSizeCThisState, 5259 5395 v->SwathHeightYThisState, 5260 5396 v->SwathHeightCThisState, 5261 - v->LBBitPerPixel, 5262 5397 v->SwathWidthYThisState, 5263 5398 v->SwathWidthCThisState, 5264 - v->HRatio, 5265 - v->HRatioChroma, 5266 - v->vtaps, 5267 - v->VTAPsChroma, 5268 - v->VRatio, 5269 - v->VRatioChroma, 5270 - v->HTotal, 5271 - v->PixelClock, 5272 - v->BlendingAndTiming, 5273 5399 v->NoOfDPPThisState, 5274 5400 v->BytePerPixelInDETY, 5275 5401 v->BytePerPixelInDETC, 5276 - v->DSTXAfterScaler, 5277 - v->DSTYAfterScaler, 5278 - v->WritebackEnable, 5279 - v->WritebackPixelFormat, 5280 - v->WritebackDestinationWidth, 5281 - v->WritebackDestinationHeight, 5282 - v->WritebackSourceHeight, 5283 5402 UnboundedRequestEnabledThisState, 5284 5403 CompressedBufferSizeInkByteThisState, 5285 5404 &v->DRAMClockChangeSupport[i][j], 5286 - &v->UrgentWatermark, 5287 - &v->WritebackUrgentWatermark, 5288 - &v->DRAMClockChangeWatermark, 5289 - &v->WritebackDRAMClockChangeWatermark, 5290 5405 &dummy, 5291 5406 &dummy, 5292 5407 &dummy, 5293 - &dummy, 5294 - &v->MinActiveDRAMClockChangeLatencySupported); 5408 + &dummy); 5295 5409 } 5296 5410 } 5297 5411 ··· 5380 5566 static void CalculateWatermarksAndDRAMSpeedChangeSupport( 5381 5567 struct display_mode_lib *mode_lib, 5382 5568 unsigned int PrefetchMode, 5383 - unsigned int NumberOfActivePlanes, 5384 - unsigned int MaxLineBufferLines, 5385 - unsigned int LineBufferSize, 5386 - unsigned int WritebackInterfaceBufferSize, 5387 5569 double DCFCLK, 5388 5570 double ReturnBW, 5389 - bool SynchronizedVBlank, 5390 - unsigned int dpte_group_bytes[], 5391 - unsigned int MetaChunkSize, 5392 5571 double UrgentLatency, 5393 5572 double ExtraLatency, 5394 - double WritebackLatency, 5395 - double WritebackChunkSize, 5396 5573 double SOCCLK, 5397 - double DRAMClockChangeLatency, 5398 - double SRExitTime, 5399 - double SREnterPlusExitTime, 5400 - double SRExitZ8Time, 5401 - double SREnterPlusExitZ8Time, 5402 5574 double DCFCLKDeepSleep, 5403 5575 unsigned int DETBufferSizeY[], 5404 5576 unsigned int DETBufferSizeC[], 5405 5577 unsigned int SwathHeightY[], 5406 5578 unsigned int SwathHeightC[], 5407 - unsigned int LBBitPerPixel[], 5408 5579 double SwathWidthY[], 5409 5580 double SwathWidthC[], 5410 - double HRatio[], 5411 - double HRatioChroma[], 5412 - unsigned int vtaps[], 5413 - unsigned int VTAPsChroma[], 5414 - double VRatio[], 5415 - double VRatioChroma[], 5416 - unsigned int HTotal[], 5417 - double PixelClock[], 5418 - unsigned int BlendingAndTiming[], 5419 5581 unsigned int DPPPerPlane[], 5420 5582 double BytePerPixelDETY[], 5421 5583 double BytePerPixelDETC[], 5422 - double DSTXAfterScaler[], 5423 - double DSTYAfterScaler[], 5424 - bool WritebackEnable[], 5425 - enum source_format_class WritebackPixelFormat[], 5426 - double WritebackDestinationWidth[], 5427 - double WritebackDestinationHeight[], 5428 - double WritebackSourceHeight[], 5429 5584 bool UnboundedRequestEnabled, 5430 5585 int unsigned CompressedBufferSizeInkByte, 5431 5586 enum clock_change_support *DRAMClockChangeSupport, 5432 - double *UrgentWatermark, 5433 - double *WritebackUrgentWatermark, 5434 - double *DRAMClockChangeWatermark, 5435 - double *WritebackDRAMClockChangeWatermark, 5436 5587 double *StutterExitWatermark, 5437 5588 double *StutterEnterPlusExitWatermark, 5438 5589 double *Z8StutterExitWatermark, 5439 - double *Z8StutterEnterPlusExitWatermark, 5440 - double *MinActiveDRAMClockChangeLatencySupported) 5590 + double *Z8StutterEnterPlusExitWatermark) 5441 5591 { 5442 5592 struct vba_vars_st *v = &mode_lib->vba; 5443 5593 double EffectiveLBLatencyHidingY; ··· 5421 5643 double TotalPixelBW = 0.0; 5422 5644 int k, j; 5423 5645 5424 - *UrgentWatermark = UrgentLatency + ExtraLatency; 5646 + v->UrgentWatermark = UrgentLatency + ExtraLatency; 5425 5647 5426 5648 #ifdef __DML_VBA_DEBUG__ 5427 5649 dml_print("DML::%s: UrgentLatency = %f\n", __func__, UrgentLatency); 5428 5650 dml_print("DML::%s: ExtraLatency = %f\n", __func__, ExtraLatency); 5429 - dml_print("DML::%s: UrgentWatermark = %f\n", __func__, *UrgentWatermark); 5651 + dml_print("DML::%s: UrgentWatermark = %f\n", __func__, v->UrgentWatermark); 5430 5652 #endif 5431 5653 5432 - *DRAMClockChangeWatermark = DRAMClockChangeLatency + *UrgentWatermark; 5654 + v->DRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->UrgentWatermark; 5433 5655 5434 5656 #ifdef __DML_VBA_DEBUG__ 5435 - dml_print("DML::%s: DRAMClockChangeLatency = %f\n", __func__, DRAMClockChangeLatency); 5436 - dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, *DRAMClockChangeWatermark); 5657 + dml_print("DML::%s: v->DRAMClockChangeLatency = %f\n", __func__, v->DRAMClockChangeLatency); 5658 + dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, v->DRAMClockChangeWatermark); 5437 5659 #endif 5438 5660 5439 5661 v->TotalActiveWriteback = 0; 5440 - for (k = 0; k < NumberOfActivePlanes; ++k) { 5441 - if (WritebackEnable[k] == true) { 5662 + for (k = 0; k < v->NumberOfActivePlanes; ++k) { 5663 + if (v->WritebackEnable[k] == true) { 5442 5664 v->TotalActiveWriteback = v->TotalActiveWriteback + 1; 5443 5665 } 5444 5666 } 5445 5667 5446 5668 if (v->TotalActiveWriteback <= 1) { 5447 - *WritebackUrgentWatermark = WritebackLatency; 5669 + v->WritebackUrgentWatermark = v->WritebackLatency; 5448 5670 } else { 5449 - *WritebackUrgentWatermark = WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; 5671 + v->WritebackUrgentWatermark = v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; 5450 5672 } 5451 5673 5452 5674 if (v->TotalActiveWriteback <= 1) { 5453 - *WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency; 5675 + v->WritebackDRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->WritebackLatency; 5454 5676 } else { 5455 - *WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; 5677 + v->WritebackDRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; 5456 5678 } 5457 5679 5458 - for (k = 0; k < NumberOfActivePlanes; ++k) { 5680 + for (k = 0; k < v->NumberOfActivePlanes; ++k) { 5459 5681 TotalPixelBW = TotalPixelBW 5460 - + DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * VRatioChroma[k]) 5461 - / (HTotal[k] / PixelClock[k]); 5682 + + DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k]) 5683 + / (v->HTotal[k] / v->PixelClock[k]); 5462 5684 } 5463 5685 5464 - for (k = 0; k < NumberOfActivePlanes; ++k) { 5686 + for (k = 0; k < v->NumberOfActivePlanes; ++k) { 5465 5687 double EffectiveDETBufferSizeY = DETBufferSizeY[k]; 5466 5688 5467 5689 v->LBLatencyHidingSourceLinesY = dml_min( 5468 - (double) MaxLineBufferLines, 5469 - dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (vtaps[k] - 1); 5690 + (double) v->MaxLineBufferLines, 5691 + dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1); 5470 5692 5471 5693 v->LBLatencyHidingSourceLinesC = dml_min( 5472 - (double) MaxLineBufferLines, 5473 - dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTAPsChroma[k] - 1); 5694 + (double) v->MaxLineBufferLines, 5695 + dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1); 5474 5696 5475 - EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / VRatio[k] * (HTotal[k] / PixelClock[k]); 5697 + EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]); 5476 5698 5477 - EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / VRatioChroma[k] * (HTotal[k] / PixelClock[k]); 5699 + EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]); 5478 5700 5479 5701 if (UnboundedRequestEnabled) { 5480 5702 EffectiveDETBufferSizeY = EffectiveDETBufferSizeY 5481 - + CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] / (HTotal[k] / PixelClock[k]) / TotalPixelBW; 5703 + + CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] / (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW; 5482 5704 } 5483 5705 5484 5706 LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; 5485 5707 LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); 5486 - FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k]; 5708 + FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k]; 5487 5709 if (BytePerPixelDETC[k] > 0) { 5488 5710 LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; 5489 5711 LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); 5490 - FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatioChroma[k]; 5712 + FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k]; 5491 5713 } else { 5492 5714 LinesInDETC = 0; 5493 5715 FullDETBufferingTimeC = 999999; 5494 5716 } 5495 5717 5496 5718 ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY 5497 - - ((double) DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k] - *UrgentWatermark - *DRAMClockChangeWatermark; 5719 + - ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark; 5498 5720 5499 - if (NumberOfActivePlanes > 1) { 5721 + if (v->NumberOfActivePlanes > 1) { 5500 5722 ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY 5501 - - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k]; 5723 + - (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k]; 5502 5724 } 5503 5725 5504 5726 if (BytePerPixelDETC[k] > 0) { 5505 5727 ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC 5506 - - ((double) DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k] - *UrgentWatermark - *DRAMClockChangeWatermark; 5728 + - ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark; 5507 5729 5508 - if (NumberOfActivePlanes > 1) { 5730 + if (v->NumberOfActivePlanes > 1) { 5509 5731 ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC 5510 - - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / VRatioChroma[k]; 5732 + - (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k]; 5511 5733 } 5512 5734 v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC); 5513 5735 } else { 5514 5736 v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY; 5515 5737 } 5516 5738 5517 - if (WritebackEnable[k] == true) { 5518 - WritebackDRAMClockChangeLatencyHiding = WritebackInterfaceBufferSize * 1024 5519 - / (WritebackDestinationWidth[k] * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4); 5520 - if (WritebackPixelFormat[k] == dm_444_64) { 5739 + if (v->WritebackEnable[k] == true) { 5740 + WritebackDRAMClockChangeLatencyHiding = v->WritebackInterfaceBufferSize * 1024 5741 + / (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4); 5742 + if (v->WritebackPixelFormat[k] == dm_444_64) { 5521 5743 WritebackDRAMClockChangeLatencyHiding = WritebackDRAMClockChangeLatencyHiding / 2; 5522 5744 } 5523 5745 WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - v->WritebackDRAMClockChangeWatermark; ··· 5527 5749 5528 5750 v->MinActiveDRAMClockChangeMargin = 999999; 5529 5751 PlaneWithMinActiveDRAMClockChangeMargin = 0; 5530 - for (k = 0; k < NumberOfActivePlanes; ++k) { 5752 + for (k = 0; k < v->NumberOfActivePlanes; ++k) { 5531 5753 if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) { 5532 5754 v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k]; 5533 - if (BlendingAndTiming[k] == k) { 5755 + if (v->BlendingAndTiming[k] == k) { 5534 5756 PlaneWithMinActiveDRAMClockChangeMargin = k; 5535 5757 } else { 5536 - for (j = 0; j < NumberOfActivePlanes; ++j) { 5537 - if (BlendingAndTiming[k] == j) { 5758 + for (j = 0; j < v->NumberOfActivePlanes; ++j) { 5759 + if (v->BlendingAndTiming[k] == j) { 5538 5760 PlaneWithMinActiveDRAMClockChangeMargin = j; 5539 5761 } 5540 5762 } ··· 5542 5764 } 5543 5765 } 5544 5766 5545 - *MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + DRAMClockChangeLatency; 5767 + v->MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + v->DRAMClockChangeLatency ; 5546 5768 5547 5769 SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999; 5548 - for (k = 0; k < NumberOfActivePlanes; ++k) { 5549 - if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k)) && !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) 5770 + for (k = 0; k < v->NumberOfActivePlanes; ++k) { 5771 + if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) 5550 5772 && v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) { 5551 5773 SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k]; 5552 5774 } ··· 5554 5776 5555 5777 v->TotalNumberOfActiveOTG = 0; 5556 5778 5557 - for (k = 0; k < NumberOfActivePlanes; ++k) { 5558 - if (BlendingAndTiming[k] == k) { 5779 + for (k = 0; k < v->NumberOfActivePlanes; ++k) { 5780 + if (v->BlendingAndTiming[k] == k) { 5559 5781 v->TotalNumberOfActiveOTG = v->TotalNumberOfActiveOTG + 1; 5560 5782 } 5561 5783 } 5562 5784 5563 5785 if (v->MinActiveDRAMClockChangeMargin > 0 && PrefetchMode == 0) { 5564 5786 *DRAMClockChangeSupport = dm_dram_clock_change_vactive; 5565 - } else if ((SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1 5787 + } else if ((v->SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1 5566 5788 || SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0) { 5567 5789 *DRAMClockChangeSupport = dm_dram_clock_change_vblank; 5568 5790 } else { 5569 5791 *DRAMClockChangeSupport = dm_dram_clock_change_unsupported; 5570 5792 } 5571 5793 5572 - *StutterExitWatermark = SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep; 5573 - *StutterEnterPlusExitWatermark = (SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep); 5574 - *Z8StutterExitWatermark = SRExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep; 5575 - *Z8StutterEnterPlusExitWatermark = SREnterPlusExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep; 5794 + *StutterExitWatermark = v->SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep; 5795 + *StutterEnterPlusExitWatermark = (v->SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep); 5796 + *Z8StutterExitWatermark = v->SRExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep; 5797 + *Z8StutterEnterPlusExitWatermark = v->SREnterPlusExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep; 5576 5798 5577 5799 #ifdef __DML_VBA_DEBUG__ 5578 5800 dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, *StutterExitWatermark);
+4 -1
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
··· 194 194 dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; 195 195 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count; 196 196 197 + if (bw_params->dram_channel_width_bytes > 0) 198 + dcn3_14_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes; 199 + 197 200 if (bw_params->num_channels > 0) 198 201 dcn3_14_soc.num_chans = bw_params->num_channels; 199 202 ··· 265 262 } 266 263 267 264 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 268 - dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31); 265 + dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN314); 269 266 else 270 267 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31_FPGA); 271 268 }
+6 -7
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
··· 61 61 // fudge factor for min dcfclk calclation 62 62 #define __DML_MIN_DCFCLK_FACTOR__ 1.15 63 63 64 - struct { 64 + typedef struct { 65 65 double DPPCLK; 66 66 double DISPCLK; 67 67 double PixelClock; ··· 1599 1599 int segment_order_vert_contiguous_luma; 1600 1600 int segment_order_vert_contiguous_chroma; 1601 1601 1602 - enum { 1602 + typedef enum { 1603 1603 REQ_256Bytes, REQ_128BytesNonContiguous, REQ_128BytesContiguous, REQ_NA 1604 1604 } RequestType; 1605 1605 RequestType RequestLuma; ··· 4071 4071 4072 4072 v->SourceFormatPixelAndScanSupport = true; 4073 4073 for (k = 0; k < v->NumberOfActivePlanes; k++) { 4074 - if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true)) 4075 - || ((v->SurfaceTiling[k] == dm_sw_64kb_d || v->SurfaceTiling[k] == dm_sw_64kb_d_t 4076 - || v->SurfaceTiling[k] == dm_sw_64kb_d_x) && !(v->SourcePixelFormat[k] == dm_444_64))) { 4074 + if (v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true)) { 4077 4075 v->SourceFormatPixelAndScanSupport = false; 4078 4076 } 4079 4077 } ··· 7155 7157 HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); 7156 7158 else 7157 7159 HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); 7158 - else 7160 + } else { 7159 7161 HostVMDynamicLevels = 0; 7162 + } 7160 7163 7161 7164 ret = ReorderingBytes + (TotalNumberOfActiveDPP * PixelChunkSizeInKByte + TotalNumberOfDCCActiveDPP * MetaChunkSize) * 1024.0; 7162 7165 7163 - if (GPUVMEnable == true) 7166 + if (GPUVMEnable == true) { 7164 7167 for (k = 0; k < NumberOfActivePlanes; ++k) 7165 7168 ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor; 7166 7169 }
+86 -174
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
··· 755 755 v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BytePerPixelY = v->BytePerPixelY[k]; 756 756 v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BytePerPixelC = v->BytePerPixelC[k]; 757 757 v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.ProgressiveToInterlaceUnitInOPP = mode_lib->vba.ProgressiveToInterlaceUnitInOPP; 758 - v->ErrorResult[k] = dml32_CalculatePrefetchSchedule(v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor, 759 - &v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe, v->DSCDelay[k], 760 - mode_lib->vba.DPPCLKDelaySubtotal + mode_lib->vba.DPPCLKDelayCNVCFormater, 761 - mode_lib->vba.DPPCLKDelaySCL, 762 - mode_lib->vba.DPPCLKDelaySCLLBOnly, 763 - mode_lib->vba.DPPCLKDelayCNVCCursor, 764 - mode_lib->vba.DISPCLKDelaySubtotal, 765 - (unsigned int) (v->SwathWidthY[k] / mode_lib->vba.HRatio[k]), 766 - mode_lib->vba.OutputFormat[k], 767 - mode_lib->vba.MaxInterDCNTileRepeaters, 758 + v->ErrorResult[k] = dml32_CalculatePrefetchSchedule( 759 + v, 760 + k, 761 + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor, 762 + &v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe, 763 + v->DSCDelay[k], 764 + (unsigned int) (v->SwathWidthY[k] / v->HRatio[k]), 768 765 dml_min(v->VStartupLines, v->MaxVStartupLines[k]), 769 766 v->MaxVStartupLines[k], 770 - mode_lib->vba.GPUVMMaxPageTableLevels, 771 - mode_lib->vba.GPUVMEnable, 772 - mode_lib->vba.HostVMEnable, 773 - mode_lib->vba.HostVMMaxNonCachedPageTableLevels, 774 - mode_lib->vba.HostVMMinPageSize, 775 - mode_lib->vba.DynamicMetadataEnable[k], 776 - mode_lib->vba.DynamicMetadataVMEnabled, 777 - mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], 778 - mode_lib->vba.DynamicMetadataTransmittedBytes[k], 779 767 v->UrgentLatency, 780 768 v->UrgentExtraLatency, 781 - mode_lib->vba.TCalc, 769 + v->TCalc, 782 770 v->PDEAndMetaPTEBytesFrame[k], 783 771 v->MetaRowByte[k], 784 772 v->PixelPTEBytesPerRow[k], ··· 780 792 v->MaxNumSwathC[k], 781 793 v->swath_width_luma_ub[k], 782 794 v->swath_width_chroma_ub[k], 783 - mode_lib->vba.SwathHeightY[k], 784 - mode_lib->vba.SwathHeightC[k], 795 + v->SwathHeightY[k], 796 + v->SwathHeightC[k], 785 797 TWait, 786 798 /* Output */ 787 799 &v->DSTXAfterScaler[k], ··· 1151 1163 v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.SMNLatency = mode_lib->vba.SMNLatency; 1152 1164 1153 1165 dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( 1154 - mode_lib->vba.USRRetrainingRequiredFinal, 1155 - mode_lib->vba.UsesMALLForPStateChange, 1156 - mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], 1157 - mode_lib->vba.NumberOfActiveSurfaces, 1158 - mode_lib->vba.MaxLineBufferLines, 1159 - mode_lib->vba.LineBufferSizeFinal, 1160 - mode_lib->vba.WritebackInterfaceBufferSize, 1161 - mode_lib->vba.DCFCLK, 1162 - mode_lib->vba.ReturnBW, 1163 - mode_lib->vba.SynchronizeTimingsFinal, 1164 - mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal, 1165 - mode_lib->vba.DRRDisplay, 1166 - v->dpte_group_bytes, 1167 - v->meta_row_height, 1168 - v->meta_row_height_chroma, 1166 + v, 1167 + v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb], 1168 + v->DCFCLK, 1169 + v->ReturnBW, 1169 1170 v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters, 1170 - mode_lib->vba.WritebackChunkSize, 1171 - mode_lib->vba.SOCCLK, 1171 + v->SOCCLK, 1172 1172 v->DCFCLKDeepSleep, 1173 - mode_lib->vba.DETBufferSizeY, 1174 - mode_lib->vba.DETBufferSizeC, 1175 - mode_lib->vba.SwathHeightY, 1176 - mode_lib->vba.SwathHeightC, 1177 - mode_lib->vba.LBBitPerPixel, 1173 + v->DETBufferSizeY, 1174 + v->DETBufferSizeC, 1175 + v->SwathHeightY, 1176 + v->SwathHeightC, 1178 1177 v->SwathWidthY, 1179 1178 v->SwathWidthC, 1180 - mode_lib->vba.HRatio, 1181 - mode_lib->vba.HRatioChroma, 1182 - mode_lib->vba.vtaps, 1183 - mode_lib->vba.VTAPsChroma, 1184 - mode_lib->vba.VRatio, 1185 - mode_lib->vba.VRatioChroma, 1186 - mode_lib->vba.HTotal, 1187 - mode_lib->vba.VTotal, 1188 - mode_lib->vba.VActive, 1189 - mode_lib->vba.PixelClock, 1190 - mode_lib->vba.BlendingAndTiming, 1191 - mode_lib->vba.DPPPerPlane, 1179 + v->DPPPerPlane, 1192 1180 v->BytePerPixelDETY, 1193 1181 v->BytePerPixelDETC, 1194 1182 v->DSTXAfterScaler, 1195 1183 v->DSTYAfterScaler, 1196 - mode_lib->vba.WritebackEnable, 1197 - mode_lib->vba.WritebackPixelFormat, 1198 - mode_lib->vba.WritebackDestinationWidth, 1199 - mode_lib->vba.WritebackDestinationHeight, 1200 - mode_lib->vba.WritebackSourceHeight, 1201 1184 v->UnboundedRequestEnabled, 1202 1185 v->CompressedBufferSizeInkByte, 1203 1186 1204 1187 /* Output */ 1205 - &v->Watermark, 1206 1188 &v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_dramchange_support, 1207 1189 v->MaxActiveDRAMClockChangeLatencySupported, 1208 1190 v->SubViewportLinesNeededInMALL, ··· 1764 1806 &mode_lib->vba.Read256BlockHeightC[k], 1765 1807 &mode_lib->vba.Read256BlockWidthY[k], 1766 1808 &mode_lib->vba.Read256BlockWidthC[k], 1767 - &mode_lib->vba.MicroTileHeightY[k], 1768 - &mode_lib->vba.MicroTileHeightC[k], 1769 - &mode_lib->vba.MicroTileWidthY[k], 1770 - &mode_lib->vba.MicroTileWidthC[k]); 1809 + &mode_lib->vba.MacroTileHeightY[k], 1810 + &mode_lib->vba.MacroTileHeightC[k], 1811 + &mode_lib->vba.MacroTileWidthY[k], 1812 + &mode_lib->vba.MacroTileWidthC[k]); 1771 1813 } 1772 1814 1773 1815 /*Bandwidth Support Check*/ ··· 2617 2659 mode_lib->vba.Read256BlockWidthC, 2618 2660 mode_lib->vba.Read256BlockHeightY, 2619 2661 mode_lib->vba.Read256BlockHeightC, 2620 - mode_lib->vba.MicroTileWidthY, 2621 - mode_lib->vba.MicroTileWidthC, 2622 - mode_lib->vba.MicroTileHeightY, 2623 - mode_lib->vba.MicroTileHeightC, 2662 + mode_lib->vba.MacroTileWidthY, 2663 + mode_lib->vba.MacroTileWidthC, 2664 + mode_lib->vba.MacroTileHeightY, 2665 + mode_lib->vba.MacroTileHeightC, 2624 2666 2625 2667 /* Output */ 2626 2668 mode_lib->vba.SurfaceSizeInMALL, ··· 2667 2709 v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k]; 2668 2710 v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k]; 2669 2711 v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k]; 2670 - v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthY = mode_lib->vba.MicroTileWidthY[k]; 2671 - v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightY = mode_lib->vba.MicroTileHeightY[k]; 2672 - v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthC = mode_lib->vba.MicroTileWidthC[k]; 2673 - v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightC = mode_lib->vba.MicroTileHeightC[k]; 2712 + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthY = mode_lib->vba.MacroTileWidthY[k]; 2713 + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightY = mode_lib->vba.MacroTileHeightY[k]; 2714 + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthC = mode_lib->vba.MacroTileWidthC[k]; 2715 + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightC = mode_lib->vba.MacroTileHeightC[k]; 2674 2716 v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k]; 2675 2717 v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].HTotal = mode_lib->vba.HTotal[k]; 2676 2718 v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k]; ··· 3216 3258 3217 3259 mode_lib->vba.NoTimeForPrefetch[i][j][k] = 3218 3260 dml32_CalculatePrefetchSchedule( 3261 + v, 3262 + k, 3219 3263 v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor, 3220 3264 &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe, 3221 - mode_lib->vba.DSCDelayPerState[i][k], 3222 - mode_lib->vba.DPPCLKDelaySubtotal + 3223 - mode_lib->vba.DPPCLKDelayCNVCFormater, 3224 - mode_lib->vba.DPPCLKDelaySCL, 3225 - mode_lib->vba.DPPCLKDelaySCLLBOnly, 3226 - mode_lib->vba.DPPCLKDelayCNVCCursor, 3227 - mode_lib->vba.DISPCLKDelaySubtotal, 3228 - mode_lib->vba.SwathWidthYThisState[k] / 3229 - mode_lib->vba.HRatio[k], 3230 - mode_lib->vba.OutputFormat[k], 3231 - mode_lib->vba.MaxInterDCNTileRepeaters, 3232 - dml_min(mode_lib->vba.MaxVStartup, 3233 - mode_lib->vba.MaximumVStartup[i][j][k]), 3234 - mode_lib->vba.MaximumVStartup[i][j][k], 3235 - mode_lib->vba.GPUVMMaxPageTableLevels, 3236 - mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable, 3237 - mode_lib->vba.HostVMMaxNonCachedPageTableLevels, 3238 - mode_lib->vba.HostVMMinPageSize, 3239 - mode_lib->vba.DynamicMetadataEnable[k], 3240 - mode_lib->vba.DynamicMetadataVMEnabled, 3241 - mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], 3242 - mode_lib->vba.DynamicMetadataTransmittedBytes[k], 3243 - mode_lib->vba.UrgLatency[i], 3244 - mode_lib->vba.ExtraLatency, 3245 - mode_lib->vba.TimeCalc, 3246 - mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k], 3247 - mode_lib->vba.MetaRowBytes[i][j][k], 3248 - mode_lib->vba.DPTEBytesPerRow[i][j][k], 3249 - mode_lib->vba.PrefetchLinesY[i][j][k], 3250 - mode_lib->vba.SwathWidthYThisState[k], 3251 - mode_lib->vba.PrefillY[k], 3252 - mode_lib->vba.MaxNumSwY[k], 3253 - mode_lib->vba.PrefetchLinesC[i][j][k], 3254 - mode_lib->vba.SwathWidthCThisState[k], 3255 - mode_lib->vba.PrefillC[k], 3256 - mode_lib->vba.MaxNumSwC[k], 3257 - mode_lib->vba.swath_width_luma_ub_this_state[k], 3258 - mode_lib->vba.swath_width_chroma_ub_this_state[k], 3259 - mode_lib->vba.SwathHeightYThisState[k], 3260 - mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.TWait, 3265 + v->DSCDelayPerState[i][k], 3266 + v->SwathWidthYThisState[k] / v->HRatio[k], 3267 + dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), 3268 + v->MaximumVStartup[i][j][k], 3269 + v->UrgLatency[i], 3270 + v->ExtraLatency, 3271 + v->TimeCalc, 3272 + v->PDEAndMetaPTEBytesPerFrame[i][j][k], 3273 + v->MetaRowBytes[i][j][k], 3274 + v->DPTEBytesPerRow[i][j][k], 3275 + v->PrefetchLinesY[i][j][k], 3276 + v->SwathWidthYThisState[k], 3277 + v->PrefillY[k], 3278 + v->MaxNumSwY[k], 3279 + v->PrefetchLinesC[i][j][k], 3280 + v->SwathWidthCThisState[k], 3281 + v->PrefillC[k], 3282 + v->MaxNumSwC[k], 3283 + v->swath_width_luma_ub_this_state[k], 3284 + v->swath_width_chroma_ub_this_state[k], 3285 + v->SwathHeightYThisState[k], 3286 + v->SwathHeightCThisState[k], v->TWait, 3261 3287 3262 3288 /* Output */ 3263 3289 &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k], 3264 3290 &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler[k], 3265 - &mode_lib->vba.LineTimesForPrefetch[k], 3266 - &mode_lib->vba.PrefetchBW[k], 3267 - &mode_lib->vba.LinesForMetaPTE[k], 3268 - &mode_lib->vba.LinesForMetaAndDPTERow[k], 3269 - &mode_lib->vba.VRatioPreY[i][j][k], 3270 - &mode_lib->vba.VRatioPreC[i][j][k], 3271 - &mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0][k], 3272 - &mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0][k], 3273 - &mode_lib->vba.NoTimeForDynamicMetadata[i][j][k], 3274 - &mode_lib->vba.Tno_bw[k], 3275 - &mode_lib->vba.prefetch_vmrow_bw[k], 3291 + &v->LineTimesForPrefetch[k], 3292 + &v->PrefetchBW[k], 3293 + &v->LinesForMetaPTE[k], 3294 + &v->LinesForMetaAndDPTERow[k], 3295 + &v->VRatioPreY[i][j][k], 3296 + &v->VRatioPreC[i][j][k], 3297 + &v->RequiredPrefetchPixelDataBWLuma[0][0][k], 3298 + &v->RequiredPrefetchPixelDataBWChroma[0][0][k], 3299 + &v->NoTimeForDynamicMetadata[i][j][k], 3300 + &v->Tno_bw[k], 3301 + &v->prefetch_vmrow_bw[k], 3276 3302 &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0], // double *Tdmdl_vm 3277 3303 &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1], // double *Tdmdl 3278 3304 &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[2], // double *TSetup ··· 3499 3557 3500 3558 { 3501 3559 dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( 3502 - mode_lib->vba.USRRetrainingRequiredFinal, 3503 - mode_lib->vba.UsesMALLForPStateChange, 3504 - mode_lib->vba.PrefetchModePerState[i][j], 3505 - mode_lib->vba.NumberOfActiveSurfaces, 3506 - mode_lib->vba.MaxLineBufferLines, 3507 - mode_lib->vba.LineBufferSizeFinal, 3508 - mode_lib->vba.WritebackInterfaceBufferSize, 3509 - mode_lib->vba.DCFCLKState[i][j], 3510 - mode_lib->vba.ReturnBWPerState[i][j], 3511 - mode_lib->vba.SynchronizeTimingsFinal, 3512 - mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal, 3513 - mode_lib->vba.DRRDisplay, 3514 - mode_lib->vba.dpte_group_bytes, 3515 - mode_lib->vba.meta_row_height, 3516 - mode_lib->vba.meta_row_height_chroma, 3560 + v, 3561 + v->PrefetchModePerState[i][j], 3562 + v->DCFCLKState[i][j], 3563 + v->ReturnBWPerState[i][j], 3517 3564 v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters, 3518 - mode_lib->vba.WritebackChunkSize, 3519 - mode_lib->vba.SOCCLKPerState[i], 3520 - mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j], 3521 - mode_lib->vba.DETBufferSizeYThisState, 3522 - mode_lib->vba.DETBufferSizeCThisState, 3523 - mode_lib->vba.SwathHeightYThisState, 3524 - mode_lib->vba.SwathHeightCThisState, 3525 - mode_lib->vba.LBBitPerPixel, 3526 - mode_lib->vba.SwathWidthYThisState, // 24 3527 - mode_lib->vba.SwathWidthCThisState, 3528 - mode_lib->vba.HRatio, 3529 - mode_lib->vba.HRatioChroma, 3530 - mode_lib->vba.vtaps, 3531 - mode_lib->vba.VTAPsChroma, 3532 - mode_lib->vba.VRatio, 3533 - mode_lib->vba.VRatioChroma, 3534 - mode_lib->vba.HTotal, 3535 - mode_lib->vba.VTotal, 3536 - mode_lib->vba.VActive, 3537 - mode_lib->vba.PixelClock, 3538 - mode_lib->vba.BlendingAndTiming, 3539 - mode_lib->vba.NoOfDPPThisState, 3540 - mode_lib->vba.BytePerPixelInDETY, 3541 - mode_lib->vba.BytePerPixelInDETC, 3565 + v->SOCCLKPerState[i], 3566 + v->ProjectedDCFCLKDeepSleep[i][j], 3567 + v->DETBufferSizeYThisState, 3568 + v->DETBufferSizeCThisState, 3569 + v->SwathHeightYThisState, 3570 + v->SwathHeightCThisState, 3571 + v->SwathWidthYThisState, // 24 3572 + v->SwathWidthCThisState, 3573 + v->NoOfDPPThisState, 3574 + v->BytePerPixelInDETY, 3575 + v->BytePerPixelInDETC, 3542 3576 v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler, 3543 3577 v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler, 3544 - mode_lib->vba.WritebackEnable, 3545 - mode_lib->vba.WritebackPixelFormat, 3546 - mode_lib->vba.WritebackDestinationWidth, 3547 - mode_lib->vba.WritebackDestinationHeight, 3548 - mode_lib->vba.WritebackSourceHeight, 3549 - mode_lib->vba.UnboundedRequestEnabledThisState, 3550 - mode_lib->vba.CompressedBufferSizeInkByteThisState, 3578 + v->UnboundedRequestEnabledThisState, 3579 + v->CompressedBufferSizeInkByteThisState, 3551 3580 3552 3581 /* Output */ 3553 - &mode_lib->vba.Watermark, // Store the values in vba 3554 - &mode_lib->vba.DRAMClockChangeSupport[i][j], 3582 + &v->DRAMClockChangeSupport[i][j], 3555 3583 &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[0], // double *MaxActiveDRAMClockChangeLatencySupported 3556 3584 &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer[0], // Long SubViewportLinesNeededInMALL[] 3557 - &mode_lib->vba.FCLKChangeSupport[i][j], 3585 + &v->FCLKChangeSupport[i][j], 3558 3586 &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[1], // double *MinActiveFCLKChangeLatencySupported 3559 3587 &mode_lib->vba.USRRetrainingSupport[i][j], 3560 3588 mode_lib->vba.ActiveDRAMClockChangeLatencyMargin);
+139 -182
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
··· 3363 3363 } // CalculateExtraLatency 3364 3364 3365 3365 bool dml32_CalculatePrefetchSchedule( 3366 + struct vba_vars_st *v, 3367 + unsigned int k, 3366 3368 double HostVMInefficiencyFactor, 3367 3369 DmlPipe *myPipe, 3368 3370 unsigned int DSCDelay, 3369 - double DPPCLKDelaySubtotalPlusCNVCFormater, 3370 - double DPPCLKDelaySCL, 3371 - double DPPCLKDelaySCLLBOnly, 3372 - double DPPCLKDelayCNVCCursor, 3373 - double DISPCLKDelaySubtotal, 3374 3371 unsigned int DPP_RECOUT_WIDTH, 3375 - enum output_format_class OutputFormat, 3376 - unsigned int MaxInterDCNTileRepeaters, 3377 3372 unsigned int VStartup, 3378 3373 unsigned int MaxVStartup, 3379 - unsigned int GPUVMPageTableLevels, 3380 - bool GPUVMEnable, 3381 - bool HostVMEnable, 3382 - unsigned int HostVMMaxNonCachedPageTableLevels, 3383 - double HostVMMinPageSize, 3384 - bool DynamicMetadataEnable, 3385 - bool DynamicMetadataVMEnabled, 3386 - int DynamicMetadataLinesBeforeActiveRequired, 3387 - unsigned int DynamicMetadataTransmittedBytes, 3388 3374 double UrgentLatency, 3389 3375 double UrgentExtraLatency, 3390 3376 double TCalc, ··· 3411 3425 double *VUpdateWidthPix, 3412 3426 double *VReadyOffsetPix) 3413 3427 { 3428 + double DPPCLKDelaySubtotalPlusCNVCFormater = v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater; 3414 3429 bool MyError = false; 3415 3430 unsigned int DPPCycles, DISPCLKCycles; 3416 3431 double DSTTotalPixelsAfterScaler; ··· 3448 3461 double Tsw_est1 = 0; 3449 3462 double Tsw_est3 = 0; 3450 3463 3451 - if (GPUVMEnable == true && HostVMEnable == true) 3452 - HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels; 3464 + if (v->GPUVMEnable == true && v->HostVMEnable == true) 3465 + HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels; 3453 3466 else 3454 3467 HostVMDynamicLevelsTrips = 0; 3455 3468 #ifdef __DML_VBA_DEBUG__ 3456 - dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable); 3457 - dml_print("DML::%s: GPUVMPageTableLevels = %d\n", __func__, GPUVMPageTableLevels); 3469 + dml_print("DML::%s: v->GPUVMEnable = %d\n", __func__, v->GPUVMEnable); 3470 + dml_print("DML::%s: v->GPUVMMaxPageTableLevels = %d\n", __func__, v->GPUVMMaxPageTableLevels); 3458 3471 dml_print("DML::%s: DCCEnable = %d\n", __func__, myPipe->DCCEnable); 3459 - dml_print("DML::%s: HostVMEnable=%d HostVMInefficiencyFactor=%f\n", 3460 - __func__, HostVMEnable, HostVMInefficiencyFactor); 3472 + dml_print("DML::%s: v->HostVMEnable=%d HostVMInefficiencyFactor=%f\n", 3473 + __func__, v->HostVMEnable, HostVMInefficiencyFactor); 3461 3474 #endif 3462 3475 dml32_CalculateVUpdateAndDynamicMetadataParameters( 3463 - MaxInterDCNTileRepeaters, 3476 + v->MaxInterDCNTileRepeaters, 3464 3477 myPipe->Dppclk, 3465 3478 myPipe->Dispclk, 3466 3479 myPipe->DCFClkDeepSleep, 3467 3480 myPipe->PixelClock, 3468 3481 myPipe->HTotal, 3469 3482 myPipe->VBlank, 3470 - DynamicMetadataTransmittedBytes, 3471 - DynamicMetadataLinesBeforeActiveRequired, 3483 + v->DynamicMetadataTransmittedBytes[k], 3484 + v->DynamicMetadataLinesBeforeActiveRequired[k], 3472 3485 myPipe->InterlaceEnable, 3473 3486 myPipe->ProgressiveToInterlaceUnitInOPP, 3474 3487 TSetup, ··· 3483 3496 3484 3497 LineTime = myPipe->HTotal / myPipe->PixelClock; 3485 3498 trip_to_mem = UrgentLatency; 3486 - Tvm_trips = UrgentExtraLatency + trip_to_mem * (GPUVMPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1); 3499 + Tvm_trips = UrgentExtraLatency + trip_to_mem * (v->GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1); 3487 3500 3488 - if (DynamicMetadataVMEnabled == true) 3501 + if (v->DynamicMetadataVMEnabled == true) 3489 3502 *Tdmdl = TWait + Tvm_trips + trip_to_mem; 3490 3503 else 3491 3504 *Tdmdl = TWait + UrgentExtraLatency; 3492 3505 3493 3506 #ifdef __DML_VBA_ALLOW_DELTA__ 3494 - if (DynamicMetadataEnable == false) 3507 + if (v->DynamicMetadataEnable[k] == false) 3495 3508 *Tdmdl = 0.0; 3496 3509 #endif 3497 3510 3498 - if (DynamicMetadataEnable == true) { 3511 + if (v->DynamicMetadataEnable[k] == true) { 3499 3512 if (VStartup * LineTime < *TSetup + *Tdmdl + Tdmbf + Tdmec + Tdmsks) { 3500 3513 *NotEnoughTimeForDynamicMetadata = true; 3501 3514 #ifdef __DML_VBA_DEBUG__ ··· 3515 3528 *NotEnoughTimeForDynamicMetadata = false; 3516 3529 } 3517 3530 3518 - *Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && 3519 - GPUVMEnable == true ? TWait + Tvm_trips : 0); 3531 + *Tdmdl_vm = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true && 3532 + v->GPUVMEnable == true ? TWait + Tvm_trips : 0); 3520 3533 3521 3534 if (myPipe->ScalerEnabled) 3522 - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL; 3535 + DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL; 3523 3536 else 3524 - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly; 3537 + DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly; 3525 3538 3526 - DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor; 3539 + DPPCycles = DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor; 3527 3540 3528 - DISPCLKCycles = DISPCLKDelaySubtotal; 3541 + DISPCLKCycles = v->DISPCLKDelaySubtotal; 3529 3542 3530 3543 if (myPipe->Dppclk == 0.0 || myPipe->Dispclk == 0.0) 3531 3544 return true; ··· 3551 3564 dml_print("DML::%s: DSTXAfterScaler: %d\n", __func__, *DSTXAfterScaler); 3552 3565 #endif 3553 3566 3554 - if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP)) 3567 + if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP)) 3555 3568 *DSTYAfterScaler = 1; 3556 3569 else 3557 3570 *DSTYAfterScaler = 0; ··· 3568 3581 3569 3582 Tr0_trips = trip_to_mem * (HostVMDynamicLevelsTrips + 1); 3570 3583 3571 - if (GPUVMEnable == true) { 3584 + if (v->GPUVMEnable == true) { 3572 3585 Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1.0) / 4.0 * LineTime; 3573 3586 Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1.0) / 4.0 * LineTime; 3574 - if (GPUVMPageTableLevels >= 3) { 3587 + if (v->GPUVMMaxPageTableLevels >= 3) { 3575 3588 *Tno_bw = UrgentExtraLatency + trip_to_mem * 3576 - (double) ((GPUVMPageTableLevels - 2) * (HostVMDynamicLevelsTrips + 1) - 1); 3577 - } else if (GPUVMPageTableLevels == 1 && myPipe->DCCEnable != true) { 3589 + (double) ((v->GPUVMMaxPageTableLevels - 2) * (HostVMDynamicLevelsTrips + 1) - 1); 3590 + } else if (v->GPUVMMaxPageTableLevels == 1 && myPipe->DCCEnable != true) { 3578 3591 Tr0_trips_rounded = dml_ceil(4.0 * UrgentExtraLatency / LineTime, 1.0) / 3579 3592 4.0 * LineTime; // VBA_ERROR 3580 3593 *Tno_bw = UrgentExtraLatency; ··· 3609 3622 min_Lsw = dml_max(min_Lsw, 1.0); 3610 3623 Lsw_oto = dml_ceil(4.0 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1.0) / 4.0; 3611 3624 3612 - if (GPUVMEnable == true) { 3625 + if (v->GPUVMEnable == true) { 3613 3626 Tvm_oto = dml_max3( 3614 3627 Tvm_trips, 3615 3628 *Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto, ··· 3617 3630 } else 3618 3631 Tvm_oto = LineTime / 4.0; 3619 3632 3620 - if ((GPUVMEnable == true || myPipe->DCCEnable == true)) { 3633 + if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) { 3621 3634 Tr0_oto = dml_max4( 3622 3635 Tr0_trips, 3623 3636 (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto, ··· 3820 3833 #endif 3821 3834 3822 3835 if (prefetch_bw_equ > 0) { 3823 - if (GPUVMEnable == true) { 3836 + if (v->GPUVMEnable == true) { 3824 3837 Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * 3825 3838 HostVMInefficiencyFactor / prefetch_bw_equ, 3826 3839 Tvm_trips, LineTime / 4); ··· 3828 3841 Tvm_equ = LineTime / 4; 3829 3842 } 3830 3843 3831 - if ((GPUVMEnable == true || myPipe->DCCEnable == true)) { 3844 + if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) { 3832 3845 Tr0_equ = dml_max4((MetaRowByte + PixelPTEBytesPerRow * 3833 3846 HostVMInefficiencyFactor) / prefetch_bw_equ, Tr0_trips, 3834 3847 (LineTime - Tvm_equ) / 2, LineTime / 4); ··· 4193 4206 } // CalculateFlipSchedule 4194 4207 4195 4208 void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( 4196 - bool USRRetrainingRequiredFinal, 4197 - enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], 4209 + struct vba_vars_st *v, 4198 4210 unsigned int PrefetchMode, 4199 - unsigned int NumberOfActiveSurfaces, 4200 - unsigned int MaxLineBufferLines, 4201 - unsigned int LineBufferSize, 4202 - unsigned int WritebackInterfaceBufferSize, 4203 4211 double DCFCLK, 4204 4212 double ReturnBW, 4205 - bool SynchronizeTimingsFinal, 4206 - bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal, 4207 - bool DRRDisplay[], 4208 - unsigned int dpte_group_bytes[], 4209 - unsigned int meta_row_height[], 4210 - unsigned int meta_row_height_chroma[], 4211 4213 SOCParametersList mmSOCParameters, 4212 - unsigned int WritebackChunkSize, 4213 4214 double SOCCLK, 4214 4215 double DCFClkDeepSleep, 4215 4216 unsigned int DETBufferSizeY[], 4216 4217 unsigned int DETBufferSizeC[], 4217 4218 unsigned int SwathHeightY[], 4218 4219 unsigned int SwathHeightC[], 4219 - unsigned int LBBitPerPixel[], 4220 4220 double SwathWidthY[], 4221 4221 double SwathWidthC[], 4222 - double HRatio[], 4223 - double HRatioChroma[], 4224 - unsigned int VTaps[], 4225 - unsigned int VTapsChroma[], 4226 - double VRatio[], 4227 - double VRatioChroma[], 4228 - unsigned int HTotal[], 4229 - unsigned int VTotal[], 4230 - unsigned int VActive[], 4231 - double PixelClock[], 4232 - unsigned int BlendingAndTiming[], 4233 4222 unsigned int DPPPerSurface[], 4234 4223 double BytePerPixelDETY[], 4235 4224 double BytePerPixelDETC[], 4236 4225 double DSTXAfterScaler[], 4237 4226 double DSTYAfterScaler[], 4238 - bool WritebackEnable[], 4239 - enum source_format_class WritebackPixelFormat[], 4240 - double WritebackDestinationWidth[], 4241 - double WritebackDestinationHeight[], 4242 - double WritebackSourceHeight[], 4243 4227 bool UnboundedRequestEnabled, 4244 4228 unsigned int CompressedBufferSizeInkByte, 4245 4229 4246 4230 /* Output */ 4247 - Watermarks *Watermark, 4248 4231 enum clock_change_support *DRAMClockChangeSupport, 4249 4232 double MaxActiveDRAMClockChangeLatencySupported[], 4250 4233 unsigned int SubViewportLinesNeededInMALL[], ··· 4256 4299 unsigned int LBLatencyHidingSourceLinesY[DC__NUM_DPP__MAX]; 4257 4300 unsigned int LBLatencyHidingSourceLinesC[DC__NUM_DPP__MAX]; 4258 4301 4259 - Watermark->UrgentWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency; 4260 - Watermark->USRRetrainingWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency 4302 + v->Watermark.UrgentWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency; 4303 + v->Watermark.USRRetrainingWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency 4261 4304 + mmSOCParameters.USRRetrainingLatency + mmSOCParameters.SMNLatency; 4262 - Watermark->DRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency + Watermark->UrgentWatermark; 4263 - Watermark->FCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency + Watermark->UrgentWatermark; 4264 - Watermark->StutterExitWatermark = mmSOCParameters.SRExitTime + mmSOCParameters.ExtraLatency 4305 + v->Watermark.DRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency + v->Watermark.UrgentWatermark; 4306 + v->Watermark.FCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency + v->Watermark.UrgentWatermark; 4307 + v->Watermark.StutterExitWatermark = mmSOCParameters.SRExitTime + mmSOCParameters.ExtraLatency 4265 4308 + 10 / DCFClkDeepSleep; 4266 - Watermark->StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitTime + mmSOCParameters.ExtraLatency 4309 + v->Watermark.StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitTime + mmSOCParameters.ExtraLatency 4267 4310 + 10 / DCFClkDeepSleep; 4268 - Watermark->Z8StutterExitWatermark = mmSOCParameters.SRExitZ8Time + mmSOCParameters.ExtraLatency 4311 + v->Watermark.Z8StutterExitWatermark = mmSOCParameters.SRExitZ8Time + mmSOCParameters.ExtraLatency 4269 4312 + 10 / DCFClkDeepSleep; 4270 - Watermark->Z8StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitZ8Time 4313 + v->Watermark.Z8StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitZ8Time 4271 4314 + mmSOCParameters.ExtraLatency + 10 / DCFClkDeepSleep; 4272 4315 4273 4316 #ifdef __DML_VBA_DEBUG__ 4274 4317 dml_print("DML::%s: UrgentLatency = %f\n", __func__, mmSOCParameters.UrgentLatency); 4275 4318 dml_print("DML::%s: ExtraLatency = %f\n", __func__, mmSOCParameters.ExtraLatency); 4276 4319 dml_print("DML::%s: DRAMClockChangeLatency = %f\n", __func__, mmSOCParameters.DRAMClockChangeLatency); 4277 - dml_print("DML::%s: UrgentWatermark = %f\n", __func__, Watermark->UrgentWatermark); 4278 - dml_print("DML::%s: USRRetrainingWatermark = %f\n", __func__, Watermark->USRRetrainingWatermark); 4279 - dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, Watermark->DRAMClockChangeWatermark); 4280 - dml_print("DML::%s: FCLKChangeWatermark = %f\n", __func__, Watermark->FCLKChangeWatermark); 4281 - dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, Watermark->StutterExitWatermark); 4282 - dml_print("DML::%s: StutterEnterPlusExitWatermark = %f\n", __func__, Watermark->StutterEnterPlusExitWatermark); 4283 - dml_print("DML::%s: Z8StutterExitWatermark = %f\n", __func__, Watermark->Z8StutterExitWatermark); 4320 + dml_print("DML::%s: UrgentWatermark = %f\n", __func__, v->Watermark.UrgentWatermark); 4321 + dml_print("DML::%s: USRRetrainingWatermark = %f\n", __func__, v->Watermark.USRRetrainingWatermark); 4322 + dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, v->Watermark.DRAMClockChangeWatermark); 4323 + dml_print("DML::%s: FCLKChangeWatermark = %f\n", __func__, v->Watermark.FCLKChangeWatermark); 4324 + dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, v->Watermark.StutterExitWatermark); 4325 + dml_print("DML::%s: StutterEnterPlusExitWatermark = %f\n", __func__, v->Watermark.StutterEnterPlusExitWatermark); 4326 + dml_print("DML::%s: Z8StutterExitWatermark = %f\n", __func__, v->Watermark.Z8StutterExitWatermark); 4284 4327 dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", 4285 - __func__, Watermark->Z8StutterEnterPlusExitWatermark); 4328 + __func__, v->Watermark.Z8StutterEnterPlusExitWatermark); 4286 4329 #endif 4287 4330 4288 4331 4289 4332 TotalActiveWriteback = 0; 4290 - for (k = 0; k < NumberOfActiveSurfaces; ++k) { 4291 - if (WritebackEnable[k] == true) 4333 + for (k = 0; k < v->NumberOfActiveSurfaces; ++k) { 4334 + if (v->WritebackEnable[k] == true) 4292 4335 TotalActiveWriteback = TotalActiveWriteback + 1; 4293 4336 } 4294 4337 4295 4338 if (TotalActiveWriteback <= 1) { 4296 - Watermark->WritebackUrgentWatermark = mmSOCParameters.WritebackLatency; 4339 + v->Watermark.WritebackUrgentWatermark = mmSOCParameters.WritebackLatency; 4297 4340 } else { 4298 - Watermark->WritebackUrgentWatermark = mmSOCParameters.WritebackLatency 4299 - + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; 4341 + v->Watermark.WritebackUrgentWatermark = mmSOCParameters.WritebackLatency 4342 + + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; 4300 4343 } 4301 - if (USRRetrainingRequiredFinal) 4302 - Watermark->WritebackUrgentWatermark = Watermark->WritebackUrgentWatermark 4344 + if (v->USRRetrainingRequiredFinal) 4345 + v->Watermark.WritebackUrgentWatermark = v->Watermark.WritebackUrgentWatermark 4303 4346 + mmSOCParameters.USRRetrainingLatency; 4304 4347 4305 4348 if (TotalActiveWriteback <= 1) { 4306 - Watermark->WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency 4349 + v->Watermark.WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency 4307 4350 + mmSOCParameters.WritebackLatency; 4308 - Watermark->WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency 4351 + v->Watermark.WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency 4309 4352 + mmSOCParameters.WritebackLatency; 4310 4353 } else { 4311 - Watermark->WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency 4312 - + mmSOCParameters.WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; 4313 - Watermark->WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency 4314 - + mmSOCParameters.WritebackLatency + WritebackChunkSize * 1024 / 32 / SOCCLK; 4354 + v->Watermark.WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency 4355 + + mmSOCParameters.WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; 4356 + v->Watermark.WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency 4357 + + mmSOCParameters.WritebackLatency + v->WritebackChunkSize * 1024 / 32 / SOCCLK; 4315 4358 } 4316 4359 4317 - if (USRRetrainingRequiredFinal) 4318 - Watermark->WritebackDRAMClockChangeWatermark = Watermark->WritebackDRAMClockChangeWatermark 4360 + if (v->USRRetrainingRequiredFinal) 4361 + v->Watermark.WritebackDRAMClockChangeWatermark = v->Watermark.WritebackDRAMClockChangeWatermark 4319 4362 + mmSOCParameters.USRRetrainingLatency; 4320 4363 4321 - if (USRRetrainingRequiredFinal) 4322 - Watermark->WritebackFCLKChangeWatermark = Watermark->WritebackFCLKChangeWatermark 4364 + if (v->USRRetrainingRequiredFinal) 4365 + v->Watermark.WritebackFCLKChangeWatermark = v->Watermark.WritebackFCLKChangeWatermark 4323 4366 + mmSOCParameters.USRRetrainingLatency; 4324 4367 4325 4368 #ifdef __DML_VBA_DEBUG__ 4326 4369 dml_print("DML::%s: WritebackDRAMClockChangeWatermark = %f\n", 4327 - __func__, Watermark->WritebackDRAMClockChangeWatermark); 4328 - dml_print("DML::%s: WritebackFCLKChangeWatermark = %f\n", __func__, Watermark->WritebackFCLKChangeWatermark); 4329 - dml_print("DML::%s: WritebackUrgentWatermark = %f\n", __func__, Watermark->WritebackUrgentWatermark); 4330 - dml_print("DML::%s: USRRetrainingRequiredFinal = %d\n", __func__, USRRetrainingRequiredFinal); 4370 + __func__, v->Watermark.WritebackDRAMClockChangeWatermark); 4371 + dml_print("DML::%s: WritebackFCLKChangeWatermark = %f\n", __func__, v->Watermark.WritebackFCLKChangeWatermark); 4372 + dml_print("DML::%s: WritebackUrgentWatermark = %f\n", __func__, v->Watermark.WritebackUrgentWatermark); 4373 + dml_print("DML::%s: v->USRRetrainingRequiredFinal = %d\n", __func__, v->USRRetrainingRequiredFinal); 4331 4374 dml_print("DML::%s: USRRetrainingLatency = %f\n", __func__, mmSOCParameters.USRRetrainingLatency); 4332 4375 #endif 4333 4376 4334 - for (k = 0; k < NumberOfActiveSurfaces; ++k) { 4335 - TotalPixelBW = TotalPixelBW + DPPPerSurface[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] + 4336 - SwathWidthC[k] * BytePerPixelDETC[k] * VRatioChroma[k]) / (HTotal[k] / PixelClock[k]); 4377 + for (k = 0; k < v->NumberOfActiveSurfaces; ++k) { 4378 + TotalPixelBW = TotalPixelBW + DPPPerSurface[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] + 4379 + SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k]) / (v->HTotal[k] / v->PixelClock[k]); 4337 4380 } 4338 4381 4339 - for (k = 0; k < NumberOfActiveSurfaces; ++k) { 4382 + for (k = 0; k < v->NumberOfActiveSurfaces; ++k) { 4340 4383 4341 - LBLatencyHidingSourceLinesY[k] = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (VTaps[k] - 1); 4342 - LBLatencyHidingSourceLinesC[k] = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTapsChroma[k] - 1); 4384 + LBLatencyHidingSourceLinesY[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1); 4385 + LBLatencyHidingSourceLinesC[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1); 4343 4386 4344 4387 4345 4388 #ifdef __DML_VBA_DEBUG__ 4346 - dml_print("DML::%s: k=%d, MaxLineBufferLines = %d\n", __func__, k, MaxLineBufferLines); 4347 - dml_print("DML::%s: k=%d, LineBufferSize = %d\n", __func__, k, LineBufferSize); 4348 - dml_print("DML::%s: k=%d, LBBitPerPixel = %d\n", __func__, k, LBBitPerPixel[k]); 4349 - dml_print("DML::%s: k=%d, HRatio = %f\n", __func__, k, HRatio[k]); 4350 - dml_print("DML::%s: k=%d, VTaps = %d\n", __func__, k, VTaps[k]); 4389 + dml_print("DML::%s: k=%d, v->MaxLineBufferLines = %d\n", __func__, k, v->MaxLineBufferLines); 4390 + dml_print("DML::%s: k=%d, v->LineBufferSizeFinal = %d\n", __func__, k, v->LineBufferSizeFinal); 4391 + dml_print("DML::%s: k=%d, v->LBBitPerPixel = %d\n", __func__, k, v->LBBitPerPixel[k]); 4392 + dml_print("DML::%s: k=%d, v->HRatio = %f\n", __func__, k, v->HRatio[k]); 4393 + dml_print("DML::%s: k=%d, v->vtaps = %d\n", __func__, k, v->vtaps[k]); 4351 4394 #endif 4352 4395 4353 - EffectiveLBLatencyHidingY = LBLatencyHidingSourceLinesY[k] / VRatio[k] * (HTotal[k] / PixelClock[k]); 4354 - EffectiveLBLatencyHidingC = LBLatencyHidingSourceLinesC[k] / VRatioChroma[k] * (HTotal[k] / PixelClock[k]); 4396 + EffectiveLBLatencyHidingY = LBLatencyHidingSourceLinesY[k] / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]); 4397 + EffectiveLBLatencyHidingC = LBLatencyHidingSourceLinesC[k] / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]); 4355 4398 EffectiveDETBufferSizeY = DETBufferSizeY[k]; 4356 4399 4357 4400 if (UnboundedRequestEnabled) { 4358 4401 EffectiveDETBufferSizeY = EffectiveDETBufferSizeY 4359 4402 + CompressedBufferSizeInkByte * 1024 4360 - * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k]) 4361 - / (HTotal[k] / PixelClock[k]) / TotalPixelBW; 4403 + * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k]) 4404 + / (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW; 4362 4405 } 4363 4406 4364 4407 LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; 4365 4408 LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); 4366 - FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k]; 4409 + FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k]; 4367 4410 4368 4411 ActiveClockChangeLatencyHidingY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY 4369 - - (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k]; 4412 + - (DSTXAfterScaler[k] / v->HTotal[k] + DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k]; 4370 4413 4371 - if (NumberOfActiveSurfaces > 1) { 4414 + if (v->NumberOfActiveSurfaces > 1) { 4372 4415 ActiveClockChangeLatencyHidingY = ActiveClockChangeLatencyHidingY 4373 - - (1 - 1 / NumberOfActiveSurfaces) * SwathHeightY[k] * HTotal[k] 4374 - / PixelClock[k] / VRatio[k]; 4416 + - (1 - 1 / v->NumberOfActiveSurfaces) * SwathHeightY[k] * v->HTotal[k] 4417 + / v->PixelClock[k] / v->VRatio[k]; 4375 4418 } 4376 4419 4377 4420 if (BytePerPixelDETC[k] > 0) { 4378 4421 LinesInDETC[k] = DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; 4379 4422 LinesInDETCRoundedDownToSwath[k] = dml_floor(LinesInDETC[k], SwathHeightC[k]); 4380 - FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) 4381 - / VRatioChroma[k]; 4423 + FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) 4424 + / v->VRatioChroma[k]; 4382 4425 ActiveClockChangeLatencyHidingC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC 4383 - - (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] 4384 - / PixelClock[k]; 4385 - if (NumberOfActiveSurfaces > 1) { 4426 + - (DSTXAfterScaler[k] / v->HTotal[k] + DSTYAfterScaler[k]) * v->HTotal[k] 4427 + / v->PixelClock[k]; 4428 + if (v->NumberOfActiveSurfaces > 1) { 4386 4429 ActiveClockChangeLatencyHidingC = ActiveClockChangeLatencyHidingC 4387 - - (1 - 1 / NumberOfActiveSurfaces) * SwathHeightC[k] * HTotal[k] 4388 - / PixelClock[k] / VRatioChroma[k]; 4430 + - (1 - 1 / v->NumberOfActiveSurfaces) * SwathHeightC[k] * v->HTotal[k] 4431 + / v->PixelClock[k] / v->VRatioChroma[k]; 4389 4432 } 4390 4433 ActiveClockChangeLatencyHiding = dml_min(ActiveClockChangeLatencyHidingY, 4391 4434 ActiveClockChangeLatencyHidingC); ··· 4393 4436 ActiveClockChangeLatencyHiding = ActiveClockChangeLatencyHidingY; 4394 4437 } 4395 4438 4396 - ActiveDRAMClockChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->UrgentWatermark 4397 - - Watermark->DRAMClockChangeWatermark; 4398 - ActiveFCLKChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->UrgentWatermark 4399 - - Watermark->FCLKChangeWatermark; 4400 - USRRetrainingLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->USRRetrainingWatermark; 4439 + ActiveDRAMClockChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.UrgentWatermark 4440 + - v->Watermark.DRAMClockChangeWatermark; 4441 + ActiveFCLKChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.UrgentWatermark 4442 + - v->Watermark.FCLKChangeWatermark; 4443 + USRRetrainingLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.USRRetrainingWatermark; 4401 4444 4402 - if (WritebackEnable[k]) { 4403 - WritebackLatencyHiding = WritebackInterfaceBufferSize * 1024 4404 - / (WritebackDestinationWidth[k] * WritebackDestinationHeight[k] 4405 - / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4); 4406 - if (WritebackPixelFormat[k] == dm_444_64) 4445 + if (v->WritebackEnable[k]) { 4446 + WritebackLatencyHiding = v->WritebackInterfaceBufferSize * 1024 4447 + / (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] 4448 + / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4); 4449 + if (v->WritebackPixelFormat[k] == dm_444_64) 4407 4450 WritebackLatencyHiding = WritebackLatencyHiding / 2; 4408 4451 4409 4452 WritebackDRAMClockChangeLatencyMargin = WritebackLatencyHiding 4410 - - Watermark->WritebackDRAMClockChangeWatermark; 4453 + - v->Watermark.WritebackDRAMClockChangeWatermark; 4411 4454 4412 4455 WritebackFCLKChangeLatencyMargin = WritebackLatencyHiding 4413 - - Watermark->WritebackFCLKChangeWatermark; 4456 + - v->Watermark.WritebackFCLKChangeWatermark; 4414 4457 4415 4458 ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMargin[k], 4416 4459 WritebackFCLKChangeLatencyMargin); ··· 4418 4461 WritebackDRAMClockChangeLatencyMargin); 4419 4462 } 4420 4463 MaxActiveDRAMClockChangeLatencySupported[k] = 4421 - (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ? 4464 + (v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ? 4422 4465 0 : 4423 4466 (ActiveDRAMClockChangeLatencyMargin[k] 4424 4467 + mmSOCParameters.DRAMClockChangeLatency); 4425 4468 } 4426 4469 4427 - for (i = 0; i < NumberOfActiveSurfaces; ++i) { 4428 - for (j = 0; j < NumberOfActiveSurfaces; ++j) { 4470 + for (i = 0; i < v->NumberOfActiveSurfaces; ++i) { 4471 + for (j = 0; j < v->NumberOfActiveSurfaces; ++j) { 4429 4472 if (i == j || 4430 - (BlendingAndTiming[i] == i && BlendingAndTiming[j] == i) || 4431 - (BlendingAndTiming[j] == j && BlendingAndTiming[i] == j) || 4432 - (BlendingAndTiming[i] == BlendingAndTiming[j] && BlendingAndTiming[i] != i) || 4433 - (SynchronizeTimingsFinal && PixelClock[i] == PixelClock[j] && 4434 - HTotal[i] == HTotal[j] && VTotal[i] == VTotal[j] && 4435 - VActive[i] == VActive[j]) || (SynchronizeDRRDisplaysForUCLKPStateChangeFinal && 4436 - (DRRDisplay[i] || DRRDisplay[j]))) { 4473 + (v->BlendingAndTiming[i] == i && v->BlendingAndTiming[j] == i) || 4474 + (v->BlendingAndTiming[j] == j && v->BlendingAndTiming[i] == j) || 4475 + (v->BlendingAndTiming[i] == v->BlendingAndTiming[j] && v->BlendingAndTiming[i] != i) || 4476 + (v->SynchronizeTimingsFinal && v->PixelClock[i] == v->PixelClock[j] && 4477 + v->HTotal[i] == v->HTotal[j] && v->VTotal[i] == v->VTotal[j] && 4478 + v->VActive[i] == v->VActive[j]) || (v->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && 4479 + (v->DRRDisplay[i] || v->DRRDisplay[j]))) { 4437 4480 SynchronizedSurfaces[i][j] = true; 4438 4481 } else { 4439 4482 SynchronizedSurfaces[i][j] = false; ··· 4441 4484 } 4442 4485 } 4443 4486 4444 - for (k = 0; k < NumberOfActiveSurfaces; ++k) { 4445 - if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) && 4487 + for (k = 0; k < v->NumberOfActiveSurfaces; ++k) { 4488 + if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) && 4446 4489 (!FoundFirstSurfaceWithMinActiveFCLKChangeMargin || 4447 4490 ActiveFCLKChangeLatencyMargin[k] < MinActiveFCLKChangeMargin)) { 4448 4491 FoundFirstSurfaceWithMinActiveFCLKChangeMargin = true; ··· 4454 4497 *MinActiveFCLKChangeLatencySupported = MinActiveFCLKChangeMargin + mmSOCParameters.FCLKChangeLatency; 4455 4498 4456 4499 SameTimingForFCLKChange = true; 4457 - for (k = 0; k < NumberOfActiveSurfaces; ++k) { 4500 + for (k = 0; k < v->NumberOfActiveSurfaces; ++k) { 4458 4501 if (!SynchronizedSurfaces[k][SurfaceWithMinActiveFCLKChangeMargin]) { 4459 - if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) && 4502 + if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) && 4460 4503 (SameTimingForFCLKChange || 4461 4504 ActiveFCLKChangeLatencyMargin[k] < 4462 4505 SecondMinActiveFCLKChangeMarginOneDisplayInVBLank)) { ··· 4476 4519 } 4477 4520 4478 4521 *USRRetrainingSupport = true; 4479 - for (k = 0; k < NumberOfActiveSurfaces; ++k) { 4480 - if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) && 4522 + for (k = 0; k < v->NumberOfActiveSurfaces; ++k) { 4523 + if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) && 4481 4524 (USRRetrainingLatencyMargin[k] < 0)) { 4482 4525 *USRRetrainingSupport = false; 4483 4526 } 4484 4527 } 4485 4528 4486 - for (k = 0; k < NumberOfActiveSurfaces; ++k) { 4487 - if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_full_frame && 4488 - UseMALLForPStateChange[k] != dm_use_mall_pstate_change_sub_viewport && 4489 - UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe && 4529 + for (k = 0; k < v->NumberOfActiveSurfaces; ++k) { 4530 + if (v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_full_frame && 4531 + v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_sub_viewport && 4532 + v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe && 4490 4533 ActiveDRAMClockChangeLatencyMargin[k] < 0) { 4491 4534 if (PrefetchMode > 0) { 4492 4535 DRAMClockChangeSupportNumber = 2; ··· 4500 4543 } 4501 4544 } 4502 4545 4503 - for (k = 0; k < NumberOfActiveSurfaces; ++k) { 4504 - if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame) 4546 + for (k = 0; k < v->NumberOfActiveSurfaces; ++k) { 4547 + if (v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame) 4505 4548 DRAMClockChangeMethod = 1; 4506 - else if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) 4549 + else if (v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) 4507 4550 DRAMClockChangeMethod = 2; 4508 4551 } 4509 4552 ··· 4530 4573 *DRAMClockChangeSupport = dm_dram_clock_change_unsupported; 4531 4574 } 4532 4575 4533 - for (k = 0; k < NumberOfActiveSurfaces; ++k) { 4576 + for (k = 0; k < v->NumberOfActiveSurfaces; ++k) { 4534 4577 unsigned int dst_y_pstate; 4535 4578 unsigned int src_y_pstate_l; 4536 4579 unsigned int src_y_pstate_c; 4537 4580 unsigned int src_y_ahead_l, src_y_ahead_c, sub_vp_lines_l, sub_vp_lines_c; 4538 4581 4539 - dst_y_pstate = dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (HTotal[k] / PixelClock[k]), 1); 4540 - src_y_pstate_l = dml_ceil(dst_y_pstate * VRatio[k], SwathHeightY[k]); 4582 + dst_y_pstate = dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (v->HTotal[k] / v->PixelClock[k]), 1); 4583 + src_y_pstate_l = dml_ceil(dst_y_pstate * v->VRatio[k], SwathHeightY[k]); 4541 4584 src_y_ahead_l = dml_floor(DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k], SwathHeightY[k]) + LBLatencyHidingSourceLinesY[k]; 4542 - sub_vp_lines_l = src_y_pstate_l + src_y_ahead_l + meta_row_height[k]; 4585 + sub_vp_lines_l = src_y_pstate_l + src_y_ahead_l + v->meta_row_height[k]; 4543 4586 4544 4587 #ifdef __DML_VBA_DEBUG__ 4545 4588 dml_print("DML::%s: k=%d, DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]); ··· 4550 4593 dml_print("DML::%s: k=%d, dst_y_pstate = %d\n", __func__, k, dst_y_pstate); 4551 4594 dml_print("DML::%s: k=%d, src_y_pstate_l = %d\n", __func__, k, src_y_pstate_l); 4552 4595 dml_print("DML::%s: k=%d, src_y_ahead_l = %d\n", __func__, k, src_y_ahead_l); 4553 - dml_print("DML::%s: k=%d, meta_row_height = %d\n", __func__, k, meta_row_height[k]); 4596 + dml_print("DML::%s: k=%d, v->meta_row_height = %d\n", __func__, k, v->meta_row_height[k]); 4554 4597 dml_print("DML::%s: k=%d, sub_vp_lines_l = %d\n", __func__, k, sub_vp_lines_l); 4555 4598 #endif 4556 4599 SubViewportLinesNeededInMALL[k] = sub_vp_lines_l; 4557 4600 4558 4601 if (BytePerPixelDETC[k] > 0) { 4559 - src_y_pstate_c = dml_ceil(dst_y_pstate * VRatioChroma[k], SwathHeightC[k]); 4602 + src_y_pstate_c = dml_ceil(dst_y_pstate * v->VRatioChroma[k], SwathHeightC[k]); 4560 4603 src_y_ahead_c = dml_floor(DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k], SwathHeightC[k]) + LBLatencyHidingSourceLinesC[k]; 4561 - sub_vp_lines_c = src_y_pstate_c + src_y_ahead_c + meta_row_height_chroma[k]; 4604 + sub_vp_lines_c = src_y_pstate_c + src_y_ahead_c + v->meta_row_height_chroma[k]; 4562 4605 SubViewportLinesNeededInMALL[k] = dml_max(sub_vp_lines_l, sub_vp_lines_c); 4563 4606 4564 4607 #ifdef __DML_VBA_DEBUG__ 4565 4608 dml_print("DML::%s: k=%d, src_y_pstate_c = %d\n", __func__, k, src_y_pstate_c); 4566 4609 dml_print("DML::%s: k=%d, src_y_ahead_c = %d\n", __func__, k, src_y_ahead_c); 4567 - dml_print("DML::%s: k=%d, meta_row_height_chroma = %d\n", __func__, k, meta_row_height_chroma[k]); 4610 + dml_print("DML::%s: k=%d, v->meta_row_height_chroma = %d\n", __func__, k, v->meta_row_height_chroma[k]); 4568 4611 dml_print("DML::%s: k=%d, sub_vp_lines_c = %d\n", __func__, k, sub_vp_lines_c); 4569 4612 #endif 4570 4613 }
+4 -47
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
··· 30 30 #include "os_types.h" 31 31 #include "../dc_features.h" 32 32 #include "../display_mode_structs.h" 33 + #include "dml/display_mode_vba.h" 33 34 34 35 unsigned int dml32_dscceComputeDelay( 35 36 unsigned int bpc, ··· 713 712 unsigned int HostVMMaxNonCachedPageTableLevels); 714 713 715 714 bool dml32_CalculatePrefetchSchedule( 715 + struct vba_vars_st *v, 716 + unsigned int k, 716 717 double HostVMInefficiencyFactor, 717 718 DmlPipe *myPipe, 718 719 unsigned int DSCDelay, 719 - double DPPCLKDelaySubtotalPlusCNVCFormater, 720 - double DPPCLKDelaySCL, 721 - double DPPCLKDelaySCLLBOnly, 722 - double DPPCLKDelayCNVCCursor, 723 - double DISPCLKDelaySubtotal, 724 720 unsigned int DPP_RECOUT_WIDTH, 725 - enum output_format_class OutputFormat, 726 - unsigned int MaxInterDCNTileRepeaters, 727 721 unsigned int VStartup, 728 722 unsigned int MaxVStartup, 729 - unsigned int GPUVMPageTableLevels, 730 - bool GPUVMEnable, 731 - bool HostVMEnable, 732 - unsigned int HostVMMaxNonCachedPageTableLevels, 733 - double HostVMMinPageSize, 734 - bool DynamicMetadataEnable, 735 - bool DynamicMetadataVMEnabled, 736 - int DynamicMetadataLinesBeforeActiveRequired, 737 - unsigned int DynamicMetadataTransmittedBytes, 738 723 double UrgentLatency, 739 724 double UrgentExtraLatency, 740 725 double TCalc, ··· 794 807 bool *ImmediateFlipSupportedForPipe); 795 808 796 809 void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( 797 - bool USRRetrainingRequiredFinal, 798 - enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], 810 + struct vba_vars_st *v, 799 811 unsigned int PrefetchMode, 800 - unsigned int NumberOfActiveSurfaces, 801 - unsigned int MaxLineBufferLines, 802 - unsigned int LineBufferSize, 803 - unsigned int WritebackInterfaceBufferSize, 804 812 double DCFCLK, 805 813 double ReturnBW, 806 - bool SynchronizeTimingsFinal, 807 - bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal, 808 - bool DRRDisplay[], 809 - unsigned int dpte_group_bytes[], 810 - unsigned int meta_row_height[], 811 - unsigned int meta_row_height_chroma[], 812 814 SOCParametersList mmSOCParameters, 813 - unsigned int WritebackChunkSize, 814 815 double SOCCLK, 815 816 double DCFClkDeepSleep, 816 817 unsigned int DETBufferSizeY[], 817 818 unsigned int DETBufferSizeC[], 818 819 unsigned int SwathHeightY[], 819 820 unsigned int SwathHeightC[], 820 - unsigned int LBBitPerPixel[], 821 821 double SwathWidthY[], 822 822 double SwathWidthC[], 823 - double HRatio[], 824 - double HRatioChroma[], 825 - unsigned int VTaps[], 826 - unsigned int VTapsChroma[], 827 - double VRatio[], 828 - double VRatioChroma[], 829 - unsigned int HTotal[], 830 - unsigned int VTotal[], 831 - unsigned int VActive[], 832 - double PixelClock[], 833 - unsigned int BlendingAndTiming[], 834 823 unsigned int DPPPerSurface[], 835 824 double BytePerPixelDETY[], 836 825 double BytePerPixelDETC[], 837 826 double DSTXAfterScaler[], 838 827 double DSTYAfterScaler[], 839 - bool WritebackEnable[], 840 - enum source_format_class WritebackPixelFormat[], 841 - double WritebackDestinationWidth[], 842 - double WritebackDestinationHeight[], 843 - double WritebackSourceHeight[], 844 828 bool UnboundedRequestEnabled, 845 829 unsigned int CompressedBufferSizeInkByte, 846 830 847 831 /* Output */ 848 - Watermarks *Watermark, 849 832 enum clock_change_support *DRAMClockChangeSupport, 850 833 double MaxActiveDRAMClockChangeLatencySupported[], 851 834 unsigned int SubViewportLinesNeededInMALL[],
+12
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
··· 35 35 #include "dcn30/display_rq_dlg_calc_30.h" 36 36 #include "dcn31/display_mode_vba_31.h" 37 37 #include "dcn31/display_rq_dlg_calc_31.h" 38 + #include "dcn314/display_mode_vba_314.h" 39 + #include "dcn314/display_rq_dlg_calc_314.h" 38 40 #include "dcn32/display_mode_vba_32.h" 39 41 #include "dcn32/display_rq_dlg_calc_32.h" 40 42 #include "dml_logger.h" ··· 76 74 .rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg 77 75 }; 78 76 77 + const struct dml_funcs dml314_funcs = { 78 + .validate = dml314_ModeSupportAndSystemConfigurationFull, 79 + .recalculate = dml314_recalculate, 80 + .rq_dlg_get_dlg_reg = dml314_rq_dlg_get_dlg_reg, 81 + .rq_dlg_get_rq_reg = dml314_rq_dlg_get_rq_reg 82 + }; 83 + 79 84 const struct dml_funcs dml32_funcs = { 80 85 .validate = dml32_ModeSupportAndSystemConfigurationFull, 81 86 .recalculate = dml32_recalculate, ··· 115 106 case DML_PROJECT_DCN31: 116 107 case DML_PROJECT_DCN31_FPGA: 117 108 lib->funcs = dml31_funcs; 109 + break; 110 + case DML_PROJECT_DCN314: 111 + lib->funcs = dml314_funcs; 118 112 break; 119 113 case DML_PROJECT_DCN32: 120 114 lib->funcs = dml32_funcs;
+1
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
··· 41 41 DML_PROJECT_DCN30, 42 42 DML_PROJECT_DCN31, 43 43 DML_PROJECT_DCN31_FPGA, 44 + DML_PROJECT_DCN314, 44 45 DML_PROJECT_DCN32, 45 46 }; 46 47
+4 -6
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
··· 651 651 652 652 unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 653 653 double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 654 - unsigned int MicroTileHeightY[DC__NUM_DPP__MAX]; 655 - unsigned int MicroTileHeightC[DC__NUM_DPP__MAX]; 656 - unsigned int MicroTileWidthY[DC__NUM_DPP__MAX]; 657 - unsigned int MicroTileWidthC[DC__NUM_DPP__MAX]; 654 + unsigned int MacroTileHeightY[DC__NUM_DPP__MAX]; 655 + unsigned int MacroTileHeightC[DC__NUM_DPP__MAX]; 656 + unsigned int MacroTileWidthY[DC__NUM_DPP__MAX]; 657 + unsigned int MacroTileWidthC[DC__NUM_DPP__MAX]; 658 658 bool ImmediateFlipRequiredFinal; 659 659 bool DCCProgrammingAssumesScanDirectionUnknownFinal; 660 660 bool EnoughWritebackUnits; ··· 800 800 double PSCL_FACTOR[DC__NUM_DPP__MAX]; 801 801 double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX]; 802 802 double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 803 - unsigned int MacroTileWidthY[DC__NUM_DPP__MAX]; 804 - unsigned int MacroTileWidthC[DC__NUM_DPP__MAX]; 805 803 double AlignedDCCMetaPitch[DC__NUM_DPP__MAX]; 806 804 double AlignedYPitch[DC__NUM_DPP__MAX]; 807 805 double AlignedCPitch[DC__NUM_DPP__MAX];
+1
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
··· 214 214 struct clk_bw_params { 215 215 unsigned int vram_type; 216 216 unsigned int num_channels; 217 + unsigned int dram_channel_width_bytes; 217 218 unsigned int dispclk_vco_khz; 218 219 unsigned int dc_mode_softmax_memclk; 219 220 struct clk_limit_table clk_table;
+4
drivers/gpu/drm/amd/display/modules/color/color_gamma.c
··· 1600 1600 struct fixed31_32 lut2; 1601 1601 struct fixed31_32 delta_lut; 1602 1602 struct fixed31_32 delta_index; 1603 + const struct fixed31_32 one = dc_fixpt_from_int(1); 1603 1604 1604 1605 i = 0; 1605 1606 /* fixed_pt library has problems handling too small values */ ··· 1628 1627 hw_x = coordinates_x[i].regamma_y_blue; 1629 1628 } else 1630 1629 hw_x = coordinates_x[i].x; 1630 + 1631 + if (dc_fixpt_le(one, hw_x)) 1632 + hw_x = one; 1631 1633 1632 1634 norm_x = dc_fixpt_mul(norm_factor, hw_x); 1633 1635 index = dc_fixpt_floor(norm_x);
+11
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
··· 368 368 smu_baco->platform_support = 369 369 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 370 370 false; 371 + 372 + /* 373 + * Disable BACO entry/exit completely on below SKUs to 374 + * avoid hardware intermittent failures. 375 + */ 376 + if (((adev->pdev->device == 0x73A1) && 377 + (adev->pdev->revision == 0x00)) || 378 + ((adev->pdev->device == 0x73BF) && 379 + (adev->pdev->revision == 0xCF))) 380 + smu_baco->platform_support = false; 381 + 371 382 } 372 383 } 373 384
+1 -3
drivers/gpu/drm/gma500/cdv_device.c
··· 581 581 static int cdv_chip_setup(struct drm_device *dev) 582 582 { 583 583 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 584 - struct pci_dev *pdev = to_pci_dev(dev->dev); 585 584 INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func); 586 585 587 - if (pci_enable_msi(pdev)) 588 - dev_warn(dev->dev, "Enabling MSI failed!\n"); 586 + dev_priv->use_msi = true; 589 587 dev_priv->regmap = cdv_regmap; 590 588 gma_get_core_freq(dev); 591 589 psb_intel_opregion_init(dev);
+2 -2
drivers/gpu/drm/gma500/gem.c
··· 112 112 { 113 113 struct psb_gem_object *pobj = to_psb_gem_object(obj); 114 114 115 - drm_gem_object_release(obj); 116 - 117 115 /* Undo the mmap pin if we are destroying the object */ 118 116 if (pobj->mmapping) 119 117 psb_gem_unpin(pobj); 118 + 119 + drm_gem_object_release(obj); 120 120 121 121 WARN_ON(pobj->in_gart && !pobj->stolen); 122 122
+7 -4
drivers/gpu/drm/gma500/gma_display.c
··· 532 532 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 533 533 534 534 gma_crtc->page_flip_event = event; 535 + spin_unlock_irqrestore(&dev->event_lock, flags); 535 536 536 537 /* Call this locked if we want an event at vblank interrupt. */ 537 538 ret = crtc_funcs->mode_set_base(crtc, crtc->x, crtc->y, old_fb); 538 539 if (ret) { 539 - gma_crtc->page_flip_event = NULL; 540 - drm_crtc_vblank_put(crtc); 540 + spin_lock_irqsave(&dev->event_lock, flags); 541 + if (gma_crtc->page_flip_event) { 542 + gma_crtc->page_flip_event = NULL; 543 + drm_crtc_vblank_put(crtc); 544 + } 545 + spin_unlock_irqrestore(&dev->event_lock, flags); 541 546 } 542 - 543 - spin_unlock_irqrestore(&dev->event_lock, flags); 544 547 } else { 545 548 ret = crtc_funcs->mode_set_base(crtc, crtc->x, crtc->y, old_fb); 546 549 }
+1 -4
drivers/gpu/drm/gma500/oaktrail_device.c
··· 501 501 static int oaktrail_chip_setup(struct drm_device *dev) 502 502 { 503 503 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 504 - struct pci_dev *pdev = to_pci_dev(dev->dev); 505 504 int ret; 506 505 507 - if (pci_enable_msi(pdev)) 508 - dev_warn(dev->dev, "Enabling MSI failed!\n"); 509 - 506 + dev_priv->use_msi = true; 510 507 dev_priv->regmap = oaktrail_regmap; 511 508 512 509 ret = mid_chip_setup(dev);
+1 -7
drivers/gpu/drm/gma500/power.c
··· 139 139 dev_priv->regs.saveBSM = bsm; 140 140 pci_read_config_dword(pdev, 0xFC, &vbt); 141 141 dev_priv->regs.saveVBT = vbt; 142 - pci_read_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, &dev_priv->msi_addr); 143 - pci_read_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, &dev_priv->msi_data); 144 142 145 143 pci_disable_device(pdev); 146 144 pci_set_power_state(pdev, PCI_D3hot); ··· 166 168 pci_restore_state(pdev); 167 169 pci_write_config_dword(pdev, 0x5c, dev_priv->regs.saveBSM); 168 170 pci_write_config_dword(pdev, 0xFC, dev_priv->regs.saveVBT); 169 - /* restoring MSI address and data in PCIx space */ 170 - pci_write_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, dev_priv->msi_addr); 171 - pci_write_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, dev_priv->msi_data); 172 171 ret = pci_enable_device(pdev); 173 172 174 173 if (ret != 0) ··· 218 223 mutex_lock(&power_mutex); 219 224 gma_resume_pci(pdev); 220 225 gma_resume_display(pdev); 221 - gma_irq_preinstall(dev); 222 - gma_irq_postinstall(dev); 226 + gma_irq_install(dev); 223 227 mutex_unlock(&power_mutex); 224 228 return 0; 225 229 }
+1 -1
drivers/gpu/drm/gma500/psb_drv.c
··· 383 383 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R); 384 384 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 385 385 386 - gma_irq_install(dev, pdev->irq); 386 + gma_irq_install(dev); 387 387 388 388 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 389 389
+1 -4
drivers/gpu/drm/gma500/psb_drv.h
··· 490 490 int rpm_enabled; 491 491 492 492 /* MID specific */ 493 + bool use_msi; 493 494 bool has_gct; 494 495 struct oaktrail_gct_data gct_data; 495 496 ··· 499 498 500 499 /* Register state */ 501 500 struct psb_save_area regs; 502 - 503 - /* MSI reg save */ 504 - uint32_t msi_addr; 505 - uint32_t msi_data; 506 501 507 502 /* Hotplug handling */ 508 503 struct work_struct hotplug_work;
+12 -3
drivers/gpu/drm/gma500/psb_irq.c
··· 316 316 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 317 317 } 318 318 319 - int gma_irq_install(struct drm_device *dev, unsigned int irq) 319 + int gma_irq_install(struct drm_device *dev) 320 320 { 321 + struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 322 + struct pci_dev *pdev = to_pci_dev(dev->dev); 321 323 int ret; 322 324 323 - if (irq == IRQ_NOTCONNECTED) 325 + if (dev_priv->use_msi && pci_enable_msi(pdev)) { 326 + dev_warn(dev->dev, "Enabling MSI failed!\n"); 327 + dev_priv->use_msi = false; 328 + } 329 + 330 + if (pdev->irq == IRQ_NOTCONNECTED) 324 331 return -ENOTCONN; 325 332 326 333 gma_irq_preinstall(dev); 327 334 328 335 /* PCI devices require shared interrupts. */ 329 - ret = request_irq(irq, gma_irq_handler, IRQF_SHARED, dev->driver->name, dev); 336 + ret = request_irq(pdev->irq, gma_irq_handler, IRQF_SHARED, dev->driver->name, dev); 330 337 if (ret) 331 338 return ret; 332 339 ··· 376 369 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 377 370 378 371 free_irq(pdev->irq, dev); 372 + if (dev_priv->use_msi) 373 + pci_disable_msi(pdev); 379 374 } 380 375 381 376 int gma_crtc_enable_vblank(struct drm_crtc *crtc)
+1 -1
drivers/gpu/drm/gma500/psb_irq.h
··· 17 17 18 18 void gma_irq_preinstall(struct drm_device *dev); 19 19 void gma_irq_postinstall(struct drm_device *dev); 20 - int gma_irq_install(struct drm_device *dev, unsigned int irq); 20 + int gma_irq_install(struct drm_device *dev); 21 21 void gma_irq_uninstall(struct drm_device *dev); 22 22 23 23 int gma_crtc_enable_vblank(struct drm_crtc *crtc);
+2
drivers/gpu/drm/i915/display/icl_dsi.c
··· 1629 1629 /* FIXME: initialize from VBT */ 1630 1630 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1631 1631 1632 + vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1633 + 1632 1634 ret = intel_dsc_compute_params(crtc_state); 1633 1635 if (ret) 1634 1636 return ret;
+4 -29
drivers/gpu/drm/i915/display/intel_dp.c
··· 389 389 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000; 390 390 } 391 391 392 - static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy) 393 - { 394 - u32 voltage; 395 - 396 - voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK; 397 - 398 - return voltage == VOLTAGE_INFO_0_85V; 399 - } 400 - 401 392 static int icl_max_source_rate(struct intel_dp *intel_dp) 402 393 { 403 394 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 404 395 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 405 396 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 406 397 407 - if (intel_phy_is_combo(dev_priv, phy) && 408 - (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp))) 398 + if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp)) 409 399 return 540000; 410 400 411 401 return 810000; ··· 403 413 404 414 static int ehl_max_source_rate(struct intel_dp *intel_dp) 405 415 { 406 - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 407 - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 408 - enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 409 - 410 - if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy)) 411 - return 540000; 412 - 413 - return 810000; 414 - } 415 - 416 - static int dg1_max_source_rate(struct intel_dp *intel_dp) 417 - { 418 - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 419 - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 420 - enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 421 - 422 - if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy)) 416 + if (intel_dp_is_edp(intel_dp)) 423 417 return 540000; 424 418 425 419 return 810000; ··· 465 491 max_rate = dg2_max_source_rate(intel_dp); 466 492 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) || 467 493 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 468 - max_rate = dg1_max_source_rate(intel_dp); 494 + max_rate = 810000; 469 495 else if (IS_JSL_EHL(dev_priv)) 470 496 max_rate = ehl_max_source_rate(intel_dp); 471 497 else ··· 1369 1395 * DP_DSC_RC_BUF_SIZE for this. 1370 1396 */ 1371 1397 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1398 + vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1372 1399 1373 1400 /* 1374 1401 * Slice Height of 8 works for all currently available panels. So start
-1
drivers/gpu/drm/i915/display/intel_vdsc.c
··· 460 460 u8 i = 0; 461 461 462 462 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; 463 - vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; 464 463 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, 465 464 pipe_config->dsc.slice_count); 466 465
+6 -1
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
··· 1438 1438 if (!guc_submission_initialized(guc)) 1439 1439 return; 1440 1440 1441 - cancel_delayed_work(&guc->timestamp.work); 1441 + /* 1442 + * There is a race with suspend flow where the worker runs after suspend 1443 + * and causes an unclaimed register access warning. Cancel the worker 1444 + * synchronously here. 1445 + */ 1446 + cancel_delayed_work_sync(&guc->timestamp.work); 1442 1447 1443 1448 /* 1444 1449 * Before parking, we should sample engine busyness stats if we need to.
+8 -8
drivers/gpu/drm/i915/i915_reg.h
··· 1857 1857 1858 1858 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) 1859 1859 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 1860 - #define PROCHOT_MASK REG_BIT(1) 1861 - #define THERMAL_LIMIT_MASK REG_BIT(2) 1862 - #define RATL_MASK REG_BIT(6) 1863 - #define VR_THERMALERT_MASK REG_BIT(7) 1864 - #define VR_TDC_MASK REG_BIT(8) 1865 - #define POWER_LIMIT_4_MASK REG_BIT(9) 1866 - #define POWER_LIMIT_1_MASK REG_BIT(11) 1867 - #define POWER_LIMIT_2_MASK REG_BIT(12) 1860 + #define PROCHOT_MASK REG_BIT(0) 1861 + #define THERMAL_LIMIT_MASK REG_BIT(1) 1862 + #define RATL_MASK REG_BIT(5) 1863 + #define VR_THERMALERT_MASK REG_BIT(6) 1864 + #define VR_TDC_MASK REG_BIT(7) 1865 + #define POWER_LIMIT_4_MASK REG_BIT(8) 1866 + #define POWER_LIMIT_1_MASK REG_BIT(10) 1867 + #define POWER_LIMIT_2_MASK REG_BIT(11) 1868 1868 1869 1869 #define CHV_CLK_CTL1 _MMIO(0x101100) 1870 1870 #define VLV_CLK_CTL2 _MMIO(0x101104)
+2 -1
drivers/gpu/drm/i915/i915_vma.c
··· 1882 1882 enum dma_resv_usage usage; 1883 1883 int idx; 1884 1884 1885 - obj->read_domains = 0; 1886 1885 if (flags & EXEC_OBJECT_WRITE) { 1887 1886 usage = DMA_RESV_USAGE_WRITE; 1888 1887 obj->write_domain = I915_GEM_DOMAIN_RENDER; 1888 + obj->read_domains = 0; 1889 1889 } else { 1890 1890 usage = DMA_RESV_USAGE_READ; 1891 + obj->write_domain = 0; 1891 1892 } 1892 1893 1893 1894 dma_fence_array_for_each(curr, idx, fence)
+1 -1
drivers/gpu/drm/meson/meson_plane.c
··· 170 170 171 171 /* Enable OSD and BLK0, set max global alpha */ 172 172 priv->viu.osd1_ctrl_stat = OSD_ENABLE | 173 - (0xFF << OSD_GLOBAL_ALPHA_SHIFT) | 173 + (0x100 << OSD_GLOBAL_ALPHA_SHIFT) | 174 174 OSD_BLK0_ENABLE; 175 175 176 176 priv->viu.osd1_ctrl_stat2 = readl(priv->io_base +
+1 -1
drivers/gpu/drm/meson/meson_viu.c
··· 94 94 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); 95 95 writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff), 96 96 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); 97 - writel((m[11] & 0x1fff) << 16, 97 + writel((m[11] & 0x1fff), 98 98 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); 99 99 100 100 writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
+2 -1
drivers/gpu/drm/panel/panel-edp.c
··· 1295 1295 }, 1296 1296 .delay = { 1297 1297 .hpd_absent = 200, 1298 - .prepare_to_enable = 80, 1298 + .enable = 80, 1299 + .disable = 50, 1299 1300 .unprepare = 500, 1300 1301 }, 1301 1302 };
+3 -2
drivers/gpu/drm/rockchip/cdn-dp-core.c
··· 283 283 return ret; 284 284 } 285 285 286 - static int cdn_dp_connector_mode_valid(struct drm_connector *connector, 287 - struct drm_display_mode *mode) 286 + static enum drm_mode_status 287 + cdn_dp_connector_mode_valid(struct drm_connector *connector, 288 + struct drm_display_mode *mode) 288 289 { 289 290 struct cdn_dp_device *dp = connector_to_dp(connector); 290 291 struct drm_display_info *display_info = &dp->connector.display_info;
+4
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
··· 1439 1439 die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX; 1440 1440 die |= RK3568_SYS_DSP_INFACE_EN_HDMI | 1441 1441 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id); 1442 + dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL; 1443 + dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags); 1442 1444 break; 1443 1445 case ROCKCHIP_VOP2_EP_EDP0: 1444 1446 die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX; 1445 1447 die |= RK3568_SYS_DSP_INFACE_EN_EDP | 1446 1448 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id); 1449 + dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL; 1450 + dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags); 1447 1451 break; 1448 1452 case ROCKCHIP_VOP2_EP_MIPI0: 1449 1453 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX;