Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/xe/pat: Move PAT setup to a dedicated file
PAT handling is growing in complexity and will continue to do so in
upcoming platforms. Separate it out to a dedicated file to keep things
tidy.
The code is moved as-is here (aside from a few unused #define's that are
just dropped); further changes will come in future patches.
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230324210415.2434992-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
authored by
Matt Roper
and committed by
Rodrigo Vivi
576c6380
cf667aec
+98
-80
+1
drivers/gpu/drm/xe/Makefile
+1
drivers/gpu/drm/xe/Makefile
-1
drivers/gpu/drm/xe/regs/xe_gt_regs.h
-1
drivers/gpu/drm/xe/regs/xe_gt_regs.h
+3
-79
drivers/gpu/drm/xe/xe_gt.c
+3
-79
drivers/gpu/drm/xe/xe_gt.c
···
29
29
#include "xe_map.h"
30
30
#include "xe_migrate.h"
31
31
#include "xe_mmio.h"
32
+
#include "xe_pat.h"
32
33
#include "xe_mocs.h"
33
34
#include "xe_reg_sr.h"
34
35
#include "xe_ring_ops.h"
···
91
90
gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", 0);
92
91
93
92
return 0;
94
-
}
95
-
96
-
/* FIXME: These should be in a common file */
97
-
#define CHV_PPAT_SNOOP REG_BIT(6)
98
-
#define GEN8_PPAT_AGE(x) ((x)<<4)
99
-
#define GEN8_PPAT_LLCeLLC (3<<2)
100
-
#define GEN8_PPAT_LLCELLC (2<<2)
101
-
#define GEN8_PPAT_LLC (1<<2)
102
-
#define GEN8_PPAT_WB (3<<0)
103
-
#define GEN8_PPAT_WT (2<<0)
104
-
#define GEN8_PPAT_WC (1<<0)
105
-
#define GEN8_PPAT_UC (0<<0)
106
-
#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
107
-
#define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
108
-
#define GEN12_PPAT_CLOS(x) ((x)<<2)
109
-
110
-
static void tgl_setup_private_ppat(struct xe_gt *gt)
111
-
{
112
-
/* TGL doesn't support LLC or AGE settings */
113
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, GEN8_PPAT_WB);
114
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg, GEN8_PPAT_WC);
115
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg, GEN8_PPAT_WT);
116
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg, GEN8_PPAT_UC);
117
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg, GEN8_PPAT_WB);
118
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(5).reg, GEN8_PPAT_WB);
119
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(6).reg, GEN8_PPAT_WB);
120
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(7).reg, GEN8_PPAT_WB);
121
-
}
122
-
123
-
static void pvc_setup_private_ppat(struct xe_gt *gt)
124
-
{
125
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, GEN8_PPAT_UC);
126
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg, GEN8_PPAT_WC);
127
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg, GEN8_PPAT_WT);
128
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg, GEN8_PPAT_WB);
129
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg,
130
-
GEN12_PPAT_CLOS(1) | GEN8_PPAT_WT);
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-
xe_mmio_write32(gt, GEN12_PAT_INDEX(5).reg,
132
-
GEN12_PPAT_CLOS(1) | GEN8_PPAT_WB);
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-
xe_mmio_write32(gt, GEN12_PAT_INDEX(6).reg,
134
-
GEN12_PPAT_CLOS(2) | GEN8_PPAT_WT);
135
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(7).reg,
136
-
GEN12_PPAT_CLOS(2) | GEN8_PPAT_WB);
137
-
}
138
-
139
-
#define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)
140
-
#define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)
141
-
#define MTL_PPAT_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3)
142
-
#define MTL_PPAT_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1)
143
-
#define MTL_PPAT_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0)
144
-
#define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3)
145
-
#define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2)
146
-
#define MTL_0_COH_NON REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 0)
147
-
148
-
static void mtl_setup_private_ppat(struct xe_gt *gt)
149
-
{
150
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, MTL_PPAT_0_WB);
151
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg,
152
-
MTL_PPAT_1_WT | MTL_2_COH_1W);
153
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg,
154
-
MTL_PPAT_3_UC | MTL_2_COH_1W);
155
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg,
156
-
MTL_PPAT_0_WB | MTL_2_COH_1W);
157
-
xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg,
158
-
MTL_PPAT_0_WB | MTL_3_COH_2W);
159
-
}
160
-
161
-
static void setup_private_ppat(struct xe_gt *gt)
162
-
{
163
-
struct xe_device *xe = gt_to_xe(gt);
164
-
165
-
if (xe->info.platform == XE_METEORLAKE)
166
-
mtl_setup_private_ppat(gt);
167
-
else if (xe->info.platform == XE_PVC)
168
-
pvc_setup_private_ppat(gt);
169
-
else
170
-
tgl_setup_private_ppat(gt);
171
93
}
172
94
173
95
static int gt_ttm_mgr_init(struct xe_gt *gt)
···
371
447
if (err)
372
448
goto err_hw_fence_irq;
373
449
374
-
setup_private_ppat(gt);
450
+
xe_pat_init(gt);
375
451
376
452
if (!xe_gt_is_media_type(gt)) {
377
453
err = xe_ggtt_init(gt, gt->mem.ggtt);
···
557
633
enum xe_hw_engine_id id;
558
634
int err;
559
635
560
-
setup_private_ppat(gt);
636
+
xe_pat_init(gt);
561
637
562
638
xe_gt_mcr_set_implicit_defaults(gt);
563
639
xe_reg_sr_apply_mmio(>->reg_sr, gt);
+81
drivers/gpu/drm/xe/xe_pat.c
+81
drivers/gpu/drm/xe/xe_pat.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/*
3
+
* Copyright © 2023 Intel Corporation
4
+
*/
5
+
6
+
#include "xe_pat.h"
7
+
8
+
#include "regs/xe_reg_defs.h"
9
+
#include "xe_gt.h"
10
+
#include "xe_mmio.h"
11
+
12
+
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
13
+
14
+
#define GEN8_PPAT_WB (3<<0)
15
+
#define GEN8_PPAT_WT (2<<0)
16
+
#define GEN8_PPAT_WC (1<<0)
17
+
#define GEN8_PPAT_UC (0<<0)
18
+
#define GEN12_PPAT_CLOS(x) ((x)<<2)
19
+
20
+
static void tgl_setup_private_ppat(struct xe_gt *gt)
21
+
{
22
+
/* TGL doesn't support LLC or AGE settings */
23
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, GEN8_PPAT_WB);
24
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg, GEN8_PPAT_WC);
25
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg, GEN8_PPAT_WT);
26
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg, GEN8_PPAT_UC);
27
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg, GEN8_PPAT_WB);
28
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(5).reg, GEN8_PPAT_WB);
29
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(6).reg, GEN8_PPAT_WB);
30
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(7).reg, GEN8_PPAT_WB);
31
+
}
32
+
33
+
static void pvc_setup_private_ppat(struct xe_gt *gt)
34
+
{
35
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, GEN8_PPAT_UC);
36
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg, GEN8_PPAT_WC);
37
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg, GEN8_PPAT_WT);
38
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg, GEN8_PPAT_WB);
39
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg,
40
+
GEN12_PPAT_CLOS(1) | GEN8_PPAT_WT);
41
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(5).reg,
42
+
GEN12_PPAT_CLOS(1) | GEN8_PPAT_WB);
43
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(6).reg,
44
+
GEN12_PPAT_CLOS(2) | GEN8_PPAT_WT);
45
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(7).reg,
46
+
GEN12_PPAT_CLOS(2) | GEN8_PPAT_WB);
47
+
}
48
+
49
+
#define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)
50
+
#define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)
51
+
#define MTL_PPAT_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3)
52
+
#define MTL_PPAT_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1)
53
+
#define MTL_PPAT_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0)
54
+
#define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3)
55
+
#define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2)
56
+
#define MTL_0_COH_NON REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 0)
57
+
58
+
static void mtl_setup_private_ppat(struct xe_gt *gt)
59
+
{
60
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, MTL_PPAT_0_WB);
61
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg,
62
+
MTL_PPAT_1_WT | MTL_2_COH_1W);
63
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg,
64
+
MTL_PPAT_3_UC | MTL_2_COH_1W);
65
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg,
66
+
MTL_PPAT_0_WB | MTL_2_COH_1W);
67
+
xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg,
68
+
MTL_PPAT_0_WB | MTL_3_COH_2W);
69
+
}
70
+
71
+
void xe_pat_init(struct xe_gt *gt)
72
+
{
73
+
struct xe_device *xe = gt_to_xe(gt);
74
+
75
+
if (xe->info.platform == XE_METEORLAKE)
76
+
mtl_setup_private_ppat(gt);
77
+
else if (xe->info.platform == XE_PVC)
78
+
pvc_setup_private_ppat(gt);
79
+
else
80
+
tgl_setup_private_ppat(gt);
81
+
}