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dt-bindings: clock: renesas,r9a06g032-sysctrl: Convert to json-schema

Convert the Renesas RZ/N1D (R9A06G032) System Controller (SYSCTRL)
Device Tree binding documentation to json-schema.

Drop the consumer example, as it doesn't belong here.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/24d1bd7c4c46747f4e2828974c2e2e48e778bff8.1620119439.git.geert+renesas@glider.be
Signed-off-by: Rob Herring <robh@kernel.org>

authored by

Geert Uytterhoeven and committed by
Rob Herring 57d4ef85 aef65474

+62 -46
-46
Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
··· 1 - * Renesas R9A06G032 SYSCTRL 2 - 3 - Required Properties: 4 - 5 - - compatible: Must be: 6 - - "renesas,r9a06g032-sysctrl" 7 - - reg: Base address and length of the SYSCTRL IO block. 8 - - #clock-cells: Must be 1 9 - - clocks: References to the parent clocks: 10 - - external 40mhz crystal. 11 - - external (optional) 32.768khz 12 - - external (optional) jtag input 13 - - external (optional) RGMII_REFCLK 14 - - clock-names: Must be: 15 - clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; 16 - - #power-domain-cells: Must be 0 17 - 18 - Examples 19 - -------- 20 - 21 - - SYSCTRL node: 22 - 23 - sysctrl: system-controller@4000c000 { 24 - compatible = "renesas,r9a06g032-sysctrl"; 25 - reg = <0x4000c000 0x1000>; 26 - #clock-cells = <1>; 27 - 28 - clocks = <&ext_mclk>, <&ext_rtc_clk>, 29 - <&ext_jtag_clk>, <&ext_rgmii_ref>; 30 - clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; 31 - #power-domain-cells = <0>; 32 - }; 33 - 34 - - Other nodes can use the clocks provided by SYSCTRL as in: 35 - 36 - #include <dt-bindings/clock/r9a06g032-sysctrl.h> 37 - uart0: serial@40060000 { 38 - compatible = "snps,dw-apb-uart"; 39 - reg = <0x40060000 0x400>; 40 - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 41 - reg-shift = <2>; 42 - reg-io-width = <4>; 43 - clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; 44 - clock-names = "baudclk", "apb_pclk"; 45 - power-domains = <&sysctrl>; 46 - };
+62
Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Renesas RZ/N1D (R9A06G032) System Controller 8 + 9 + maintainers: 10 + - Gareth Williams <gareth.williams.jx@renesas.com> 11 + - Geert Uytterhoeven <geert+renesas@glider.be> 12 + 13 + properties: 14 + compatible: 15 + const: renesas,r9a06g032-sysctrl 16 + 17 + reg: 18 + maxItems: 1 19 + 20 + clocks: 21 + minItems: 1 22 + items: 23 + - description: External 40 MHz crystal 24 + - description: Optional external 32.768 kHz crystal 25 + - description: Optional external JTAG input 26 + - description: Optional external RGMII_REFCLK 27 + 28 + clock-names: 29 + minItems: 1 30 + items: 31 + - const: mclk 32 + - const: rtc 33 + - const: jtag 34 + - const: rgmii_ref_ext 35 + 36 + '#clock-cells': 37 + const: 1 38 + 39 + '#power-domain-cells': 40 + const: 0 41 + 42 + required: 43 + - compatible 44 + - reg 45 + - clocks 46 + - clock-names 47 + - '#clock-cells' 48 + - '#power-domain-cells' 49 + 50 + additionalProperties: false 51 + 52 + examples: 53 + - | 54 + sysctrl: system-controller@4000c000 { 55 + compatible = "renesas,r9a06g032-sysctrl"; 56 + reg = <0x4000c000 0x1000>; 57 + clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>, 58 + <&ext_rgmii_ref>; 59 + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; 60 + #clock-cells = <1>; 61 + #power-domain-cells = <0>; 62 + };