Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
i3c: mipi-i3c-hci: Quieten initialization messages
The copious initialization messages are at most useful only for debugging.
Change them from dev_info() or dev_notice() to dev_dbg().
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260106164416.67074-4-adrian.hunter@intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
authored by
Adrian Hunter
and committed by
Alexandre Belloni
581d5b79
0818e4aa
+45
-48
+9
-9
drivers/i3c/master/mipi-i3c-hci/core.c
+9
-9
drivers/i3c/master/mipi-i3c-hci/core.c
···
597
597
hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8;
598
598
if (size_in_dwords)
599
599
hci->DAT_entries = 4 * hci->DAT_entries / hci->DAT_entry_size;
600
-
dev_info(&hci->master.dev, "DAT: %u %u-bytes entries at offset %#x\n",
601
-
hci->DAT_entries, hci->DAT_entry_size, offset);
600
+
dev_dbg(&hci->master.dev, "DAT: %u %u-bytes entries at offset %#x\n",
601
+
hci->DAT_entries, hci->DAT_entry_size, offset);
602
602
603
603
regval = reg_read(DCT_SECTION);
604
604
offset = FIELD_GET(DCT_TABLE_OFFSET, regval);
···
607
607
hci->DCT_entry_size = FIELD_GET(DCT_ENTRY_SIZE, regval) ? 0 : 16;
608
608
if (size_in_dwords)
609
609
hci->DCT_entries = 4 * hci->DCT_entries / hci->DCT_entry_size;
610
-
dev_info(&hci->master.dev, "DCT: %u %u-bytes entries at offset %#x\n",
611
-
hci->DCT_entries, hci->DCT_entry_size, offset);
610
+
dev_dbg(&hci->master.dev, "DCT: %u %u-bytes entries at offset %#x\n",
611
+
hci->DCT_entries, hci->DCT_entry_size, offset);
612
612
613
613
regval = reg_read(RING_HEADERS_SECTION);
614
614
offset = FIELD_GET(RING_HEADERS_OFFSET, regval);
615
615
hci->RHS_regs = offset ? hci->base_regs + offset : NULL;
616
-
dev_info(&hci->master.dev, "Ring Headers at offset %#x\n", offset);
616
+
dev_dbg(&hci->master.dev, "Ring Headers at offset %#x\n", offset);
617
617
618
618
regval = reg_read(PIO_SECTION);
619
619
offset = FIELD_GET(PIO_REGS_OFFSET, regval);
620
620
hci->PIO_regs = offset ? hci->base_regs + offset : NULL;
621
-
dev_info(&hci->master.dev, "PIO section at offset %#x\n", offset);
621
+
dev_dbg(&hci->master.dev, "PIO section at offset %#x\n", offset);
622
622
623
623
regval = reg_read(EXT_CAPS_SECTION);
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offset = FIELD_GET(EXT_CAPS_OFFSET, regval);
625
625
hci->EXTCAPS_regs = offset ? hci->base_regs + offset : NULL;
626
-
dev_info(&hci->master.dev, "Extended Caps at offset %#x\n", offset);
626
+
dev_dbg(&hci->master.dev, "Extended Caps at offset %#x\n", offset);
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628
ret = i3c_hci_parse_ext_caps(hci);
629
629
if (ret)
···
705
705
ret = -EIO;
706
706
} else {
707
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hci->io = &mipi_i3c_hci_dma;
708
-
dev_info(&hci->master.dev, "Using DMA\n");
708
+
dev_dbg(&hci->master.dev, "Using DMA\n");
709
709
}
710
710
}
711
711
···
717
717
ret = -EIO;
718
718
} else {
719
719
hci->io = &mipi_i3c_hci_pio;
720
-
dev_info(&hci->master.dev, "Using PIO\n");
720
+
dev_dbg(&hci->master.dev, "Using PIO\n");
721
721
}
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}
723
723
+2
-2
drivers/i3c/master/mipi-i3c-hci/dma.c
+2
-2
drivers/i3c/master/mipi-i3c-hci/dma.c
···
212
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213
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regval = rhs_reg_read(CONTROL);
214
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nr_rings = FIELD_GET(MAX_HEADER_COUNT_CAP, regval);
215
-
dev_info(&hci->master.dev, "%d DMA rings available\n", nr_rings);
215
+
dev_dbg(&hci->master.dev, "%d DMA rings available\n", nr_rings);
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if (unlikely(nr_rings > 8)) {
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dev_err(&hci->master.dev, "number of rings should be <= 8\n");
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nr_rings = 8;
···
232
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for (i = 0; i < rings->total; i++) {
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u32 offset = rhs_reg_read(RHn_OFFSET(i));
234
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235
-
dev_info(&hci->master.dev, "Ring %d at offset %#x\n", i, offset);
235
+
dev_dbg(&hci->master.dev, "Ring %d at offset %#x\n", i, offset);
236
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ret = -EINVAL;
237
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if (!offset)
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goto err_out;
+26
-29
drivers/i3c/master/mipi-i3c-hci/ext_caps.c
+26
-29
drivers/i3c/master/mipi-i3c-hci/ext_caps.c
···
26
26
hci->vendor_version_id = readl(base + 0x08);
27
27
hci->vendor_product_id = readl(base + 0x0c);
28
28
29
-
dev_info(&hci->master.dev, "vendor MIPI ID: %#x\n", hci->vendor_mipi_id);
30
-
dev_info(&hci->master.dev, "vendor version ID: %#x\n", hci->vendor_version_id);
31
-
dev_info(&hci->master.dev, "vendor product ID: %#x\n", hci->vendor_product_id);
29
+
dev_dbg(&hci->master.dev, "vendor MIPI ID: %#x\n", hci->vendor_mipi_id);
30
+
dev_dbg(&hci->master.dev, "vendor version ID: %#x\n", hci->vendor_version_id);
31
+
dev_dbg(&hci->master.dev, "vendor product ID: %#x\n", hci->vendor_product_id);
32
32
33
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/* ought to go in a table if this grows too much */
34
34
switch (hci->vendor_mipi_id) {
···
48
48
static const char * const functionality[] = {
49
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"(unknown)", "master only", "target only",
50
50
"primary/secondary master" };
51
-
dev_info(&hci->master.dev, "operation mode: %s\n", functionality[operation_mode]);
51
+
dev_dbg(&hci->master.dev, "operation mode: %s\n", functionality[operation_mode]);
52
52
if (operation_mode & 0x1)
53
53
return 0;
54
54
dev_err(&hci->master.dev, "only master mode is currently supported\n");
···
60
60
u32 bus_instance = readl(base + 0x04);
61
61
unsigned int count = FIELD_GET(GENMASK(3, 0), bus_instance);
62
62
63
-
dev_info(&hci->master.dev, "%d bus instances\n", count);
63
+
dev_dbg(&hci->master.dev, "%d bus instances\n", count);
64
64
return 0;
65
65
}
66
66
···
70
70
u32 entries = FIELD_GET(CAP_HEADER_LENGTH, header) - 1;
71
71
unsigned int index;
72
72
73
-
dev_info(&hci->master.dev, "transfer mode table has %d entries\n",
74
-
entries);
73
+
dev_dbg(&hci->master.dev, "transfer mode table has %d entries\n", entries);
75
74
base += 4; /* skip header */
76
75
for (index = 0; index < entries; index++) {
77
76
u32 mode_entry = readl(base);
···
93
94
94
95
base += 4; /* skip header */
95
96
96
-
dev_info(&hci->master.dev, "available data rates:\n");
97
+
dev_dbg(&hci->master.dev, "available data rates:\n");
97
98
for (index = 0; index < entries; index++) {
98
99
rate_entry = readl(base);
99
100
dev_dbg(&hci->master.dev, "entry %d: 0x%08x",
···
101
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rate = FIELD_GET(XFERRATE_ACTUAL_RATE_KHZ, rate_entry);
102
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rate_id = FIELD_GET(XFERRATE_RATE_ID, rate_entry);
103
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mode_id = FIELD_GET(XFERRATE_MODE_ID, rate_entry);
104
-
dev_info(&hci->master.dev, "rate %d for %s = %d kHz\n",
105
-
rate_id,
106
-
mode_id == XFERRATE_MODE_I3C ? "I3C" :
107
-
mode_id == XFERRATE_MODE_I2C ? "I2C" :
108
-
"unknown mode",
109
-
rate);
105
+
dev_dbg(&hci->master.dev, "rate %d for %s = %d kHz\n",
106
+
rate_id,
107
+
mode_id == XFERRATE_MODE_I3C ? "I3C" :
108
+
mode_id == XFERRATE_MODE_I2C ? "I2C" :
109
+
"unknown mode",
110
+
rate);
110
111
base += 4;
111
112
}
112
113
···
120
121
u32 autocmd_ext_config = readl(base + 0x08);
121
122
unsigned int count = FIELD_GET(GENMASK(3, 0), autocmd_ext_config);
122
123
123
-
dev_info(&hci->master.dev, "%d/%d active auto-command entries\n",
124
-
count, max_count);
124
+
dev_dbg(&hci->master.dev, "%d/%d active auto-command entries\n",
125
+
count, max_count);
125
126
/* remember auto-command register location for later use */
126
127
hci->AUTOCMD_regs = base;
127
128
return 0;
···
129
130
130
131
static int hci_extcap_debug(struct i3c_hci *hci, void __iomem *base)
131
132
{
132
-
dev_info(&hci->master.dev, "debug registers present\n");
133
+
dev_dbg(&hci->master.dev, "debug registers present\n");
133
134
hci->DEBUG_regs = base;
134
135
return 0;
135
136
}
136
137
137
138
static int hci_extcap_scheduled_cmd(struct i3c_hci *hci, void __iomem *base)
138
139
{
139
-
dev_info(&hci->master.dev, "scheduled commands available\n");
140
+
dev_dbg(&hci->master.dev, "scheduled commands available\n");
140
141
/* hci->schedcmd_regs = base; */
141
142
return 0;
142
143
}
143
144
144
145
static int hci_extcap_non_curr_master(struct i3c_hci *hci, void __iomem *base)
145
146
{
146
-
dev_info(&hci->master.dev, "Non-Current Master support available\n");
147
+
dev_dbg(&hci->master.dev, "Non-Current Master support available\n");
147
148
/* hci->NCM_regs = base; */
148
149
return 0;
149
150
}
150
151
151
152
static int hci_extcap_ccc_resp_conf(struct i3c_hci *hci, void __iomem *base)
152
153
{
153
-
dev_info(&hci->master.dev, "CCC Response Configuration available\n");
154
+
dev_dbg(&hci->master.dev, "CCC Response Configuration available\n");
154
155
return 0;
155
156
}
156
157
157
158
static int hci_extcap_global_DAT(struct i3c_hci *hci, void __iomem *base)
158
159
{
159
-
dev_info(&hci->master.dev, "Global DAT available\n");
160
+
dev_dbg(&hci->master.dev, "Global DAT available\n");
160
161
return 0;
161
162
}
162
163
163
164
static int hci_extcap_multilane(struct i3c_hci *hci, void __iomem *base)
164
165
{
165
-
dev_info(&hci->master.dev, "Master Multi-Lane support available\n");
166
+
dev_dbg(&hci->master.dev, "Master Multi-Lane support available\n");
166
167
return 0;
167
168
}
168
169
169
170
static int hci_extcap_ncm_multilane(struct i3c_hci *hci, void __iomem *base)
170
171
{
171
-
dev_info(&hci->master.dev, "NCM Multi-Lane support available\n");
172
+
dev_dbg(&hci->master.dev, "NCM Multi-Lane support available\n");
172
173
return 0;
173
174
}
174
175
···
201
202
static int hci_extcap_vendor_NXP(struct i3c_hci *hci, void __iomem *base)
202
203
{
203
204
hci->vendor_data = (__force void *)base;
204
-
dev_info(&hci->master.dev, "Build Date Info = %#x\n", readl(base + 1*4));
205
+
dev_dbg(&hci->master.dev, "Build Date Info = %#x\n", readl(base + 1 * 4));
205
206
/* reset the FPGA */
206
207
writel(0xdeadbeef, base + 1*4);
207
208
return 0;
···
239
240
}
240
241
241
242
if (!vendor_cap_entry) {
242
-
dev_notice(&hci->master.dev,
243
-
"unknown ext_cap 0x%02x for vendor 0x%02x\n",
244
-
cap_id, hci->vendor_mipi_id);
243
+
dev_dbg(&hci->master.dev, "unknown ext_cap 0x%02x for vendor 0x%02x\n",
244
+
cap_id, hci->vendor_mipi_id);
245
245
return 0;
246
246
}
247
247
if (cap_length < vendor_cap_entry->min_length) {
···
293
295
}
294
296
}
295
297
if (!cap_entry) {
296
-
dev_notice(&hci->master.dev,
297
-
"unknown ext_cap 0x%02x\n", cap_id);
298
+
dev_dbg(&hci->master.dev, "unknown ext_cap 0x%02x\n", cap_id);
298
299
} else if (cap_length < cap_entry->min_length) {
299
300
dev_err(&hci->master.dev,
300
301
"ext_cap 0x%02x has size %d (expecting >= %d)\n",
+8
-8
drivers/i3c/master/mipi-i3c-hci/pio.c
+8
-8
drivers/i3c/master/mipi-i3c-hci/pio.c
···
148
148
spin_lock_init(&pio->lock);
149
149
150
150
size_val = pio_reg_read(QUEUE_SIZE);
151
-
dev_info(&hci->master.dev, "CMD/RESP FIFO = %ld entries\n",
152
-
FIELD_GET(CR_QUEUE_SIZE, size_val));
153
-
dev_info(&hci->master.dev, "IBI FIFO = %ld bytes\n",
154
-
4 * FIELD_GET(IBI_STATUS_SIZE, size_val));
155
-
dev_info(&hci->master.dev, "RX data FIFO = %d bytes\n",
156
-
4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val)));
157
-
dev_info(&hci->master.dev, "TX data FIFO = %d bytes\n",
158
-
4 * (2 << FIELD_GET(TX_DATA_BUFFER_SIZE, size_val)));
151
+
dev_dbg(&hci->master.dev, "CMD/RESP FIFO = %ld entries\n",
152
+
FIELD_GET(CR_QUEUE_SIZE, size_val));
153
+
dev_dbg(&hci->master.dev, "IBI FIFO = %ld bytes\n",
154
+
4 * FIELD_GET(IBI_STATUS_SIZE, size_val));
155
+
dev_dbg(&hci->master.dev, "RX data FIFO = %d bytes\n",
156
+
4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val)));
157
+
dev_dbg(&hci->master.dev, "TX data FIFO = %d bytes\n",
158
+
4 * (2 << FIELD_GET(TX_DATA_BUFFER_SIZE, size_val)));
159
159
160
160
/*
161
161
* Let's initialize data thresholds to half of the actual FIFO size.