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perf vendor events: Update TigerLake events

Update events from v1.17 to v1.18.

Bring in the event updates v1.18:
https://github.com/intel/perfmon/commit/943fea37d0d54232605f12abf72a812ac314cd1d

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Link: https://lore.kernel.org/r/20250630163101.1920170-16-irogers@google.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>

authored by

Ian Rogers and committed by
Namhyung Kim
58518933 80c6b822

+2 -2
+1 -1
tools/perf/pmu-events/arch/x86/mapfile.csv
··· 35 35 GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core 36 36 GenuineIntel-6-55-[01234],v1.37,skylakex,core 37 37 GenuineIntel-6-86,v1.23,snowridgex,core 38 - GenuineIntel-6-8[CD],v1.17,tigerlake,core 38 + GenuineIntel-6-8[CD],v1.18,tigerlake,core 39 39 GenuineIntel-6-2C,v5,westmereep-dp,core 40 40 GenuineIntel-6-25,v4,westmereep-sp,core 41 41 GenuineIntel-6-2F,v4,westmereex,core
+1 -1
tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
··· 497 497 "Counter": "0,1,2,3", 498 498 "EventCode": "0x4c", 499 499 "EventName": "LOAD_HIT_PREFETCH.SWPF", 500 - "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", 500 + "PublicDescription": "Counts all software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", 501 501 "SampleAfterValue": "100003", 502 502 "UMask": "0x1" 503 503 },