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riscv: Flush the instruction cache during SMP bringup

Instruction cache flush IPIs are sent only to CPUs in cpu_online_mask,
so they will not target a CPU until it calls set_cpu_online() earlier in
smp_callin(). As a result, if instruction memory is modified between the
CPU coming out of reset and that point, then its instruction cache may
contain stale data. Therefore, the instruction cache must be flushed
after the set_cpu_online() synchronization point.

Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable")
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20240327045035.368512-2-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

authored by

Samuel Holland and committed by
Palmer Dabbelt 58661a30 4cece764

+4 -3
+4 -3
arch/riscv/kernel/smpboot.c
··· 26 26 #include <linux/sched/task_stack.h> 27 27 #include <linux/sched/mm.h> 28 28 29 - #include <asm/cpufeature.h> 29 + #include <asm/cacheflush.h> 30 30 #include <asm/cpu_ops.h> 31 31 #include <asm/irq.h> 32 32 #include <asm/mmu_context.h> ··· 234 234 riscv_user_isa_enable(); 235 235 236 236 /* 237 - * Remote TLB flushes are ignored while the CPU is offline, so emit 238 - * a local TLB flush right now just in case. 237 + * Remote cache and TLB flushes are ignored while the CPU is offline, 238 + * so flush them both right now just in case. 239 239 */ 240 + local_flush_icache_all(); 240 241 local_flush_tlb_all(); 241 242 complete(&cpu_running); 242 243 /*