Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.15-rc7' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Just collecting some fixes to finish my hoildays :-).
A few fixes for i915 (one documentation build fix), one ttm fix, one
AMD display fix, one omapdrm fix, and a set of armada fixes from
Russell.
All seem pretty small, you can now return to your latest security news
site"
* tag 'drm-fixes-for-v4.15-rc7' of git://people.freedesktop.org/~airlied/linux:
drm/i915: Apply Display WA #1183 on skl, kbl, and cfl
drm/ttm: check the return value of kzalloc
drm/amd/display: call set csc_default if enable adjustment is false
docs: fix, intel_guc_loader.c has been moved to intel_guc_fw.c
omapdrm/dss/hdmi4_cec: fix interrupt handling
documentation/gpu/i915: fix docs build error after file rename
drm/i915: Put all non-blocking modesets onto an ordered wq
drm/i915: Disable DC states around GMBUS on GLK
drm/i915/psr: Fix register name mess up.
drm/armada: fix YUV planar format framebuffer offsets
drm/armada: improve efficiency of armada_drm_plane_calc_addrs()
drm/armada: fix UV swap code
drm/armada: fix SRAM powerdown
drm/armada: fix leak of crtc structure
+127
-106
+1
-4
Documentation/gpu/i915.rst
+1
-4
Documentation/gpu/i915.rst
···
341
341
GuC-specific firmware loader
342
342
----------------------------
343
343
344
-
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c
345
-
:doc: GuC-specific firmware loader
346
-
347
-
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c
344
+
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c
348
345
:internal:
349
346
350
347
GuC-based command submission
+1
-1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+1
-1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+2
-4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+2
-4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
···
225
225
226
226
void dpp1_cm_set_output_csc_default(
227
227
struct dpp *dpp_base,
228
-
const struct default_adjustment *default_adjust)
228
+
enum dc_color_space colorspace)
229
229
{
230
230
231
231
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
232
232
uint32_t ocsc_mode = 0;
233
233
234
-
if (default_adjust != NULL) {
235
-
switch (default_adjust->out_color_space) {
234
+
switch (colorspace) {
236
235
case COLOR_SPACE_SRGB:
237
236
case COLOR_SPACE_2020_RGB_FULLRANGE:
238
237
ocsc_mode = 0;
···
252
253
case COLOR_SPACE_UNKNOWN:
253
254
default:
254
255
break;
255
-
}
256
256
}
257
257
258
258
REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
+2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
···
2097
2097
tbl_entry.color_space = color_space;
2098
2098
//tbl_entry.regval = matrix;
2099
2099
pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);
2100
+
} else {
2101
+
pipe_ctx->plane_res.dpp->funcs->opp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
2100
2102
}
2101
2103
}
2102
2104
static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+1
-1
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+1
-1
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+27
-20
drivers/gpu/drm/armada/armada_crtc.c
+27
-20
drivers/gpu/drm/armada/armada_crtc.c
···
168
168
void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
169
169
int x, int y)
170
170
{
171
+
const struct drm_format_info *format = fb->format;
172
+
unsigned int num_planes = format->num_planes;
171
173
u32 addr = drm_fb_obj(fb)->dev_addr;
172
-
int num_planes = fb->format->num_planes;
173
174
int i;
174
175
175
176
if (num_planes > 3)
176
177
num_planes = 3;
177
178
178
-
for (i = 0; i < num_planes; i++)
179
+
addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] +
180
+
x * format->cpp[0];
181
+
182
+
y /= format->vsub;
183
+
x /= format->hsub;
184
+
185
+
for (i = 1; i < num_planes; i++)
179
186
addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
180
-
x * fb->format->cpp[i];
187
+
x * format->cpp[i];
181
188
for (; i < 3; i++)
182
189
addrs[i] = 0;
183
190
}
···
751
744
if (plane->fb)
752
745
drm_framebuffer_put(plane->fb);
753
746
754
-
/* Power down the Y/U/V FIFOs */
755
-
sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
756
-
757
747
/* Power down most RAMs and FIFOs if this is the primary plane */
758
748
if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
759
-
sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
760
-
CFG_PDWN32x32 | CFG_PDWN64x66;
749
+
sram_para1 = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
750
+
CFG_PDWN32x32 | CFG_PDWN64x66;
761
751
dma_ctrl0_mask = CFG_GRA_ENA;
762
752
} else {
753
+
/* Power down the Y/U/V FIFOs */
754
+
sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
763
755
dma_ctrl0_mask = CFG_DMA_ENA;
764
756
}
765
757
···
1231
1225
1232
1226
ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1233
1227
dcrtc);
1234
-
if (ret < 0) {
1235
-
kfree(dcrtc);
1236
-
return ret;
1237
-
}
1228
+
if (ret < 0)
1229
+
goto err_crtc;
1238
1230
1239
1231
if (dcrtc->variant->init) {
1240
1232
ret = dcrtc->variant->init(dcrtc, dev);
1241
-
if (ret) {
1242
-
kfree(dcrtc);
1243
-
return ret;
1244
-
}
1233
+
if (ret)
1234
+
goto err_crtc;
1245
1235
}
1246
1236
1247
1237
/* Ensure AXI pipeline is enabled */
···
1248
1246
dcrtc->crtc.port = port;
1249
1247
1250
1248
primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1251
-
if (!primary)
1252
-
return -ENOMEM;
1249
+
if (!primary) {
1250
+
ret = -ENOMEM;
1251
+
goto err_crtc;
1252
+
}
1253
1253
1254
1254
ret = armada_drm_plane_init(primary);
1255
1255
if (ret) {
1256
1256
kfree(primary);
1257
-
return ret;
1257
+
goto err_crtc;
1258
1258
}
1259
1259
1260
1260
ret = drm_universal_plane_init(drm, &primary->base, 0,
···
1267
1263
DRM_PLANE_TYPE_PRIMARY, NULL);
1268
1264
if (ret) {
1269
1265
kfree(primary);
1270
-
return ret;
1266
+
goto err_crtc;
1271
1267
}
1272
1268
1273
1269
ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
···
1286
1282
1287
1283
err_crtc_init:
1288
1284
primary->base.funcs->destroy(&primary->base);
1285
+
err_crtc:
1286
+
kfree(dcrtc);
1287
+
1289
1288
return ret;
1290
1289
}
1291
1290
+2
drivers/gpu/drm/armada/armada_crtc.h
+2
drivers/gpu/drm/armada/armada_crtc.h
+19
-19
drivers/gpu/drm/armada/armada_overlay.c
+19
-19
drivers/gpu/drm/armada/armada_overlay.c
···
99
99
{
100
100
struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
101
101
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
102
+
const struct drm_format_info *format;
102
103
struct drm_rect src = {
103
104
.x1 = src_x,
104
105
.y1 = src_y,
···
118
117
};
119
118
uint32_t val, ctrl0;
120
119
unsigned idx = 0;
121
-
bool visible;
120
+
bool visible, fb_changed;
122
121
int ret;
123
122
124
123
trace_armada_ovl_plane_update(plane, crtc, fb,
···
139
138
if (!visible)
140
139
ctrl0 &= ~CFG_DMA_ENA;
141
140
141
+
/*
142
+
* Shifting a YUV packed format image by one pixel causes the U/V
143
+
* planes to swap. Compensate for it by also toggling the UV swap.
144
+
*/
145
+
format = fb->format;
146
+
if (format->num_planes == 1 && src.x1 >> 16 & (format->hsub - 1))
147
+
ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
148
+
149
+
fb_changed = plane->fb != fb ||
150
+
dplane->base.state.src_x != src.x1 >> 16 ||
151
+
dplane->base.state.src_y != src.y1 >> 16;
152
+
142
153
if (!dcrtc->plane) {
143
154
dcrtc->plane = plane;
144
155
armada_ovl_update_attr(&dplane->prop, dcrtc);
···
158
145
159
146
/* FIXME: overlay on an interlaced display */
160
147
/* Just updating the position/size? */
161
-
if (plane->fb == fb && dplane->base.state.ctrl0 == ctrl0) {
148
+
if (!fb_changed && dplane->base.state.ctrl0 == ctrl0) {
162
149
val = (drm_rect_height(&src) & 0xffff0000) |
163
150
drm_rect_width(&src) >> 16;
164
151
dplane->base.state.src_hw = val;
···
182
169
if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0)
183
170
armada_drm_plane_work_cancel(dcrtc, &dplane->base);
184
171
185
-
if (plane->fb != fb) {
186
-
u32 addrs[3], pixel_format;
187
-
int num_planes, hsub;
172
+
if (fb_changed) {
173
+
u32 addrs[3];
188
174
189
175
/*
190
176
* Take a reference on the new framebuffer - we want to
···
194
182
if (plane->fb)
195
183
armada_ovl_retire_fb(dplane, plane->fb);
196
184
197
-
src_y = src.y1 >> 16;
198
-
src_x = src.x1 >> 16;
185
+
dplane->base.state.src_y = src_y = src.y1 >> 16;
186
+
dplane->base.state.src_x = src_x = src.x1 >> 16;
199
187
200
188
armada_drm_plane_calc_addrs(addrs, fb, src_x, src_y);
201
-
202
-
pixel_format = fb->format->format;
203
-
hsub = drm_format_horz_chroma_subsampling(pixel_format);
204
-
num_planes = fb->format->num_planes;
205
-
206
-
/*
207
-
* Annoyingly, shifting a YUYV-format image by one pixel
208
-
* causes the U/V planes to toggle. Toggle the UV swap.
209
-
* (Unfortunately, this causes momentary colour flickering.)
210
-
*/
211
-
if (src_x & (hsub - 1) && num_planes == 1)
212
-
ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
213
189
214
190
armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0],
215
191
LCD_SPU_DMA_START_ADDR_Y0);
+3
drivers/gpu/drm/i915/i915_drv.h
+3
drivers/gpu/drm/i915/i915_drv.h
+2
drivers/gpu/drm/i915/i915_reg.h
+2
drivers/gpu/drm/i915/i915_reg.h
···
6977
6977
#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
6978
6978
6979
6979
#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
6980
+
#define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30)
6980
6981
#define MASK_WAKEMEM (1<<13)
6981
6982
6982
6983
#define SKL_DFSM _MMIO(0x51000)
···
8523
8522
#define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
8524
8523
#define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
8525
8524
#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
8525
+
#define CDCLK_DIVMUX_CD_OVERRIDE (1<<19)
8526
8526
#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
8527
8527
#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
8528
8528
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
+26
-9
drivers/gpu/drm/i915/intel_cdclk.c
+26
-9
drivers/gpu/drm/i915/intel_cdclk.c
···
860
860
861
861
static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
862
862
{
863
-
int min_cdclk = skl_calc_cdclk(0, vco);
864
863
u32 val;
865
864
866
865
WARN_ON(vco != 8100000 && vco != 8640000);
867
-
868
-
/* select the minimum CDCLK before enabling DPLL 0 */
869
-
val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
870
-
I915_WRITE(CDCLK_CTL, val);
871
-
POSTING_READ(CDCLK_CTL);
872
866
873
867
/*
874
868
* We always enable DPLL0 with the lowest link rate possible, but still
···
917
923
{
918
924
int cdclk = cdclk_state->cdclk;
919
925
int vco = cdclk_state->vco;
920
-
u32 freq_select, pcu_ack;
926
+
u32 freq_select, pcu_ack, cdclk_ctl;
921
927
int ret;
922
928
923
929
WARN_ON((cdclk == 24000) != (vco == 0));
···
934
940
return;
935
941
}
936
942
937
-
/* set CDCLK_CTL */
943
+
/* Choose frequency for this cdclk */
938
944
switch (cdclk) {
939
945
case 450000:
940
946
case 432000:
···
962
968
dev_priv->cdclk.hw.vco != vco)
963
969
skl_dpll0_disable(dev_priv);
964
970
971
+
cdclk_ctl = I915_READ(CDCLK_CTL);
972
+
973
+
if (dev_priv->cdclk.hw.vco != vco) {
974
+
/* Wa Display #1183: skl,kbl,cfl */
975
+
cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
976
+
cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
977
+
I915_WRITE(CDCLK_CTL, cdclk_ctl);
978
+
}
979
+
980
+
/* Wa Display #1183: skl,kbl,cfl */
981
+
cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
982
+
I915_WRITE(CDCLK_CTL, cdclk_ctl);
983
+
POSTING_READ(CDCLK_CTL);
984
+
965
985
if (dev_priv->cdclk.hw.vco != vco)
966
986
skl_dpll0_enable(dev_priv, vco);
967
987
968
-
I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
988
+
/* Wa Display #1183: skl,kbl,cfl */
989
+
cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
990
+
I915_WRITE(CDCLK_CTL, cdclk_ctl);
991
+
992
+
cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
993
+
I915_WRITE(CDCLK_CTL, cdclk_ctl);
994
+
995
+
/* Wa Display #1183: skl,kbl,cfl */
996
+
cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
997
+
I915_WRITE(CDCLK_CTL, cdclk_ctl);
969
998
POSTING_READ(CDCLK_CTL);
970
999
971
1000
/* inform PCU of the change */
+11
-3
drivers/gpu/drm/i915/intel_display.c
+11
-3
drivers/gpu/drm/i915/intel_display.c
···
12544
12544
INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12545
12545
12546
12546
i915_sw_fence_commit(&intel_state->commit_ready);
12547
-
if (nonblock)
12547
+
if (nonblock && intel_state->modeset) {
12548
+
queue_work(dev_priv->modeset_wq, &state->commit_work);
12549
+
} else if (nonblock) {
12548
12550
queue_work(system_unbound_wq, &state->commit_work);
12549
-
else
12551
+
} else {
12552
+
if (intel_state->modeset)
12553
+
flush_workqueue(dev_priv->modeset_wq);
12550
12554
intel_atomic_commit_tail(state);
12551
-
12555
+
}
12552
12556
12553
12557
return 0;
12554
12558
}
···
14466
14462
enum pipe pipe;
14467
14463
struct intel_crtc *crtc;
14468
14464
14465
+
dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
14466
+
14469
14467
drm_mode_config_init(dev);
14470
14468
14471
14469
dev->mode_config.min_width = 0;
···
15276
15270
intel_cleanup_gt_powersave(dev_priv);
15277
15271
15278
15272
intel_teardown_gmbus(dev_priv);
15273
+
15274
+
destroy_workqueue(dev_priv->modeset_wq);
15279
15275
}
15280
15276
15281
15277
void intel_connector_attach_encoder(struct intel_connector *connector,
+8
-8
drivers/gpu/drm/i915/intel_psr.c
+8
-8
drivers/gpu/drm/i915/intel_psr.c
···
590
590
struct drm_i915_private *dev_priv = to_i915(dev);
591
591
592
592
if (dev_priv->psr.active) {
593
-
i915_reg_t psr_ctl;
593
+
i915_reg_t psr_status;
594
594
u32 psr_status_mask;
595
595
596
596
if (dev_priv->psr.aux_frame_sync)
···
599
599
0);
600
600
601
601
if (dev_priv->psr.psr2_support) {
602
-
psr_ctl = EDP_PSR2_CTL;
602
+
psr_status = EDP_PSR2_STATUS_CTL;
603
603
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
604
604
605
-
I915_WRITE(psr_ctl,
606
-
I915_READ(psr_ctl) &
605
+
I915_WRITE(EDP_PSR2_CTL,
606
+
I915_READ(EDP_PSR2_CTL) &
607
607
~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
608
608
609
609
} else {
610
-
psr_ctl = EDP_PSR_STATUS_CTL;
610
+
psr_status = EDP_PSR_STATUS_CTL;
611
611
psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
612
612
613
-
I915_WRITE(psr_ctl,
614
-
I915_READ(psr_ctl) & ~EDP_PSR_ENABLE);
613
+
I915_WRITE(EDP_PSR_CTL,
614
+
I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
615
615
}
616
616
617
617
/* Wait till PSR is idle */
618
618
if (intel_wait_for_register(dev_priv,
619
-
psr_ctl, psr_status_mask, 0,
619
+
psr_status, psr_status_mask, 0,
620
620
2000))
621
621
DRM_ERROR("Timed out waiting for PSR Idle State\n");
622
622
+11
drivers/gpu/drm/i915/intel_runtime_pm.c
+11
drivers/gpu/drm/i915/intel_runtime_pm.c
···
598
598
599
599
DRM_DEBUG_KMS("Enabling DC5\n");
600
600
601
+
/* Wa Display #1183: skl,kbl,cfl */
602
+
if (IS_GEN9_BC(dev_priv))
603
+
I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
604
+
SKL_SELECT_ALTERNATE_DC_EXIT);
605
+
601
606
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
602
607
}
603
608
···
629
624
void skl_disable_dc6(struct drm_i915_private *dev_priv)
630
625
{
631
626
DRM_DEBUG_KMS("Disabling DC6\n");
627
+
628
+
/* Wa Display #1183: skl,kbl,cfl */
629
+
if (IS_GEN9_BC(dev_priv))
630
+
I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
631
+
SKL_SELECT_ALTERNATE_DC_EXIT);
632
632
633
633
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
634
634
}
···
1796
1786
GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
1797
1787
BIT_ULL(POWER_DOMAIN_MODESET) | \
1798
1788
BIT_ULL(POWER_DOMAIN_AUX_A) | \
1789
+
BIT_ULL(POWER_DOMAIN_GMBUS) | \
1799
1790
BIT_ULL(POWER_DOMAIN_INIT))
1800
1791
1801
1792
#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
+9
-37
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
+9
-37
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
···
78
78
79
79
/* then read the message */
80
80
msg.len = cnt & 0xf;
81
+
if (msg.len > CEC_MAX_MSG_SIZE - 2)
82
+
msg.len = CEC_MAX_MSG_SIZE - 2;
81
83
msg.msg[0] = hdmi_read_reg(core->base,
82
84
HDMI_CEC_RX_CMD_HEADER);
83
85
msg.msg[1] = hdmi_read_reg(core->base,
···
106
104
}
107
105
}
108
106
109
-
static void hdmi_cec_transmit_fifo_empty(struct hdmi_core_data *core, u32 stat1)
110
-
{
111
-
if (stat1 & 2) {
112
-
u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
113
-
114
-
cec_transmit_done(core->adap,
115
-
CEC_TX_STATUS_NACK |
116
-
CEC_TX_STATUS_MAX_RETRIES,
117
-
0, (dbg3 >> 4) & 7, 0, 0);
118
-
} else if (stat1 & 1) {
119
-
cec_transmit_done(core->adap,
120
-
CEC_TX_STATUS_ARB_LOST |
121
-
CEC_TX_STATUS_MAX_RETRIES,
122
-
0, 0, 0, 0);
123
-
} else if (stat1 == 0) {
124
-
cec_transmit_done(core->adap, CEC_TX_STATUS_OK,
125
-
0, 0, 0, 0);
126
-
}
127
-
}
128
-
129
107
void hdmi4_cec_irq(struct hdmi_core_data *core)
130
108
{
131
109
u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0);
···
114
132
hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, stat0);
115
133
hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, stat1);
116
134
117
-
if (stat0 & 0x40)
135
+
if (stat0 & 0x20) {
136
+
cec_transmit_done(core->adap, CEC_TX_STATUS_OK,
137
+
0, 0, 0, 0);
118
138
REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
119
-
else if (stat0 & 0x24)
120
-
hdmi_cec_transmit_fifo_empty(core, stat1);
121
-
if (stat1 & 2) {
139
+
} else if (stat1 & 0x02) {
122
140
u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
123
141
124
142
cec_transmit_done(core->adap,
125
143
CEC_TX_STATUS_NACK |
126
144
CEC_TX_STATUS_MAX_RETRIES,
127
145
0, (dbg3 >> 4) & 7, 0, 0);
128
-
} else if (stat1 & 1) {
129
-
cec_transmit_done(core->adap,
130
-
CEC_TX_STATUS_ARB_LOST |
131
-
CEC_TX_STATUS_MAX_RETRIES,
132
-
0, 0, 0, 0);
146
+
REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
133
147
}
134
148
if (stat0 & 0x02)
135
149
hdmi_cec_received_msg(core);
136
-
if (stat1 & 0x3)
137
-
REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
138
150
}
139
151
140
152
static bool hdmi_cec_clear_tx_fifo(struct cec_adapter *adap)
···
207
231
/*
208
232
* Enable CEC interrupts:
209
233
* Transmit Buffer Full/Empty Change event
210
-
* Transmitter FIFO Empty event
211
234
* Receiver FIFO Not Empty event
212
235
*/
213
-
hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x26);
236
+
hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x22);
214
237
/*
215
238
* Enable CEC interrupts:
216
-
* RX FIFO Overrun Error event
217
-
* Short Pulse Detected event
218
239
* Frame Retransmit Count Exceeded event
219
-
* Start Bit Irregularity event
220
240
*/
221
-
hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x0f);
241
+
hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x02);
222
242
223
243
/* cec calibration enable (self clearing) */
224
244
hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x03);
+2
drivers/gpu/drm/ttm/ttm_page_alloc.c
+2
drivers/gpu/drm/ttm/ttm_page_alloc.c