Merge tag 'spi-fix-v6.18-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

+8 -3

Documentation/devicetree/bindings/spi/spi-cadence.yaml

··· 14 14 15 15 properties: 16 16 compatible: 17 - enum: 18 - - cdns,spi-r1p6 19 - - xlnx,zynq-spi-r1p6 17 + oneOf: 18 + - enum: 19 + - xlnx,zynq-spi-r1p6 20 + - items: 21 + - enum: 22 + - xlnx,zynqmp-spi-r1p6 23 + - xlnx,versal-net-spi-r1p6 24 + - const: cdns,spi-r1p6 20 25 21 26 reg: 22 27 maxItems: 1

+1

Documentation/devicetree/bindings/spi/spi-rockchip.yaml

··· 34 34 - rockchip,rk3328-spi 35 35 - rockchip,rk3368-spi 36 36 - rockchip,rk3399-spi 37 + - rockchip,rk3506-spi 37 38 - rockchip,rk3528-spi 38 39 - rockchip,rk3562-spi 39 40 - rockchip,rk3568-spi

+97 -31

drivers/spi/spi-airoha-snfi.c

··· 192 192 #define SPI_NAND_OP_RESET 0xff 193 193 #define SPI_NAND_OP_DIE_SELECT 0xc2 194 194 195 + /* SNAND FIFO commands */ 196 + #define SNAND_FIFO_TX_BUSWIDTH_SINGLE 0x08 197 + #define SNAND_FIFO_TX_BUSWIDTH_DUAL 0x09 198 + #define SNAND_FIFO_TX_BUSWIDTH_QUAD 0x0a 199 + #define SNAND_FIFO_RX_BUSWIDTH_SINGLE 0x0c 200 + #define SNAND_FIFO_RX_BUSWIDTH_DUAL 0x0e 201 + #define SNAND_FIFO_RX_BUSWIDTH_QUAD 0x0f 202 + 195 203 #define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256) 196 204 #define SPI_MAX_TRANSFER_SIZE 511 197 205 ··· 395 387 return regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0); 396 388 } 397 389 398 - static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd, 399 - const u8 *data, int len) 390 + static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, 391 + const u8 *data, int len, int buswidth) 400 392 { 401 393 int i, data_len; 394 + u8 cmd; 395 + 396 + switch (buswidth) { 397 + case 0: 398 + case 1: 399 + cmd = SNAND_FIFO_TX_BUSWIDTH_SINGLE; 400 + break; 401 + case 2: 402 + cmd = SNAND_FIFO_TX_BUSWIDTH_DUAL; 403 + break; 404 + case 4: 405 + cmd = SNAND_FIFO_TX_BUSWIDTH_QUAD; 406 + break; 407 + default: 408 + return -EINVAL; 409 + } 402 410 403 411 for (i = 0; i < len; i += data_len) { 404 412 int err; ··· 433 409 return 0; 434 410 } 435 411 436 - static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data, 437 - int len) 412 + static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, 413 + u8 *data, int len, int buswidth) 438 414 { 439 415 int i, data_len; 416 + u8 cmd; 417 + 418 + switch (buswidth) { 419 + case 0: 420 + case 1: 421 + cmd = SNAND_FIFO_RX_BUSWIDTH_SINGLE; 422 + break; 423 + case 2: 424 + cmd = SNAND_FIFO_RX_BUSWIDTH_DUAL; 425 + break; 426 + case 4: 427 + cmd = SNAND_FIFO_RX_BUSWIDTH_QUAD; 428 + break; 429 + default: 430 + return -EINVAL; 431 + } 440 432 441 433 for (i = 0; i < len; i += data_len) { 442 434 int err; 443 435 444 436 data_len = min(len - i, SPI_MAX_TRANSFER_SIZE); 445 - err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len); 437 + err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len); 446 438 if (err) 447 439 return err; 448 440 ··· 658 618 if (desc->info.offset + desc->info.length > U32_MAX) 659 619 return -EINVAL; 660 620 621 + /* continuous reading is not supported */ 622 + if (desc->info.length > SPI_NAND_CACHE_SIZE) 623 + return -E2BIG; 624 + 661 625 if (!airoha_snand_supports_op(desc->mem, &desc->info.op_tmpl)) 662 626 return -EOPNOTSUPP; 663 627 ··· 698 654 699 655 err = airoha_snand_nfi_config(as_ctrl); 700 656 if (err) 701 - return err; 657 + goto error_dma_mode_off; 702 658 703 659 dma_addr = dma_map_single(as_ctrl->dev, txrx_buf, SPI_NAND_CACHE_SIZE, 704 660 DMA_FROM_DEVICE); 705 661 err = dma_mapping_error(as_ctrl->dev, dma_addr); 706 662 if (err) 707 - return err; 663 + goto error_dma_mode_off; 708 664 709 665 /* set dma addr */ 710 666 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR, ··· 733 689 if (err) 734 690 goto error_dma_unmap; 735 691 736 - /* set read addr */ 737 - err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 0x0); 692 + /* set read addr: zero page offset + descriptor read offset */ 693 + err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 694 + desc->info.offset); 738 695 if (err) 739 696 goto error_dma_unmap; 740 697 ··· 805 760 error_dma_unmap: 806 761 dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE, 807 762 DMA_FROM_DEVICE); 763 + error_dma_mode_off: 764 + airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL); 808 765 return err; 809 766 } 810 767 ··· 871 824 if (err) 872 825 goto error_dma_unmap; 873 826 874 - err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 0x0); 827 + /* set write addr: zero page offset + descriptor write offset */ 828 + err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 829 + desc->info.offset); 875 830 if (err) 876 831 goto error_dma_unmap; 877 832 ··· 941 892 error_dma_unmap: 942 893 dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE, 943 894 DMA_TO_DEVICE); 895 + airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL); 944 896 return err; 945 897 } 946 898 947 899 static int airoha_snand_exec_op(struct spi_mem *mem, 948 900 const struct spi_mem_op *op) 949 901 { 950 - u8 data[8], cmd, opcode = op->cmd.opcode; 951 902 struct airoha_snand_ctrl *as_ctrl; 903 + int op_len, addr_len, dummy_len; 904 + u8 buf[20], *data; 952 905 int i, err; 953 906 954 907 as_ctrl = spi_controller_get_devdata(mem->spi->controller); 908 + 909 + op_len = op->cmd.nbytes; 910 + addr_len = op->addr.nbytes; 911 + dummy_len = op->dummy.nbytes; 912 + 913 + if (op_len + dummy_len + addr_len > sizeof(buf)) 914 + return -EIO; 915 + 916 + data = buf; 917 + for (i = 0; i < op_len; i++) 918 + *data++ = op->cmd.opcode >> (8 * (op_len - i - 1)); 919 + for (i = 0; i < addr_len; i++) 920 + *data++ = op->addr.val >> (8 * (addr_len - i - 1)); 921 + for (i = 0; i < dummy_len; i++) 922 + *data++ = 0xff; 955 923 956 924 /* switch to manual mode */ 957 925 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL); ··· 980 914 return err; 981 915 982 916 /* opcode */ 983 - err = airoha_snand_write_data(as_ctrl, 0x8, &opcode, sizeof(opcode)); 917 + data = buf; 918 + err = airoha_snand_write_data(as_ctrl, data, op_len, 919 + op->cmd.buswidth); 984 920 if (err) 985 921 return err; 986 922 987 923 /* addr part */ 988 - cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8; 989 - put_unaligned_be64(op->addr.val, data); 990 - 991 - for (i = ARRAY_SIZE(data) - op->addr.nbytes; 992 - i < ARRAY_SIZE(data); i++) { 993 - err = airoha_snand_write_data(as_ctrl, cmd, &data[i], 994 - sizeof(data[0])); 924 + data += op_len; 925 + if (addr_len) { 926 + err = airoha_snand_write_data(as_ctrl, data, addr_len, 927 + op->addr.buswidth); 995 928 if (err) 996 929 return err; 997 930 } 998 931 999 932 /* dummy */ 1000 - data[0] = 0xff; 1001 - for (i = 0; i < op->dummy.nbytes; i++) { 1002 - err = airoha_snand_write_data(as_ctrl, 0x8, &data[0], 1003 - sizeof(data[0])); 933 + data += addr_len; 934 + if (dummy_len) { 935 + err = airoha_snand_write_data(as_ctrl, data, dummy_len, 936 + op->dummy.buswidth); 1004 937 if (err) 1005 938 return err; 1006 939 } 1007 940 1008 941 /* data */ 1009 - if (op->data.dir == SPI_MEM_DATA_IN) { 1010 - err = airoha_snand_read_data(as_ctrl, op->data.buf.in, 1011 - op->data.nbytes); 1012 - if (err) 1013 - return err; 1014 - } else { 1015 - err = airoha_snand_write_data(as_ctrl, 0x8, op->data.buf.out, 1016 - op->data.nbytes); 942 + if (op->data.nbytes) { 943 + if (op->data.dir == SPI_MEM_DATA_IN) 944 + err = airoha_snand_read_data(as_ctrl, op->data.buf.in, 945 + op->data.nbytes, 946 + op->data.buswidth); 947 + else 948 + err = airoha_snand_write_data(as_ctrl, op->data.buf.out, 949 + op->data.nbytes, 950 + op->data.buswidth); 1017 951 if (err) 1018 952 return err; 1019 953 }

+2 -2

drivers/spi/spi-amlogic-spifc-a4.c

··· 286 286 287 287 for (i = 0; i <= LANE_MAX; i++) { 288 288 if (buswidth == 1 << i) { 289 - conf = i << __bf_shf(mask); 289 + conf = i << __ffs(mask); 290 290 return regmap_update_bits(sfc->regmap_base, SFC_SPI_CFG, 291 291 mask, conf); 292 292 } ··· 566 566 if (!op->data.nbytes) 567 567 goto end_xfer; 568 568 569 - conf = (op->data.nbytes >> RAW_SIZE_BW) << __bf_shf(RAW_EXT_SIZE); 569 + conf = (op->data.nbytes >> RAW_SIZE_BW) << __ffs(RAW_EXT_SIZE); 570 570 ret = regmap_update_bits(sfc->regmap_base, SFC_SPI_CFG, RAW_EXT_SIZE, conf); 571 571 if (ret) 572 572 goto err_out;

+3 -2

drivers/spi/spi-cadence-quadspi.c

··· 1995 1995 if (cqspi->use_direct_mode) { 1996 1996 ret = cqspi_request_mmap_dma(cqspi); 1997 1997 if (ret == -EPROBE_DEFER) 1998 - goto probe_setup_failed; 1998 + goto probe_dma_failed; 1999 1999 } 2000 2000 2001 2001 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { ··· 2019 2019 2020 2020 return 0; 2021 2021 probe_setup_failed: 2022 - cqspi_controller_enable(cqspi, 0); 2023 2022 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 2024 2023 pm_runtime_disable(dev); 2024 + probe_dma_failed: 2025 + cqspi_controller_enable(cqspi, 0); 2025 2026 probe_reset_failed: 2026 2027 if (cqspi->is_jh7110) 2027 2028 cqspi_jh7110_disable_clk(pdev, cqspi);

+3 -1

drivers/spi/spi-dw-mmio.c

··· 358 358 if (IS_ERR(dwsmmio->rstc)) 359 359 return PTR_ERR(dwsmmio->rstc); 360 360 361 - reset_control_deassert(dwsmmio->rstc); 361 + ret = reset_control_deassert(dwsmmio->rstc); 362 + if (ret) 363 + return dev_err_probe(&pdev->dev, ret, "Failed to deassert resets\n"); 362 364 363 365 dws->bus_num = pdev->id; 364 366

+2

drivers/spi/spi-intel-pci.c

··· 75 75 { PCI_VDEVICE(INTEL, 0x38a4), (unsigned long)&bxt_info }, 76 76 { PCI_VDEVICE(INTEL, 0x43a4), (unsigned long)&cnl_info }, 77 77 { PCI_VDEVICE(INTEL, 0x4b24), (unsigned long)&bxt_info }, 78 + { PCI_VDEVICE(INTEL, 0x4d23), (unsigned long)&cnl_info }, 78 79 { PCI_VDEVICE(INTEL, 0x4da4), (unsigned long)&bxt_info }, 79 80 { PCI_VDEVICE(INTEL, 0x51a4), (unsigned long)&cnl_info }, 80 81 { PCI_VDEVICE(INTEL, 0x54a4), (unsigned long)&cnl_info }, 81 82 { PCI_VDEVICE(INTEL, 0x5794), (unsigned long)&cnl_info }, 83 + { PCI_VDEVICE(INTEL, 0x7723), (unsigned long)&cnl_info }, 82 84 { PCI_VDEVICE(INTEL, 0x7a24), (unsigned long)&cnl_info }, 83 85 { PCI_VDEVICE(INTEL, 0x7aa4), (unsigned long)&cnl_info }, 84 86 { PCI_VDEVICE(INTEL, 0x7e23), (unsigned long)&cnl_info },

+6

drivers/spi/spi-intel.c

··· 132 132 #define FLCOMP_C0DEN_16M 0x05 133 133 #define FLCOMP_C0DEN_32M 0x06 134 134 #define FLCOMP_C0DEN_64M 0x07 135 + #define FLCOMP_C0DEN_128M 0x08 135 136 136 137 #define INTEL_SPI_TIMEOUT 5000 /* ms */ 137 138 #define INTEL_SPI_FIFO_SZ 64 ··· 1348 1347 case FLCOMP_C0DEN_64M: 1349 1348 ispi->chip0_size = SZ_64M; 1350 1349 break; 1350 + case FLCOMP_C0DEN_128M: 1351 + ispi->chip0_size = SZ_128M; 1352 + break; 1351 1353 default: 1354 + dev_warn(ispi->dev, "unsupported C0DEN: %#lx\n", 1355 + flcomp & FLCOMP_C0DEN_MASK); 1352 1356 return -EINVAL; 1353 1357 } 1354 1358

+27 -5

drivers/spi/spi-nxp-fspi.c

··· 404 404 #define FSPI_NEED_INIT BIT(0) 405 405 #define FSPI_DTR_MODE BIT(1) 406 406 int flags; 407 + /* save the previous operation clock rate */ 408 + unsigned long pre_op_rate; 409 + /* the max clock rate fspi output to device */ 410 + unsigned long max_rate; 407 411 }; 408 412 409 413 static inline int needs_ip_only(struct nxp_fspi *f) ··· 689 685 * change the mode back to mode 0. 690 686 */ 691 687 reg = fspi_readl(f, f->iobase + FSPI_MCR0); 692 - if (op_is_dtr) 688 + if (op_is_dtr) { 693 689 reg |= FSPI_MCR0_RXCLKSRC(3); 694 - else /*select mode 0 */ 690 + f->max_rate = 166000000; 691 + } else { /*select mode 0 */ 695 692 reg &= ~FSPI_MCR0_RXCLKSRC(3); 693 + f->max_rate = 66000000; 694 + } 696 695 fspi_writel(f, reg, f->iobase + FSPI_MCR0); 697 696 } 698 697 ··· 726 719 0, POLL_TOUT, true); 727 720 if (ret) 728 721 dev_warn(f->dev, "DLL lock failed, please fix it!\n"); 722 + 723 + /* 724 + * For ERR050272, DLL lock status bit is not accurate, 725 + * wait for 4us more as a workaround. 726 + */ 727 + udelay(4); 729 728 } 730 729 731 730 /* ··· 793 780 uint64_t size_kb; 794 781 795 782 /* 796 - * Return, if previously selected target device is same as current 797 - * requested target device. Also the DTR or STR mode do not change. 783 + * Return when following condition all meet, 784 + * 1, if previously selected target device is same as current 785 + * requested target device. 786 + * 2, the DTR or STR mode do not change. 787 + * 3, previous operation max rate equals current one. 788 + * 789 + * For other case, need to re-config. 798 790 */ 799 791 if ((f->selected == spi_get_chipselect(spi, 0)) && 800 - (!!(f->flags & FSPI_DTR_MODE) == op_is_dtr)) 792 + (!!(f->flags & FSPI_DTR_MODE) == op_is_dtr) && 793 + (f->pre_op_rate == op->max_freq)) 801 794 return; 802 795 803 796 /* Reset FLSHxxCR0 registers */ ··· 821 802 dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0)); 822 803 823 804 nxp_fspi_select_rx_sample_clk_source(f, op_is_dtr); 805 + rate = min(f->max_rate, op->max_freq); 824 806 825 807 if (op_is_dtr) { 826 808 f->flags |= FSPI_DTR_MODE; ··· 851 831 nxp_fspi_dll_calibration(f); 852 832 else 853 833 nxp_fspi_dll_override(f); 834 + 835 + f->pre_op_rate = op->max_freq; 854 836 855 837 f->selected = spi_get_chipselect(spi, 0); 856 838 }

+11 -1

drivers/spi/spi-rockchip-sfc.c

··· 704 704 ret = -ENOMEM; 705 705 goto err_dma; 706 706 } 707 - sfc->dma_buffer = virt_to_phys(sfc->buffer); 707 + sfc->dma_buffer = dma_map_single(dev, sfc->buffer, 708 + sfc->max_iosize, DMA_BIDIRECTIONAL); 709 + if (dma_mapping_error(dev, sfc->dma_buffer)) { 710 + ret = -ENOMEM; 711 + goto err_dma_map; 712 + } 708 713 } 709 714 710 715 ret = devm_spi_register_controller(dev, host); ··· 720 715 721 716 return 0; 722 717 err_register: 718 + dma_unmap_single(dev, sfc->dma_buffer, sfc->max_iosize, 719 + DMA_BIDIRECTIONAL); 720 + err_dma_map: 723 721 free_pages((unsigned long)sfc->buffer, get_order(sfc->max_iosize)); 724 722 err_dma: 725 723 pm_runtime_get_sync(dev); ··· 744 736 struct spi_controller *host = sfc->host; 745 737 746 738 spi_unregister_controller(host); 739 + dma_unmap_single(&pdev->dev, sfc->dma_buffer, sfc->max_iosize, 740 + DMA_BIDIRECTIONAL); 747 741 free_pages((unsigned long)sfc->buffer, get_order(sfc->max_iosize)); 748 742 749 743 clk_disable_unprepare(sfc->clk);

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