Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'imx-dt64-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm64 device tree changes for 6.4:
- New board device trees: Apalis quadmax, DH electronics i.MX8M Plus
DHCOM and PDK3, Data Modul i.MX8M Plus eDM SBC, Colibri Aster and
Iris, etc.
- Add FlexSPI, BBNSM and TPM PWM devices for i.MX93 SoC.
- A series of imx8mq-librem5 udpates which includes minor fixes,
magnetometer, CSI/camera support, and powersaving improvements.
- Add Cadence USB3 support for i.MX8QXP.
- Add FlexCAN support for i.MX8QXP and i.MX8QM.
- Add UART DMA support for i.MX8MQ.
- Add GPT devices for i.MX8MP.
- Add VPU decoder and encoder support for i.MX8QM.
- Add display pipeline and PCIe EP support for i.MX8M family SoCs.
- A series from Peng Fan updating various i.MX8M device trees to pinctrl
nodes match DT schema.
- A series from Philippe Schenker improving colibri-imx8x device trees
in various aspects.
- Other random device tree updates.
* tag 'imx-dt64-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (87 commits)
arm64: dts: imx8mp: Add support for Data Modul i.MX8M Plus eDM SBC
arm64: dts: imx8mp: Add display pipeline components
arm64: dts: imx8mn: Add display pipeline components
arm64: dts: imx8mm: Add display pipeline components
arm64: dts: freescale: imx8qxp-mek: enable cadence usb3
arm64: dts: imx8qxp: add cadence usb3 support
arm64: dts: imx8mq-librem5: add missing #clock-cells
arm64: dts: imx8mm-prt8mm: update pinctrl to match dtschema
arm64: dts: imx8mn-bsh-smm: update pinctrl to match dtschema
arm64: dts: imx8mm-emcon: update pinctrl to match dtschema
arm64: dts: imx8mq-librem5: update pinctrl to match dtschema
arm64: dts: imx8mm-ddr4-evk: update gpmi pinctrl to match dtschema
arm64: dts: imx8mn-evk: update i2c pinctrl to match dtschema
arm64: dts: imx8mp: Add GPT blocks
arm64: dts: imx8-apalis-v1.1: drop ci-disable-lpm
arm64: dts: imx8dxl: drop clocks from scu clock controller
arm64: dts: imx8mp: verdin-yavia: drop disable-over-current
arm64: dts: imx8mq: tqma8mq-mba8mx: drop disable-over-current
arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK3
arm64: dts: colibri-imx8x: Add iris v2 carrier board
...
Link: https://lore.kernel.org/r/20230408101928.280271-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+5912
-745
+10
arch/arm64/boot/dts/freescale/Makefile
+10
arch/arm64/boot/dts/freescale/Makefile
···
89
89
dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
90
90
dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
91
91
dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
92
+
dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
92
93
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
93
94
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb
95
+
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
94
96
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
95
97
dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
96
98
dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
···
124
122
dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb
125
123
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
126
124
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
125
+
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-eval.dtb
126
+
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-ixora-v1.1.dtb
127
+
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval.dtb
128
+
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb
129
+
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb
127
130
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
128
131
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
132
+
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb
129
133
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
134
+
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb
135
+
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb
130
136
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
131
137
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
132
138
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
···
131
131
interrupt-controller;
132
132
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
133
133
IRQ_TYPE_LEVEL_LOW)>;
134
-
its: gic-its@6020000 {
134
+
its: msi-controller@6020000 {
135
135
compatible = "arm,gic-v3-its";
136
136
msi-controller;
137
137
reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+1
-1
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+1
-1
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+144
arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi
+144
arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2022 Toradex
4
+
*/
5
+
6
+
/ {
7
+
aliases {
8
+
rtc0 = &rtc_i2c;
9
+
rtc1 = &rtc;
10
+
};
11
+
12
+
reg_usb_host_vbus: regulator-usb-host-vbus {
13
+
regulator-name = "VCC USBH2(ABCD) / USBH(3|4)";
14
+
};
15
+
};
16
+
17
+
&adc0 {
18
+
status = "okay";
19
+
};
20
+
21
+
&adc1 {
22
+
status = "okay";
23
+
};
24
+
25
+
/* TODO: Audio Mixer */
26
+
27
+
/* TODO: Asynchronous Sample Rate Converter (ASRC) */
28
+
29
+
/* TODO: Display Controller */
30
+
31
+
/* TODO: DPU */
32
+
33
+
/* Apalis ETH1 */
34
+
&fec1 {
35
+
status = "okay";
36
+
};
37
+
38
+
/* Apalis CAN1 */
39
+
&flexcan1 {
40
+
status = "okay";
41
+
};
42
+
43
+
/* Apalis CAN2 */
44
+
&flexcan2 {
45
+
status = "okay";
46
+
};
47
+
48
+
/* TODO: GPU */
49
+
50
+
/* Apalis I2C1 */
51
+
&i2c2 {
52
+
status = "okay";
53
+
54
+
/* M41T0M6 real time clock on carrier board */
55
+
rtc_i2c: rtc@68 {
56
+
status = "okay";
57
+
};
58
+
};
59
+
60
+
/* Apalis I2C3 (CAM) */
61
+
&i2c3 {
62
+
status = "okay";
63
+
};
64
+
65
+
/* Apalis SPI1 */
66
+
&lpspi0 {
67
+
status = "okay";
68
+
};
69
+
70
+
/* Apalis SPI2 */
71
+
&lpspi2 {
72
+
status = "okay";
73
+
};
74
+
75
+
/* Apalis UART3 */
76
+
&lpuart0 {
77
+
status = "okay";
78
+
};
79
+
80
+
/* Apalis UART1 */
81
+
&lpuart1 {
82
+
status = "okay";
83
+
};
84
+
85
+
/* Apalis UART4 */
86
+
&lpuart2 {
87
+
status = "okay";
88
+
};
89
+
90
+
/* Apalis UART2 */
91
+
&lpuart3 {
92
+
status = "okay";
93
+
};
94
+
95
+
/* Apalis PWM3, MXM3 pin 6 */
96
+
&lsio_pwm0 {
97
+
status = "okay";
98
+
};
99
+
100
+
/* Apalis PWM4, MXM3 pin 8 */
101
+
&lsio_pwm1 {
102
+
status = "okay";
103
+
};
104
+
105
+
/* Apalis PWM1, MXM3 pin 2 */
106
+
&lsio_pwm2 {
107
+
status = "okay";
108
+
};
109
+
110
+
/* Apalis PWM2, MXM3 pin 4 */
111
+
&lsio_pwm3 {
112
+
status = "okay";
113
+
};
114
+
115
+
/* TODO: Apalis PCIE1 */
116
+
117
+
/* TODO: Apalis BKL1_PWM */
118
+
119
+
/* TODO: Apalis DAP1 */
120
+
121
+
/* TODO: Apalis Analogue Audio */
122
+
123
+
/* TODO: Apalis SATA1 */
124
+
125
+
/* TODO: Apalis SPDIF1 */
126
+
127
+
/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
128
+
129
+
/* Apalis USBO1 */
130
+
&usbotg1 {
131
+
status = "okay";
132
+
};
133
+
134
+
/* TODO: Apalis USBH4 SuperSpeed */
135
+
136
+
/* Apalis MMC1 */
137
+
&usdhc2 {
138
+
status = "okay";
139
+
};
140
+
141
+
/* Apalis SD1 */
142
+
&usdhc3 {
143
+
status = "okay";
144
+
};
+220
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi
+220
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2022 Toradex
4
+
*/
5
+
6
+
#include <dt-bindings/leds/common.h>
7
+
8
+
/ {
9
+
aliases {
10
+
rtc0 = &rtc_i2c;
11
+
rtc1 = &rtc;
12
+
};
13
+
14
+
leds {
15
+
compatible = "gpio-leds";
16
+
pinctrl-names = "default";
17
+
pinctrl-0 = <&pinctrl_leds_ixora>;
18
+
19
+
/* LED_4_GREEN / MXM3_188 */
20
+
led-1 {
21
+
color = <LED_COLOR_ID_GREEN>;
22
+
default-state = "off";
23
+
function = LED_FUNCTION_STATUS;
24
+
gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>;
25
+
};
26
+
27
+
/* LED_4_RED / MXM3_178 */
28
+
led-2 {
29
+
color = <LED_COLOR_ID_RED>;
30
+
default-state = "off";
31
+
function = LED_FUNCTION_STATUS;
32
+
gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>;
33
+
};
34
+
35
+
/* LED_5_GREEN / MXM3_152 */
36
+
led-3 {
37
+
color = <LED_COLOR_ID_GREEN>;
38
+
default-state = "off";
39
+
function = LED_FUNCTION_STATUS;
40
+
gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>;
41
+
};
42
+
43
+
/* LED_5_RED / MXM3_156 */
44
+
led-4 {
45
+
color = <LED_COLOR_ID_RED>;
46
+
default-state = "off";
47
+
function = LED_FUNCTION_STATUS;
48
+
gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
49
+
};
50
+
};
51
+
52
+
reg_usb_host_vbus: regulator-usb-host-vbus {
53
+
regulator-name = "VCC_USBH(2|4)";
54
+
};
55
+
};
56
+
57
+
&adc0 {
58
+
status = "okay";
59
+
};
60
+
61
+
&adc1 {
62
+
status = "okay";
63
+
};
64
+
65
+
/* TODO: Audio Mixer */
66
+
67
+
/* TODO: Asynchronous Sample Rate Converter (ASRC) */
68
+
69
+
/* TODO: Display Controller */
70
+
71
+
/* TODO: DPU */
72
+
73
+
/* Apalis ETH1 */
74
+
&fec1 {
75
+
status = "okay";
76
+
};
77
+
78
+
/* Apalis CAN1 */
79
+
&flexcan1 {
80
+
status = "okay";
81
+
};
82
+
83
+
/* Apalis CAN2 */
84
+
&flexcan2 {
85
+
status = "okay";
86
+
};
87
+
88
+
/* TODO: GPU */
89
+
90
+
/* Apalis I2C1 */
91
+
&i2c2 {
92
+
status = "okay";
93
+
94
+
/* M41T0M6 real time clock on carrier board */
95
+
rtc_i2c: rtc@68 {
96
+
status = "okay";
97
+
};
98
+
};
99
+
100
+
/* Apalis I2C3 (CAM) */
101
+
&i2c3 {
102
+
status = "okay";
103
+
};
104
+
105
+
&iomuxc {
106
+
pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
107
+
<&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
108
+
<&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_usbh_oc_n>,
109
+
<&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>,
110
+
<&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>,
111
+
<&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>,
112
+
<&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>,
113
+
<&pinctrl_sim0_gpios>, <&pinctrl_uart24_forceoff>,
114
+
<&pinctrl_usdhc1_gpios>;
115
+
116
+
pinctrl_leds_ixora: ledsixoragrp {
117
+
fsl,pins = <IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 0x06000061>, /* LED_4_GREEN */
118
+
<IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 0x06000061>, /* LED_4_RED */
119
+
<IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x06000061>, /* LED_5_GREEN */
120
+
<IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x06000061>; /* LED_5_RED */
121
+
};
122
+
123
+
pinctrl_uart24_forceoff: uart24forceoffgrp {
124
+
fsl,pins = <IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 0x00000021>;
125
+
};
126
+
};
127
+
128
+
/* Apalis SPI1 */
129
+
&lpspi0 {
130
+
status = "okay";
131
+
};
132
+
133
+
/* Apalis SPI2 */
134
+
&lpspi2 {
135
+
status = "okay";
136
+
};
137
+
138
+
/* Apalis UART3 */
139
+
&lpuart0 {
140
+
status = "okay";
141
+
};
142
+
143
+
/* Apalis UART1 */
144
+
&lpuart1 {
145
+
status = "okay";
146
+
};
147
+
148
+
/* Apalis UART4 */
149
+
&lpuart2 {
150
+
status = "okay";
151
+
};
152
+
153
+
/* Apalis UART2 */
154
+
&lpuart3 {
155
+
status = "okay";
156
+
};
157
+
158
+
&lsio_gpio5 {
159
+
gpio-line-names = "gpio5-00", "gpio5-01", "gpio5-02", "gpio5-03",
160
+
"gpio5-04", "gpio5-05", "gpio5-06", "gpio5-07",
161
+
"gpio5-08", "gpio5-09", "gpio5-10", "gpio5-11",
162
+
"gpio5-12", "gpio5-13", "gpio5-14", "gpio5-15",
163
+
"gpio5-16", "gpio5-17", "gpio5-18", "gpio5-19",
164
+
"LED-5-GREEN", "LED-5-RED", "gpio5-22", "gpio5-23",
165
+
"gpio5-24", "UART24-FORCEOFF", "gpio5-26",
166
+
"LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30",
167
+
"gpio5-31";
168
+
ngpios = <32>;
169
+
};
170
+
171
+
/* Apalis PWM3, MXM3 pin 6 */
172
+
&lsio_pwm0 {
173
+
status = "okay";
174
+
};
175
+
176
+
/* Apalis PWM4, MXM3 pin 8 */
177
+
&lsio_pwm1 {
178
+
status = "okay";
179
+
};
180
+
181
+
/* Apalis PWM1, MXM3 pin 2 */
182
+
&lsio_pwm2 {
183
+
status = "okay";
184
+
};
185
+
186
+
/* Apalis PWM2, MXM3 pin 4 */
187
+
&lsio_pwm3 {
188
+
status = "okay";
189
+
};
190
+
191
+
/* TODO: Apalis PCIE1 */
192
+
193
+
/* TODO: Apalis BKL1_PWM */
194
+
195
+
/* TODO: Apalis DAP1 */
196
+
197
+
/* TODO: Apalis Analogue Audio */
198
+
199
+
/* TODO: Apalis SATA1 */
200
+
201
+
/* TODO: Apalis SPDIF1 */
202
+
203
+
/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
204
+
205
+
/* Apalis USBO1 */
206
+
&usbotg1 {
207
+
status = "okay";
208
+
};
209
+
210
+
/* TODO: Apalis USBH4 SuperSpeed */
211
+
212
+
/* Apalis MMC1 */
213
+
&usdhc2 {
214
+
pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>;
215
+
pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>;
216
+
pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>;
217
+
pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>;
218
+
bus-width = <4>;
219
+
status = "okay";
220
+
};
+270
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi
+270
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2022 Toradex
4
+
*/
5
+
6
+
#include <dt-bindings/leds/common.h>
7
+
8
+
/ {
9
+
aliases {
10
+
rtc0 = &rtc_i2c;
11
+
rtc1 = &rtc;
12
+
};
13
+
14
+
leds {
15
+
compatible = "gpio-leds";
16
+
pinctrl-names = "default";
17
+
pinctrl-0 = <&pinctrl_leds_ixora>;
18
+
19
+
/* LED_4_GREEN / MXM3_188 */
20
+
led-1 {
21
+
color = <LED_COLOR_ID_GREEN>;
22
+
default-state = "off";
23
+
function = LED_FUNCTION_STATUS;
24
+
gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>;
25
+
};
26
+
27
+
/* LED_4_RED / MXM3_178 */
28
+
led-2 {
29
+
color = <LED_COLOR_ID_RED>;
30
+
default-state = "off";
31
+
function = LED_FUNCTION_STATUS;
32
+
gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>;
33
+
};
34
+
35
+
/* LED_5_GREEN / MXM3_152 */
36
+
led-3 {
37
+
color = <LED_COLOR_ID_GREEN>;
38
+
default-state = "off";
39
+
function = LED_FUNCTION_STATUS;
40
+
gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>;
41
+
};
42
+
43
+
/* LED_5_RED / MXM3_156 */
44
+
led-4 {
45
+
color = <LED_COLOR_ID_RED>;
46
+
default-state = "off";
47
+
function = LED_FUNCTION_STATUS;
48
+
gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
49
+
};
50
+
};
51
+
52
+
reg_3v3_vmmc: regulator-3v3-vmmc {
53
+
compatible = "regulator-fixed";
54
+
pinctrl-names = "default";
55
+
pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
56
+
/* MMC1_PWR_CTRL */
57
+
gpio = <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>;
58
+
enable-active-high;
59
+
regulator-max-microvolt = <3300000>;
60
+
regulator-min-microvolt = <3300000>;
61
+
regulator-name = "3v3_vmmc";
62
+
};
63
+
64
+
reg_can1_supply: regulator-can1-supply {
65
+
compatible = "regulator-fixed";
66
+
pinctrl-names = "default";
67
+
pinctrl-0 = <&pinctrl_enable_can1_power>;
68
+
gpio = <&lsio_gpio5 22 GPIO_ACTIVE_HIGH>;
69
+
enable-active-high;
70
+
regulator-name = "can1_supply";
71
+
};
72
+
73
+
reg_can2_supply: regulator-can2-supply {
74
+
compatible = "regulator-fixed";
75
+
pinctrl-names = "default";
76
+
pinctrl-0 = <&pinctrl_sata1_act>;
77
+
gpio = <&lsio_gpio2 8 GPIO_ACTIVE_HIGH>;
78
+
enable-active-high;
79
+
regulator-name = "can2_supply";
80
+
};
81
+
82
+
reg_usb_host_vbus: regulator-usb-host-vbus {
83
+
regulator-name = "VCC_USBH(2|4)";
84
+
};
85
+
};
86
+
87
+
&adc0 {
88
+
status = "okay";
89
+
};
90
+
91
+
&adc1 {
92
+
status = "okay";
93
+
};
94
+
95
+
/* TODO: Audio Mixer */
96
+
97
+
/* TODO: Asynchronous Sample Rate Converter (ASRC) */
98
+
99
+
/* TODO: Display Controller */
100
+
101
+
/* TODO: DPU */
102
+
103
+
/* Apalis ETH1 */
104
+
&fec1 {
105
+
status = "okay";
106
+
};
107
+
108
+
/* Apalis CAN1 */
109
+
&flexcan1 {
110
+
xceiver-supply = <®_can1_supply>;
111
+
status = "okay";
112
+
};
113
+
114
+
/* Apalis CAN2 */
115
+
&flexcan2 {
116
+
xceiver-supply = <®_can2_supply>;
117
+
status = "okay";
118
+
};
119
+
120
+
/* TODO: GPU */
121
+
122
+
/* Apalis I2C1 */
123
+
&i2c2 {
124
+
status = "okay";
125
+
126
+
eeprom: eeprom@50 {
127
+
compatible = "atmel,24c02";
128
+
reg = <0x50>;
129
+
pagesize = <16>;
130
+
};
131
+
132
+
/* M41T0M6 real time clock on carrier board */
133
+
rtc_i2c: rtc@68 {
134
+
status = "okay";
135
+
};
136
+
};
137
+
138
+
/* Apalis I2C3 (CAM) */
139
+
&i2c3 {
140
+
status = "okay";
141
+
};
142
+
143
+
&iomuxc {
144
+
pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
145
+
<&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
146
+
<&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_usbh_oc_n>,
147
+
<&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>,
148
+
<&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>,
149
+
<&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>,
150
+
<&pinctrl_qspi1a_gpios>, <&pinctrl_sim0_gpios>,
151
+
<&pinctrl_uart24_forceoff>, <&pinctrl_usdhc1_gpios>;
152
+
153
+
/* PMIC MMC1 power-switch */
154
+
pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp {
155
+
fsl,pins = <IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 0x00000021>; /* MXM3_148, PMIC */
156
+
};
157
+
158
+
/* FlexCAN PMIC */
159
+
pinctrl_enable_can1_power: enablecan1powergrp {
160
+
fsl,pins = <IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021>; /* MXM3_158, PMIC */
161
+
};
162
+
163
+
pinctrl_leds_ixora: ledsixoragrp {
164
+
fsl,pins = <IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 0x06000061>, /* LED_4_GREEN */
165
+
<IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 0x06000061>, /* LED_4_RED */
166
+
<IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x06000061>, /* LED_5_GREEN */
167
+
<IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x06000061>; /* LED_5_RED */
168
+
};
169
+
170
+
pinctrl_uart24_forceoff: uart24forceoffgrp {
171
+
fsl,pins = <IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 0x00000021>;
172
+
};
173
+
};
174
+
175
+
/* Apalis SPI1 */
176
+
&lpspi0 {
177
+
status = "okay";
178
+
};
179
+
180
+
/* Apalis SPI2 */
181
+
&lpspi2 {
182
+
status = "okay";
183
+
};
184
+
185
+
/* Apalis UART3 */
186
+
&lpuart0 {
187
+
status = "okay";
188
+
};
189
+
190
+
/* Apalis UART1 */
191
+
&lpuart1 {
192
+
status = "okay";
193
+
};
194
+
195
+
/* Apalis UART4 */
196
+
&lpuart2 {
197
+
status = "okay";
198
+
};
199
+
200
+
/* Apalis UART2 */
201
+
&lpuart3 {
202
+
status = "okay";
203
+
};
204
+
205
+
&lsio_gpio5 {
206
+
gpio-line-names = "gpio5-00", "gpio5-01", "gpio5-02", "gpio5-03",
207
+
"gpio5-04", "gpio5-05", "gpio5-06", "gpio5-07",
208
+
"gpio5-08", "gpio5-09", "gpio5-10", "gpio5-11",
209
+
"gpio5-12", "gpio5-13", "gpio5-14", "gpio5-15",
210
+
"gpio5-16", "gpio5-17", "gpio5-18", "gpio5-19",
211
+
"LED-5-GREEN", "LED-5-RED", "gpio5-22", "gpio5-23",
212
+
"gpio5-24", "UART24-FORCEOFF", "gpio5-26",
213
+
"LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30",
214
+
"gpio5-31";
215
+
ngpios = <32>;
216
+
};
217
+
218
+
/* Apalis PWM3, MXM3 pin 6 */
219
+
&lsio_pwm0 {
220
+
status = "okay";
221
+
};
222
+
223
+
/* Apalis PWM4, MXM3 pin 8 */
224
+
&lsio_pwm1 {
225
+
status = "okay";
226
+
};
227
+
228
+
/* Apalis PWM1, MXM3 pin 2 */
229
+
&lsio_pwm2 {
230
+
status = "okay";
231
+
};
232
+
233
+
/* Apalis PWM2, MXM3 pin 4 */
234
+
&lsio_pwm3 {
235
+
status = "okay";
236
+
};
237
+
238
+
/* TODO: Apalis PCIE1 */
239
+
240
+
/* TODO: Apalis BKL1_PWM */
241
+
242
+
/* TODO: Apalis DAP1 */
243
+
244
+
/* TODO: Apalis Analogue Audio */
245
+
246
+
/* TODO: Apalis SATA1 */
247
+
248
+
/* TODO: Apalis SPDIF1 */
249
+
250
+
/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
251
+
252
+
/* Apalis USBO1 */
253
+
&usbotg1 {
254
+
status = "okay";
255
+
};
256
+
257
+
/* TODO: Apalis USBH4 SuperSpeed */
258
+
259
+
/* Apalis MMC1 */
260
+
&usdhc2 {
261
+
pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>;
262
+
pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>;
263
+
pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>;
264
+
pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>;
265
+
bus-width = <4>;
266
+
cap-power-off-card;
267
+
/delete-property/ no-1-8-v;
268
+
vmmc-supply = <®_3v3_vmmc>;
269
+
status = "okay";
270
+
};
+1484
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
+1484
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2022 Toradex
4
+
*/
5
+
6
+
#include <dt-bindings/pwm/pwm.h>
7
+
8
+
/ {
9
+
chosen {
10
+
stdout-path = &lpuart1;
11
+
};
12
+
13
+
/* Apalis BKL1 */
14
+
backlight: backlight {
15
+
compatible = "pwm-backlight";
16
+
pinctrl-names = "default";
17
+
pinctrl-0 = <&pinctrl_gpio_bkl_on>;
18
+
brightness-levels = <0 45 63 88 119 158 203 255>;
19
+
default-brightness-level = <4>;
20
+
enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */
21
+
/* TODO: hook-up to Apalis BKL1_PWM */
22
+
status = "disabled";
23
+
};
24
+
25
+
gpio_fan: gpio-fan {
26
+
compatible = "gpio-fan";
27
+
pinctrl-names = "default";
28
+
pinctrl-0 = <&pinctrl_gpio8>;
29
+
gpios = <&lsio_gpio3 28 GPIO_ACTIVE_HIGH>;
30
+
gpio-fan,speed-map = < 0 0
31
+
3000 1>;
32
+
};
33
+
34
+
/* TODO: LVDS Panel */
35
+
36
+
/* TODO: Shared PCIe/SATA Reference Clock */
37
+
38
+
/* TODO: PCIe Wi-Fi Reference Clock */
39
+
40
+
/*
41
+
* Power management bus used to control LDO1OUT of the
42
+
* second PMIC PF8100. This is used for controlling voltage levels of
43
+
* typespecific RGMII signals and Apalis UART2_RTS UART2_CTS.
44
+
*
45
+
* IMX_SC_R_BOARD_R1 for 3.3V
46
+
* IMX_SC_R_BOARD_R2 for 1.8V
47
+
* IMX_SC_R_BOARD_R3 for 2.5V
48
+
* Note that for 2.5V operation the pad muxing needs to be changed,
49
+
* compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD.
50
+
*
51
+
* those power domains are mutually exclusive.
52
+
*/
53
+
reg_ext_rgmii: regulator-ext-rgmii {
54
+
compatible = "regulator-fixed";
55
+
power-domains = <&pd IMX_SC_R_BOARD_R1>;
56
+
regulator-max-microvolt = <3300000>;
57
+
regulator-min-microvolt = <3300000>;
58
+
regulator-name = "VDD_EXT_RGMII (LDO1)";
59
+
60
+
regulator-state-mem {
61
+
regulator-off-in-suspend;
62
+
};
63
+
};
64
+
65
+
reg_module_3v3: regulator-module-3v3 {
66
+
compatible = "regulator-fixed";
67
+
regulator-max-microvolt = <3300000>;
68
+
regulator-min-microvolt = <3300000>;
69
+
regulator-name = "+V3.3";
70
+
};
71
+
72
+
reg_module_3v3_avdd: regulator-module-3v3-avdd {
73
+
compatible = "regulator-fixed";
74
+
regulator-max-microvolt = <3300000>;
75
+
regulator-min-microvolt = <3300000>;
76
+
regulator-name = "+V3.3_AUDIO";
77
+
};
78
+
79
+
reg_module_wifi: regulator-module-wifi {
80
+
compatible = "regulator-fixed";
81
+
pinctrl-names = "default";
82
+
pinctrl-0 = <&pinctrl_wifi_pdn>;
83
+
gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
84
+
enable-active-high;
85
+
regulator-name = "wifi_pwrdn_fake_regulator";
86
+
regulator-settling-time-us = <100>;
87
+
88
+
regulator-state-mem {
89
+
regulator-off-in-suspend;
90
+
};
91
+
};
92
+
93
+
reg_pcie_switch: regulator-pcie-switch {
94
+
compatible = "regulator-fixed";
95
+
pinctrl-names = "default";
96
+
pinctrl-0 = <&pinctrl_gpio7>;
97
+
gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>;
98
+
enable-active-high;
99
+
regulator-max-microvolt = <1800000>;
100
+
regulator-min-microvolt = <1800000>;
101
+
regulator-name = "pcie_switch";
102
+
startup-delay-us = <100000>;
103
+
};
104
+
105
+
reg_usb_host_vbus: regulator-usb-host-vbus {
106
+
compatible = "regulator-fixed";
107
+
pinctrl-names = "default";
108
+
pinctrl-0 = <&pinctrl_usbh_en>;
109
+
/* Apalis USBH_EN */
110
+
gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>;
111
+
enable-active-high;
112
+
regulator-always-on;
113
+
regulator-max-microvolt = <5000000>;
114
+
regulator-min-microvolt = <5000000>;
115
+
regulator-name = "usb-host-vbus";
116
+
};
117
+
118
+
reg_usb_hsic: regulator-usb-hsic {
119
+
compatible = "regulator-fixed";
120
+
regulator-max-microvolt = <3000000>;
121
+
regulator-min-microvolt = <3000000>;
122
+
regulator-name = "usb-hsic-dummy";
123
+
};
124
+
125
+
reg_usb_phy: regulator-usb-hsic1 {
126
+
compatible = "regulator-fixed";
127
+
regulator-max-microvolt = <3000000>;
128
+
regulator-min-microvolt = <3000000>;
129
+
regulator-name = "usb-phy-dummy";
130
+
};
131
+
132
+
reserved-memory {
133
+
#address-cells = <2>;
134
+
#size-cells = <2>;
135
+
ranges;
136
+
137
+
decoder_boot: decoder-boot@84000000 {
138
+
reg = <0 0x84000000 0 0x2000000>;
139
+
no-map;
140
+
};
141
+
142
+
encoder1_boot: encoder1-boot@86000000 {
143
+
reg = <0 0x86000000 0 0x200000>;
144
+
no-map;
145
+
};
146
+
147
+
encoder2_boot: encoder2-boot@86200000 {
148
+
reg = <0 0x86200000 0 0x200000>;
149
+
no-map;
150
+
};
151
+
152
+
/*
153
+
* reserved-memory layout
154
+
* 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
155
+
* Shouldn't be used at A core and Linux side.
156
+
*
157
+
*/
158
+
m4_reserved: m4@88000000 {
159
+
reg = <0 0x88000000 0 0x8000000>;
160
+
no-map;
161
+
};
162
+
163
+
rpmsg_reserved: rpmsg@90200000 {
164
+
reg = <0 0x90200000 0 0x200000>;
165
+
no-map;
166
+
};
167
+
168
+
vdevbuffer: vdevbuffer@90400000 {
169
+
compatible = "shared-dma-pool";
170
+
reg = <0 0x90400000 0 0x100000>;
171
+
no-map;
172
+
};
173
+
174
+
decoder_rpc: decoder-rpc@92000000 {
175
+
reg = <0 0x92000000 0 0x200000>;
176
+
no-map;
177
+
};
178
+
179
+
dsp_reserved: dsp@92400000 {
180
+
reg = <0 0x92400000 0 0x2000000>;
181
+
no-map;
182
+
};
183
+
184
+
encoder1_rpc: encoder1-rpc@94400000 {
185
+
reg = <0 0x94400000 0 0x700000>;
186
+
no-map;
187
+
};
188
+
189
+
encoder2_rpc: encoder2-rpc@94b00000 {
190
+
reg = <0 0x94b00000 0 0x700000>;
191
+
no-map;
192
+
};
193
+
194
+
/* global autoconfigured region for contiguous allocations */
195
+
linux,cma {
196
+
compatible = "shared-dma-pool";
197
+
alloc-ranges = <0 0xc0000000 0 0x3c000000>;
198
+
linux,cma-default;
199
+
reusable;
200
+
size = <0 0x3c000000>;
201
+
};
202
+
};
203
+
204
+
/* TODO: Apalis Analogue Audio */
205
+
206
+
/* TODO: HDMI Audio */
207
+
208
+
/* TODO: Apalis SPDIF1 */
209
+
210
+
touchscreen: touchscreen {
211
+
compatible = "toradex,vf50-touchscreen";
212
+
interrupt-parent = <&lsio_gpio3>;
213
+
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
214
+
pinctrl-names = "idle", "default";
215
+
pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>;
216
+
pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>;
217
+
io-channels = <&adc1 2>, <&adc1 1>,
218
+
<&adc1 0>, <&adc1 3>;
219
+
vf50-ts-min-pressure = <200>;
220
+
xp-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>;
221
+
xm-gpios = <&lsio_gpio2 5 GPIO_ACTIVE_HIGH>;
222
+
yp-gpios = <&lsio_gpio2 17 GPIO_ACTIVE_LOW>;
223
+
ym-gpios = <&lsio_gpio2 21 GPIO_ACTIVE_HIGH>;
224
+
/*
225
+
* NOTE: you must remove the pinctrl-adc1 from the adc1
226
+
* node below to use the touchscreen
227
+
*/
228
+
status = "disabled";
229
+
};
230
+
231
+
};
232
+
233
+
&adc0 {
234
+
pinctrl-names = "default";
235
+
pinctrl-0 = <&pinctrl_adc0>;
236
+
};
237
+
238
+
&adc1 {
239
+
pinctrl-names = "default";
240
+
pinctrl-0 = <&pinctrl_adc1>;
241
+
};
242
+
243
+
/* TODO: Asynchronous Sample Rate Converter (ASRC) */
244
+
245
+
/* Apalis ETH1 */
246
+
&fec1 {
247
+
pinctrl-names = "default", "sleep";
248
+
pinctrl-0 = <&pinctrl_fec1>;
249
+
pinctrl-1 = <&pinctrl_fec1_sleep>;
250
+
fsl,magic-packet;
251
+
phy-handle = <ðphy0>;
252
+
phy-mode = "rgmii-id";
253
+
254
+
mdio {
255
+
#address-cells = <1>;
256
+
#size-cells = <0>;
257
+
258
+
ethphy0: ethernet-phy@7 {
259
+
compatible = "ethernet-phy-ieee802.3-c22";
260
+
reg = <7>;
261
+
interrupt-parent = <&lsio_gpio1>;
262
+
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
263
+
micrel,led-mode = <0>;
264
+
reset-assert-us = <2>;
265
+
reset-deassert-us = <2>;
266
+
reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
267
+
reset-names = "phy-reset";
268
+
};
269
+
};
270
+
};
271
+
272
+
/* Apalis CAN1 */
273
+
&flexcan1 {
274
+
pinctrl-names = "default";
275
+
pinctrl-0 = <&pinctrl_flexcan1>;
276
+
};
277
+
278
+
/* Apalis CAN2 */
279
+
&flexcan2 {
280
+
pinctrl-names = "default";
281
+
pinctrl-0 = <&pinctrl_flexcan2>;
282
+
};
283
+
284
+
/* Apalis CAN3 (optional) */
285
+
&flexcan3 {
286
+
pinctrl-names = "default";
287
+
pinctrl-0 = <&pinctrl_flexcan3>;
288
+
};
289
+
290
+
/* TODO: Apalis HDMI1 */
291
+
292
+
/* On-module I2C */
293
+
&i2c1 {
294
+
pinctrl-names = "default";
295
+
pinctrl-0 = <&pinctrl_lpi2c1>;
296
+
#address-cells = <1>;
297
+
#size-cells = <0>;
298
+
clock-frequency = <100000>;
299
+
status = "okay";
300
+
301
+
/* TODO: Audio Codec */
302
+
303
+
/* USB3503A */
304
+
usb-hub@8 {
305
+
compatible = "smsc,usb3503a";
306
+
reg = <0x08>;
307
+
pinctrl-names = "default";
308
+
pinctrl-0 = <&pinctrl_usb3503a>;
309
+
connect-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_LOW>;
310
+
initial-mode = <1>;
311
+
intn-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>;
312
+
refclk-frequency = <25000000>;
313
+
reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>;
314
+
};
315
+
};
316
+
317
+
/* Apalis I2C1 */
318
+
&i2c2 {
319
+
pinctrl-names = "default";
320
+
pinctrl-0 = <&pinctrl_lpi2c2>;
321
+
#address-cells = <1>;
322
+
#size-cells = <0>;
323
+
clock-frequency = <100000>;
324
+
325
+
atmel_mxt_ts: touch@4a {
326
+
compatible = "atmel,maxtouch";
327
+
reg = <0x4a>;
328
+
interrupt-parent = <&lsio_gpio4>;
329
+
interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */
330
+
pinctrl-names = "default";
331
+
pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>;
332
+
reset-gpios = <&lsio_gpio4 2 GPIO_ACTIVE_LOW>; /* Apalis GPIO6 */
333
+
status = "disabled";
334
+
};
335
+
336
+
/* M41T0M6 real time clock on carrier board */
337
+
rtc_i2c: rtc@68 {
338
+
compatible = "st,m41t0";
339
+
reg = <0x68>;
340
+
status = "disabled";
341
+
};
342
+
};
343
+
344
+
/* Apalis I2C3 (CAM) */
345
+
&i2c3 {
346
+
pinctrl-names = "default";
347
+
pinctrl-0 = <&pinctrl_lpi2c3>;
348
+
#address-cells = <1>;
349
+
#size-cells = <0>;
350
+
clock-frequency = <100000>;
351
+
};
352
+
353
+
&jpegdec {
354
+
status = "okay";
355
+
};
356
+
357
+
&jpegenc {
358
+
status = "okay";
359
+
};
360
+
361
+
/* TODO: Apalis LVDS1 */
362
+
363
+
/* Apalis SPI1 */
364
+
&lpspi0 {
365
+
pinctrl-names = "default";
366
+
pinctrl-0 = <&pinctrl_lpspi0>;
367
+
#address-cells = <1>;
368
+
#size-cells = <0>;
369
+
cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>;
370
+
};
371
+
372
+
/* Apalis SPI2 */
373
+
&lpspi2 {
374
+
pinctrl-names = "default";
375
+
pinctrl-0 = <&pinctrl_lpspi2>;
376
+
#address-cells = <1>;
377
+
#size-cells = <0>;
378
+
cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
379
+
};
380
+
381
+
/* Apalis UART3 */
382
+
&lpuart0 {
383
+
pinctrl-names = "default";
384
+
pinctrl-0 = <&pinctrl_lpuart0>;
385
+
};
386
+
387
+
/* Apalis UART1 */
388
+
&lpuart1 {
389
+
pinctrl-names = "default";
390
+
pinctrl-0 = <&pinctrl_lpuart1>;
391
+
};
392
+
393
+
/* Apalis UART4 */
394
+
&lpuart2 {
395
+
pinctrl-names = "default";
396
+
pinctrl-0 = <&pinctrl_lpuart2>;
397
+
};
398
+
399
+
/* Apalis UART2 */
400
+
&lpuart3 {
401
+
pinctrl-names = "default";
402
+
pinctrl-0 = <&pinctrl_lpuart3>;
403
+
};
404
+
405
+
&lsio_gpio0 {
406
+
gpio-line-names = "MXM3_279",
407
+
"MXM3_277",
408
+
"MXM3_135",
409
+
"MXM3_203",
410
+
"MXM3_201",
411
+
"MXM3_275",
412
+
"MXM3_110",
413
+
"MXM3_120",
414
+
"MXM3_1/GPIO1",
415
+
"MXM3_3/GPIO2",
416
+
"MXM3_124",
417
+
"MXM3_122",
418
+
"MXM3_5/GPIO3",
419
+
"MXM3_7/GPIO4",
420
+
"",
421
+
"",
422
+
"MXM3_4",
423
+
"MXM3_211",
424
+
"MXM3_209",
425
+
"MXM3_2",
426
+
"MXM3_136",
427
+
"MXM3_134",
428
+
"MXM3_6",
429
+
"MXM3_8",
430
+
"MXM3_112",
431
+
"MXM3_118",
432
+
"MXM3_114",
433
+
"MXM3_116";
434
+
};
435
+
436
+
&lsio_gpio1 {
437
+
gpio-line-names = "",
438
+
"",
439
+
"",
440
+
"",
441
+
"MXM3_286",
442
+
"",
443
+
"MXM3_87",
444
+
"MXM3_99",
445
+
"MXM3_138",
446
+
"MXM3_140",
447
+
"MXM3_239",
448
+
"",
449
+
"MXM3_281",
450
+
"MXM3_283",
451
+
"MXM3_126",
452
+
"MXM3_132",
453
+
"",
454
+
"",
455
+
"",
456
+
"",
457
+
"MXM3_173",
458
+
"MXM3_175",
459
+
"MXM3_123";
460
+
461
+
hdmi-ctrl-hog {
462
+
pinctrl-names = "default";
463
+
pinctrl-0 = <&pinctrl_hdmi_ctrl>;
464
+
gpio-hog;
465
+
gpios = <30 GPIO_ACTIVE_HIGH>;
466
+
line-name = "CONNECTOR_IS_HDMI";
467
+
/* Set signals depending on HDP device type, 0 DP, 1 HDMI */
468
+
output-high;
469
+
};
470
+
};
471
+
472
+
&lsio_gpio2 {
473
+
gpio-line-names = "",
474
+
"",
475
+
"",
476
+
"",
477
+
"",
478
+
"",
479
+
"",
480
+
"MXM3_198",
481
+
"MXM3_35",
482
+
"MXM3_164",
483
+
"",
484
+
"",
485
+
"",
486
+
"",
487
+
"MXM3_217",
488
+
"MXM3_215",
489
+
"",
490
+
"",
491
+
"MXM3_193",
492
+
"MXM3_194",
493
+
"MXM3_37",
494
+
"",
495
+
"MXM3_271",
496
+
"MXM3_273",
497
+
"MXM3_195",
498
+
"MXM3_197",
499
+
"MXM3_177",
500
+
"MXM3_179",
501
+
"MXM3_181",
502
+
"MXM3_183",
503
+
"MXM3_185",
504
+
"MXM3_187";
505
+
506
+
/*
507
+
* Add GPIO2_20 as a wakeup source:
508
+
* Pin: 101 SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO)
509
+
* Type: 5 SC_PAD_WAKEUP_FALL_EDGE
510
+
* Line: 20
511
+
*/
512
+
pad-wakeup = <IMX8QM_SPI3_CS0 5 20>;
513
+
pad-wakeup-num = <1>;
514
+
515
+
pcie-wifi-hog {
516
+
pinctrl-names = "default";
517
+
pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
518
+
gpio-hog;
519
+
gpios = <11 GPIO_ACTIVE_HIGH>;
520
+
line-name = "PCIE_WIFI_CLK";
521
+
output-high;
522
+
};
523
+
};
524
+
525
+
&lsio_gpio3 {
526
+
gpio-line-names = "MXM3_191",
527
+
"",
528
+
"MXM3_221",
529
+
"MXM3_225",
530
+
"MXM3_223",
531
+
"MXM3_227",
532
+
"MXM3_200",
533
+
"MXM3_235",
534
+
"MXM3_231",
535
+
"MXM3_229",
536
+
"MXM3_233",
537
+
"MXM3_204",
538
+
"MXM3_196",
539
+
"",
540
+
"MXM3_202",
541
+
"",
542
+
"",
543
+
"",
544
+
"MXM3_305",
545
+
"MXM3_307",
546
+
"MXM3_309",
547
+
"MXM3_311",
548
+
"MXM3_315",
549
+
"MXM3_317",
550
+
"MXM3_319",
551
+
"MXM3_321",
552
+
"MXM3_15/GPIO7",
553
+
"MXM3_63",
554
+
"MXM3_17/GPIO8",
555
+
"MXM3_12",
556
+
"MXM3_14",
557
+
"MXM3_16";
558
+
};
559
+
560
+
&lsio_gpio4 {
561
+
gpio-line-names = "MXM3_18",
562
+
"MXM3_11/GPIO5",
563
+
"MXM3_13/GPIO6",
564
+
"MXM3_274",
565
+
"MXM3_84",
566
+
"MXM3_262",
567
+
"MXM3_96",
568
+
"",
569
+
"",
570
+
"",
571
+
"",
572
+
"",
573
+
"MXM3_190",
574
+
"",
575
+
"",
576
+
"",
577
+
"MXM3_269",
578
+
"MXM3_251",
579
+
"MXM3_253",
580
+
"MXM3_295",
581
+
"MXM3_299",
582
+
"MXM3_301",
583
+
"MXM3_297",
584
+
"MXM3_293",
585
+
"MXM3_291",
586
+
"MXM3_289",
587
+
"MXM3_287";
588
+
589
+
/* Enable pcie root / sata ref clock unconditionally */
590
+
pcie-sata-hog {
591
+
pinctrl-names = "default";
592
+
pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
593
+
gpio-hog;
594
+
gpios = <11 GPIO_ACTIVE_HIGH>;
595
+
line-name = "PCIE_SATA_CLK";
596
+
output-high;
597
+
};
598
+
};
599
+
600
+
&lsio_gpio5 {
601
+
gpio-line-names = "",
602
+
"",
603
+
"",
604
+
"",
605
+
"",
606
+
"",
607
+
"",
608
+
"",
609
+
"",
610
+
"",
611
+
"",
612
+
"",
613
+
"",
614
+
"",
615
+
"MXM3_150",
616
+
"MXM3_160",
617
+
"MXM3_162",
618
+
"MXM3_144",
619
+
"MXM3_146",
620
+
"MXM3_148",
621
+
"MXM3_152",
622
+
"MXM3_156",
623
+
"MXM3_158",
624
+
"MXM3_159",
625
+
"MXM3_184",
626
+
"MXM3_180",
627
+
"MXM3_186",
628
+
"MXM3_188",
629
+
"MXM3_176",
630
+
"MXM3_178";
631
+
};
632
+
633
+
&lsio_gpio6 {
634
+
gpio-line-names = "",
635
+
"",
636
+
"",
637
+
"",
638
+
"",
639
+
"",
640
+
"",
641
+
"",
642
+
"",
643
+
"",
644
+
"MXM3_261",
645
+
"MXM3_263",
646
+
"MXM3_259",
647
+
"MXM3_257",
648
+
"MXM3_255",
649
+
"MXM3_128",
650
+
"MXM3_130",
651
+
"MXM3_265",
652
+
"MXM3_249",
653
+
"MXM3_247",
654
+
"MXM3_245",
655
+
"MXM3_243";
656
+
};
657
+
658
+
/* Apalis PWM3, MXM3 pin 6 */
659
+
&lsio_pwm0 {
660
+
pinctrl-names = "default";
661
+
pinctrl-0 = <&pinctrl_pwm0>;
662
+
#pwm-cells = <3>;
663
+
};
664
+
665
+
/* Apalis PWM4, MXM3 pin 8 */
666
+
&lsio_pwm1 {
667
+
pinctrl-names = "default";
668
+
pinctrl-0 = <&pinctrl_pwm1>;
669
+
#pwm-cells = <3>;
670
+
};
671
+
672
+
/* Apalis PWM1, MXM3 pin 2 */
673
+
&lsio_pwm2 {
674
+
pinctrl-names = "default";
675
+
pinctrl-0 = <&pinctrl_pwm2>;
676
+
#pwm-cells = <3>;
677
+
};
678
+
679
+
/* Apalis PWM2, MXM3 pin 4 */
680
+
&lsio_pwm3 {
681
+
pinctrl-names = "default";
682
+
pinctrl-0 = <&pinctrl_pwm3>;
683
+
#pwm-cells = <3>;
684
+
};
685
+
686
+
/* Messaging Units */
687
+
&mu_m0{
688
+
status = "okay";
689
+
};
690
+
691
+
&mu1_m0{
692
+
status = "okay";
693
+
};
694
+
695
+
&mu2_m0{
696
+
status = "okay";
697
+
};
698
+
699
+
/* TODO: Apalis PCIE1 */
700
+
701
+
/* TODO: On-module Wi-Fi */
702
+
703
+
/* TODO: Apalis BKL1_PWM */
704
+
705
+
/* TODO: Apalis DAP1 */
706
+
707
+
/* TODO: Analogue Audio */
708
+
709
+
/* TODO: Apalis SATA1 */
710
+
711
+
/* TODO: Apalis SPDIF1 */
712
+
713
+
/* TODO: Thermal Zones */
714
+
715
+
/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
716
+
717
+
/* TODO: Apalis USBH4 */
718
+
719
+
/* Apalis USBO1 */
720
+
&usbphy1 {
721
+
phy-3p0-supply = <®_usb_phy>;
722
+
status = "okay";
723
+
};
724
+
725
+
&usbotg1 {
726
+
pinctrl-names = "default";
727
+
pinctrl-0 = <&pinctrl_usbotg1>;
728
+
adp-disable;
729
+
hnp-disable;
730
+
over-current-active-low;
731
+
power-active-high;
732
+
srp-disable;
733
+
};
734
+
735
+
/* On-module eMMC */
736
+
&usdhc1 {
737
+
pinctrl-names = "default", "state_100mhz", "state_200mhz";
738
+
pinctrl-0 = <&pinctrl_usdhc1>;
739
+
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
740
+
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
741
+
bus-width = <8>;
742
+
non-removable;
743
+
status = "okay";
744
+
};
745
+
746
+
/* Apalis MMC1 */
747
+
&usdhc2 {
748
+
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
749
+
pinctrl-0 = <&pinctrl_usdhc2_4bit>,
750
+
<&pinctrl_usdhc2_8bit>,
751
+
<&pinctrl_mmc1_cd>;
752
+
pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>,
753
+
<&pinctrl_usdhc2_8bit_100mhz>,
754
+
<&pinctrl_mmc1_cd>;
755
+
pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>,
756
+
<&pinctrl_usdhc2_8bit_200mhz>,
757
+
<&pinctrl_mmc1_cd>;
758
+
pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>,
759
+
<&pinctrl_usdhc2_8bit_sleep>,
760
+
<&pinctrl_mmc1_cd_sleep>;
761
+
bus-width = <8>;
762
+
cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
763
+
no-1-8-v;
764
+
};
765
+
766
+
/* Apalis SD1 */
767
+
&usdhc3 {
768
+
pinctrl-names = "default", "state_100mhz", "state_200mhz";
769
+
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
770
+
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>;
771
+
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>;
772
+
bus-width = <4>;
773
+
cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */
774
+
no-1-8-v;
775
+
};
776
+
777
+
/* Video Processing Unit */
778
+
&vpu {
779
+
compatible = "nxp,imx8qm-vpu";
780
+
status = "okay";
781
+
};
782
+
783
+
&vpu_core0 {
784
+
reg = <0x2d080000 0x10000>;
785
+
memory-region = <&decoder_boot>, <&decoder_rpc>;
786
+
status = "okay";
787
+
};
788
+
789
+
&vpu_core1 {
790
+
reg = <0x2d090000 0x10000>;
791
+
memory-region = <&encoder1_boot>, <&encoder1_rpc>;
792
+
status = "okay";
793
+
};
794
+
795
+
&vpu_core2 {
796
+
reg = <0x2d0a0000 0x10000>;
797
+
memory-region = <&encoder2_boot>, <&encoder2_rpc>;
798
+
status = "okay";
799
+
};
800
+
801
+
&iomuxc {
802
+
pinctrl-names = "default";
803
+
pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
804
+
<&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
805
+
<&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>,
806
+
<&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>,
807
+
<&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>,
808
+
<&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>,
809
+
<&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>,
810
+
<&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>,
811
+
<&pinctrl_usdhc1_gpios>;
812
+
813
+
/* Apalis AN1_ADC */
814
+
pinctrl_adc0: adc0grp {
815
+
fsl,pins = /* Apalis AN1_ADC0 */
816
+
<IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060>,
817
+
/* Apalis AN1_ADC1 */
818
+
<IMX8QM_ADC_IN1_DMA_ADC0_IN1 0xc0000060>,
819
+
/* Apalis AN1_ADC2 */
820
+
<IMX8QM_ADC_IN2_DMA_ADC0_IN2 0xc0000060>,
821
+
/* Apalis AN1_TSWIP_ADC3 */
822
+
<IMX8QM_ADC_IN3_DMA_ADC0_IN3 0xc0000060>;
823
+
};
824
+
825
+
/* Apalis AN1_TS */
826
+
pinctrl_adc1: adc1grp {
827
+
fsl,pins = /* Apalis AN1_TSPX */
828
+
<IMX8QM_ADC_IN4_DMA_ADC1_IN0 0xc0000060>,
829
+
/* Apalis AN1_TSMX */
830
+
<IMX8QM_ADC_IN5_DMA_ADC1_IN1 0xc0000060>,
831
+
/* Apalis AN1_TSPY */
832
+
<IMX8QM_ADC_IN6_DMA_ADC1_IN2 0xc0000060>,
833
+
/* Apalis AN1_TSMY */
834
+
<IMX8QM_ADC_IN7_DMA_ADC1_IN3 0xc0000060>;
835
+
};
836
+
837
+
/* Apalis CAM1 */
838
+
pinctrl_cam1_gpios: cam1gpiosgrp {
839
+
fsl,pins = /* Apalis CAM1_D7 */
840
+
<IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021>,
841
+
/* Apalis CAM1_D6 */
842
+
<IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021>,
843
+
/* Apalis CAM1_D5 */
844
+
<IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021>,
845
+
/* Apalis CAM1_D4 */
846
+
<IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021>,
847
+
/* Apalis CAM1_D3 */
848
+
<IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021>,
849
+
/* Apalis CAM1_D2 */
850
+
<IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021>,
851
+
/* Apalis CAM1_D1 */
852
+
<IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021>,
853
+
/* Apalis CAM1_D0 */
854
+
<IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021>,
855
+
/* Apalis CAM1_PCLK */
856
+
<IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021>,
857
+
/* Apalis CAM1_MCLK */
858
+
<IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021>,
859
+
/* Apalis CAM1_VSYNC */
860
+
<IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021>,
861
+
/* Apalis CAM1_HSYNC */
862
+
<IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021>;
863
+
};
864
+
865
+
/* Apalis DAP1 */
866
+
pinctrl_dap1_gpios: dap1gpiosgrp {
867
+
fsl,pins = /* Apalis DAP1_MCLK */
868
+
<IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19 0x00000021>,
869
+
/* Apalis DAP1_D_OUT */
870
+
<IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12 0x00000021>,
871
+
/* Apalis DAP1_RESET */
872
+
<IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021>,
873
+
/* Apalis DAP1_BIT_CLK */
874
+
<IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021>,
875
+
/* Apalis DAP1_D_IN */
876
+
<IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14 0x00000021>,
877
+
/* Apalis DAP1_SYNC */
878
+
<IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021>,
879
+
/* On-module Wi-Fi_I2S_EN# */
880
+
<IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 0x00000021>;
881
+
};
882
+
883
+
/* Apalis LCD1_G1+2 */
884
+
pinctrl_esai0_gpios: esai0gpiosgrp {
885
+
fsl,pins = /* Apalis LCD1_G1 */
886
+
<IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22 0x00000021>,
887
+
/* Apalis LCD1_G2 */
888
+
<IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23 0x00000021>;
889
+
};
890
+
891
+
/* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */
892
+
pinctrl_fec1: fec1grp {
893
+
fsl,pins = /* Use pads in 3.3V mode */
894
+
<IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>,
895
+
<IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020>,
896
+
<IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>,
897
+
<IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020>,
898
+
<IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020>,
899
+
<IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020>,
900
+
<IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020>,
901
+
<IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020>,
902
+
<IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020>,
903
+
<IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020>,
904
+
<IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020>,
905
+
<IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020>,
906
+
<IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020>,
907
+
<IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020>,
908
+
<IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020>,
909
+
<IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020>,
910
+
/* On-module ETH_RESET# */
911
+
<IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020>,
912
+
/* On-module ETH_INT# */
913
+
<IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000060>;
914
+
};
915
+
916
+
pinctrl_fec1_sleep: fec1-sleepgrp {
917
+
fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>,
918
+
<IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040>,
919
+
<IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040>,
920
+
<IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040>,
921
+
<IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040>,
922
+
<IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040>,
923
+
<IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040>,
924
+
<IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040>,
925
+
<IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040>,
926
+
<IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040>,
927
+
<IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040>,
928
+
<IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040>,
929
+
<IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040>,
930
+
<IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040>,
931
+
<IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040>,
932
+
<IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040>,
933
+
<IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020>,
934
+
<IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000040>;
935
+
};
936
+
937
+
/* Apalis LCD1_ */
938
+
pinctrl_fec2_gpios: fec2gpiosgrp {
939
+
fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0>,
940
+
/* Apalis LCD1_R1 */
941
+
<IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18 0x00000021>,
942
+
/* Apalis LCD1_R0 */
943
+
<IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17 0x00000021>,
944
+
/* Apalis LCD1_G0 */
945
+
<IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 0x00000021>,
946
+
/* Apalis LCD1_R7 */
947
+
<IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 0x00000021>,
948
+
/* Apalis LCD1_DE */
949
+
<IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 0x00000021>,
950
+
/* Apalis LCD1_HSYNC */
951
+
<IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 0x00000021>,
952
+
/* Apalis LCD1_VSYNC */
953
+
<IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 0x00000021>,
954
+
/* Apalis LCD1_PCLK */
955
+
<IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 0x00000021>,
956
+
/* Apalis LCD1_R6 */
957
+
<IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 0x00000021>,
958
+
/* Apalis LCD1_R5 */
959
+
<IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 0x00000021>,
960
+
/* Apalis LCD1_R4 */
961
+
<IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 0x00000021>,
962
+
/* Apalis LCD1_R3 */
963
+
<IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 0x00000021>,
964
+
/* Apalis LCD1_R2 */
965
+
<IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 0x00000021>;
966
+
};
967
+
968
+
/* Apalis CAN1 */
969
+
pinctrl_flexcan1: flexcan0grp {
970
+
fsl,pins = <IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x00000021>,
971
+
<IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x00000021>;
972
+
};
973
+
974
+
/* Apalis CAN2 */
975
+
pinctrl_flexcan2: flexcan1grp {
976
+
fsl,pins = <IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x00000021>,
977
+
<IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x00000021>;
978
+
};
979
+
980
+
/* Apalis CAN3 (optional) */
981
+
pinctrl_flexcan3: flexcan2grp {
982
+
fsl,pins = <IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x00000021>,
983
+
<IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x00000021>;
984
+
};
985
+
986
+
/* Apalis GPIO1 */
987
+
pinctrl_gpio1: gpio1grp {
988
+
fsl,pins = <IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08 0x06000021>;
989
+
};
990
+
991
+
/* Apalis GPIO2 */
992
+
pinctrl_gpio2: gpio2grp {
993
+
fsl,pins = <IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09 0x06000021>;
994
+
};
995
+
996
+
/* Apalis GPIO3 */
997
+
pinctrl_gpio3: gpio3grp {
998
+
fsl,pins = <IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021>;
999
+
};
1000
+
1001
+
/* Apalis GPIO4 */
1002
+
pinctrl_gpio4: gpio4grp {
1003
+
fsl,pins = <IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021>;
1004
+
};
1005
+
1006
+
/* Apalis GPIO5 */
1007
+
pinctrl_gpio5: gpio5grp {
1008
+
fsl,pins = <IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021>;
1009
+
};
1010
+
1011
+
/* Apalis GPIO6 */
1012
+
pinctrl_gpio6: gpio6grp {
1013
+
fsl,pins = <IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x00000021>;
1014
+
};
1015
+
1016
+
/* Apalis GPIO7 */
1017
+
pinctrl_gpio7: gpio7grp {
1018
+
fsl,pins = <IMX8QM_MLB_SIG_LSIO_GPIO3_IO26 0x00000021>;
1019
+
};
1020
+
1021
+
/* Apalis GPIO8 */
1022
+
pinctrl_gpio8: gpio8grp {
1023
+
fsl,pins = <IMX8QM_MLB_DATA_LSIO_GPIO3_IO28 0x00000021>;
1024
+
};
1025
+
1026
+
/* Apalis BKL1_ON */
1027
+
pinctrl_gpio_bkl_on: gpiobklongrp {
1028
+
fsl,pins = <IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04 0x00000021>;
1029
+
};
1030
+
1031
+
/* Apalis WAKE1_MICO */
1032
+
pinctrl_gpio_keys: gpiokeysgrp {
1033
+
fsl,pins = <IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20 0x06700021>;
1034
+
};
1035
+
1036
+
/* Apalis USBH_OC# */
1037
+
pinctrl_gpio_usbh_oc_n: gpiousbhocngrp {
1038
+
fsl,pins = <IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x04000021>;
1039
+
};
1040
+
1041
+
/* On-module HDMI_CTRL */
1042
+
pinctrl_hdmi_ctrl: hdmictrlgrp {
1043
+
fsl,pins = <IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0x00000061>;
1044
+
};
1045
+
1046
+
/* On-module I2C */
1047
+
pinctrl_lpi2c1: lpi2c1grp {
1048
+
fsl,pins = <IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x04000020>,
1049
+
<IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x04000020>;
1050
+
};
1051
+
1052
+
/* Apalis I2C1 */
1053
+
pinctrl_lpi2c2: lpi2c2grp {
1054
+
fsl,pins = <IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0x04000020>,
1055
+
<IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0x04000020>;
1056
+
};
1057
+
1058
+
/* Apalis I2C3 (CAM) */
1059
+
pinctrl_lpi2c3: lpi2c3grp {
1060
+
fsl,pins = <IMX8QM_SIM0_PD_DMA_I2C3_SCL 0x04000020>,
1061
+
<IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA 0x04000020>;
1062
+
};
1063
+
1064
+
/* Apalis SPI1 */
1065
+
pinctrl_lpspi0: lpspi0grp {
1066
+
fsl,pins = <IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x0600004c>,
1067
+
<IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x0600004c>,
1068
+
<IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x0600004c>,
1069
+
<IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 0x0600004c>;
1070
+
};
1071
+
1072
+
/* Apalis SPI2 */
1073
+
pinctrl_lpspi2: lpspi2grp {
1074
+
fsl,pins = <IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c>,
1075
+
<IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c>,
1076
+
<IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c>,
1077
+
<IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x0600004c>;
1078
+
};
1079
+
1080
+
/* Apalis UART3 */
1081
+
pinctrl_lpuart0: lpuart0grp {
1082
+
fsl,pins = <IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020>,
1083
+
<IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020>;
1084
+
};
1085
+
1086
+
/* Apalis UART1 */
1087
+
pinctrl_lpuart1: lpuart1grp {
1088
+
fsl,pins = <IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020>,
1089
+
<IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020>,
1090
+
<IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020>,
1091
+
<IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020>;
1092
+
};
1093
+
1094
+
/* Apalis UART1 */
1095
+
pinctrl_lpuart1ctrl: lpuart1ctrlgrp {
1096
+
fsl,pins = /* Apalis UART1_DTR */
1097
+
<IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06 0x00000021>,
1098
+
/* Apalis UART1_DSR */
1099
+
<IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07 0x00000021>,
1100
+
/* Apalis UART1_DCD */
1101
+
<IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10 0x00000021>,
1102
+
/* Apalis UART1_RI */
1103
+
<IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11 0x00000021>;
1104
+
};
1105
+
1106
+
/* Apalis UART4 */
1107
+
pinctrl_lpuart2: lpuart2grp {
1108
+
fsl,pins = <IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020>,
1109
+
<IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020>;
1110
+
};
1111
+
1112
+
/* Apalis UART2 */
1113
+
pinctrl_lpuart3: lpuart3grp {
1114
+
fsl,pins = <IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020>,
1115
+
<IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020>,
1116
+
<IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020>,
1117
+
<IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020>;
1118
+
};
1119
+
1120
+
/* Apalis TS_2 */
1121
+
pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpiogrp {
1122
+
fsl,pins = <IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x00000021>;
1123
+
};
1124
+
1125
+
/* Apalis LCD1_G6+7 */
1126
+
pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp {
1127
+
fsl,pins = /* Apalis LCD1_G6 */
1128
+
<IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x00000021>,
1129
+
/* Apalis LCD1_G7 */
1130
+
<IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x00000021>;
1131
+
};
1132
+
1133
+
/* Apalis TS_3 */
1134
+
pinctrl_mipi_dsi_0_1_en: mipidsi0-1engrp {
1135
+
fsl,pins = <IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021>;
1136
+
};
1137
+
1138
+
/* Apalis TS_4 */
1139
+
pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp {
1140
+
fsl,pins = <IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021>;
1141
+
};
1142
+
1143
+
/* Apalis TS_1 */
1144
+
pinctrl_mlb_gpios: mlbgpiosgrp {
1145
+
fsl,pins = <IMX8QM_MLB_CLK_LSIO_GPIO3_IO27 0x00000021>;
1146
+
};
1147
+
1148
+
/* Apalis MMC1_CD# */
1149
+
pinctrl_mmc1_cd: mmc1cdgrp {
1150
+
fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021>;
1151
+
};
1152
+
1153
+
pinctrl_mmc1_cd_sleep: mmc1cdsleepgrp {
1154
+
fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x04000021>;
1155
+
};
1156
+
1157
+
/* On-module PCIe_Wi-Fi */
1158
+
pinctrl_pcieb: pciebgrp {
1159
+
fsl,pins = <IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x00000021>,
1160
+
<IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x00000021>,
1161
+
<IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x00000021>;
1162
+
};
1163
+
1164
+
/* On-module PCIe_CLK_EN1 */
1165
+
pinctrl_pcie_sata_refclk: pciesatarefclkgrp {
1166
+
fsl,pins = <IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021>;
1167
+
};
1168
+
1169
+
/* On-module PCIe_CLK_EN2 */
1170
+
pinctrl_pcie_wifi_refclk: pciewifirefclkgrp {
1171
+
fsl,pins = <IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 0x00000021>;
1172
+
};
1173
+
1174
+
/* Apalis PWM3 */
1175
+
pinctrl_pwm0: pwm0grp {
1176
+
fsl,pins = <IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT 0x00000020>;
1177
+
};
1178
+
1179
+
/* Apalis PWM4 */
1180
+
pinctrl_pwm1: pwm1grp {
1181
+
fsl,pins = <IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT 0x00000020>;
1182
+
};
1183
+
1184
+
/* Apalis PWM1 */
1185
+
pinctrl_pwm2: pwm2grp {
1186
+
fsl,pins = <IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT 0x00000020>;
1187
+
};
1188
+
1189
+
/* Apalis PWM2 */
1190
+
pinctrl_pwm3: pwm3grp {
1191
+
fsl,pins = <IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT 0x00000020>;
1192
+
};
1193
+
1194
+
/* Apalis BKL1_PWM */
1195
+
pinctrl_pwm_bkl: pwmbklgrp {
1196
+
fsl,pins = <IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020>;
1197
+
};
1198
+
1199
+
/* Apalis LCD1_ */
1200
+
pinctrl_qspi1a_gpios: qspi1agpiosgrp {
1201
+
fsl,pins = /* Apalis LCD1_B0 */
1202
+
<IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021>,
1203
+
/* Apalis LCD1_B1 */
1204
+
<IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x00000021>,
1205
+
/* Apalis LCD1_B2 */
1206
+
<IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x00000021>,
1207
+
/* Apalis LCD1_B3 */
1208
+
<IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x00000021>,
1209
+
/* Apalis LCD1_B5 */
1210
+
<IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021>,
1211
+
/* Apalis LCD1_B7 */
1212
+
<IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21 0x00000021>,
1213
+
/* Apalis LCD1_B4 */
1214
+
<IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x00000021>,
1215
+
/* Apalis LCD1_B6 */
1216
+
<IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x00000021>;
1217
+
};
1218
+
1219
+
/* On-module RESET_MOCI#_DRV */
1220
+
pinctrl_reset_moci: resetmocigrp {
1221
+
fsl,pins = <IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021>;
1222
+
};
1223
+
1224
+
/* On-module I2S SGTL5000 for Apalis Analogue Audio */
1225
+
pinctrl_sai1: sai1grp {
1226
+
fsl,pins = <IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0xc600006c>,
1227
+
<IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0xc600004c>,
1228
+
<IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0xc600004c>,
1229
+
<IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0xc600004c>;
1230
+
};
1231
+
1232
+
/* Apalis SATA1_ACT# */
1233
+
pinctrl_sata1_act: sata1actgrp {
1234
+
fsl,pins = <IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021>;
1235
+
};
1236
+
1237
+
/* Apalis SD1_CD# */
1238
+
pinctrl_sd1_cd: sd1cdgrp {
1239
+
fsl,pins = <IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021>;
1240
+
};
1241
+
1242
+
/* On-module I2S SGTL5000 SYS_MCLK */
1243
+
pinctrl_sgtl5000: sgtl5000grp {
1244
+
fsl,pins = <IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c>;
1245
+
};
1246
+
1247
+
/* Apalis LCD1_ */
1248
+
pinctrl_sim0_gpios: sim0gpiosgrp {
1249
+
fsl,pins = /* Apalis LCD1_G5 */
1250
+
<IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021>,
1251
+
/* Apalis LCD1_G3 */
1252
+
<IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021>,
1253
+
/* Apalis TS_5 */
1254
+
<IMX8QM_SIM0_IO_LSIO_GPIO0_IO02 0x00000021>,
1255
+
/* Apalis LCD1_G4 */
1256
+
<IMX8QM_SIM0_RST_LSIO_GPIO0_IO01 0x00000021>;
1257
+
};
1258
+
1259
+
/* Apalis SPDIF */
1260
+
pinctrl_spdif0: spdif0grp {
1261
+
fsl,pins = <IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040>,
1262
+
<IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040>;
1263
+
};
1264
+
1265
+
pinctrl_touchctrl_gpios: touchctrlgpiosgrp {
1266
+
fsl,pins = <IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000021>,
1267
+
<IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041>,
1268
+
<IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17 0x00000021>,
1269
+
<IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21 0x00000041>;
1270
+
};
1271
+
1272
+
pinctrl_touchctrl_idle: touchctrlidlegrp {
1273
+
fsl,pins = <IMX8QM_ADC_IN4_LSIO_GPIO3_IO22 0x00000021>,
1274
+
<IMX8QM_ADC_IN5_LSIO_GPIO3_IO23 0x00000021>,
1275
+
<IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021>,
1276
+
<IMX8QM_ADC_IN7_LSIO_GPIO3_IO25 0x00000021>;
1277
+
};
1278
+
1279
+
/* On-module USB HSIC HUB (active) */
1280
+
pinctrl_usb_hsic_active: usbh1activegrp {
1281
+
fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0x000000cf>,
1282
+
<IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0x000000ff>;
1283
+
};
1284
+
1285
+
/* On-module USB HSIC HUB (idle) */
1286
+
pinctrl_usb_hsic_idle: usbh1idlegrp {
1287
+
fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0x000000cf>,
1288
+
<IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0x000000cf>;
1289
+
};
1290
+
1291
+
/* On-module USB HSIC HUB */
1292
+
pinctrl_usb3503a: usb3503agrp {
1293
+
fsl,pins = /* On-module HSIC_HUB_CONNECT */
1294
+
<IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x00000041>,
1295
+
/* On-module HSIC_INT_N */
1296
+
<IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01 0x00000021>,
1297
+
/* On-module HSIC_RESET_N */
1298
+
<IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02 0x00000041>;
1299
+
};
1300
+
1301
+
/* Apalis USBH_EN */
1302
+
pinctrl_usbh_en: usbhengrp {
1303
+
fsl,pins = <IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021>;
1304
+
};
1305
+
1306
+
/* Apalis USBO1 */
1307
+
pinctrl_usbotg1: usbotg1grp {
1308
+
fsl,pins = /* Apalis USBO1_EN */
1309
+
<IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>,
1310
+
/* Apalis USBO1_OC# */
1311
+
<IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC 0x04000021>;
1312
+
};
1313
+
1314
+
/* On-module eMMC */
1315
+
pinctrl_usdhc1: usdhc1grp {
1316
+
fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
1317
+
<IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
1318
+
<IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
1319
+
<IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
1320
+
<IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
1321
+
<IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
1322
+
<IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
1323
+
<IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
1324
+
<IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
1325
+
<IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
1326
+
<IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041>,
1327
+
<IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;
1328
+
};
1329
+
1330
+
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1331
+
fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>,
1332
+
<IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020>,
1333
+
<IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020>,
1334
+
<IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020>,
1335
+
<IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020>,
1336
+
<IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020>,
1337
+
<IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020>,
1338
+
<IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020>,
1339
+
<IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020>,
1340
+
<IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020>,
1341
+
<IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040>,
1342
+
<IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020>;
1343
+
};
1344
+
1345
+
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1346
+
fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>,
1347
+
<IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020>,
1348
+
<IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020>,
1349
+
<IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020>,
1350
+
<IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020>,
1351
+
<IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020>,
1352
+
<IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020>,
1353
+
<IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020>,
1354
+
<IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020>,
1355
+
<IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020>,
1356
+
<IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040>,
1357
+
<IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020>;
1358
+
};
1359
+
1360
+
/* Apalis TS_6 */
1361
+
pinctrl_usdhc1_gpios: usdhc1gpiosgrp {
1362
+
fsl,pins = <IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021>;
1363
+
};
1364
+
1365
+
/* Apalis MMC1 */
1366
+
pinctrl_usdhc2_4bit: usdhc2grp4bitgrp {
1367
+
fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>,
1368
+
<IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>,
1369
+
<IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>,
1370
+
<IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>,
1371
+
<IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>,
1372
+
<IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>,
1373
+
/* On-module PMIC use */
1374
+
<IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
1375
+
};
1376
+
1377
+
pinctrl_usdhc2_4bit_100mhz: usdhc2-4bit100mhzgrp {
1378
+
fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
1379
+
<IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
1380
+
<IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
1381
+
<IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
1382
+
<IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
1383
+
<IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
1384
+
/* On-module PMIC use */
1385
+
<IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
1386
+
};
1387
+
1388
+
pinctrl_usdhc2_4bit_200mhz: usdhc2-4bit200mhzgrp {
1389
+
fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
1390
+
<IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
1391
+
<IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
1392
+
<IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
1393
+
<IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
1394
+
<IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
1395
+
/* On-module PMIC use */
1396
+
<IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
1397
+
};
1398
+
1399
+
pinctrl_usdhc2_8bit: usdhc2grp8bitgrp {
1400
+
fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021>,
1401
+
<IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021>,
1402
+
<IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021>,
1403
+
<IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021>;
1404
+
};
1405
+
1406
+
pinctrl_usdhc2_8bit_100mhz: usdhc2-8bit100mhzgrp {
1407
+
fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020>,
1408
+
<IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020>,
1409
+
<IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020>,
1410
+
<IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020>;
1411
+
};
1412
+
1413
+
pinctrl_usdhc2_8bit_200mhz: usdhc2-8bit200mhzgrp {
1414
+
fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020>,
1415
+
<IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020>,
1416
+
<IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020>,
1417
+
<IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020>;
1418
+
};
1419
+
1420
+
pinctrl_usdhc2_4bit_sleep: usdhc2-4bitsleepgrp {
1421
+
fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x04000061>,
1422
+
<IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x04000061>,
1423
+
<IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x04000061>,
1424
+
<IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x04000061>,
1425
+
<IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x04000061>,
1426
+
<IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x04000061>,
1427
+
/* On-module PMIC use */
1428
+
<IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
1429
+
};
1430
+
1431
+
pinctrl_usdhc2_8bit_sleep: usdhc2-8bitsleepgrp {
1432
+
fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x04000061>,
1433
+
<IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x04000061>,
1434
+
<IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x04000061>,
1435
+
<IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x04000061>;
1436
+
};
1437
+
1438
+
/* Apalis SD1 */
1439
+
pinctrl_usdhc3: usdhc3grp {
1440
+
fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041>,
1441
+
<IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021>,
1442
+
<IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021>,
1443
+
<IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021>,
1444
+
<IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021>,
1445
+
<IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021>,
1446
+
/* On-module PMIC use */
1447
+
<IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021>;
1448
+
};
1449
+
1450
+
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1451
+
fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041>,
1452
+
<IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021>,
1453
+
<IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021>,
1454
+
<IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021>,
1455
+
<IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021>,
1456
+
<IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021>,
1457
+
/* On-module PMIC use */
1458
+
<IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021>;
1459
+
};
1460
+
1461
+
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1462
+
fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041>,
1463
+
<IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021>,
1464
+
<IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021>,
1465
+
<IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021>,
1466
+
<IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021>,
1467
+
<IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021>,
1468
+
/* On-module PMIC use */
1469
+
<IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021>;
1470
+
};
1471
+
1472
+
/* On-module Wi-Fi */
1473
+
pinctrl_wifi: wifigrp {
1474
+
fsl,pins = /* On-module Wi-Fi_SUSCLK_32k */
1475
+
<IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x06000021>,
1476
+
/* On-module Wi-Fi_PCIE_W_DISABLE */
1477
+
<IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x06000021>;
1478
+
};
1479
+
1480
+
pinctrl_wifi_pdn: wifipdngrp {
1481
+
fsl,pins = /* On-module Wi-Fi_POWER_DOWN */
1482
+
<IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021>;
1483
+
};
1484
+
};
+69
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+69
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
···
138
138
status = "disabled";
139
139
};
140
140
141
+
usbotg3: usb@5b110000 {
142
+
compatible = "fsl,imx8qm-usb3";
143
+
reg = <0x5b110000 0x10000>;
144
+
#address-cells = <1>;
145
+
#size-cells = <1>;
146
+
ranges;
147
+
clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
148
+
<&usb3_lpcg IMX_LPCG_CLK_0>,
149
+
<&usb3_lpcg IMX_LPCG_CLK_7>,
150
+
<&usb3_lpcg IMX_LPCG_CLK_4>,
151
+
<&usb3_lpcg IMX_LPCG_CLK_5>;
152
+
clock-names = "lpm", "bus", "aclk", "ipg", "core";
153
+
assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
154
+
assigned-clock-rates = <250000000>;
155
+
power-domains = <&pd IMX_SC_R_USB_2>;
156
+
status = "disabled";
157
+
158
+
usbotg3_cdns3: usb@5b120000 {
159
+
compatible = "cdns,usb3";
160
+
reg = <0x5b130000 0x10000>, /* memory area for HOST registers */
161
+
<0x5b140000 0x10000>, /* memory area for DEVICE registers */
162
+
<0x5b120000 0x10000>; /* memory area for OTG/DRD registers */
163
+
reg-names = "xhci", "dev", "otg";
164
+
#address-cells = <1>;
165
+
#size-cells = <1>;
166
+
interrupt-parent = <&gic>;
167
+
interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
168
+
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
169
+
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
170
+
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
171
+
interrupt-names = "host", "peripheral", "otg", "wakeup";
172
+
phys = <&usb3_phy>;
173
+
phy-names = "cdns3,usb3-phy";
174
+
status = "disabled";
175
+
};
176
+
};
177
+
178
+
usb3_phy: usb-phy@5b160000 {
179
+
compatible = "nxp,salvo-phy";
180
+
reg = <0x5b160000 0x40000>;
181
+
clocks = <&usb3_lpcg IMX_LPCG_CLK_6>;
182
+
clock-names = "salvo_phy_clk";
183
+
power-domains = <&pd IMX_SC_R_USB_2_PHY>;
184
+
#phy-cells = <0>;
185
+
status = "disabled";
186
+
};
187
+
141
188
/* LPCG clocks */
142
189
sdhc0_lpcg: clock-controller@5b200000 {
143
190
compatible = "fsl,imx8qxp-lpcg";
···
280
233
clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
281
234
clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
282
235
power-domains = <&pd IMX_SC_R_USB_0_PHY>;
236
+
};
237
+
238
+
usb3_lpcg: clock-controller@5b280000 {
239
+
compatible = "fsl,imx8qxp-lpcg";
240
+
reg = <0x5b280000 0x10000>;
241
+
#clock-cells = <1>;
242
+
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
243
+
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
244
+
<IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
245
+
clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
246
+
<&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
247
+
<&conn_ipg_clk>,
248
+
<&conn_ipg_clk>,
249
+
<&conn_ipg_clk>,
250
+
<&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
251
+
clock-output-names = "usb3_app_clk",
252
+
"usb3_lpm_clk",
253
+
"usb3_ipg_clk",
254
+
"usb3_core_pclk",
255
+
"usb3_phy_clk",
256
+
"usb3_aclk";
257
+
power-domains = <&pd IMX_SC_R_USB_2_PHY>;
283
258
};
284
259
};
+75
-1
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+75
-1
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
···
31
31
<&spi0_lpcg 1>;
32
32
clock-names = "per", "ipg";
33
33
assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
34
-
assigned-clock-rates = <20000000>;
34
+
assigned-clock-rates = <60000000>;
35
35
power-domains = <&pd IMX_SC_R_SPI_0>;
36
36
status = "disabled";
37
37
};
···
270
270
271
271
adc0: adc@5a880000 {
272
272
compatible = "nxp,imx8qxp-adc";
273
+
#io-channel-cells = <1>;
273
274
reg = <0x5a880000 0x10000>;
274
275
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
275
276
interrupt-parent = <&gic>;
···
285
284
286
285
adc1: adc@5a890000 {
287
286
compatible = "nxp,imx8qxp-adc";
287
+
#io-channel-cells = <1>;
288
288
reg = <0x5a890000 0x10000>;
289
289
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
290
290
interrupt-parent = <&gic>;
···
295
293
assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
296
294
assigned-clock-rates = <24000000>;
297
295
power-domains = <&pd IMX_SC_R_ADC_1>;
296
+
status = "disabled";
297
+
};
298
+
299
+
flexcan1: can@5a8d0000 {
300
+
compatible = "fsl,imx8qm-flexcan";
301
+
reg = <0x5a8d0000 0x10000>;
302
+
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
303
+
interrupt-parent = <&gic>;
304
+
clocks = <&can0_lpcg 1>,
305
+
<&can0_lpcg 0>;
306
+
clock-names = "ipg", "per";
307
+
assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
308
+
assigned-clock-rates = <40000000>;
309
+
power-domains = <&pd IMX_SC_R_CAN_0>;
310
+
/* SLSlice[4] */
311
+
fsl,clk-source = /bits/ 8 <0>;
312
+
fsl,scu-index = /bits/ 8 <0>;
313
+
status = "disabled";
314
+
};
315
+
316
+
flexcan2: can@5a8e0000 {
317
+
compatible = "fsl,imx8qm-flexcan";
318
+
reg = <0x5a8e0000 0x10000>;
319
+
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
320
+
interrupt-parent = <&gic>;
321
+
/* CAN0 clock and PD is shared among all CAN instances as
322
+
* CAN1 shares CAN0's clock and to enable CAN0's clock it
323
+
* has to be powered on.
324
+
*/
325
+
clocks = <&can0_lpcg 1>,
326
+
<&can0_lpcg 0>;
327
+
clock-names = "ipg", "per";
328
+
assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
329
+
assigned-clock-rates = <40000000>;
330
+
power-domains = <&pd IMX_SC_R_CAN_1>;
331
+
/* SLSlice[4] */
332
+
fsl,clk-source = /bits/ 8 <0>;
333
+
fsl,scu-index = /bits/ 8 <1>;
334
+
status = "disabled";
335
+
};
336
+
337
+
flexcan3: can@5a8f0000 {
338
+
compatible = "fsl,imx8qm-flexcan";
339
+
reg = <0x5a8f0000 0x10000>;
340
+
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
341
+
interrupt-parent = <&gic>;
342
+
/* CAN0 clock and PD is shared among all CAN instances as
343
+
* CAN2 shares CAN0's clock and to enable CAN0's clock it
344
+
* has to be powered on.
345
+
*/
346
+
clocks = <&can0_lpcg 1>,
347
+
<&can0_lpcg 0>;
348
+
clock-names = "ipg", "per";
349
+
assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
350
+
assigned-clock-rates = <40000000>;
351
+
power-domains = <&pd IMX_SC_R_CAN_2>;
352
+
/* SLSlice[4] */
353
+
fsl,clk-source = /bits/ 8 <0>;
354
+
fsl,scu-index = /bits/ 8 <2>;
298
355
status = "disabled";
299
356
};
300
357
···
427
366
clock-output-names = "adc1_lpcg_clk",
428
367
"adc1_lpcg_ipg_clk";
429
368
power-domains = <&pd IMX_SC_R_ADC_1>;
369
+
};
370
+
371
+
can0_lpcg: clock-controller@5acd0000 {
372
+
compatible = "fsl,imx8qxp-lpcg";
373
+
reg = <0x5acd0000 0x10000>;
374
+
#clock-cells = <1>;
375
+
clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>,
376
+
<&dma_ipg_clk>, <&dma_ipg_clk>;
377
+
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
378
+
clock-output-names = "can0_lpcg_pe_clk",
379
+
"can0_lpcg_ipg_clk",
380
+
"can0_lpcg_chi_clk";
381
+
power-domains = <&pd IMX_SC_R_CAN_0>;
430
382
};
431
383
};
+48
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+48
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
···
28
28
clock-output-names = "lsio_bus_clk";
29
29
};
30
30
31
+
lsio_pwm0: pwm@5d000000 {
32
+
compatible = "fsl,imx27-pwm";
33
+
reg = <0x5d000000 0x10000>;
34
+
clock-names = "ipg", "per";
35
+
clocks = <&pwm0_lpcg 4>,
36
+
<&pwm0_lpcg 1>;
37
+
assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
38
+
assigned-clock-rates = <24000000>;
39
+
#pwm-cells = <2>;
40
+
status = "disabled";
41
+
};
42
+
43
+
lsio_pwm1: pwm@5d010000 {
44
+
compatible = "fsl,imx27-pwm";
45
+
reg = <0x5d010000 0x10000>;
46
+
clock-names = "ipg", "per";
47
+
clocks = <&pwm1_lpcg 4>,
48
+
<&pwm1_lpcg 1>;
49
+
assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
50
+
assigned-clock-rates = <24000000>;
51
+
#pwm-cells = <2>;
52
+
status = "disabled";
53
+
};
54
+
55
+
lsio_pwm2: pwm@5d020000 {
56
+
compatible = "fsl,imx27-pwm";
57
+
reg = <0x5d020000 0x10000>;
58
+
clock-names = "ipg", "per";
59
+
clocks = <&pwm2_lpcg 4>,
60
+
<&pwm2_lpcg 1>;
61
+
assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
62
+
assigned-clock-rates = <24000000>;
63
+
#pwm-cells = <2>;
64
+
status = "disabled";
65
+
};
66
+
67
+
lsio_pwm3: pwm@5d030000 {
68
+
compatible = "fsl,imx27-pwm";
69
+
reg = <0x5d030000 0x10000>;
70
+
clock-names = "ipg", "per";
71
+
clocks = <&pwm3_lpcg 4>,
72
+
<&pwm3_lpcg 1>;
73
+
assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
74
+
assigned-clock-rates = <24000000>;
75
+
#pwm-cells = <2>;
76
+
status = "disabled";
77
+
};
78
+
31
79
lsio_gpio0: gpio@5d080000 {
32
80
reg = <0x5d080000 0x10000>;
33
81
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+1
-1
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+1
-3
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+1
-3
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
···
130
130
clk: clock-controller {
131
131
compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
132
132
#clock-cells = <2>;
133
-
clocks = <&xtal32k &xtal24m>;
134
-
clock-names = "xtal_32KHz", "xtal_24Mhz";
135
133
};
136
134
137
135
scu_gpio: gpio {
···
186
188
};
187
189
188
190
thermal_zones: thermal-zones {
189
-
cpu-thermal0 {
191
+
cpu-thermal {
190
192
polling-delay-passive = <250>;
191
193
polling-delay = <2000>;
192
194
thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
+1
-1
arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts
+2
-2
arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi
+2
-2
arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi
···
124
124
>;
125
125
};
126
126
127
-
pinctrl_ecspi1_cs: ecspi1-cs {
127
+
pinctrl_ecspi1_cs: ecspi1cs-grp {
128
128
fsl,pins = <
129
129
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000
130
130
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000
···
215
215
>;
216
216
};
217
217
218
-
pinctrl_pmic: pmic-irq {
218
+
pinctrl_pmic: pmicirq-grp {
219
219
fsl,pins = <
220
220
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x41
221
221
>;
+13
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
+13
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
···
168
168
"", "ECSPI1_SS0";
169
169
};
170
170
171
+
&i2c4 {
172
+
clock-frequency = <400000>;
173
+
pinctrl-names = "default";
174
+
pinctrl-0 = <&pinctrl_i2c4>;
175
+
};
176
+
171
177
/* PCIe */
172
178
&pcie0 {
173
179
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
···
336
330
pinctrl_fan: fan0grp {
337
331
fsl,pins = <
338
332
MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
333
+
>;
334
+
};
335
+
336
+
pinctrl_i2c4: i2c4grp {
337
+
fsl,pins = <
338
+
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
339
+
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
339
340
>;
340
341
};
341
342
+2
-2
arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts
+2
-2
arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts
···
264
264
>;
265
265
};
266
266
267
-
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
267
+
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
268
268
fsl,pins = <
269
269
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
270
270
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
···
280
280
>;
281
281
};
282
282
283
-
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
283
+
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
284
284
fsl,pins = <
285
285
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
286
286
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+79
arch/arm64/boot/dts/freescale/imx8mm.dtsi
+79
arch/arm64/boot/dts/freescale/imx8mm.dtsi
···
1119
1119
#size-cells = <1>;
1120
1120
ranges = <0x32c00000 0x32c00000 0x400000>;
1121
1121
1122
+
lcdif: lcdif@32e00000 {
1123
+
compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
1124
+
reg = <0x32e00000 0x10000>;
1125
+
clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
1126
+
<&clk IMX8MM_CLK_DISP_APB_ROOT>,
1127
+
<&clk IMX8MM_CLK_DISP_AXI_ROOT>;
1128
+
clock-names = "pix", "axi", "disp_axi";
1129
+
assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
1130
+
<&clk IMX8MM_CLK_DISP_AXI>,
1131
+
<&clk IMX8MM_CLK_DISP_APB>;
1132
+
assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
1133
+
<&clk IMX8MM_SYS_PLL2_1000M>,
1134
+
<&clk IMX8MM_SYS_PLL1_800M>;
1135
+
assigned-clock-rates = <594000000>, <500000000>, <200000000>;
1136
+
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1137
+
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
1138
+
status = "disabled";
1139
+
1140
+
port {
1141
+
lcdif_to_dsim: endpoint {
1142
+
remote-endpoint = <&dsim_from_lcdif>;
1143
+
};
1144
+
};
1145
+
};
1146
+
1147
+
mipi_dsi: dsi@32e10000 {
1148
+
compatible = "fsl,imx8mm-mipi-dsim";
1149
+
reg = <0x32e10000 0x400>;
1150
+
clocks = <&clk IMX8MM_CLK_DSI_CORE>,
1151
+
<&clk IMX8MM_CLK_DSI_PHY_REF>;
1152
+
clock-names = "bus_clk", "sclk_mipi";
1153
+
assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
1154
+
<&clk IMX8MM_CLK_DSI_PHY_REF>;
1155
+
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1156
+
<&clk IMX8MM_CLK_24M>;
1157
+
assigned-clock-rates = <266000000>, <24000000>;
1158
+
samsung,pll-clock-frequency = <24000000>;
1159
+
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1160
+
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
1161
+
status = "disabled";
1162
+
1163
+
ports {
1164
+
#address-cells = <1>;
1165
+
#size-cells = <0>;
1166
+
1167
+
port@0 {
1168
+
reg = <0>;
1169
+
1170
+
dsim_from_lcdif: endpoint {
1171
+
remote-endpoint = <&lcdif_to_dsim>;
1172
+
};
1173
+
};
1174
+
};
1175
+
};
1176
+
1122
1177
csi: csi@32e20000 {
1123
1178
compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
1124
1179
reg = <0x32e20000 0x1000>;
···
1367
1312
reset-names = "apps", "turnoff";
1368
1313
phys = <&pcie_phy>;
1369
1314
phy-names = "pcie-phy";
1315
+
status = "disabled";
1316
+
};
1317
+
1318
+
pcie0_ep: pcie-ep@33800000 {
1319
+
compatible = "fsl,imx8mm-pcie-ep";
1320
+
reg = <0x33800000 0x400000>,
1321
+
<0x18000000 0x8000000>;
1322
+
reg-names = "dbi", "addr_space";
1323
+
num-lanes = <1>;
1324
+
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1325
+
interrupt-names = "dma";
1326
+
fsl,max-link-speed = <2>;
1327
+
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
1328
+
<&clk IMX8MM_CLK_PCIE1_PHY>,
1329
+
<&clk IMX8MM_CLK_PCIE1_AUX>;
1330
+
clock-names = "pcie", "pcie_bus", "pcie_aux";
1331
+
power-domains = <&pgc_pcie>;
1332
+
resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1333
+
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1334
+
reset-names = "apps", "turnoff";
1335
+
phys = <&pcie_phy>;
1336
+
phy-names = "pcie-phy";
1337
+
num-ib-windows = <4>;
1338
+
num-ob-windows = <4>;
1370
1339
status = "disabled";
1371
1340
};
1372
1341
+3
-3
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
+3
-3
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
···
341
341
>;
342
342
};
343
343
344
-
pinctrl_pmic: pmicirq {
344
+
pinctrl_pmic: pmicirqgrp {
345
345
fsl,pins = <
346
346
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040
347
347
>;
···
381
381
>;
382
382
};
383
383
384
-
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
384
+
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
385
385
fsl,pins = <
386
386
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094
387
387
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4
···
392
392
>;
393
393
};
394
394
395
-
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
395
+
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
396
396
fsl,pins = <
397
397
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096
398
398
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6
+1
-1
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts
+2
-2
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts
+2
-2
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts
···
136
136
>;
137
137
};
138
138
139
-
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
139
+
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
140
140
fsl,pins = <
141
141
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094
142
142
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4
···
152
152
>;
153
153
};
154
154
155
-
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
155
+
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
156
156
fsl,pins = <
157
157
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096
158
158
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6
+2
-2
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+2
-2
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
···
389
389
>;
390
390
};
391
391
392
-
pinctrl_i2c2_gpio: i2c2grp-gpio {
392
+
pinctrl_i2c2_gpio: i2c2gpiogrp {
393
393
fsl,pins = <
394
394
MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
395
395
MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
···
403
403
>;
404
404
};
405
405
406
-
pinctrl_i2c3_gpio: i2c3grp-gpio {
406
+
pinctrl_i2c3_gpio: i2c3gpiogrp {
407
407
fsl,pins = <
408
408
MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
409
409
MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
+55
arch/arm64/boot/dts/freescale/imx8mn.dtsi
+55
arch/arm64/boot/dts/freescale/imx8mn.dtsi
···
1057
1057
#size-cells = <1>;
1058
1058
ranges;
1059
1059
1060
+
lcdif: lcdif@32e00000 {
1061
+
compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";
1062
+
reg = <0x32e00000 0x10000>;
1063
+
clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
1064
+
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
1065
+
<&clk IMX8MN_CLK_DISP_AXI_ROOT>;
1066
+
clock-names = "pix", "axi", "disp_axi";
1067
+
assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
1068
+
<&clk IMX8MN_CLK_DISP_AXI>,
1069
+
<&clk IMX8MN_CLK_DISP_APB>;
1070
+
assigned-clock-parents = <&clk IMX8MN_CLK_DISP_PIXEL>,
1071
+
<&clk IMX8MN_SYS_PLL2_1000M>,
1072
+
<&clk IMX8MN_SYS_PLL1_800M>;
1073
+
assigned-clock-rates = <594000000>, <500000000>, <200000000>;
1074
+
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1075
+
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
1076
+
status = "disabled";
1077
+
1078
+
port {
1079
+
lcdif_to_dsim: endpoint {
1080
+
remote-endpoint = <&dsim_from_lcdif>;
1081
+
};
1082
+
};
1083
+
};
1084
+
1085
+
mipi_dsi: dsi@32e10000 {
1086
+
compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";
1087
+
reg = <0x32e10000 0x400>;
1088
+
clocks = <&clk IMX8MN_CLK_DSI_CORE>,
1089
+
<&clk IMX8MN_CLK_DSI_PHY_REF>;
1090
+
clock-names = "bus_clk", "sclk_mipi";
1091
+
assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
1092
+
<&clk IMX8MN_CLK_DSI_PHY_REF>;
1093
+
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1094
+
<&clk IMX8MN_CLK_24M>;
1095
+
assigned-clock-rates = <266000000>, <24000000>;
1096
+
samsung,pll-clock-frequency = <24000000>;
1097
+
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1098
+
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
1099
+
status = "disabled";
1100
+
1101
+
ports {
1102
+
#address-cells = <1>;
1103
+
#size-cells = <0>;
1104
+
1105
+
port@0 {
1106
+
reg = <0>;
1107
+
1108
+
dsim_from_lcdif: endpoint {
1109
+
remote-endpoint = <&lcdif_to_dsim>;
1110
+
};
1111
+
};
1112
+
};
1113
+
};
1114
+
1060
1115
disp_blk_ctrl: blk-ctrl@32e28000 {
1061
1116
compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
1062
1117
reg = <0x32e28000 0x100>;
+977
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
+977
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include <dt-bindings/net/qca-ar803x.h>
9
+
#include "imx8mp.dtsi"
10
+
11
+
/ {
12
+
model = "Data Modul i.MX8M Plus eDM SBC";
13
+
compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp";
14
+
15
+
aliases {
16
+
rtc0 = &rtc;
17
+
rtc1 = &snvs_rtc;
18
+
};
19
+
20
+
chosen {
21
+
stdout-path = &uart3;
22
+
};
23
+
24
+
memory@40000000 {
25
+
device_type = "memory";
26
+
/* There are 1/2/4 GiB options, adjusted by bootloader. */
27
+
reg = <0x0 0x40000000 0 0x40000000>;
28
+
};
29
+
30
+
backlight: backlight {
31
+
compatible = "pwm-backlight";
32
+
pinctrl-names = "default";
33
+
pinctrl-0 = <&pinctrl_panel_backlight>;
34
+
brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
35
+
default-brightness-level = <7>;
36
+
enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
37
+
pwms = <&pwm1 0 5000000 0>;
38
+
/* Disabled by default, unless display board plugged in. */
39
+
status = "disabled";
40
+
};
41
+
42
+
clk_xtal25: clock-xtal25 {
43
+
compatible = "fixed-clock";
44
+
#clock-cells = <0>;
45
+
clock-frequency = <25000000>;
46
+
};
47
+
48
+
panel: panel {
49
+
/* Compatible string is filled in by panel board DT Overlay. */
50
+
backlight = <&backlight>;
51
+
power-supply = <®_panel_vcc>;
52
+
/* Disabled by default, unless display board plugged in. */
53
+
status = "disabled";
54
+
};
55
+
56
+
reg_panel_vcc: regulator-panel-vcc {
57
+
compatible = "regulator-fixed";
58
+
pinctrl-names = "default";
59
+
pinctrl-0 = <&pinctrl_panel_vcc_reg>;
60
+
regulator-min-microvolt = <5000000>;
61
+
regulator-max-microvolt = <5000000>;
62
+
regulator-name = "PANEL_VCC";
63
+
/* GPIO flags are ignored, enable-active-high applies. */
64
+
gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>;
65
+
enable-active-high;
66
+
/* Disabled by default, unless display board plugged in. */
67
+
status = "disabled";
68
+
};
69
+
70
+
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
71
+
compatible = "regulator-fixed";
72
+
pinctrl-names = "default";
73
+
pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
74
+
regulator-max-microvolt = <3300000>;
75
+
regulator-min-microvolt = <3300000>;
76
+
regulator-name = "VDD_3V3_SD";
77
+
/* GPIO flags are ignored, enable-active-high applies. */
78
+
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; /* SD2_RESET */
79
+
enable-active-high;
80
+
off-on-delay-us = <12000>;
81
+
startup-delay-us = <100>;
82
+
vin-supply = <&buck4>;
83
+
};
84
+
85
+
watchdog { /* TPS3813 */
86
+
compatible = "linux,wdt-gpio";
87
+
pinctrl-names = "default";
88
+
pinctrl-0 = <&pinctrl_watchdog_gpio>;
89
+
always-running;
90
+
gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
91
+
hw_algo = "level";
92
+
/* Reset triggers in 2..3 seconds */
93
+
hw_margin_ms = <1500>;
94
+
/* Disabled by default */
95
+
status = "disabled";
96
+
};
97
+
};
98
+
99
+
&A53_0 {
100
+
cpu-supply = <&buck2>;
101
+
};
102
+
103
+
&A53_1 {
104
+
cpu-supply = <&buck2>;
105
+
};
106
+
107
+
&A53_2 {
108
+
cpu-supply = <&buck2>;
109
+
};
110
+
111
+
&A53_3 {
112
+
cpu-supply = <&buck2>;
113
+
};
114
+
115
+
&ecspi1 {
116
+
pinctrl-names = "default";
117
+
pinctrl-0 = <&pinctrl_ecspi1>;
118
+
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
119
+
status = "okay";
120
+
121
+
flash@0 { /* W25Q128JVEI */
122
+
compatible = "jedec,spi-nor";
123
+
reg = <0>;
124
+
spi-max-frequency = <100000000>; /* Up to 133 MHz */
125
+
spi-tx-bus-width = <1>;
126
+
spi-rx-bus-width = <1>;
127
+
};
128
+
};
129
+
130
+
&ecspi2 { /* Feature connector SPI */
131
+
pinctrl-names = "default";
132
+
pinctrl-0 = <&pinctrl_ecspi2>;
133
+
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
134
+
/* Disabled by default, unless feature board plugged in. */
135
+
status = "disabled";
136
+
};
137
+
138
+
&ecspi3 { /* Display connector SPI */
139
+
pinctrl-names = "default";
140
+
pinctrl-0 = <&pinctrl_ecspi3>;
141
+
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
142
+
/* Disabled by default, unless display board plugged in. */
143
+
status = "disabled";
144
+
};
145
+
146
+
&eqos { /* First ethernet */
147
+
pinctrl-names = "default";
148
+
pinctrl-0 = <&pinctrl_eqos>;
149
+
phy-handle = <&phy_eqos>;
150
+
phy-mode = "rgmii-id";
151
+
status = "okay";
152
+
153
+
mdio {
154
+
compatible = "snps,dwmac-mdio";
155
+
#address-cells = <1>;
156
+
#size-cells = <0>;
157
+
158
+
/* Atheros AR8031 PHY */
159
+
phy_eqos: ethernet-phy@0 {
160
+
compatible = "ethernet-phy-ieee802.3-c22";
161
+
reg = <0>;
162
+
/*
163
+
* Dedicated ENET_WOL# signal is unused, the PHY
164
+
* can wake the SoC up via INT signal as well.
165
+
*/
166
+
interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
167
+
reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
168
+
reset-assert-us = <10000>;
169
+
reset-deassert-us = <10000>;
170
+
qca,keep-pll-enabled;
171
+
vddio-supply = <&vddio_eqos>;
172
+
173
+
vddio_eqos: vddio-regulator {
174
+
regulator-name = "VDDIO_EQOS";
175
+
regulator-min-microvolt = <1800000>;
176
+
regulator-max-microvolt = <1800000>;
177
+
};
178
+
179
+
vddh_eqos: vddh-regulator {
180
+
regulator-name = "VDDH_EQOS";
181
+
};
182
+
};
183
+
};
184
+
};
185
+
186
+
&fec { /* Second ethernet */
187
+
pinctrl-names = "default";
188
+
pinctrl-0 = <&pinctrl_fec>;
189
+
phy-handle = <&phy_fec>;
190
+
phy-mode = "rgmii-id";
191
+
fsl,magic-packet;
192
+
status = "okay";
193
+
194
+
mdio {
195
+
#address-cells = <1>;
196
+
#size-cells = <0>;
197
+
198
+
/* Atheros AR8031 PHY */
199
+
phy_fec: ethernet-phy@0 {
200
+
compatible = "ethernet-phy-ieee802.3-c22";
201
+
reg = <0>;
202
+
/*
203
+
* Dedicated ENET_WOL# signal is unused, the PHY
204
+
* can wake the SoC up via INT signal as well.
205
+
*/
206
+
interrupts-extended = <&gpio2 2 IRQ_TYPE_LEVEL_LOW>;
207
+
reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
208
+
reset-assert-us = <10000>;
209
+
reset-deassert-us = <10000>;
210
+
qca,keep-pll-enabled;
211
+
vddio-supply = <&vddio_fec>;
212
+
213
+
vddio_fec: vddio-regulator {
214
+
regulator-name = "VDDIO_FEC";
215
+
regulator-min-microvolt = <1800000>;
216
+
regulator-max-microvolt = <1800000>;
217
+
};
218
+
219
+
vddh_fec: vddh-regulator {
220
+
regulator-name = "VDDH_FEC";
221
+
};
222
+
};
223
+
};
224
+
};
225
+
226
+
&flexcan1 {
227
+
pinctrl-names = "default";
228
+
pinctrl-0 = <&pinctrl_flexcan1>;
229
+
status = "okay";
230
+
};
231
+
232
+
&gpio1 {
233
+
gpio-line-names =
234
+
"", "USBHUB_RESET#", "WDOG_B#", "PMIC_INT#",
235
+
"", "M2_PCIE_RST#", "M2_PCIE_WAKE#", "GPIO5_IO03",
236
+
"GPIO5_IO04", "PDM_SEL", "ENET_WOL#", "ENET_INT#",
237
+
"", "", "", "ENET_RST#",
238
+
"", "", "", "", "", "", "", "",
239
+
"", "", "", "", "", "", "", "";
240
+
};
241
+
242
+
&gpio2 {
243
+
gpio-line-names =
244
+
"", "", "ENET2_INT#", "", "", "", "", "",
245
+
"WDOG_KICK#", "ENET2_RST#", "CAN_INT#", "RTC_IRQ#",
246
+
"", "", "", "",
247
+
"", "", "", "SD2_RESET#", "", "", "", "",
248
+
"", "", "", "", "", "", "", "";
249
+
};
250
+
251
+
&gpio3 {
252
+
gpio-line-names =
253
+
"BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
254
+
"", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
255
+
"CSI2_PD_1V8", "CSI2_RESET_1V8#", "", "",
256
+
"", "", "EEPROM_WP_1V8#", "", "", "", "", "",
257
+
"MEMCFG0", "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#",
258
+
"", "M2_W_DISABLE1_1V8#",
259
+
"M2_W_DISABLE2_1V8#", "", "I2C5_SCL_3V3", "I2C5_SDA_3V3",
260
+
"", "", "", "";
261
+
};
262
+
263
+
&gpio4 {
264
+
gpio-line-names =
265
+
"DSI_RESET_1V8#", "MEMCFG2", "", "MEMCFG1", "", "", "", "",
266
+
"", "", "", "", "", "", "", "",
267
+
"", "", "GRAPHICS_PRSNT_1V8#", "DSI_IRQ_1V8#",
268
+
"", "DIS_USB_DN1", "DIS_USB_DN2", "",
269
+
"", "", "", "", "", "", "", "";
270
+
};
271
+
272
+
&gpio5 {
273
+
gpio-line-names =
274
+
"", "", "", "", "", "WDOG_EN", "", "",
275
+
"", "SPI1_CS#", "", "",
276
+
"", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
277
+
"I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
278
+
"", "", "", "",
279
+
"", "SPI3_CS#", "", "", "", "", "", "";
280
+
};
281
+
282
+
&i2c1 {
283
+
clock-frequency = <100000>;
284
+
pinctrl-names = "default", "gpio";
285
+
pinctrl-0 = <&pinctrl_i2c1>;
286
+
pinctrl-1 = <&pinctrl_i2c1_gpio>;
287
+
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
288
+
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
289
+
status = "okay";
290
+
291
+
usb-hub@2c {
292
+
compatible = "microchip,usb2514bi";
293
+
reg = <0x2c>;
294
+
pinctrl-names = "default";
295
+
pinctrl-0 = <&pinctrl_usb_hub>;
296
+
individual-port-switching;
297
+
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
298
+
self-powered;
299
+
};
300
+
301
+
eeprom: eeprom@50 {
302
+
compatible = "atmel,24c32";
303
+
reg = <0x50>;
304
+
pagesize = <32>;
305
+
};
306
+
307
+
rtc: rtc@68 {
308
+
compatible = "st,m41t62";
309
+
reg = <0x68>;
310
+
pinctrl-names = "default";
311
+
pinctrl-0 = <&pinctrl_rtc>;
312
+
interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
313
+
};
314
+
315
+
pcieclk: clk@6a {
316
+
compatible = "renesas,9fgv0241";
317
+
reg = <0x6a>;
318
+
clocks = <&clk_xtal25>;
319
+
#clock-cells = <1>;
320
+
};
321
+
};
322
+
323
+
&i2c2 {
324
+
clock-frequency = <100000>;
325
+
pinctrl-names = "default", "gpio";
326
+
pinctrl-0 = <&pinctrl_i2c2>;
327
+
pinctrl-1 = <&pinctrl_i2c2_gpio>;
328
+
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
329
+
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
330
+
status = "okay";
331
+
};
332
+
333
+
&i2c3 {
334
+
clock-frequency = <100000>;
335
+
pinctrl-names = "default", "gpio";
336
+
pinctrl-0 = <&pinctrl_i2c3>;
337
+
pinctrl-1 = <&pinctrl_i2c3_gpio>;
338
+
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
339
+
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
340
+
status = "okay";
341
+
342
+
pmic: pmic@25 {
343
+
compatible = "nxp,pca9450c";
344
+
reg = <0x25>;
345
+
pinctrl-names = "default";
346
+
pinctrl-0 = <&pinctrl_pmic>;
347
+
interrupt-parent = <&gpio1>;
348
+
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
349
+
350
+
/*
351
+
* i.MX 8M Plus Data Sheet for Consumer Products
352
+
* 3.1.4 Operating ranges
353
+
* MIMX8ML8CVNKZAB
354
+
*/
355
+
regulators {
356
+
buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
357
+
regulator-min-microvolt = <850000>;
358
+
regulator-max-microvolt = <1000000>;
359
+
regulator-ramp-delay = <3125>;
360
+
regulator-always-on;
361
+
regulator-boot-on;
362
+
};
363
+
364
+
buck2: BUCK2 { /* VDD_ARM */
365
+
regulator-min-microvolt = <850000>;
366
+
regulator-max-microvolt = <1000000>;
367
+
regulator-ramp-delay = <3125>;
368
+
regulator-always-on;
369
+
regulator-boot-on;
370
+
};
371
+
372
+
buck4: BUCK4 { /* VDD_3V3 */
373
+
regulator-min-microvolt = <3300000>;
374
+
regulator-max-microvolt = <3300000>;
375
+
regulator-always-on;
376
+
regulator-boot-on;
377
+
};
378
+
379
+
buck5: BUCK5 { /* VDD_1V8 */
380
+
regulator-min-microvolt = <1800000>;
381
+
regulator-max-microvolt = <1800000>;
382
+
regulator-always-on;
383
+
regulator-boot-on;
384
+
};
385
+
386
+
buck6: BUCK6 { /* NVCC_DRAM_1V1 */
387
+
regulator-min-microvolt = <1100000>;
388
+
regulator-max-microvolt = <1100000>;
389
+
regulator-always-on;
390
+
regulator-boot-on;
391
+
};
392
+
393
+
ldo1: LDO1 { /* NVCC_SNVS_1V8 */
394
+
regulator-min-microvolt = <1800000>;
395
+
regulator-max-microvolt = <1800000>;
396
+
regulator-always-on;
397
+
regulator-boot-on;
398
+
};
399
+
400
+
ldo3: LDO3 { /* VDDA_1V8 */
401
+
regulator-min-microvolt = <1800000>;
402
+
regulator-max-microvolt = <1800000>;
403
+
regulator-always-on;
404
+
regulator-boot-on;
405
+
};
406
+
407
+
ldo4: LDO4 { /* PMIC_LDO4 */
408
+
regulator-min-microvolt = <3300000>;
409
+
regulator-max-microvolt = <3300000>;
410
+
};
411
+
412
+
ldo5: LDO5 { /* NVCC_SD2 */
413
+
regulator-min-microvolt = <1800000>;
414
+
regulator-max-microvolt = <3300000>;
415
+
};
416
+
};
417
+
};
418
+
};
419
+
420
+
&i2c5 { /* HDMI EDID bus */
421
+
clock-frequency = <100000>;
422
+
pinctrl-names = "default", "gpio";
423
+
pinctrl-0 = <&pinctrl_i2c5>;
424
+
pinctrl-1 = <&pinctrl_i2c5_gpio>;
425
+
scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
426
+
sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
427
+
status = "okay";
428
+
};
429
+
430
+
&pwm1 {
431
+
pinctrl-names = "default";
432
+
pinctrl-0 = <&pinctrl_panel_pwm>;
433
+
/* Disabled by default, unless display board plugged in. */
434
+
status = "disabled";
435
+
};
436
+
437
+
/* SD slot */
438
+
&usdhc2 {
439
+
pinctrl-names = "default", "state_100mhz", "state_200mhz";
440
+
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
441
+
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
442
+
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
443
+
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
444
+
vmmc-supply = <®_usdhc2_vmmc>;
445
+
bus-width = <4>;
446
+
status = "okay";
447
+
};
448
+
449
+
/* eMMC */
450
+
&usdhc3 {
451
+
pinctrl-names = "default", "state_100mhz", "state_200mhz";
452
+
pinctrl-0 = <&pinctrl_usdhc3>;
453
+
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
454
+
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
455
+
vmmc-supply = <&buck4>;
456
+
vqmmc-supply = <&buck5>;
457
+
bus-width = <8>;
458
+
no-sd;
459
+
no-sdio;
460
+
non-removable;
461
+
status = "okay";
462
+
};
463
+
464
+
&uart1 { /* RS485 */
465
+
pinctrl-names = "default";
466
+
pinctrl-0 = <&pinctrl_uart1>;
467
+
uart-has-rtscts;
468
+
status = "disabled"; /* Optional */
469
+
};
470
+
471
+
&uart2 {
472
+
pinctrl-names = "default";
473
+
pinctrl-0 = <&pinctrl_uart2>;
474
+
uart-has-rtscts;
475
+
status = "okay";
476
+
};
477
+
478
+
&uart3 { /* A53 Debug */
479
+
pinctrl-names = "default";
480
+
pinctrl-0 = <&pinctrl_uart3>;
481
+
status = "okay";
482
+
};
483
+
484
+
&uart4 {
485
+
pinctrl-names = "default";
486
+
pinctrl-0 = <&pinctrl_uart4>;
487
+
status = "okay";
488
+
};
489
+
490
+
&usb3_phy0 {
491
+
status = "okay";
492
+
};
493
+
494
+
&usb3_0 {
495
+
fsl,over-current-active-low;
496
+
status = "okay";
497
+
};
498
+
499
+
&usb_dwc3_0 { /* Lower plug direct */
500
+
pinctrl-names = "default";
501
+
pinctrl-0 = <&pinctrl_usb1>;
502
+
dr_mode = "host";
503
+
status = "okay";
504
+
};
505
+
506
+
&usb3_phy1 {
507
+
status = "okay";
508
+
};
509
+
510
+
&usb3_1 {
511
+
status = "okay";
512
+
};
513
+
514
+
&usb_dwc3_1 { /* Upper plug via HUB */
515
+
dr_mode = "host";
516
+
status = "okay";
517
+
};
518
+
519
+
&wdog1 {
520
+
status = "okay";
521
+
};
522
+
523
+
/* IOMUXC node should be at the end of DT to improve readability. */
524
+
&iomuxc {
525
+
pinctrl-names = "default";
526
+
pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
527
+
<&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
528
+
<&pinctrl_panel_expansion>;
529
+
530
+
pinctrl_ecspi1: ecspi1-grp {
531
+
fsl,pins = <
532
+
MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44
533
+
MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44
534
+
MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44
535
+
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40
536
+
>;
537
+
};
538
+
539
+
pinctrl_ecspi2: ecspi2-grp {
540
+
fsl,pins = <
541
+
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
542
+
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
543
+
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
544
+
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
545
+
>;
546
+
};
547
+
548
+
pinctrl_ecspi3: ecspi3-grp {
549
+
fsl,pins = <
550
+
MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x44
551
+
MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x44
552
+
MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x44
553
+
MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x40
554
+
>;
555
+
};
556
+
557
+
pinctrl_eqos: eqos-grp {
558
+
fsl,pins = <
559
+
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
560
+
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
561
+
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
562
+
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
563
+
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
564
+
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
565
+
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
566
+
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
567
+
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
568
+
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
569
+
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
570
+
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
571
+
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
572
+
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
573
+
/* ENET_RST# */
574
+
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6
575
+
/* ENET_INT# */
576
+
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090
577
+
>;
578
+
};
579
+
580
+
pinctrl_fec: fec-grp {
581
+
fsl,pins = <
582
+
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
583
+
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
584
+
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
585
+
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
586
+
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
587
+
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
588
+
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
589
+
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
590
+
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
591
+
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
592
+
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
593
+
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
594
+
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
595
+
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
596
+
/* ENET2_RST# */
597
+
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6
598
+
/* ENET2_INT# */
599
+
MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090
600
+
>;
601
+
};
602
+
603
+
pinctrl_flexcan1: flexcan1-grp {
604
+
fsl,pins = <
605
+
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
606
+
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
607
+
>;
608
+
};
609
+
610
+
pinctrl_hog_feature: hog-feature-grp {
611
+
fsl,pins = <
612
+
/* GPIO5_IO03 */
613
+
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40000006
614
+
/* GPIO5_IO04 */
615
+
MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40000006
616
+
617
+
/* CAN_INT# */
618
+
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x40000090
619
+
>;
620
+
};
621
+
622
+
pinctrl_hog_panel: hog-panel-grp {
623
+
fsl,pins = <
624
+
/* GRAPHICS_GPIO0_1V8 */
625
+
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x26
626
+
>;
627
+
};
628
+
629
+
pinctrl_hog_misc: hog-misc-grp {
630
+
fsl,pins = <
631
+
/* ENET_WOL# -- shared by both PHYs */
632
+
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000090
633
+
634
+
/* PG_V_IN_VAR# */
635
+
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000
636
+
/* CSI2_PD_1V8 */
637
+
MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0
638
+
/* CSI2_RESET_1V8# */
639
+
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0
640
+
641
+
/* DIS_USB_DN1 */
642
+
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0
643
+
/* DIS_USB_DN2 */
644
+
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0
645
+
646
+
/* EEPROM_WP_1V8# */
647
+
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x100
648
+
/* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
649
+
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x0
650
+
/* GRAPHICS_PRSNT_1V8# */
651
+
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000
652
+
653
+
/* CLK_CCM_CLKO1_3V3 */
654
+
MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10
655
+
>;
656
+
};
657
+
658
+
pinctrl_hog_sbc: hog-sbc-grp {
659
+
fsl,pins = <
660
+
/* MEMCFG[0..2] straps */
661
+
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x40000140
662
+
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40000140
663
+
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000140
664
+
>;
665
+
};
666
+
667
+
pinctrl_i2c1: i2c1-grp {
668
+
fsl,pins = <
669
+
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x40000084
670
+
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x40000084
671
+
>;
672
+
};
673
+
674
+
pinctrl_i2c1_gpio: i2c1-gpio-grp {
675
+
fsl,pins = <
676
+
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x84
677
+
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x84
678
+
>;
679
+
};
680
+
681
+
pinctrl_i2c2: i2c2-grp {
682
+
fsl,pins = <
683
+
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x40000084
684
+
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x40000084
685
+
>;
686
+
};
687
+
688
+
pinctrl_i2c2_gpio: i2c2-gpio-grp {
689
+
fsl,pins = <
690
+
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x84
691
+
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x84
692
+
>;
693
+
};
694
+
695
+
pinctrl_i2c3: i2c3-grp {
696
+
fsl,pins = <
697
+
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084
698
+
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084
699
+
>;
700
+
};
701
+
702
+
pinctrl_i2c3_gpio: i2c3-gpio-grp {
703
+
fsl,pins = <
704
+
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84
705
+
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84
706
+
>;
707
+
};
708
+
709
+
pinctrl_i2c5: i2c5-grp {
710
+
fsl,pins = <
711
+
MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084
712
+
MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084
713
+
>;
714
+
};
715
+
716
+
pinctrl_i2c5_gpio: i2c5-gpio-grp {
717
+
fsl,pins = <
718
+
MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84
719
+
MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84
720
+
>;
721
+
};
722
+
723
+
pinctrl_panel_backlight: panel-backlight-grp {
724
+
fsl,pins = <
725
+
/* BL_ENABLE_1V8 */
726
+
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x104
727
+
>;
728
+
};
729
+
730
+
pinctrl_panel_expansion: panel-expansion-grp {
731
+
fsl,pins = <
732
+
/* DSI_RESET_1V8# */
733
+
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x2
734
+
/* DSI_IRQ_1V8# */
735
+
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000090
736
+
>;
737
+
};
738
+
739
+
pinctrl_panel_pwm: panel-pwm-grp {
740
+
fsl,pins = <
741
+
/* BL_PWM_3V3 */
742
+
MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x12
743
+
>;
744
+
};
745
+
746
+
pinctrl_panel_vcc_reg: panel-vcc-grp {
747
+
fsl,pins = <
748
+
/* TFT_ENABLE_1V8 */
749
+
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x104
750
+
>;
751
+
};
752
+
753
+
pinctrl_pcie0: pcie-grp {
754
+
fsl,pins = <
755
+
/* M2_PCIE_RST# */
756
+
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
757
+
/* M2_W_DISABLE1_1V8# */
758
+
MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2
759
+
/* M2_W_DISABLE2_1V8# */
760
+
MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2
761
+
/* CLK_M2_32K768 */
762
+
MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14
763
+
/* M2_PCIE_WAKE# */
764
+
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140
765
+
/* M2_PCIE_CLKREQ# */
766
+
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61
767
+
>;
768
+
};
769
+
770
+
pinctrl_pdm: pdm-grp {
771
+
fsl,pins = <
772
+
/* PDM_SEL */
773
+
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x0
774
+
MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x0
775
+
MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x0
776
+
>;
777
+
};
778
+
779
+
pinctrl_pmic: pmic-grp {
780
+
fsl,pins = <
781
+
/* PMIC_nINT */
782
+
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
783
+
>;
784
+
};
785
+
786
+
pinctrl_rtc: rtc-grp {
787
+
fsl,pins = <
788
+
/* RTC_IRQ# */
789
+
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000090
790
+
>;
791
+
};
792
+
793
+
pinctrl_sai1: sai1-grp {
794
+
fsl,pins = <
795
+
MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0xd6
796
+
MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0xd6
797
+
MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0xd6
798
+
MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6
799
+
MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0xd6
800
+
>;
801
+
};
802
+
803
+
pinctrl_sai2: sai2-grp {
804
+
fsl,pins = <
805
+
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
806
+
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
807
+
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
808
+
MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
809
+
>;
810
+
};
811
+
812
+
pinctrl_sai3: sai3-grp {
813
+
fsl,pins = <
814
+
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
815
+
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
816
+
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
817
+
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
818
+
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
819
+
>;
820
+
};
821
+
822
+
pinctrl_uart1: uart1-grp {
823
+
fsl,pins = <
824
+
MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x49
825
+
MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x49
826
+
MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x49
827
+
MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49
828
+
>;
829
+
};
830
+
831
+
pinctrl_uart2: uart2-grp {
832
+
fsl,pins = <
833
+
MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x49
834
+
MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x49
835
+
MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49
836
+
MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49
837
+
>;
838
+
};
839
+
840
+
pinctrl_uart3: uart3-grp {
841
+
fsl,pins = <
842
+
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
843
+
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
844
+
>;
845
+
};
846
+
847
+
pinctrl_uart4: uart4-grp {
848
+
fsl,pins = <
849
+
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
850
+
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
851
+
>;
852
+
};
853
+
854
+
pinctrl_usdhc2: usdhc2-grp {
855
+
fsl,pins = <
856
+
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
857
+
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
858
+
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
859
+
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
860
+
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
861
+
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
862
+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
863
+
>;
864
+
};
865
+
866
+
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
867
+
fsl,pins = <
868
+
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
869
+
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
870
+
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
871
+
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
872
+
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
873
+
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
874
+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
875
+
>;
876
+
};
877
+
878
+
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
879
+
fsl,pins = <
880
+
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
881
+
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
882
+
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
883
+
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
884
+
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
885
+
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
886
+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
887
+
>;
888
+
};
889
+
890
+
pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
891
+
fsl,pins = <
892
+
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20
893
+
>;
894
+
};
895
+
896
+
pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
897
+
fsl,pins = <
898
+
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080
899
+
>;
900
+
};
901
+
902
+
pinctrl_usdhc3: usdhc3-grp {
903
+
fsl,pins = <
904
+
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
905
+
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
906
+
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
907
+
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
908
+
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
909
+
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
910
+
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
911
+
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
912
+
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
913
+
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
914
+
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
915
+
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
916
+
>;
917
+
};
918
+
919
+
pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
920
+
fsl,pins = <
921
+
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
922
+
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
923
+
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
924
+
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
925
+
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
926
+
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
927
+
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
928
+
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
929
+
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
930
+
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
931
+
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
932
+
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
933
+
>;
934
+
};
935
+
936
+
pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
937
+
fsl,pins = <
938
+
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
939
+
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
940
+
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
941
+
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
942
+
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
943
+
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
944
+
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
945
+
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
946
+
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
947
+
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
948
+
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
949
+
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
950
+
>;
951
+
};
952
+
953
+
pinctrl_usb_hub: usb-hub-grp {
954
+
fsl,pins = <
955
+
/* USBHUB_RESET# */
956
+
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x4
957
+
>;
958
+
};
959
+
960
+
pinctrl_usb1: usb1-grp {
961
+
fsl,pins = <
962
+
MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x6
963
+
MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x80
964
+
>;
965
+
};
966
+
967
+
pinctrl_watchdog_gpio: watchdog-gpio-grp {
968
+
fsl,pins = <
969
+
/* WDOG_B# */
970
+
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x26
971
+
/* WDOG_EN -- ungate WDT RESET# signal propagation */
972
+
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x6
973
+
/* WDOG_KICK# / WDI */
974
+
MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26
975
+
>;
976
+
};
977
+
};
+59
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
+59
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
···
43
43
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
44
44
enable-active-high;
45
45
};
46
+
47
+
reg_usb_hub: regulator-usb-hub {
48
+
compatible = "regulator-fixed";
49
+
pinctrl-names = "default";
50
+
pinctrl-0 = <&pinctrl_reg_usb_hub>;
51
+
regulator-name = "USB_HUB";
52
+
regulator-min-microvolt = <5000000>;
53
+
regulator-max-microvolt = <5000000>;
54
+
gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
55
+
enable-active-high;
56
+
};
46
57
};
47
58
48
59
&A53_0 {
···
265
254
status = "okay";
266
255
};
267
256
257
+
&usb3_phy1 {
258
+
status = "okay";
259
+
};
260
+
261
+
&usb3_1 {
262
+
status = "okay";
263
+
};
264
+
265
+
&usb_dwc3_1 {
266
+
#address-cells = <1>;
267
+
#size-cells = <0>;
268
+
pinctrl-names = "default";
269
+
pinctrl-0 = <&pinctrl_usb1>;
270
+
dr_mode = "host";
271
+
status = "okay";
272
+
273
+
/* 2.x hub on port 1 */
274
+
usb_hub_2_x: hub@1 {
275
+
compatible = "usbbda,5411";
276
+
reg = <1>;
277
+
reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
278
+
vdd-supply = <®_usb_hub>;
279
+
peer-hub = <&usb_hub_3_x>;
280
+
};
281
+
282
+
/* 3.x hub on port 2 */
283
+
usb_hub_3_x: hub@2 {
284
+
compatible = "usbbda,411";
285
+
reg = <2>;
286
+
reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
287
+
vdd-supply = <®_usb_hub>;
288
+
peer-hub = <&usb_hub_2_x>;
289
+
};
290
+
};
291
+
268
292
/* SD Card */
269
293
&usdhc2 {
270
294
pinctrl-names = "default", "state_100mhz", "state_200mhz";
···
430
384
>;
431
385
};
432
386
387
+
pinctrl_reg_usb_hub: regusbhubgrp {
388
+
fsl,pins = <
389
+
MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x19
390
+
>;
391
+
};
392
+
433
393
pinctrl_rtc_int: rtcintgrp {
434
394
fsl,pins = <
435
395
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140
···
460
408
fsl,pins = <
461
409
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
462
410
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
411
+
>;
412
+
};
413
+
414
+
pinctrl_usb1: usb1grp {
415
+
fsl,pins = <
416
+
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
417
+
MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19
463
418
>;
464
419
};
465
420
+17
-13
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts
+17
-13
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts
···
104
104
};
105
105
};
106
106
107
-
/*
108
-
* PDK2 carrier board uses SoM with KSZ9131 populated and connected to
109
-
* SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node.
110
-
*/
111
-
/delete-node/ ðphy0f;
112
-
113
-
/*
114
-
* PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC
115
-
* ethernet RGMII interface. The SoM is not populated with second FEC PHY.
116
-
*/
117
-
/delete-node/ ðphy1f;
118
-
119
107
&fec { /* Second ethernet */
108
+
pinctrl-0 = <&pinctrl_fec_rgmii>;
120
109
phy-handle = <ðphypdk>;
110
+
phy-mode = "rgmii";
121
111
122
112
mdio {
123
113
ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
···
141
151
status = "okay";
142
152
};
143
153
154
+
&pcie_phy {
155
+
clock-names = "ref";
156
+
clocks = <&clk IMX8MP_SYS_PLL2_100M>;
157
+
fsl,clkreq-unsupported;
158
+
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_UNUSED>;
159
+
status = "okay";
160
+
};
161
+
162
+
&pcie {
163
+
fsl,max-link-speed = <1>;
164
+
reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; /* GPIO J */
165
+
status = "okay";
166
+
};
167
+
144
168
&usb3_1 {
145
169
fsl,over-current-active-low;
146
170
};
···
163
159
/*
164
160
* GPIO_A,B,C,D are connected to buttons.
165
161
* GPIO_E,F,H,I are connected to LEDs.
166
-
* GPIO_M is connected to CLKOUT2.
162
+
* GPIO_M is connected to CLKOUT1.
167
163
*/
168
164
pinctrl-0 = <&pinctrl_hog_base
169
165
&pinctrl_dhcom_g &pinctrl_dhcom_j
+306
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts
+306
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (C) 2023 Marek Vasut <marex@denx.de>
4
+
*
5
+
* DHCOM iMX8MP variant:
6
+
* DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
7
+
* DHCOM PCB number: 660-100 or newer
8
+
* PDK3 PCB number: 669-100 or newer
9
+
*/
10
+
11
+
/dts-v1/;
12
+
13
+
#include <dt-bindings/leds/common.h>
14
+
#include <dt-bindings/phy/phy-imx8-pcie.h>
15
+
#include "imx8mp-dhcom-som.dtsi"
16
+
17
+
/ {
18
+
model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (3)";
19
+
compatible = "dh,imx8mp-dhcom-pdk3", "dh,imx8mp-dhcom-som",
20
+
"fsl,imx8mp";
21
+
22
+
chosen {
23
+
stdout-path = &uart1;
24
+
};
25
+
26
+
clk_pcie: clock-pcie {
27
+
compatible = "fixed-clock";
28
+
#clock-cells = <0>;
29
+
clock-frequency = <100000000>;
30
+
};
31
+
32
+
connector {
33
+
compatible = "usb-c-connector";
34
+
label = "USB-C";
35
+
data-role = "dual";
36
+
37
+
ports {
38
+
#address-cells = <1>;
39
+
#size-cells = <0>;
40
+
41
+
port@0 {
42
+
reg = <0>;
43
+
44
+
usb_c_0_hs_ep: endpoint {
45
+
remote-endpoint = <&dwc3_0_hs_ep>;
46
+
};
47
+
};
48
+
49
+
port@1 {
50
+
reg = <1>;
51
+
52
+
usb_c_0_ss_ep: endpoint {
53
+
remote-endpoint = <&ptn5150_in_ep>;
54
+
};
55
+
};
56
+
};
57
+
};
58
+
59
+
gpio-keys {
60
+
compatible = "gpio-keys";
61
+
62
+
button-0 {
63
+
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */
64
+
label = "TA1-GPIO-A";
65
+
linux,code = <KEY_A>;
66
+
pinctrl-0 = <&pinctrl_dhcom_a>;
67
+
pinctrl-names = "default";
68
+
wakeup-source;
69
+
};
70
+
71
+
button-1 {
72
+
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */
73
+
label = "TA2-GPIO-B";
74
+
linux,code = <KEY_B>;
75
+
pinctrl-0 = <&pinctrl_dhcom_b>;
76
+
pinctrl-names = "default";
77
+
wakeup-source;
78
+
};
79
+
80
+
button-2 {
81
+
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
82
+
label = "TA3-GPIO-C";
83
+
linux,code = <KEY_C>;
84
+
pinctrl-0 = <&pinctrl_dhcom_c>;
85
+
pinctrl-names = "default";
86
+
wakeup-source;
87
+
};
88
+
89
+
button-3 {
90
+
gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; /* GPIO E */
91
+
label = "TA4-GPIO-E";
92
+
linux,code = <KEY_E>;
93
+
pinctrl-0 = <&pinctrl_dhcom_e>;
94
+
pinctrl-names = "default";
95
+
wakeup-source;
96
+
};
97
+
};
98
+
99
+
led {
100
+
compatible = "gpio-leds";
101
+
102
+
led-0 {
103
+
color = <LED_COLOR_ID_GREEN>;
104
+
default-state = "off";
105
+
function = LED_FUNCTION_INDICATOR;
106
+
function-enumerator = <0>;
107
+
gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; /* GPIO D */
108
+
pinctrl-0 = <&pinctrl_dhcom_d>;
109
+
pinctrl-names = "default";
110
+
};
111
+
112
+
led-1 {
113
+
color = <LED_COLOR_ID_GREEN>;
114
+
default-state = "off";
115
+
function = LED_FUNCTION_INDICATOR;
116
+
function-enumerator = <1>;
117
+
gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */
118
+
pinctrl-0 = <&pinctrl_dhcom_f>;
119
+
pinctrl-names = "default";
120
+
};
121
+
122
+
led-2 {
123
+
color = <LED_COLOR_ID_GREEN>;
124
+
default-state = "off";
125
+
function = LED_FUNCTION_INDICATOR;
126
+
function-enumerator = <2>;
127
+
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* GPIO G */
128
+
pinctrl-0 = <&pinctrl_dhcom_g>;
129
+
pinctrl-names = "default";
130
+
};
131
+
132
+
led-3 {
133
+
color = <LED_COLOR_ID_GREEN>;
134
+
default-state = "off";
135
+
function = LED_FUNCTION_INDICATOR;
136
+
function-enumerator = <3>;
137
+
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
138
+
pinctrl-0 = <&pinctrl_dhcom_i>;
139
+
pinctrl-names = "default";
140
+
};
141
+
};
142
+
143
+
reg_avdd: regulator-avdd { /* AUDIO_VDD */
144
+
compatible = "regulator-fixed";
145
+
regulator-always-on;
146
+
regulator-min-microvolt = <3300000>;
147
+
regulator-max-microvolt = <3300000>;
148
+
regulator-name = "AUDIO_VDD";
149
+
};
150
+
};
151
+
152
+
&i2c5 {
153
+
i2c-mux@70 {
154
+
compatible = "nxp,pca9540";
155
+
reg = <0x70>;
156
+
#address-cells = <1>;
157
+
#size-cells = <0>;
158
+
159
+
i2cmuxed0: i2c@0 {
160
+
#address-cells = <1>;
161
+
#size-cells = <0>;
162
+
reg = <0>;
163
+
164
+
typec@3d {
165
+
compatible = "nxp,ptn5150";
166
+
reg = <0x3d>;
167
+
interrupt-parent = <&gpio4>;
168
+
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
169
+
pinctrl-names = "default";
170
+
pinctrl-0 = <&pinctrl_ptn5150>;
171
+
172
+
ports {
173
+
#address-cells = <1>;
174
+
#size-cells = <0>;
175
+
176
+
port@0 {
177
+
reg = <0>;
178
+
179
+
ptn5150_in_ep: endpoint {
180
+
remote-endpoint = <&usb_c_0_ss_ep>;
181
+
};
182
+
};
183
+
184
+
port@1 {
185
+
reg = <1>;
186
+
187
+
ptn5150_out_ep: endpoint {
188
+
remote-endpoint = <&dwc3_0_ss_ep>;
189
+
};
190
+
};
191
+
};
192
+
};
193
+
194
+
power-sensor@40 {
195
+
compatible = "ti,ina238";
196
+
reg = <0x40>;
197
+
shunt-resistor = <20000>; /* 0.02 R */
198
+
ti,shunt-gain = <1>; /* Drop cca. 40mV */
199
+
};
200
+
201
+
eeprom_board: eeprom@54 {
202
+
compatible = "atmel,24c04";
203
+
pagesize = <16>;
204
+
reg = <0x54>;
205
+
};
206
+
};
207
+
208
+
i2cmuxed1: i2c@1 { /* HDMI DDC I2C */
209
+
#address-cells = <1>;
210
+
#size-cells = <0>;
211
+
reg = <1>;
212
+
};
213
+
};
214
+
};
215
+
216
+
ðphy0g {
217
+
reg = <7>;
218
+
};
219
+
220
+
&fec { /* Second ethernet */
221
+
pinctrl-0 = <&pinctrl_fec_rgmii>;
222
+
phy-handle = <ðphypdk>;
223
+
phy-mode = "rgmii-id";
224
+
225
+
mdio {
226
+
ethphypdk: ethernet-phy@7 { /* Micrel KSZ9131RNXI */
227
+
compatible = "ethernet-phy-id0022.1642",
228
+
"ethernet-phy-ieee802.3-c22";
229
+
interrupt-parent = <&gpio4>;
230
+
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
231
+
pinctrl-0 = <&pinctrl_ethphy1>;
232
+
pinctrl-names = "default";
233
+
reg = <7>;
234
+
reset-assert-us = <1000>;
235
+
/* RESET_N signal rise time ~100ms */
236
+
reset-deassert-us = <120000>;
237
+
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
238
+
};
239
+
};
240
+
};
241
+
242
+
&flexcan1 {
243
+
status = "okay";
244
+
};
245
+
246
+
&pcie_phy {
247
+
clocks = <&clk_pcie>;
248
+
clock-names = "ref";
249
+
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
250
+
status = "okay";
251
+
};
252
+
253
+
&pcie {
254
+
fsl,max-link-speed = <3>;
255
+
reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
256
+
status = "okay";
257
+
};
258
+
259
+
&usb_dwc3_0 {
260
+
usb-role-switch;
261
+
262
+
port {
263
+
#address-cells = <1>;
264
+
#size-cells = <0>;
265
+
266
+
dwc3_0_hs_ep: endpoint@0 {
267
+
reg = <0>;
268
+
remote-endpoint = <&usb_c_0_hs_ep>;
269
+
};
270
+
271
+
dwc3_0_ss_ep: endpoint@1 {
272
+
reg = <1>;
273
+
remote-endpoint = <&ptn5150_out_ep>;
274
+
};
275
+
};
276
+
};
277
+
278
+
&usb3_1 {
279
+
fsl,disable-port-power-control;
280
+
fsl,permanently-attached;
281
+
};
282
+
283
+
&usb_dwc3_1 {
284
+
/* This port has USB5734 Hub connected to it, PWR/OC pins are unused */
285
+
/delete-property/ pinctrl-names;
286
+
/delete-property/ pinctrl-0;
287
+
};
288
+
289
+
&iomuxc {
290
+
/*
291
+
* GPIO_A,B,C,E are connected to buttons.
292
+
* GPIO_D,F,G,I are connected to LEDs.
293
+
* GPIO_H is connected to USB Hub RESET_N.
294
+
* GPIO_M is connected to CLKOUT2.
295
+
*/
296
+
pinctrl-0 = <&pinctrl_hog_base
297
+
&pinctrl_dhcom_h &pinctrl_dhcom_j &pinctrl_dhcom_k
298
+
&pinctrl_dhcom_l
299
+
&pinctrl_dhcom_int>;
300
+
301
+
pinctrl_ptn5150: ptn5150grp {
302
+
fsl,pins = <
303
+
MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40000000
304
+
>;
305
+
};
306
+
};
+42
-10
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
+42
-10
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
···
83
83
84
84
&eqos { /* First ethernet */
85
85
pinctrl-names = "default";
86
-
pinctrl-0 = <&pinctrl_eqos>;
86
+
pinctrl-0 = <&pinctrl_eqos_rgmii>;
87
87
phy-handle = <ðphy0g>;
88
88
phy-mode = "rgmii-id";
89
89
status = "okay";
···
94
94
#size-cells = <0>;
95
95
96
96
/* Up to one of these two PHYs may be populated. */
97
-
ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
97
+
ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
98
98
compatible = "ethernet-phy-id0007.c110",
99
99
"ethernet-phy-ieee802.3-c22";
100
100
interrupt-parent = <&gpio3>;
101
101
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
102
102
pinctrl-0 = <&pinctrl_ethphy0>;
103
103
pinctrl-names = "default";
104
-
reg = <1>;
104
+
reg = <0>;
105
105
reset-assert-us = <1000>;
106
106
reset-deassert-us = <1000>;
107
107
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
···
129
129
130
130
&fec { /* Second ethernet */
131
131
pinctrl-names = "default";
132
-
pinctrl-0 = <&pinctrl_fec>;
132
+
pinctrl-0 = <&pinctrl_fec_rmii>;
133
133
phy-handle = <ðphy1f>;
134
-
phy-mode = "rgmii";
134
+
phy-mode = "rmii";
135
135
fsl,magic-packet;
136
136
status = "okay";
137
137
···
547
547
&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
548
548
&pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
549
549
&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
550
-
/* GPIO_M is connected to CLKOUT2 */
550
+
/* GPIO_M is connected to CLKOUT1 */
551
551
&pinctrl_dhcom_int>;
552
552
pinctrl-names = "default";
553
553
···
673
673
>;
674
674
};
675
675
676
-
pinctrl_eqos: dhcom-eqos-grp { /* RGMII */
676
+
pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp { /* RGMII */
677
677
fsl,pins = <
678
678
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
679
679
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
···
692
692
>;
693
693
};
694
694
695
+
pinctrl_eqos_rmii: dhcom-eqos-rmii-grp { /* RMII */
696
+
fsl,pins = <
697
+
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
698
+
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
699
+
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
700
+
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
701
+
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
702
+
MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x1f
703
+
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
704
+
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
705
+
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
706
+
/* Clock */
707
+
MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000001f
708
+
>;
709
+
};
710
+
695
711
pinctrl_enet_vio: dhcom-enet-vio-grp {
696
712
fsl,pins = <
697
713
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
···
716
700
717
701
pinctrl_ethphy0: dhcom-ethphy0-grp {
718
702
fsl,pins = <
719
-
/* ENET1_#RST Reset */
703
+
/* ENET_QOS_#RST Reset */
720
704
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
721
-
/* ENET1_#INT Interrupt */
705
+
/* ENET_QOS_#INT Interrupt */
722
706
MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22
723
707
>;
724
708
};
···
732
716
>;
733
717
};
734
718
735
-
pinctrl_fec: dhcom-fec-grp {
719
+
pinctrl_fec_rgmii: dhcom-fec-rgmii-grp { /* RGMII */
736
720
fsl,pins = <
737
721
MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f
738
722
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
···
750
734
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
751
735
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
752
736
MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f
737
+
>;
738
+
};
739
+
740
+
pinctrl_fec_rmii: dhcom-fec-rmii-grp { /* RMII */
741
+
fsl,pins = <
742
+
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
743
+
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
744
+
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
745
+
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
746
+
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
747
+
MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x91
748
+
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
749
+
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
750
+
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
751
+
/* Clock */
752
+
MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x4000001f
753
753
>;
754
754
};
755
755
+2
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
+2
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
+8
-1
arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
+8
-1
arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
+8
-1
arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi
+8
-1
arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi
+5
arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi
+5
arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi
+2
-3
arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi
+2
-3
arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi
···
87
87
status = "okay";
88
88
};
89
89
90
-
/* EEPROM on Verdin yavia board */
90
+
/* EEPROM on Verdin Yavia board */
91
91
&eeprom_carrier_board {
92
92
status = "okay";
93
93
};
···
122
122
status = "okay";
123
123
};
124
124
125
-
&pcie_phy{
125
+
&pcie_phy {
126
126
status = "okay";
127
127
};
128
128
···
183
183
};
184
184
185
185
&usb_dwc3_1 {
186
-
disable-over-current;
187
186
status = "okay";
188
187
};
189
188
+14
-1
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
+14
-1
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
···
748
748
};
749
749
};
750
750
751
-
/* TODO: Verdin PCIE_1 */
751
+
/* Verdin PCIE_1 */
752
+
&pcie {
753
+
pinctrl-names = "default";
754
+
pinctrl-0 = <&pinctrl_pcie>;
755
+
/* PCIE_1_RESET# (SODIMM 244) */
756
+
reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
757
+
};
758
+
759
+
&pcie_phy {
760
+
clocks = <&hsio_blk_ctrl>;
761
+
clock-names = "ref";
762
+
fsl,clkreq-unsupported;
763
+
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
764
+
};
752
765
753
766
/* Verdin PWM_1 */
754
767
&pwm1 {
+132
-3
arch/arm64/boot/dts/freescale/imx8mp.dtsi
+132
-3
arch/arm64/boot/dts/freescale/imx8mp.dtsi
···
409
409
status = "disabled";
410
410
};
411
411
412
+
gpt1: timer@302d0000 {
413
+
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
414
+
reg = <0x302d0000 0x10000>;
415
+
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
416
+
clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>;
417
+
clock-names = "ipg", "per";
418
+
};
419
+
420
+
gpt2: timer@302e0000 {
421
+
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
422
+
reg = <0x302e0000 0x10000>;
423
+
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
424
+
clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>;
425
+
clock-names = "ipg", "per";
426
+
};
427
+
428
+
gpt3: timer@302f0000 {
429
+
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
430
+
reg = <0x302f0000 0x10000>;
431
+
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
432
+
clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>;
433
+
clock-names = "ipg", "per";
434
+
};
435
+
412
436
iomuxc: pinctrl@30330000 {
413
437
compatible = "fsl,imx8mp-iomuxc";
414
438
reg = <0x30330000 0x10000>;
···
745
721
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
746
722
clocks = <&osc_24m>;
747
723
clock-names = "per";
724
+
};
725
+
726
+
gpt6: timer@306e0000 {
727
+
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
728
+
reg = <0x306e0000 0x10000>;
729
+
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
730
+
clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>;
731
+
clock-names = "ipg", "per";
732
+
};
733
+
734
+
gpt5: timer@306f0000 {
735
+
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
736
+
reg = <0x306f0000 0x10000>;
737
+
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
738
+
clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>;
739
+
clock-names = "ipg", "per";
740
+
};
741
+
742
+
gpt4: timer@30700000 {
743
+
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
744
+
reg = <0x30700000 0x10000>;
745
+
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
746
+
clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>;
747
+
clock-names = "ipg", "per";
748
748
};
749
749
};
750
750
···
1174
1126
#size-cells = <1>;
1175
1127
ranges;
1176
1128
1129
+
mipi_dsi: dsi@32e60000 {
1130
+
compatible = "fsl,imx8mp-mipi-dsim";
1131
+
reg = <0x32e60000 0x400>;
1132
+
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1133
+
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1134
+
clock-names = "bus_clk", "sclk_mipi";
1135
+
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
1136
+
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1137
+
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1138
+
<&clk IMX8MP_CLK_24M>;
1139
+
assigned-clock-rates = <200000000>, <24000000>;
1140
+
samsung,pll-clock-frequency = <24000000>;
1141
+
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1142
+
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
1143
+
status = "disabled";
1144
+
1145
+
ports {
1146
+
#address-cells = <1>;
1147
+
#size-cells = <0>;
1148
+
1149
+
port@0 {
1150
+
reg = <0>;
1151
+
1152
+
dsim_from_lcdif1: endpoint {
1153
+
remote-endpoint = <&lcdif1_to_dsim>;
1154
+
};
1155
+
};
1156
+
};
1157
+
};
1158
+
1159
+
lcdif1: display-controller@32e80000 {
1160
+
compatible = "fsl,imx8mp-lcdif";
1161
+
reg = <0x32e80000 0x10000>;
1162
+
clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1163
+
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1164
+
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1165
+
clock-names = "pix", "axi", "disp_axi";
1166
+
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1167
+
<&clk IMX8MP_CLK_MEDIA_AXI>,
1168
+
<&clk IMX8MP_CLK_MEDIA_APB>;
1169
+
assigned-clock-parents = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
1170
+
<&clk IMX8MP_SYS_PLL2_1000M>,
1171
+
<&clk IMX8MP_SYS_PLL1_800M>;
1172
+
assigned-clock-rates = <594000000>, <500000000>, <200000000>;
1173
+
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1174
+
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
1175
+
status = "disabled";
1176
+
1177
+
port {
1178
+
lcdif1_to_dsim: endpoint {
1179
+
remote-endpoint = <&dsim_from_lcdif1>;
1180
+
};
1181
+
};
1182
+
};
1183
+
1177
1184
lcdif2: display-controller@32e90000 {
1178
1185
compatible = "fsl,imx8mp-lcdif";
1179
1186
reg = <0x32e90000 0x238>;
···
1254
1151
1255
1152
media_blk_ctrl: blk-ctrl@32ec0000 {
1256
1153
compatible = "fsl,imx8mp-media-blk-ctrl",
1257
-
"simple-bus", "syscon";
1154
+
"syscon";
1258
1155
reg = <0x32ec0000 0x10000>;
1259
1156
#address-cells = <1>;
1260
1157
#size-cells = <1>;
···
1305
1202
1306
1203
lvds_bridge: bridge@5c {
1307
1204
compatible = "fsl,imx8mp-ldb";
1308
-
clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1309
-
clock-names = "ldb";
1310
1205
reg = <0x5c 0x4>, <0x128 0x4>;
1311
1206
reg-names = "ldb", "lvds";
1207
+
clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1208
+
clock-names = "ldb";
1312
1209
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1313
1210
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
1314
1211
status = "disabled";
···
1409
1306
reset-names = "apps", "turnoff";
1410
1307
phys = <&pcie_phy>;
1411
1308
phy-names = "pcie-phy";
1309
+
status = "disabled";
1310
+
};
1311
+
1312
+
pcie_ep: pcie-ep@33800000 {
1313
+
compatible = "fsl,imx8mp-pcie-ep";
1314
+
reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
1315
+
reg-names = "dbi", "addr_space";
1316
+
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1317
+
<&clk IMX8MP_CLK_HSIO_AXI>,
1318
+
<&clk IMX8MP_CLK_PCIE_ROOT>;
1319
+
clock-names = "pcie", "pcie_bus", "pcie_aux";
1320
+
assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
1321
+
assigned-clock-rates = <10000000>;
1322
+
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
1323
+
num-lanes = <1>;
1324
+
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
1325
+
interrupt-names = "dma";
1326
+
fsl,max-link-speed = <3>;
1327
+
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1328
+
resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
1329
+
<&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
1330
+
reset-names = "apps", "turnoff";
1331
+
phys = <&pcie_phy>;
1332
+
phy-names = "pcie-phy";
1333
+
num-ib-windows = <4>;
1334
+
num-ob-windows = <4>;
1412
1335
status = "disabled";
1413
1336
};
1414
1337
+1
-1
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
+5
-7
arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts
+5
-7
arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts
···
12
12
compatible = "purism,librem5r2", "purism,librem5", "fsl,imx8mq";
13
13
};
14
14
15
-
&bq25895 {
16
-
ti,battery-regulation-voltage = <4192000>; /* uV */
17
-
ti,charge-current = <1600000>; /* uA */
18
-
ti,termination-current = <66000>; /* uA */
19
-
};
20
-
21
15
&accel_gyro {
22
16
mount-matrix = "1", "0", "0",
23
17
"0", "-1", "0",
24
18
"0", "0", "1";
25
19
};
26
20
21
+
&bq25895 {
22
+
ti,charge-current = <1600000>; /* uA */
23
+
};
24
+
27
25
&proximity {
28
-
proximity-near-level = <120>;
26
+
proximity-near-level = <50>;
29
27
};
+1
-1
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
+7
-3
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi
+7
-3
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi
···
22
22
};
23
23
24
24
&bq25895 {
25
-
ti,battery-regulation-voltage = <4200000>; /* uV */
26
25
ti,charge-current = <1500000>; /* uA */
27
-
ti,termination-current = <144000>; /* uA */
28
26
};
29
27
30
28
&camera_front {
···
38
40
};
39
41
};
40
42
43
+
&magnetometer {
44
+
mount-matrix = "1", "0", "0",
45
+
"0", "-1", "0",
46
+
"0", "0", "-1";
47
+
};
48
+
41
49
&proximity {
42
-
proximity-near-level = <25>;
50
+
proximity-near-level = <10>;
43
51
};
+1
-1
arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts
+58
-21
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
+58
-21
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
···
20
20
backlight_dsi: backlight-dsi {
21
21
compatible = "led-backlight";
22
22
leds = <&led_backlight>;
23
+
brightness-levels = <255>;
24
+
default-brightness-level = <190>;
23
25
};
24
26
25
27
pmic_osc: clock-pmic {
···
86
84
compatible = "regulator-fixed";
87
85
pinctrl-names = "default";
88
86
pinctrl-0 = <&pinctrl_audiopwr>;
89
-
regulator-name = "AUDIO_PWR_EN";
87
+
regulator-name = "AUD_1V8";
90
88
regulator-min-microvolt = <1800000>;
91
89
regulator-max-microvolt = <1800000>;
92
90
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
93
91
enable-active-high;
92
+
};
93
+
94
+
reg_mic_2v4: regulator-mic-2v4 {
95
+
compatible = "regulator-fixed";
96
+
regulator-name = "MIC_2V4";
97
+
regulator-min-microvolt = <2400000>;
98
+
regulator-max-microvolt = <2400000>;
99
+
vin-supply = <®_aud_1v8>;
94
100
};
95
101
96
102
/*
···
329
319
opp-hz = /bits/ 64 <100000000>;
330
320
};
331
321
322
+
opp-166000000 {
323
+
opp-hz = /bits/ 64 <166935483>;
324
+
};
325
+
332
326
opp-800000000 {
333
327
opp-hz = /bits/ 64 <800000000>;
334
328
};
···
385
371
};
386
372
387
373
&iomuxc {
374
+
pinctrl-names = "default";
375
+
pinctrl-0 = <&pinctrl_hog>;
376
+
377
+
pinctrl_hog: hoggrp {
378
+
fsl,pins = <
379
+
/* CLKO2 for cameras on both CSI1 and CSI2 */
380
+
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
381
+
>;
382
+
};
383
+
388
384
pinctrl_audiopwr: audiopwrgrp {
389
385
fsl,pins = <
390
386
/* AUDIO_POWER_EN_3V3 */
···
686
662
>;
687
663
};
688
664
689
-
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
665
+
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
690
666
fsl,pins = <
691
667
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
692
668
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
···
703
679
>;
704
680
};
705
681
706
-
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
682
+
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
707
683
fsl,pins = <
708
684
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
709
685
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
···
733
709
>;
734
710
};
735
711
736
-
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
712
+
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
737
713
fsl,pins = <
738
714
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80
739
715
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
···
746
722
>;
747
723
};
748
724
749
-
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
725
+
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
750
726
fsl,pins = <
751
727
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80
752
728
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
···
782
758
};
783
759
784
760
&i2c1 {
785
-
clock-frequency = <387000>;
761
+
clock-frequency = <384000>;
786
762
pinctrl-names = "default";
787
763
pinctrl-0 = <&pinctrl_i2c1>;
788
764
status = "okay";
···
830
806
pinctrl-names = "default";
831
807
pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>;
832
808
clocks = <&pmic_osc>;
809
+
#clock-cells = <0>;
833
810
clock-names = "osc";
834
811
clock-output-names = "pmic_clk";
835
812
interrupt-parent = <&gpio1>;
···
844
819
regulator-max-microvolt = <1300000>;
845
820
regulator-boot-on;
846
821
regulator-ramp-delay = <1250>;
847
-
rohm,dvs-run-voltage = <900000>;
848
-
rohm,dvs-idle-voltage = <850000>;
849
-
rohm,dvs-suspend-voltage = <800000>;
822
+
rohm,dvs-run-voltage = <880000>;
823
+
rohm,dvs-idle-voltage = <820000>;
824
+
rohm,dvs-suspend-voltage = <810000>;
850
825
regulator-always-on;
851
826
};
852
827
···
856
831
regulator-max-microvolt = <1300000>;
857
832
regulator-boot-on;
858
833
regulator-ramp-delay = <1250>;
859
-
rohm,dvs-run-voltage = <1000000>;
860
-
rohm,dvs-idle-voltage = <900000>;
834
+
rohm,dvs-run-voltage = <950000>;
835
+
rohm,dvs-idle-voltage = <850000>;
861
836
regulator-always-on;
862
837
};
863
838
···
866
841
regulator-min-microvolt = <700000>;
867
842
regulator-max-microvolt = <1300000>;
868
843
regulator-boot-on;
869
-
rohm,dvs-run-voltage = <900000>;
844
+
rohm,dvs-run-voltage = <850000>;
870
845
};
871
846
872
847
buck4_reg: BUCK4 {
873
848
regulator-name = "buck4";
874
849
regulator-min-microvolt = <700000>;
875
850
regulator-max-microvolt = <1300000>;
876
-
rohm,dvs-run-voltage = <1000000>;
851
+
rohm,dvs-run-voltage = <930000>;
877
852
};
878
853
879
854
buck5_reg: BUCK5 {
···
981
956
};
982
957
983
958
&i2c2 {
984
-
clock-frequency = <387000>;
959
+
clock-frequency = <384000>;
985
960
pinctrl-names = "default";
986
961
pinctrl-0 = <&pinctrl_i2c2>;
987
962
status = "okay";
988
963
989
-
magnetometer@1e {
964
+
magnetometer: magnetometer@1e {
990
965
compatible = "st,lsm9ds1-magn";
991
966
reg = <0x1e>;
992
967
pinctrl-names = "default";
···
1030
1005
};
1031
1006
1032
1007
&i2c3 {
1033
-
clock-frequency = <387000>;
1008
+
clock-frequency = <384000>;
1034
1009
pinctrl-names = "default";
1035
1010
pinctrl-0 = <&pinctrl_i2c3>;
1036
1011
status = "okay";
···
1048
1023
DBVDD-supply = <®_aud_1v8>;
1049
1024
AVDD-supply = <®_aud_1v8>;
1050
1025
CPVDD-supply = <®_aud_1v8>;
1051
-
MICVDD-supply = <®_aud_1v8>;
1026
+
MICVDD-supply = <®_mic_2v4>;
1052
1027
PLLVDD-supply = <®_aud_1v8>;
1053
1028
SPKVDD1-supply = <®_vsys_3v4>;
1054
1029
SPKVDD2-supply = <®_vsys_3v4>;
···
1120
1095
};
1121
1096
1122
1097
&i2c4 {
1123
-
clock-frequency = <387000>;
1098
+
clock-frequency = <384000>;
1124
1099
pinctrl-names = "default";
1125
1100
pinctrl-0 = <&pinctrl_i2c4>;
1126
1101
status = "okay";
···
1152
1127
interrupt-parent = <&gpio3>;
1153
1128
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
1154
1129
phys = <&usb3_phy0>;
1155
-
ti,precharge-current = <130000>; /* uA */
1130
+
ti,battery-regulation-voltage = <4208000>; /* uV */
1131
+
ti,termination-current = <128000>; /* uA */
1132
+
ti,precharge-current = <128000>; /* uA */
1156
1133
ti,minimum-sys-voltage = <3700000>; /* uV */
1157
1134
ti,boost-voltage = <5000000>; /* uV */
1158
1135
ti,boost-max-current = <1500000>; /* uA */
···
1170
1143
};
1171
1144
1172
1145
&mipi_csi1 {
1146
+
assigned-clock-rates = <266000000>, <200000000>, <66000000>;
1173
1147
status = "okay";
1174
1148
1175
1149
ports {
···
1327
1299
#address-cells = <1>;
1328
1300
#size-cells = <0>;
1329
1301
dr_mode = "otg";
1330
-
snps,dis_u3_susphy_quirk;
1331
1302
usb-role-switch;
1332
1303
status = "okay";
1333
1304
···
1393
1366
mmc-pwrseq = <&usdhc2_pwrseq>;
1394
1367
post-power-on-delay-ms = <1000>;
1395
1368
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
1396
-
max-frequency = <50000000>;
1369
+
max-frequency = <100000000>;
1397
1370
disable-wp;
1398
1371
cap-sdio-irq;
1399
1372
keep-power-in-suspend;
···
1406
1379
pinctrl-0 = <&pinctrl_wdog>;
1407
1380
fsl,ext-reset-output;
1408
1381
status = "okay";
1382
+
};
1383
+
1384
+
&a53_opp_table {
1385
+
opp-1000000000 {
1386
+
opp-microvolt = <850000>;
1387
+
};
1388
+
1389
+
opp-1500000000 {
1390
+
opp-microvolt = <950000>;
1391
+
};
1409
1392
};
-2
arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
-2
arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
+40
arch/arm64/boot/dts/freescale/imx8mq.dtsi
+40
arch/arm64/boot/dts/freescale/imx8mq.dtsi
···
940
940
clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
941
941
<&clk IMX8MQ_CLK_UART1_ROOT>;
942
942
clock-names = "ipg", "per";
943
+
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
944
+
dma-names = "rx", "tx";
943
945
status = "disabled";
944
946
};
945
947
···
953
951
clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
954
952
<&clk IMX8MQ_CLK_UART3_ROOT>;
955
953
clock-names = "ipg", "per";
954
+
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
955
+
dma-names = "rx", "tx";
956
956
status = "disabled";
957
957
};
958
958
···
966
962
clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
967
963
<&clk IMX8MQ_CLK_UART2_ROOT>;
968
964
clock-names = "ipg", "per";
965
+
dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
966
+
dma-names = "rx", "tx";
969
967
status = "disabled";
970
968
};
971
969
···
1163
1157
clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
1164
1158
<&clk IMX8MQ_CLK_UART4_ROOT>;
1165
1159
clock-names = "ipg", "per";
1160
+
dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1161
+
dma-names = "rx", "tx";
1166
1162
status = "disabled";
1167
1163
};
1168
1164
···
1610
1602
<&clk IMX8MQ_SYS1_PLL_80M>;
1611
1603
assigned-clock-rates = <250000000>, <100000000>,
1612
1604
<10000000>;
1605
+
status = "disabled";
1606
+
};
1607
+
1608
+
pcie1_ep: pcie-ep@33c00000 {
1609
+
compatible = "fsl,imx8mq-pcie-ep";
1610
+
reg = <0x33c00000 0x000400000>,
1611
+
<0x20000000 0x08000000>;
1612
+
reg-names = "dbi", "addr_space";
1613
+
num-lanes = <1>;
1614
+
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1615
+
interrupt-names = "dma";
1616
+
fsl,max-link-speed = <2>;
1617
+
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
1618
+
<&clk IMX8MQ_CLK_PCIE2_PHY>,
1619
+
<&clk IMX8MQ_CLK_PCIE2_PHY>,
1620
+
<&clk IMX8MQ_CLK_PCIE2_AUX>;
1621
+
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1622
+
power-domains = <&pgc_pcie>;
1623
+
resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1624
+
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1625
+
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1626
+
reset-names = "pciephy", "apps", "turnoff";
1627
+
assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1628
+
<&clk IMX8MQ_CLK_PCIE2_PHY>,
1629
+
<&clk IMX8MQ_CLK_PCIE2_AUX>;
1630
+
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1631
+
<&clk IMX8MQ_SYS2_PLL_100M>,
1632
+
<&clk IMX8MQ_SYS1_PLL_80M>;
1633
+
assigned-clock-rates = <250000000>, <100000000>,
1634
+
<10000000>;
1635
+
num-ib-windows = <4>;
1636
+
num-ob-windows = <4>;
1613
1637
status = "disabled";
1614
1638
};
1615
1639
+16
arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts
+16
arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2022 Toradex
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "imx8qm-apalis.dtsi"
9
+
#include "imx8-apalis-eval.dtsi"
10
+
11
+
/ {
12
+
model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board";
13
+
compatible = "toradex,apalis-imx8-eval",
14
+
"toradex,apalis-imx8",
15
+
"fsl,imx8qm";
16
+
};
+16
arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts
+16
arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2022 Toradex
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "imx8qm-apalis.dtsi"
9
+
#include "imx8-apalis-ixora-v1.1.dtsi"
10
+
11
+
/ {
12
+
model = "Toradex Apalis iMX8QM/QP on Apalis Ixora V1.1 Carrier Board";
13
+
compatible = "toradex,apalis-imx8-ixora-v1.1",
14
+
"toradex,apalis-imx8",
15
+
"fsl,imx8qm";
16
+
};
+16
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts
+16
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2022 Toradex
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "imx8qm-apalis-v1.1.dtsi"
9
+
#include "imx8-apalis-eval.dtsi"
10
+
11
+
/ {
12
+
model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board";
13
+
compatible = "toradex,apalis-imx8-v1.1-eval",
14
+
"toradex,apalis-imx8-v1.1",
15
+
"fsl,imx8qm";
16
+
};
+16
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts
+16
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2022 Toradex
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "imx8qm-apalis-v1.1.dtsi"
9
+
#include "imx8-apalis-ixora-v1.1.dtsi"
10
+
11
+
/ {
12
+
model = "Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.1 Carrier Board";
13
+
compatible = "toradex,apalis-imx8-v1.1-ixora-v1.1",
14
+
"toradex,apalis-imx8-v1.1",
15
+
"fsl,imx8qm";
16
+
};
+16
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts
+16
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2022 Toradex
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "imx8qm-apalis-v1.1.dtsi"
9
+
#include "imx8-apalis-ixora-v1.2.dtsi"
10
+
11
+
/ {
12
+
model = "Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.2 Carrier Board";
13
+
compatible = "toradex,apalis-imx8-v1.1-ixora-v1.2",
14
+
"toradex,apalis-imx8-v1.1",
15
+
"fsl,imx8qm";
16
+
};
+16
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi
+16
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2022 Toradex
4
+
*/
5
+
6
+
#include <dt-bindings/pwm/pwm.h>
7
+
#include "imx8qm.dtsi"
8
+
#include "imx8-apalis-v1.1.dtsi"
9
+
10
+
/ {
11
+
model = "Toradex Apalis iMX8QM V1.1";
12
+
compatible = "toradex,apalis-imx8-v1.1",
13
+
"fsl,imx8qm";
14
+
};
15
+
16
+
/* TODO: Cooling Maps */
+340
arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
+340
arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2022 Toradex
4
+
*/
5
+
6
+
#include "imx8qm-apalis-v1.1.dtsi"
7
+
8
+
/ {
9
+
model = "Toradex Apalis iMX8QM";
10
+
compatible = "toradex,apalis-imx8",
11
+
"fsl,imx8qm";
12
+
};
13
+
14
+
ðphy0 {
15
+
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
16
+
};
17
+
18
+
/*
19
+
* Apalis iMX8QM V1.0 has PHY KSZ9031. the Micrel PHY driver
20
+
* doesn't support setting internal PHY delay for TXC line for
21
+
* this PHY model. Use delay on MAC side instead.
22
+
*/
23
+
&fec1 {
24
+
fsl,rgmii_txc_dly;
25
+
phy-mode = "rgmii-rxid";
26
+
};
27
+
28
+
/* TODO: Apalis HDMI1 */
29
+
30
+
/* Apalis I2C2 (DDC) */
31
+
&i2c0 {
32
+
pinctrl-names = "default";
33
+
pinctrl-0 = <&pinctrl_lpi2c0>;
34
+
#address-cells = <1>;
35
+
#size-cells = <0>;
36
+
clock-frequency = <100000>;
37
+
};
38
+
39
+
&lsio_gpio0 {
40
+
gpio-line-names = "MXM3_279",
41
+
"MXM3_277",
42
+
"MXM3_135",
43
+
"MXM3_203",
44
+
"MXM3_201",
45
+
"MXM3_275",
46
+
"MXM3_110",
47
+
"MXM3_120",
48
+
"MXM3_1/GPIO1",
49
+
"MXM3_3/GPIO2",
50
+
"MXM3_124",
51
+
"MXM3_122",
52
+
"MXM3_5/GPIO3",
53
+
"MXM3_7/GPIO4",
54
+
"",
55
+
"",
56
+
"MXM3_4",
57
+
"MXM3_211",
58
+
"MXM3_209",
59
+
"MXM3_2",
60
+
"MXM3_136",
61
+
"MXM3_134",
62
+
"MXM3_6",
63
+
"MXM3_8",
64
+
"MXM3_112",
65
+
"MXM3_118",
66
+
"MXM3_114",
67
+
"MXM3_116";
68
+
};
69
+
70
+
&lsio_gpio1 {
71
+
gpio-line-names = "",
72
+
"",
73
+
"",
74
+
"",
75
+
"MXM3_286",
76
+
"",
77
+
"MXM3_87",
78
+
"MXM3_99",
79
+
"MXM3_138",
80
+
"MXM3_140",
81
+
"MXM3_239",
82
+
"",
83
+
"MXM3_281",
84
+
"MXM3_283",
85
+
"MXM3_126",
86
+
"MXM3_132",
87
+
"",
88
+
"",
89
+
"",
90
+
"",
91
+
"MXM3_173",
92
+
"MXM3_175",
93
+
"MXM3_123";
94
+
};
95
+
96
+
&lsio_gpio2 {
97
+
gpio-line-names = "",
98
+
"",
99
+
"",
100
+
"",
101
+
"",
102
+
"",
103
+
"",
104
+
"MXM3_198",
105
+
"MXM3_35",
106
+
"MXM3_164",
107
+
"",
108
+
"",
109
+
"",
110
+
"",
111
+
"MXM3_217",
112
+
"MXM3_215",
113
+
"",
114
+
"",
115
+
"MXM3_193",
116
+
"MXM3_194",
117
+
"MXM3_37",
118
+
"",
119
+
"MXM3_271",
120
+
"MXM3_273",
121
+
"MXM3_195",
122
+
"MXM3_197",
123
+
"MXM3_177",
124
+
"MXM3_179",
125
+
"MXM3_181",
126
+
"MXM3_183",
127
+
"MXM3_185",
128
+
"MXM3_187";
129
+
};
130
+
131
+
&lsio_gpio3 {
132
+
gpio-line-names = "MXM3_191",
133
+
"",
134
+
"MXM3_221",
135
+
"MXM3_225",
136
+
"MXM3_223",
137
+
"MXM3_227",
138
+
"MXM3_200",
139
+
"MXM3_235",
140
+
"MXM3_231",
141
+
"MXM3_229",
142
+
"MXM3_233",
143
+
"MXM3_204",
144
+
"MXM3_196",
145
+
"",
146
+
"MXM3_202",
147
+
"",
148
+
"",
149
+
"",
150
+
"MXM3_305",
151
+
"MXM3_307",
152
+
"MXM3_309",
153
+
"MXM3_311",
154
+
"MXM3_315",
155
+
"MXM3_317",
156
+
"MXM3_319",
157
+
"MXM3_321",
158
+
"MXM3_15/GPIO7",
159
+
"MXM3_63",
160
+
"MXM3_17/GPIO8",
161
+
"MXM3_12",
162
+
"MXM3_14",
163
+
"MXM3_16";
164
+
};
165
+
166
+
&lsio_gpio4 {
167
+
gpio-line-names = "MXM3_18",
168
+
"MXM3_11/GPIO5",
169
+
"MXM3_13/GPIO6",
170
+
"MXM3_274",
171
+
"MXM3_84",
172
+
"MXM3_262",
173
+
"MXM3_96",
174
+
"",
175
+
"",
176
+
"",
177
+
"",
178
+
"",
179
+
"MXM3_190",
180
+
"",
181
+
"",
182
+
"",
183
+
"MXM3_269",
184
+
"MXM3_251",
185
+
"MXM3_253",
186
+
"MXM3_295",
187
+
"MXM3_299",
188
+
"MXM3_301",
189
+
"MXM3_297",
190
+
"MXM3_293",
191
+
"MXM3_291",
192
+
"MXM3_289",
193
+
"MXM3_287";
194
+
195
+
/* Enable pcie root / sata ref clock unconditionally */
196
+
pcie-sata-hog {
197
+
gpios = <27 GPIO_ACTIVE_HIGH>;
198
+
};
199
+
200
+
};
201
+
202
+
&lsio_gpio5 {
203
+
gpio-line-names = "",
204
+
"",
205
+
"",
206
+
"",
207
+
"",
208
+
"",
209
+
"",
210
+
"",
211
+
"",
212
+
"",
213
+
"",
214
+
"",
215
+
"",
216
+
"",
217
+
"MXM3_150",
218
+
"MXM3_160",
219
+
"MXM3_162",
220
+
"MXM3_144",
221
+
"MXM3_146",
222
+
"MXM3_148",
223
+
"MXM3_152",
224
+
"MXM3_156",
225
+
"MXM3_158",
226
+
"MXM3_159",
227
+
"MXM3_184",
228
+
"MXM3_180",
229
+
"MXM3_186",
230
+
"MXM3_188",
231
+
"MXM3_176",
232
+
"MXM3_178";
233
+
};
234
+
235
+
&lsio_gpio6 {
236
+
gpio-line-names = "",
237
+
"",
238
+
"",
239
+
"",
240
+
"",
241
+
"",
242
+
"",
243
+
"",
244
+
"",
245
+
"",
246
+
"MXM3_261",
247
+
"MXM3_263",
248
+
"MXM3_259",
249
+
"MXM3_257",
250
+
"MXM3_255",
251
+
"MXM3_128",
252
+
"MXM3_130",
253
+
"MXM3_265",
254
+
"MXM3_249",
255
+
"MXM3_247",
256
+
"MXM3_245",
257
+
"MXM3_243";
258
+
};
259
+
260
+
&pinctrl_fec1 {
261
+
fsl,pins =
262
+
/* Use pads in 1.8V mode */
263
+
<IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>,
264
+
<IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020>,
265
+
<IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>,
266
+
<IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020>,
267
+
<IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020>,
268
+
<IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020>,
269
+
<IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020>,
270
+
<IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020>,
271
+
<IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020>,
272
+
<IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020>,
273
+
<IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020>,
274
+
<IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020>,
275
+
<IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020>,
276
+
<IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020>,
277
+
<IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020>,
278
+
<IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020>,
279
+
/* On-module ETH_RESET# */
280
+
<IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020>,
281
+
/* On-module ETH_INT# */
282
+
<IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000060>;
283
+
};
284
+
285
+
&pinctrl_fec1_sleep {
286
+
fsl,pins =
287
+
<IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>,
288
+
<IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040>,
289
+
<IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040>,
290
+
<IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040>,
291
+
<IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040>,
292
+
<IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040>,
293
+
<IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040>,
294
+
<IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040>,
295
+
<IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040>,
296
+
<IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040>,
297
+
<IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040>,
298
+
<IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040>,
299
+
<IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040>,
300
+
<IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040>,
301
+
<IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040>,
302
+
<IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040>,
303
+
<IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x04000040>,
304
+
<IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000040>;
305
+
};
306
+
307
+
&iomuxc {
308
+
/* Apalis I2C2 (DDC) */
309
+
pinctrl_lpi2c0: lpi2c0grp {
310
+
fsl,pins =
311
+
<IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x04000022>,
312
+
<IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x04000022>;
313
+
};
314
+
};
315
+
316
+
/* On-module PCIe_CTRL0_CLKREQ */
317
+
&pinctrl_pcie_sata_refclk {
318
+
fsl,pins =
319
+
<IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021>;
320
+
};
321
+
322
+
/* TODO: On-module Wi-Fi */
323
+
324
+
/* Apalis MMC1 */
325
+
&usdhc2 {
326
+
/*
327
+
* The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates
328
+
* issues with certain SD cards, disable 1.8V signaling for now.
329
+
*/
330
+
no-1-8-v;
331
+
};
332
+
333
+
/* Apalis SD1 */
334
+
&usdhc3 {
335
+
/*
336
+
* The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates
337
+
* issues with certain SD cards, disable 1.8V signaling for now.
338
+
*/
339
+
no-1-8-v;
340
+
};
+44
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
+44
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
···
16
16
"uart4_lpcg_ipg_clk";
17
17
power-domains = <&pd IMX_SC_R_UART_4>;
18
18
};
19
+
20
+
can1_lpcg: clock-controller@5ace0000 {
21
+
compatible = "fsl,imx8qxp-lpcg";
22
+
reg = <0x5ace0000 0x10000>;
23
+
#clock-cells = <1>;
24
+
clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>,
25
+
<&dma_ipg_clk>, <&dma_ipg_clk>;
26
+
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
27
+
clock-output-names = "can1_lpcg_pe_clk",
28
+
"can1_lpcg_ipg_clk",
29
+
"can1_lpcg_chi_clk";
30
+
power-domains = <&pd IMX_SC_R_CAN_1>;
31
+
};
32
+
33
+
can2_lpcg: clock-controller@5acf0000 {
34
+
compatible = "fsl,imx8qxp-lpcg";
35
+
reg = <0x5acf0000 0x10000>;
36
+
#clock-cells = <1>;
37
+
clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>,
38
+
<&dma_ipg_clk>, <&dma_ipg_clk>;
39
+
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
40
+
clock-output-names = "can2_lpcg_pe_clk",
41
+
"can2_lpcg_ipg_clk",
42
+
"can2_lpcg_chi_clk";
43
+
power-domains = <&pd IMX_SC_R_CAN_2>;
44
+
};
45
+
};
46
+
47
+
&flexcan1 {
48
+
fsl,clk-source = /bits/ 8 <1>;
49
+
};
50
+
51
+
&flexcan2 {
52
+
clocks = <&can1_lpcg 1>,
53
+
<&can1_lpcg 0>;
54
+
assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>;
55
+
fsl,clk-source = /bits/ 8 <1>;
56
+
};
57
+
58
+
&flexcan3 {
59
+
clocks = <&can2_lpcg 1>,
60
+
<&can2_lpcg 0>;
61
+
assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>;
62
+
fsl,clk-source = /bits/ 8 <1>;
19
63
};
20
64
21
65
&lpuart0 {
+4
arch/arm64/boot/dts/freescale/imx8qm.dtsi
+4
arch/arm64/boot/dts/freescale/imx8qm.dtsi
···
23
23
serial1 = &lpuart1;
24
24
serial2 = &lpuart2;
25
25
serial3 = &lpuart3;
26
+
vpu_core0 = &vpu_core0;
27
+
vpu_core1 = &vpu_core1;
28
+
vpu_core2 = &vpu_core2;
26
29
};
27
30
28
31
cpus {
···
215
212
};
216
213
217
214
/* sorted in register address */
215
+
#include "imx8-ss-vpu.dtsi"
218
216
#include "imx8-ss-img.dtsi"
219
217
#include "imx8-ss-dma.dtsi"
220
218
#include "imx8-ss-conn.dtsi"
+16
arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts
+16
arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2018-2021 Toradex
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "imx8qxp-colibri.dtsi"
9
+
#include "imx8x-colibri-aster.dtsi"
10
+
11
+
/ {
12
+
model = "Toradex Colibri iMX8QXP on Aster Board";
13
+
compatible = "toradex,colibri-imx8x-aster",
14
+
"toradex,colibri-imx8x",
15
+
"fsl,imx8qxp";
16
+
};
+3
-3
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts
+3
-3
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0+ OR MIT
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
2
/*
3
3
* Copyright 2019 Toradex
4
4
*/
···
6
6
/dts-v1/;
7
7
8
8
#include "imx8qxp-colibri.dtsi"
9
-
#include "imx8qxp-colibri-eval-v3.dtsi"
9
+
#include "imx8x-colibri-eval-v3.dtsi"
10
10
11
11
/ {
12
-
model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3";
12
+
model = "Toradex Colibri iMX8QXP on Colibri Evaluation Board V3";
13
13
compatible = "toradex,colibri-imx8x-eval-v3",
14
14
"toradex,colibri-imx8x", "fsl,imx8qxp";
15
15
};
-62
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
-62
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
···
1
-
// SPDX-License-Identifier: GPL-2.0+ OR MIT
2
-
/*
3
-
* Copyright 2019 Toradex
4
-
*/
5
-
6
-
#include <dt-bindings/input/linux-event-codes.h>
7
-
8
-
/ {
9
-
aliases {
10
-
rtc0 = &rtc_i2c;
11
-
rtc1 = &rtc;
12
-
};
13
-
14
-
gpio-keys {
15
-
compatible = "gpio-keys";
16
-
pinctrl-names = "default";
17
-
pinctrl-0 = <&pinctrl_gpiokeys>;
18
-
19
-
key-wakeup {
20
-
label = "Wake-Up";
21
-
gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
22
-
linux,code = <KEY_WAKEUP>;
23
-
debounce-interval = <10>;
24
-
wakeup-source;
25
-
};
26
-
};
27
-
};
28
-
29
-
&i2c1 {
30
-
status = "okay";
31
-
32
-
/* M41T0M6 real time clock on carrier board */
33
-
rtc_i2c: rtc@68 {
34
-
compatible = "st,m41t0";
35
-
reg = <0x68>;
36
-
};
37
-
};
38
-
39
-
/* Colibri UART_B */
40
-
&lpuart0 {
41
-
status = "okay";
42
-
};
43
-
44
-
/* Colibri UART_C */
45
-
&lpuart2 {
46
-
status = "okay";
47
-
};
48
-
49
-
/* Colibri UART_A */
50
-
&lpuart3 {
51
-
status = "okay";
52
-
};
53
-
54
-
/* Colibri FastEthernet */
55
-
&fec1 {
56
-
status = "okay";
57
-
};
58
-
59
-
/* Colibri SD/MMC Card */
60
-
&usdhc2 {
61
-
status = "okay";
62
-
};
+16
arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts
+16
arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2018-2021 Toradex
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "imx8qxp-colibri.dtsi"
9
+
#include "imx8x-colibri-iris-v2.dtsi"
10
+
11
+
/ {
12
+
model = "Toradex Colibri iMX8QXP on Colibri Iris V2 Board";
13
+
compatible = "toradex,colibri-imx8x-iris-v2",
14
+
"toradex,colibri-imx8x",
15
+
"fsl,imx8qxp";
16
+
};
+16
arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts
+16
arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2018-2021 Toradex
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "imx8qxp-colibri.dtsi"
9
+
#include "imx8x-colibri-iris.dtsi"
10
+
11
+
/ {
12
+
model = "Toradex Colibri iMX8QXP on Colibri Iris Board";
13
+
compatible = "toradex,colibri-imx8x-iris",
14
+
"toradex,colibri-imx8x",
15
+
"fsl,imx8qxp";
16
+
};
+3
-589
arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
+3
-589
arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
···
1
-
// SPDX-License-Identifier: GPL-2.0+ OR MIT
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
2
/*
3
3
* Copyright 2019 Toradex
4
4
*/
5
5
6
6
#include "imx8qxp.dtsi"
7
+
#include "imx8x-colibri.dtsi"
7
8
8
9
/ {
9
-
model = "Toradex Colibri iMX8QXP/DX Module";
10
+
model = "Toradex Colibri iMX8QXP Module";
10
11
compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
11
-
12
-
chosen {
13
-
stdout-path = &lpuart3;
14
-
};
15
-
16
-
reg_module_3v3: regulator-module-3v3 {
17
-
compatible = "regulator-fixed";
18
-
regulator-name = "+V3.3";
19
-
regulator-min-microvolt = <3300000>;
20
-
regulator-max-microvolt = <3300000>;
21
-
};
22
-
};
23
-
24
-
/* On-module I2C */
25
-
&i2c0 {
26
-
#address-cells = <1>;
27
-
#size-cells = <0>;
28
-
clock-frequency = <100000>;
29
-
pinctrl-names = "default";
30
-
pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
31
-
status = "okay";
32
-
33
-
/* Touch controller */
34
-
touchscreen@2c {
35
-
compatible = "adi,ad7879-1";
36
-
pinctrl-names = "default";
37
-
pinctrl-0 = <&pinctrl_ad7879_int>;
38
-
reg = <0x2c>;
39
-
interrupt-parent = <&lsio_gpio3>;
40
-
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
41
-
touchscreen-max-pressure = <4096>;
42
-
adi,resistance-plate-x = <120>;
43
-
adi,first-conversion-delay = /bits/ 8 <3>;
44
-
adi,acquisition-time = /bits/ 8 <1>;
45
-
adi,median-filter-size = /bits/ 8 <2>;
46
-
adi,averaging = /bits/ 8 <1>;
47
-
adi,conversion-interval = /bits/ 8 <255>;
48
-
};
49
-
};
50
-
51
-
/* Colibri I2C */
52
-
&i2c1 {
53
-
#address-cells = <1>;
54
-
#size-cells = <0>;
55
-
clock-frequency = <100000>;
56
-
pinctrl-names = "default";
57
-
pinctrl-0 = <&pinctrl_i2c1>;
58
-
};
59
-
60
-
/* Colibri UART_B */
61
-
&lpuart0 {
62
-
pinctrl-names = "default";
63
-
pinctrl-0 = <&pinctrl_lpuart0>;
64
-
};
65
-
66
-
/* Colibri UART_C */
67
-
&lpuart2 {
68
-
pinctrl-names = "default";
69
-
pinctrl-0 = <&pinctrl_lpuart2>;
70
-
};
71
-
72
-
/* Colibri UART_A */
73
-
&lpuart3 {
74
-
pinctrl-names = "default";
75
-
pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
76
-
};
77
-
78
-
/* Colibri FastEthernet */
79
-
&fec1 {
80
-
pinctrl-names = "default", "sleep";
81
-
pinctrl-0 = <&pinctrl_fec1>;
82
-
pinctrl-1 = <&pinctrl_fec1_sleep>;
83
-
phy-mode = "rmii";
84
-
phy-handle = <ðphy0>;
85
-
fsl,magic-packet;
86
-
87
-
mdio {
88
-
#address-cells = <1>;
89
-
#size-cells = <0>;
90
-
91
-
ethphy0: ethernet-phy@2 {
92
-
compatible = "ethernet-phy-ieee802.3-c22";
93
-
max-speed = <100>;
94
-
reg = <2>;
95
-
};
96
-
};
97
-
};
98
-
99
-
/* On-module eMMC */
100
-
&usdhc1 {
101
-
bus-width = <8>;
102
-
non-removable;
103
-
no-sd;
104
-
no-sdio;
105
-
pinctrl-names = "default", "state_100mhz", "state_200mhz";
106
-
pinctrl-0 = <&pinctrl_usdhc1>;
107
-
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
108
-
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
109
-
status = "okay";
110
-
};
111
-
112
-
/* Colibri SD/MMC Card */
113
-
&usdhc2 {
114
-
bus-width = <4>;
115
-
cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
116
-
vmmc-supply = <®_module_3v3>;
117
-
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
118
-
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
119
-
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
120
-
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
121
-
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
122
-
disable-wp;
123
-
};
124
-
125
-
&iomuxc {
126
-
pinctrl-names = "default";
127
-
pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>;
128
-
129
-
/* On-module touch pen-down interrupt */
130
-
pinctrl_ad7879_int: ad7879intgrp {
131
-
fsl,pins = <
132
-
IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21
133
-
>;
134
-
};
135
-
136
-
/* Colibri Analogue Inputs */
137
-
pinctrl_adc0: adc0grp {
138
-
fsl,pins = <
139
-
IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */
140
-
IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */
141
-
IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */
142
-
IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */
143
-
>;
144
-
};
145
-
146
-
pinctrl_can_int: canintgrp {
147
-
fsl,pins = <
148
-
IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */
149
-
>;
150
-
};
151
-
152
-
pinctrl_csi_ctl: csictlgrp {
153
-
fsl,pins = <
154
-
IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */
155
-
IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */
156
-
>;
157
-
};
158
-
159
-
pinctrl_ext_io0: extio0grp {
160
-
fsl,pins = <
161
-
IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */
162
-
>;
163
-
};
164
-
165
-
/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
166
-
pinctrl_fec1: fec1grp {
167
-
fsl,pins = <
168
-
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
169
-
IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
170
-
IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61
171
-
IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061
172
-
IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61
173
-
IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61
174
-
IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61
175
-
IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61
176
-
IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61
177
-
IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61
178
-
>;
179
-
};
180
-
181
-
pinctrl_fec1_sleep: fec1slpgrp {
182
-
fsl,pins = <
183
-
IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041
184
-
IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041
185
-
IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41
186
-
IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41
187
-
IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41
188
-
IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41
189
-
IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41
190
-
IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41
191
-
IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41
192
-
IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41
193
-
>;
194
-
};
195
-
196
-
/* Colibri optional CAN on UART_B RTS/CTS */
197
-
pinctrl_flexcan1: flexcan0grp {
198
-
fsl,pins = <
199
-
IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */
200
-
IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */
201
-
>;
202
-
};
203
-
204
-
/* Colibri optional CAN on PS2 */
205
-
pinctrl_flexcan2: flexcan1grp {
206
-
fsl,pins = <
207
-
IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */
208
-
IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */
209
-
>;
210
-
};
211
-
212
-
/* Colibri optional CAN on UART_A TXD/RXD */
213
-
pinctrl_flexcan3: flexcan2grp {
214
-
fsl,pins = <
215
-
IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */
216
-
IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */
217
-
>;
218
-
};
219
-
220
-
/* Colibri LCD Back-Light GPIO */
221
-
pinctrl_gpio_bl_on: gpioblongrp {
222
-
fsl,pins = <
223
-
IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */
224
-
>;
225
-
};
226
-
227
-
pinctrl_gpiokeys: gpiokeysgrp {
228
-
fsl,pins = <
229
-
IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */
230
-
>;
231
-
};
232
-
233
-
pinctrl_hog0: hog0grp {
234
-
fsl,pins = <
235
-
IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */
236
-
IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */
237
-
IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */
238
-
IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */
239
-
IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */
240
-
IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */
241
-
IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */
242
-
IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */
243
-
IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */
244
-
IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */
245
-
IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */
246
-
IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */
247
-
IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */
248
-
IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */
249
-
IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */
250
-
IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */
251
-
IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */
252
-
IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */
253
-
IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */
254
-
IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */
255
-
IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */
256
-
IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */
257
-
IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */
258
-
IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */
259
-
IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */
260
-
IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */
261
-
>;
262
-
};
263
-
264
-
pinctrl_hog1: hog1grp {
265
-
fsl,pins = <
266
-
IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */
267
-
IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */
268
-
>;
269
-
};
270
-
271
-
/*
272
-
* This pin is used in the SCFW as a UART. Using it from
273
-
* Linux would require rewritting the SCFW board file.
274
-
*/
275
-
pinctrl_hog_scfw: hogscfwgrp {
276
-
fsl,pins = <
277
-
IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */
278
-
>;
279
-
};
280
-
281
-
/* On Module I2C */
282
-
pinctrl_i2c0: i2c0grp {
283
-
fsl,pins = <
284
-
IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021
285
-
IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021
286
-
>;
287
-
};
288
-
289
-
/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
290
-
pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
291
-
fsl,pins = <
292
-
IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */
293
-
IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */
294
-
>;
295
-
};
296
-
297
-
/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
298
-
pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
299
-
fsl,pins = <
300
-
IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */
301
-
IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */
302
-
>;
303
-
};
304
-
305
-
/* Colibri I2C */
306
-
pinctrl_i2c1: i2c1grp {
307
-
fsl,pins = <
308
-
IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */
309
-
IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */
310
-
>;
311
-
};
312
-
313
-
/* Colibri Parallel RGB LCD Interface */
314
-
pinctrl_lcdif: lcdifgrp {
315
-
fsl,pins = <
316
-
IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */
317
-
IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */
318
-
IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */
319
-
IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */
320
-
IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */
321
-
IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */
322
-
IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */
323
-
IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */
324
-
IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */
325
-
IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */
326
-
IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */
327
-
IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */
328
-
IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */
329
-
IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */
330
-
IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */
331
-
IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */
332
-
IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */
333
-
IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */
334
-
IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */
335
-
IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */
336
-
IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */
337
-
IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */
338
-
IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */
339
-
IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */
340
-
IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */
341
-
>;
342
-
};
343
-
344
-
/* Colibri SPI */
345
-
pinctrl_lpspi2: lpspi2grp {
346
-
fsl,pins = <
347
-
IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */
348
-
IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */
349
-
IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */
350
-
IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */
351
-
>;
352
-
};
353
-
354
-
/* Colibri UART_B */
355
-
pinctrl_lpuart0: lpuart0grp {
356
-
fsl,pins = <
357
-
IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */
358
-
IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */
359
-
IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */
360
-
IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */
361
-
>;
362
-
};
363
-
364
-
/* Colibri UART_C */
365
-
pinctrl_lpuart2: lpuart2grp {
366
-
fsl,pins = <
367
-
IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */
368
-
IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */
369
-
>;
370
-
};
371
-
372
-
/* Colibri UART_A */
373
-
pinctrl_lpuart3: lpuart3grp {
374
-
fsl,pins = <
375
-
IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */
376
-
IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */
377
-
>;
378
-
};
379
-
380
-
/* Colibri UART_A Control */
381
-
pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
382
-
fsl,pins = <
383
-
IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */
384
-
IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */
385
-
IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */
386
-
IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */
387
-
IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */
388
-
IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */
389
-
>;
390
-
};
391
-
392
-
/* On module wifi module */
393
-
pinctrl_pcieb: pciebgrp {
394
-
fsl,pins = <
395
-
IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */
396
-
IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */
397
-
IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */
398
-
>;
399
-
};
400
-
401
-
/* Colibri PWM_A */
402
-
pinctrl_pwm_a: pwmagrp {
403
-
/* both pins are connected together, reserve the unused CSI_D05 */
404
-
fsl,pins = <
405
-
IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */
406
-
IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */
407
-
>;
408
-
};
409
-
410
-
/* Colibri PWM_B */
411
-
pinctrl_pwm_b: pwmbgrp {
412
-
fsl,pins = <
413
-
IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */
414
-
>;
415
-
};
416
-
417
-
/* Colibri PWM_C */
418
-
pinctrl_pwm_c: pwmcgrp {
419
-
fsl,pins = <
420
-
IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */
421
-
>;
422
-
};
423
-
424
-
/* Colibri PWM_D */
425
-
pinctrl_pwm_d: pwmdgrp {
426
-
/* both pins are connected together, reserve the unused CSI_D04 */
427
-
fsl,pins = <
428
-
IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */
429
-
IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */
430
-
>;
431
-
};
432
-
433
-
/* On-module I2S */
434
-
pinctrl_sai0: sai0grp {
435
-
fsl,pins = <
436
-
IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040
437
-
IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040
438
-
IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040
439
-
IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040
440
-
>;
441
-
};
442
-
443
-
/* Colibri Audio Analogue Microphone GND */
444
-
pinctrl_sgtl5000: sgtl5000grp {
445
-
fsl,pins = <
446
-
/* MIC GND EN */
447
-
IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41
448
-
>;
449
-
};
450
-
451
-
/* On-module SGTL5000 clock */
452
-
pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
453
-
fsl,pins = <
454
-
IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21
455
-
>;
456
-
};
457
-
458
-
/* On-module USB interrupt */
459
-
pinctrl_usb3503a: usb3503agrp {
460
-
fsl,pins = <
461
-
IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61
462
-
>;
463
-
};
464
-
465
-
/* Colibri USB Client Cable Detect */
466
-
pinctrl_usbc_det: usbcdetgrp {
467
-
fsl,pins = <
468
-
IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */
469
-
>;
470
-
};
471
-
472
-
/* USB Host Power Enable */
473
-
pinctrl_usbh1_reg: usbh1reggrp {
474
-
fsl,pins = <
475
-
IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */
476
-
>;
477
-
};
478
-
479
-
/* On-module eMMC */
480
-
pinctrl_usdhc1: usdhc1grp {
481
-
fsl,pins = <
482
-
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
483
-
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
484
-
IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
485
-
IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
486
-
IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
487
-
IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
488
-
IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
489
-
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
490
-
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
491
-
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
492
-
IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
493
-
IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
494
-
>;
495
-
};
496
-
497
-
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
498
-
fsl,pins = <
499
-
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
500
-
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
501
-
IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
502
-
IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
503
-
IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
504
-
IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
505
-
IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
506
-
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
507
-
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
508
-
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
509
-
IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
510
-
IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
511
-
>;
512
-
};
513
-
514
-
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
515
-
fsl,pins = <
516
-
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
517
-
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
518
-
IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
519
-
IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
520
-
IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
521
-
IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
522
-
IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
523
-
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
524
-
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
525
-
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
526
-
IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
527
-
IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
528
-
>;
529
-
};
530
-
531
-
/* Colibri SD/MMC Card Detect */
532
-
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
533
-
fsl,pins = <
534
-
IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */
535
-
>;
536
-
};
537
-
538
-
pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
539
-
fsl,pins = <
540
-
IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */
541
-
>;
542
-
};
543
-
544
-
/* Colibri SD/MMC Card */
545
-
pinctrl_usdhc2: usdhc2grp {
546
-
fsl,pins = <
547
-
IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
548
-
IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
549
-
IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
550
-
IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
551
-
IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
552
-
IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
553
-
IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
554
-
>;
555
-
};
556
-
557
-
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
558
-
fsl,pins = <
559
-
IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
560
-
IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
561
-
IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
562
-
IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
563
-
IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
564
-
IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
565
-
IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
566
-
>;
567
-
};
568
-
569
-
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
570
-
fsl,pins = <
571
-
IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
572
-
IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
573
-
IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
574
-
IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
575
-
IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
576
-
IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
577
-
IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
578
-
>;
579
-
};
580
-
581
-
pinctrl_usdhc2_sleep: usdhc2slpgrp {
582
-
fsl,pins = <
583
-
IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */
584
-
IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */
585
-
IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */
586
-
IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */
587
-
IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */
588
-
IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */
589
-
IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
590
-
>;
591
-
};
592
-
593
-
pinctrl_wifi: wifigrp {
594
-
fsl,pins = <
595
-
IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20
596
-
>;
597
-
};
598
12
};
+86
-1
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+86
-1
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
···
6
6
/dts-v1/;
7
7
8
8
#include "imx8qxp.dtsi"
9
+
#include <dt-bindings/usb/pd.h>
9
10
10
11
/ {
11
12
model = "Freescale i.MX8QXP MEK";
···
28
27
regulator-max-microvolt = <3000000>;
29
28
gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
30
29
enable-active-high;
30
+
};
31
+
32
+
gpio-sbu-mux {
33
+
compatible = "gpio-sbu-mux";
34
+
pinctrl-names = "default";
35
+
pinctrl-0 = <&pinctrl_typec_mux>;
36
+
select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>;
37
+
enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>;
38
+
orientation-switch;
39
+
40
+
port {
41
+
usb3_data_ss: endpoint {
42
+
remote-endpoint = <&typec_con_ss>;
43
+
};
44
+
};
31
45
};
32
46
};
33
47
···
143
127
};
144
128
};
145
129
};
130
+
131
+
ptn5110: tcpc@50 {
132
+
compatible = "nxp,ptn5110";
133
+
pinctrl-names = "default";
134
+
pinctrl-0 = <&pinctrl_typec>;
135
+
reg = <0x50>;
136
+
interrupt-parent = <&lsio_gpio1>;
137
+
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
138
+
139
+
port {
140
+
typec_dr_sw: endpoint {
141
+
remote-endpoint = <&usb3_drd_sw>;
142
+
};
143
+
};
144
+
145
+
usb_con1: connector {
146
+
compatible = "usb-c-connector";
147
+
label = "USB-C";
148
+
power-role = "source";
149
+
data-role = "dual";
150
+
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
151
+
152
+
ports {
153
+
#address-cells = <1>;
154
+
#size-cells = <0>;
155
+
156
+
port@1 {
157
+
reg = <1>;
158
+
typec_con_ss: endpoint {
159
+
remote-endpoint = <&usb3_data_ss>;
160
+
};
161
+
};
162
+
};
163
+
};
164
+
};
165
+
146
166
};
147
167
148
168
&lpuart0 {
···
200
148
};
201
149
202
150
&thermal_zones {
203
-
pmic-thermal0 {
151
+
pmic-thermal {
204
152
polling-delay-passive = <250>;
205
153
polling-delay = <2000>;
206
154
thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
···
255
203
wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
256
204
status = "okay";
257
205
};
206
+
207
+
&usb3_phy {
208
+
status = "okay";
209
+
};
210
+
211
+
&usbotg3 {
212
+
status = "okay";
213
+
};
214
+
215
+
&usbotg3_cdns3 {
216
+
dr_mode = "otg";
217
+
usb-role-switch;
218
+
status = "okay";
219
+
220
+
port {
221
+
usb3_drd_sw: endpoint {
222
+
remote-endpoint = <&typec_dr_sw>;
223
+
};
224
+
};
225
+
};
226
+
258
227
259
228
&vpu {
260
229
compatible = "nxp,imx8qxp-vpu";
···
337
264
fsl,pins = <
338
265
IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
339
266
IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
267
+
>;
268
+
};
269
+
270
+
pinctrl_typec: typecgrp {
271
+
fsl,pins = <
272
+
IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
273
+
>;
274
+
};
275
+
276
+
pinctrl_typec_mux: typecmuxgrp {
277
+
fsl,pins = <
278
+
IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
340
279
>;
341
280
};
342
281
+44
arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi
+44
arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2018-2021 Toradex
4
+
*/
5
+
6
+
&colibri_gpio_keys {
7
+
status = "okay";
8
+
};
9
+
10
+
/* Colibri Ethernet */
11
+
&fec1 {
12
+
status = "okay";
13
+
};
14
+
15
+
&iomuxc {
16
+
pinctrl-names = "default";
17
+
pinctrl-0 = <&pinctrl_hog0>;
18
+
};
19
+
20
+
/* Colibri SPI */
21
+
&lpspi2 {
22
+
cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>,
23
+
<&lsio_gpio5 2 GPIO_ACTIVE_LOW>;
24
+
};
25
+
26
+
/* Colibri UART_B */
27
+
&lpuart0 {
28
+
status = "okay";
29
+
};
30
+
31
+
/* Colibri UART_C */
32
+
&lpuart2 {
33
+
status = "okay";
34
+
};
35
+
36
+
/* Colibri UART_A */
37
+
&lpuart3 {
38
+
status= "okay";
39
+
};
40
+
41
+
/* Colibri SDCard */
42
+
&usdhc2 {
43
+
status = "okay";
44
+
};
+90
arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
+90
arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2019 Toradex
4
+
*/
5
+
6
+
#include <dt-bindings/input/linux-event-codes.h>
7
+
8
+
/ {
9
+
aliases {
10
+
rtc0 = &rtc_i2c;
11
+
rtc1 = &rtc;
12
+
};
13
+
14
+
/* fixed crystal dedicated to mcp25xx */
15
+
clk16m: clock-16mhz {
16
+
compatible = "fixed-clock";
17
+
#clock-cells = <0>;
18
+
clock-frequency = <16000000>;
19
+
};
20
+
};
21
+
22
+
&colibri_gpio_keys {
23
+
status = "okay";
24
+
};
25
+
26
+
&i2c1 {
27
+
status = "okay";
28
+
29
+
/* M41T0M6 real time clock on carrier board */
30
+
rtc_i2c: rtc@68 {
31
+
compatible = "st,m41t0";
32
+
reg = <0x68>;
33
+
};
34
+
};
35
+
36
+
/* Colibri SPI */
37
+
&lpspi2 {
38
+
status = "okay";
39
+
40
+
mcp2515: can@0 {
41
+
compatible = "microchip,mcp2515";
42
+
reg = <0>;
43
+
interrupt-parent = <&lsio_gpio3>;
44
+
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
45
+
pinctrl-0 = <&pinctrl_can_int>;
46
+
pinctrl-names = "default";
47
+
clocks = <&clk16m>;
48
+
spi-max-frequency = <10000000>;
49
+
};
50
+
};
51
+
52
+
/* Colibri UART_B */
53
+
&lpuart0 {
54
+
status = "okay";
55
+
};
56
+
57
+
/* Colibri UART_C */
58
+
&lpuart2 {
59
+
status = "okay";
60
+
};
61
+
62
+
/* Colibri PWM_B */
63
+
&lsio_pwm0 {
64
+
status = "okay";
65
+
};
66
+
67
+
/* Colibri PWM_C */
68
+
&lsio_pwm1 {
69
+
status = "okay";
70
+
};
71
+
72
+
/* Colibri PWM_D */
73
+
&lsio_pwm2 {
74
+
status = "okay";
75
+
};
76
+
77
+
/* Colibri UART_A */
78
+
&lpuart3 {
79
+
status = "okay";
80
+
};
81
+
82
+
/* Colibri FastEthernet */
83
+
&fec1 {
84
+
status = "okay";
85
+
};
86
+
87
+
/* Colibri SD/MMC Card */
88
+
&usdhc2 {
89
+
status = "okay";
90
+
};
+45
arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi
+45
arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2018-2021 Toradex
4
+
*/
5
+
6
+
#include "imx8x-colibri-iris.dtsi"
7
+
8
+
/ {
9
+
reg_3v3_vmmc: regulator-3v3-vmmc {
10
+
compatible = "regulator-fixed";
11
+
pinctrl-names = "default";
12
+
pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
13
+
enable-active-high;
14
+
gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
15
+
regulator-max-microvolt = <3300000>;
16
+
regulator-min-microvolt = <3300000>;
17
+
regulator-name = "3v3_vmmc";
18
+
startup-delay-us = <100>;
19
+
};
20
+
};
21
+
22
+
&iomuxc {
23
+
pinctrl-names = "default";
24
+
pinctrl-0 = <&pinctrl_lvds_converter &pinctrl_gpio_iris>;
25
+
26
+
pinctrl_enable_3v3_vmmc: enable_3v3_vmmc {
27
+
fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20>; /* SODIMM 100 */
28
+
};
29
+
30
+
pinctrl_lvds_converter: lcd-lvds {
31
+
fsl,pins = <IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x20>, /* SODIMM 55 */
32
+
/* 6B/8B mode. Select LOW - 8B mode (24bit) */
33
+
<IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x20>, /* SODIMM 63 */
34
+
<IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20>, /* SODIMM 95 */
35
+
<IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20>; /* SODIMM 99 */
36
+
};
37
+
};
38
+
39
+
/* Colibri SD/MMC Card */
40
+
&usdhc2 {
41
+
cap-power-off-card;
42
+
/delete-property/ no-1-8-v;
43
+
vmmc-supply = <®_3v3_vmmc>;
44
+
status = "okay";
45
+
};
+115
arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi
+115
arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2018-2021 Toradex
4
+
*/
5
+
6
+
/ {
7
+
aliases {
8
+
rtc0 = &rtc_i2c;
9
+
rtc1 = &rtc;
10
+
};
11
+
12
+
reg_3v3: regulator-3v3 {
13
+
compatible = "regulator-fixed";
14
+
regulator-max-microvolt = <3300000>;
15
+
regulator-min-microvolt = <3300000>;
16
+
regulator-name = "3.3V";
17
+
};
18
+
};
19
+
20
+
&colibri_gpio_keys {
21
+
status = "okay";
22
+
};
23
+
24
+
/* Colibri FastEthernet */
25
+
&fec1 {
26
+
status = "okay";
27
+
};
28
+
29
+
/* Colibri I2C */
30
+
&i2c1 {
31
+
status = "okay";
32
+
33
+
/* M41T0M6 real time clock on carrier board */
34
+
rtc_i2c: rtc@68 {
35
+
compatible = "st,m41t0";
36
+
reg = <0x68>;
37
+
};
38
+
};
39
+
40
+
&iomuxc {
41
+
pinctrl-names = "default";
42
+
pinctrl-0 = <&pinctrl_gpio_iris>;
43
+
44
+
pinctrl_gpio_iris: gpioirisgrp {
45
+
fsl,pins = <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20>, /* SODIMM 98 */
46
+
<IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20>, /* SODIMM 133 */
47
+
<IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20>, /* SODIMM 103 */
48
+
<IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20>, /* SODIMM 101 */
49
+
<IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20>, /* SODIMM 97 */
50
+
<IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020>, /* SODIMM 85 */
51
+
<IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>, /* SODIMM 79 */
52
+
<IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041>; /* SODIMM 45 */
53
+
};
54
+
55
+
pinctrl_uart1_forceoff: uart1forceoffgrp {
56
+
fsl,pins = <IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20>; /* SODIMM 22 */
57
+
};
58
+
59
+
pinctrl_uart23_forceoff: uart23forceoffgrp {
60
+
fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20>; /* SODIMM 23 */
61
+
};
62
+
};
63
+
64
+
/* Colibri SPI */
65
+
&lpspi2 {
66
+
status = "okay";
67
+
};
68
+
69
+
/* Colibri UART_B */
70
+
&lpuart0 {
71
+
status = "okay";
72
+
};
73
+
74
+
/* Colibri UART_C */
75
+
&lpuart2 {
76
+
status = "okay";
77
+
};
78
+
79
+
/* Colibri UART_A */
80
+
&lpuart3 {
81
+
status= "okay";
82
+
};
83
+
84
+
&lsio_gpio3 {
85
+
/*
86
+
* This turns the LVDS transceiver on. If one wants to turn the
87
+
* transceiver off, that property has to be deleted and the gpio handled
88
+
* in userspace.
89
+
*/
90
+
lvds-tx-on-hog {
91
+
gpio-hog;
92
+
gpios = <18 0>;
93
+
output-high;
94
+
};
95
+
};
96
+
97
+
/* Colibri PWM_B */
98
+
&lsio_pwm0 {
99
+
status = "okay";
100
+
};
101
+
102
+
/* Colibri PWM_C */
103
+
&lsio_pwm1 {
104
+
status = "okay";
105
+
};
106
+
107
+
/* Colibri PWM_D */
108
+
&lsio_pwm2 {
109
+
status = "okay";
110
+
};
111
+
112
+
/* Colibri SD/MMC Card */
113
+
&usdhc2 {
114
+
status = "okay";
115
+
};
+776
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+776
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright 2019 Toradex
4
+
*/
5
+
6
+
/ {
7
+
chosen {
8
+
stdout-path = &lpuart3;
9
+
};
10
+
11
+
colibri_gpio_keys: gpio-keys {
12
+
compatible = "gpio-keys";
13
+
pinctrl-names = "default";
14
+
pinctrl-0 = <&pinctrl_gpiokeys>;
15
+
status = "disabled";
16
+
17
+
key-wakeup {
18
+
debounce-interval = <10>;
19
+
gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
20
+
label = "Wake-Up";
21
+
linux,code = <KEY_WAKEUP>;
22
+
wakeup-source;
23
+
};
24
+
};
25
+
26
+
reg_module_3v3: regulator-module-3v3 {
27
+
compatible = "regulator-fixed";
28
+
regulator-name = "+V3.3";
29
+
regulator-min-microvolt = <3300000>;
30
+
regulator-max-microvolt = <3300000>;
31
+
};
32
+
};
33
+
34
+
/* TODO Analogue Inputs */
35
+
36
+
/* TODO Cooling maps for DX */
37
+
38
+
&cpu_alert0 {
39
+
hysteresis = <2000>;
40
+
temperature = <90000>;
41
+
type = "passive";
42
+
};
43
+
44
+
&cpu_crit0 {
45
+
hysteresis = <2000>;
46
+
temperature = <105000>;
47
+
type = "critical";
48
+
};
49
+
50
+
/* TODO flexcan1 - 3 */
51
+
52
+
/* TODO GPU */
53
+
54
+
/* On-module I2C */
55
+
&i2c0 {
56
+
#address-cells = <1>;
57
+
#size-cells = <0>;
58
+
clock-frequency = <100000>;
59
+
pinctrl-names = "default";
60
+
pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
61
+
status = "okay";
62
+
63
+
/* Touch controller */
64
+
touchscreen@2c {
65
+
compatible = "adi,ad7879-1";
66
+
pinctrl-names = "default";
67
+
pinctrl-0 = <&pinctrl_ad7879_int>;
68
+
reg = <0x2c>;
69
+
interrupt-parent = <&lsio_gpio3>;
70
+
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
71
+
touchscreen-max-pressure = <4096>;
72
+
adi,resistance-plate-x = <120>;
73
+
adi,first-conversion-delay = /bits/ 8 <3>;
74
+
adi,acquisition-time = /bits/ 8 <1>;
75
+
adi,median-filter-size = /bits/ 8 <2>;
76
+
adi,averaging = /bits/ 8 <1>;
77
+
adi,conversion-interval = /bits/ 8 <255>;
78
+
status = "disabled";
79
+
};
80
+
};
81
+
82
+
/* TODO i2c lvds0 accessible on FFC (X2) */
83
+
84
+
/* TODO i2c lvds1 accessible on FFC (X3) */
85
+
86
+
/* Colibri I2C */
87
+
&i2c1 {
88
+
#address-cells = <1>;
89
+
#size-cells = <0>;
90
+
clock-frequency = <100000>;
91
+
pinctrl-names = "default";
92
+
pinctrl-0 = <&pinctrl_i2c1>;
93
+
};
94
+
95
+
&jpegdec {
96
+
status = "okay";
97
+
};
98
+
99
+
&jpegenc {
100
+
status = "okay";
101
+
};
102
+
103
+
/* TODO Parallel RRB */
104
+
105
+
/* Colibri UART_B */
106
+
&lpuart0 {
107
+
pinctrl-names = "default";
108
+
pinctrl-0 = <&pinctrl_lpuart0>;
109
+
};
110
+
111
+
/* Colibri UART_C */
112
+
&lpuart2 {
113
+
pinctrl-names = "default";
114
+
pinctrl-0 = <&pinctrl_lpuart2>;
115
+
};
116
+
117
+
/* Colibri UART_A */
118
+
&lpuart3 {
119
+
pinctrl-names = "default";
120
+
pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
121
+
};
122
+
123
+
/* Colibri FastEthernet */
124
+
&fec1 {
125
+
pinctrl-names = "default", "sleep";
126
+
pinctrl-0 = <&pinctrl_fec1>;
127
+
pinctrl-1 = <&pinctrl_fec1_sleep>;
128
+
phy-mode = "rmii";
129
+
phy-handle = <ðphy0>;
130
+
fsl,magic-packet;
131
+
132
+
mdio {
133
+
#address-cells = <1>;
134
+
#size-cells = <0>;
135
+
136
+
ethphy0: ethernet-phy@2 {
137
+
compatible = "ethernet-phy-ieee802.3-c22";
138
+
max-speed = <100>;
139
+
reg = <2>;
140
+
};
141
+
};
142
+
};
143
+
144
+
/* Colibri SPI */
145
+
&lpspi2 {
146
+
pinctrl-names = "default";
147
+
pinctrl-0 = <&pinctrl_lpspi2>;
148
+
cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
149
+
};
150
+
151
+
&lsio_gpio0 {
152
+
gpio-line-names = "",
153
+
"SODIMM_70",
154
+
"SODIMM_60",
155
+
"SODIMM_58",
156
+
"SODIMM_78",
157
+
"SODIMM_72",
158
+
"SODIMM_80",
159
+
"SODIMM_46",
160
+
"SODIMM_62",
161
+
"SODIMM_48",
162
+
"SODIMM_74",
163
+
"SODIMM_50",
164
+
"SODIMM_52",
165
+
"SODIMM_54",
166
+
"SODIMM_66",
167
+
"SODIMM_64",
168
+
"SODIMM_68",
169
+
"",
170
+
"",
171
+
"SODIMM_82",
172
+
"SODIMM_56",
173
+
"SODIMM_28",
174
+
"SODIMM_30",
175
+
"",
176
+
"SODIMM_61",
177
+
"SODIMM_103",
178
+
"",
179
+
"",
180
+
"",
181
+
"SODIMM_25",
182
+
"SODIMM_27",
183
+
"SODIMM_100";
184
+
};
185
+
186
+
&lsio_gpio1 {
187
+
gpio-line-names = "SODIMM_86",
188
+
"SODIMM_92",
189
+
"SODIMM_90",
190
+
"SODIMM_88",
191
+
"",
192
+
"",
193
+
"",
194
+
"SODIMM_59",
195
+
"",
196
+
"SODIMM_6",
197
+
"SODIMM_8",
198
+
"",
199
+
"",
200
+
"SODIMM_2",
201
+
"SODIMM_4",
202
+
"SODIMM_34",
203
+
"SODIMM_32",
204
+
"SODIMM_63",
205
+
"SODIMM_55",
206
+
"SODIMM_33",
207
+
"SODIMM_35",
208
+
"SODIMM_36",
209
+
"SODIMM_38",
210
+
"SODIMM_21",
211
+
"SODIMM_19",
212
+
"SODIMM_140",
213
+
"SODIMM_142",
214
+
"SODIMM_196",
215
+
"SODIMM_194",
216
+
"SODIMM_186",
217
+
"SODIMM_188",
218
+
"SODIMM_138";
219
+
};
220
+
221
+
&lsio_gpio2 {
222
+
gpio-line-names = "SODIMM_23",
223
+
"",
224
+
"",
225
+
"SODIMM_144";
226
+
};
227
+
228
+
&lsio_gpio3 {
229
+
gpio-line-names = "SODIMM_96",
230
+
"SODIMM_75",
231
+
"SODIMM_37",
232
+
"SODIMM_29",
233
+
"",
234
+
"",
235
+
"",
236
+
"",
237
+
"",
238
+
"SODIMM_43",
239
+
"SODIMM_45",
240
+
"SODIMM_69",
241
+
"SODIMM_71",
242
+
"SODIMM_73",
243
+
"SODIMM_77",
244
+
"SODIMM_89",
245
+
"SODIMM_93",
246
+
"SODIMM_95",
247
+
"SODIMM_99",
248
+
"SODIMM_105",
249
+
"SODIMM_107",
250
+
"SODIMM_98",
251
+
"SODIMM_102",
252
+
"SODIMM_104",
253
+
"SODIMM_106";
254
+
};
255
+
256
+
&lsio_gpio4 {
257
+
gpio-line-names = "",
258
+
"",
259
+
"",
260
+
"SODIMM_129",
261
+
"SODIMM_133",
262
+
"SODIMM_127",
263
+
"SODIMM_131",
264
+
"",
265
+
"",
266
+
"",
267
+
"",
268
+
"",
269
+
"",
270
+
"",
271
+
"",
272
+
"",
273
+
"",
274
+
"",
275
+
"",
276
+
"SODIMM_44",
277
+
"",
278
+
"SODIMM_76",
279
+
"SODIMM_31",
280
+
"SODIMM_47",
281
+
"SODIMM_190",
282
+
"SODIMM_192",
283
+
"SODIMM_49",
284
+
"SODIMM_51",
285
+
"SODIMM_53";
286
+
};
287
+
288
+
&lsio_gpio5 {
289
+
gpio-line-names = "",
290
+
"SODIMM_57",
291
+
"SODIMM_65",
292
+
"SODIMM_85",
293
+
"",
294
+
"",
295
+
"",
296
+
"",
297
+
"SODIMM_135",
298
+
"SODIMM_137",
299
+
"UNUSABLE_SODIMM_180",
300
+
"UNUSABLE_SODIMM_184";
301
+
};
302
+
303
+
/* Colibri PWM_B */
304
+
&lsio_pwm0 {
305
+
#pwm-cells = <3>;
306
+
pinctrl-0 = <&pinctrl_pwm_b>;
307
+
pinctrl-names = "default";
308
+
};
309
+
310
+
/* Colibri PWM_C */
311
+
&lsio_pwm1 {
312
+
#pwm-cells = <3>;
313
+
pinctrl-0 = <&pinctrl_pwm_c>;
314
+
pinctrl-names = "default";
315
+
};
316
+
317
+
/* Colibri PWM_D */
318
+
&lsio_pwm2 {
319
+
#pwm-cells = <3>;
320
+
pinctrl-0 = <&pinctrl_pwm_d>;
321
+
pinctrl-names = "default";
322
+
};
323
+
324
+
/* TODO MIPI CSI */
325
+
326
+
/* TODO MIPI DSI with DSI-to-HDMI bridge lt8912 */
327
+
328
+
/* TODO on-module PCIe for Wi-Fi */
329
+
330
+
/* TODO On-module i2s / Audio */
331
+
332
+
/* On-module eMMC */
333
+
&usdhc1 {
334
+
bus-width = <8>;
335
+
non-removable;
336
+
no-sd;
337
+
no-sdio;
338
+
pinctrl-names = "default", "state_100mhz", "state_200mhz";
339
+
pinctrl-0 = <&pinctrl_usdhc1>;
340
+
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
341
+
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
342
+
status = "okay";
343
+
};
344
+
345
+
/* Colibri SD/MMC Card */
346
+
&usdhc2 {
347
+
bus-width = <4>;
348
+
cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
349
+
vmmc-supply = <®_module_3v3>;
350
+
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
351
+
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
352
+
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
353
+
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
354
+
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
355
+
disable-wp;
356
+
no-1-8-v;
357
+
};
358
+
359
+
/* TODO USB Client/Host */
360
+
361
+
/* TODO USB Host */
362
+
363
+
/* TODO VPU Encoder/Decoder */
364
+
365
+
&iomuxc {
366
+
pinctrl-names = "default";
367
+
pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>,
368
+
<&pinctrl_hog2>, <&pinctrl_lpspi2_cs2>;
369
+
370
+
/* On-module touch pen-down interrupt */
371
+
pinctrl_ad7879_int: ad7879intgrp {
372
+
fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21>;
373
+
};
374
+
375
+
/* Colibri Analogue Inputs */
376
+
pinctrl_adc0: adc0grp {
377
+
fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60>, /* SODIMM 8 */
378
+
<IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60>, /* SODIMM 6 */
379
+
<IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60>, /* SODIMM 4 */
380
+
<IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60>; /* SODIMM 2 */
381
+
};
382
+
383
+
/* Atmel MXT touchsceen + Capacitive Touch Adapter */
384
+
/* NOTE: This pingroup conflicts with pingroups
385
+
* pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them
386
+
* simultaneously.
387
+
*/
388
+
pinctrl_atmel_adap: atmeladaptergrp {
389
+
fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x21>, /* SODIMM 30 */
390
+
<IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x4000021>; /* SODIMM 28 */
391
+
};
392
+
393
+
/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
394
+
pinctrl_atmel_conn: atmelconnectorgrp {
395
+
fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x4000021>, /* SODIMM 107 */
396
+
<IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21>; /* SODIMM 106 */
397
+
};
398
+
399
+
pinctrl_can_int: canintgrp {
400
+
fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40>; /* SODIMM 73 */
401
+
};
402
+
403
+
pinctrl_csi_ctl: csictlgrp {
404
+
fsl,pins = <IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20>, /* SODIMM 77 */
405
+
<IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20>; /* SODIMM 89 */
406
+
};
407
+
408
+
pinctrl_csi_mclk: csimclkgrp {
409
+
fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041>; /* SODIMM 75 / X3-12 */
410
+
};
411
+
412
+
pinctrl_ext_io0: extio0grp {
413
+
fsl,pins = <IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040>; /* SODIMM 135 */
414
+
};
415
+
416
+
/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
417
+
pinctrl_fec1: fec1grp {
418
+
fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020>,
419
+
<IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>,
420
+
<IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61>,
421
+
<IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061>,
422
+
<IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61>,
423
+
<IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61>,
424
+
<IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61>,
425
+
<IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61>,
426
+
<IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61>,
427
+
<IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61>;
428
+
};
429
+
430
+
pinctrl_fec1_sleep: fec1slpgrp {
431
+
fsl,pins = <IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041>,
432
+
<IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041>,
433
+
<IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41>,
434
+
<IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41>,
435
+
<IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41>,
436
+
<IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41>,
437
+
<IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41>,
438
+
<IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41>,
439
+
<IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41>,
440
+
<IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41>;
441
+
};
442
+
443
+
/* Colibri optional CAN on UART_B RTS/CTS */
444
+
pinctrl_flexcan1: flexcan0grp {
445
+
fsl,pins = <IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21>, /* SODIMM 32 */
446
+
<IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21>; /* SODIMM 34 */
447
+
};
448
+
449
+
/* Colibri optional CAN on PS2 */
450
+
pinctrl_flexcan2: flexcan1grp {
451
+
fsl,pins = <IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21>, /* SODIMM 55 */
452
+
<IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21>; /* SODIMM 63 */
453
+
};
454
+
455
+
/* Colibri optional CAN on UART_A TXD/RXD */
456
+
pinctrl_flexcan3: flexcan2grp {
457
+
fsl,pins = <IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21>, /* SODIMM 35 */
458
+
<IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21>; /* SODIMM 33 */
459
+
};
460
+
461
+
/* Colibri LCD Back-Light GPIO */
462
+
pinctrl_gpio_bl_on: gpioblongrp {
463
+
fsl,pins = <IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60>; /* SODIMM 71 */
464
+
};
465
+
466
+
/* HDMI Hot Plug Detect on FFC (X2) */
467
+
pinctrl_gpio_hpd: gpiohpdgrp {
468
+
fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x20>; /* SODIMM 138 */
469
+
};
470
+
471
+
pinctrl_gpiokeys: gpiokeysgrp {
472
+
fsl,pins = <IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041>; /* SODIMM 45 */
473
+
};
474
+
475
+
pinctrl_hog0: hog0grp {
476
+
fsl,pins = <IMX8QXP_CSI_D07_CI_PI_D09 0x61>, /* SODIMM 65 */
477
+
<IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20>, /* SODIMM 69 */
478
+
<IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>, /* SODIMM 79 */
479
+
<IMX8QXP_CSI_D02_CI_PI_D04 0x61>, /* SODIMM 79 */
480
+
<IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020>, /* SODIMM 85 */
481
+
<IMX8QXP_CSI_D06_CI_PI_D08 0x61>, /* SODIMM 85 */
482
+
<IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20>, /* SODIMM 95 */
483
+
<IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20>, /* SODIMM 97 */
484
+
<IMX8QXP_CSI_D03_CI_PI_D05 0x61>, /* SODIMM 97 */
485
+
<IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20>, /* SODIMM 99 */
486
+
<IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20>, /* SODIMM 101 */
487
+
<IMX8QXP_CSI_D00_CI_PI_D02 0x61>, /* SODIMM 101 */
488
+
<IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20>, /* SODIMM 103 */
489
+
<IMX8QXP_CSI_D01_CI_PI_D03 0x61>, /* SODIMM 103 */
490
+
<IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20>, /* SODIMM 105 */
491
+
<IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20>, /* SODIMM 127 */
492
+
<IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20>, /* SODIMM 131 */
493
+
<IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20>, /* SODIMM 133 */
494
+
<IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20>, /* SODIMM 96 */
495
+
<IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20>, /* SODIMM 98 */
496
+
<IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20>, /* SODIMM 100 */
497
+
<IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20>, /* SODIMM 102 */
498
+
<IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20>; /* SODIMM 104 */
499
+
};
500
+
501
+
pinctrl_hog1: hog1grp {
502
+
fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20>, /* SODIMM 75 */
503
+
<IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20>; /* SODIMM 93 */
504
+
};
505
+
506
+
pinctrl_hog2: hog2grp {
507
+
fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20>; /* SODIMM 75 */
508
+
};
509
+
510
+
/*
511
+
* This pin is used in the SCFW as a UART. Using it from
512
+
* Linux would require rewritting the SCFW board file.
513
+
*/
514
+
pinctrl_hog_scfw: hogscfwgrp {
515
+
fsl,pins = <IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20>; /* SODIMM 144 */
516
+
};
517
+
518
+
/* On Module I2C */
519
+
pinctrl_i2c0: i2c0grp {
520
+
fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021>,
521
+
<IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021>;
522
+
};
523
+
524
+
/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
525
+
pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
526
+
fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020>, /* SODIMM 140 */
527
+
<IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020>; /* SODIMM 142 */
528
+
};
529
+
530
+
/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
531
+
pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
532
+
fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020>, /* SODIMM 186 */
533
+
<IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020>; /* SODIMM 188 */
534
+
};
535
+
536
+
/* Colibri I2C */
537
+
pinctrl_i2c1: i2c1grp {
538
+
fsl,pins = <IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021>, /* SODIMM 196 */
539
+
<IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021>; /* SODIMM 194 */
540
+
};
541
+
542
+
/* Colibri Parallel RGB LCD Interface */
543
+
pinctrl_lcdif: lcdifgrp {
544
+
fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60>, /* SODIMM 56 */
545
+
<IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60>, /* SODIMM 68 */
546
+
<IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60>, /* SODIMM 82 */
547
+
<IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x40>, /* SODIMM 44 */
548
+
<IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x40>, /* SODIMM 44 */
549
+
<IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60>, /* SODIMM 76 */
550
+
<IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60>, /* SODIMM 76 */
551
+
<IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60>, /* SODIMM 70 */
552
+
<IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60>, /* SODIMM 60 */
553
+
<IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60>, /* SODIMM 58 */
554
+
<IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60>, /* SODIMM 78 */
555
+
<IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60>, /* SODIMM 72 */
556
+
<IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60>, /* SODIMM 80 */
557
+
<IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60>, /* SODIMM 46 */
558
+
<IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60>, /* SODIMM 62 */
559
+
<IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60>, /* SODIMM 48 */
560
+
<IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60>, /* SODIMM 74 */
561
+
<IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60>, /* SODIMM 50 */
562
+
<IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60>, /* SODIMM 52 */
563
+
<IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60>, /* SODIMM 54 */
564
+
<IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60>, /* SODIMM 66 */
565
+
<IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60>, /* SODIMM 64 */
566
+
<IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60>, /* SODIMM 57 */
567
+
<IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60>, /* SODIMM 57 */
568
+
<IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60>; /* SODIMM 61 */
569
+
};
570
+
571
+
/* Colibri SPI */
572
+
pinctrl_lpspi2: lpspi2grp {
573
+
fsl,pins = <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21>, /* SODIMM 86 */
574
+
<IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040>, /* SODIMM 92 */
575
+
<IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040>, /* SODIMM 90 */
576
+
<IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040>; /* SODIMM 88 */
577
+
};
578
+
579
+
pinctrl_lpspi2_cs2: lpspi2cs2grp {
580
+
fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x21>; /* SODIMM 65 */
581
+
};
582
+
583
+
/* Colibri UART_B */
584
+
pinctrl_lpuart0: lpuart0grp {
585
+
fsl,pins = <IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020>, /* SODIMM 36 */
586
+
<IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020>, /* SODIMM 38 */
587
+
<IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020>, /* SODIMM 34 */
588
+
<IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020>; /* SODIMM 32 */
589
+
};
590
+
591
+
/* Colibri UART_C */
592
+
pinctrl_lpuart2: lpuart2grp {
593
+
fsl,pins = <IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020>, /* SODIMM 19 */
594
+
<IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020>; /* SODIMM 21 */
595
+
};
596
+
597
+
/* Colibri UART_A */
598
+
pinctrl_lpuart3: lpuart3grp {
599
+
fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020>, /* SODIMM 33 */
600
+
<IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>; /* SODIMM 35 */
601
+
};
602
+
603
+
/* Colibri UART_A Control */
604
+
pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
605
+
fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20>, /* SODIMM 23 */
606
+
<IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20>, /* SODIMM 25 */
607
+
<IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20>, /* SODIMM 27 */
608
+
<IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20>, /* SODIMM 29 */
609
+
<IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20>, /* SODIMM 31 */
610
+
<IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20>; /* SODIMM 37 */
611
+
};
612
+
613
+
/* On module wifi module */
614
+
pinctrl_pcieb: pciebgrp {
615
+
fsl,pins = <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061>, /* SODIMM 178 */
616
+
<IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061>, /* SODIMM 94 */
617
+
<IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60>; /* SODIMM 81 */
618
+
};
619
+
620
+
/* Colibri PWM_A */
621
+
pinctrl_pwm_a: pwmagrp {
622
+
/* both pins are connected together, reserve the unused CSI_D05 */
623
+
fsl,pins = <IMX8QXP_CSI_D05_CI_PI_D07 0x61>, /* SODIMM 59 */
624
+
<IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60>; /* SODIMM 59 */
625
+
};
626
+
627
+
/* Colibri PWM_B */
628
+
pinctrl_pwm_b: pwmbgrp {
629
+
fsl,pins = <IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60>; /* SODIMM 28 */
630
+
};
631
+
632
+
/* Colibri PWM_C */
633
+
pinctrl_pwm_c: pwmcgrp {
634
+
fsl,pins = <IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60>; /* SODIMM 30 */
635
+
};
636
+
637
+
/* Colibri PWM_D */
638
+
pinctrl_pwm_d: pwmdgrp {
639
+
/* both pins are connected together, reserve the unused CSI_D04 */
640
+
fsl,pins = <IMX8QXP_CSI_D04_CI_PI_D06 0x61>, /* SODIMM 67 */
641
+
<IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60>; /* SODIMM 67 */
642
+
};
643
+
644
+
/* On-module I2S */
645
+
pinctrl_sai0: sai0grp {
646
+
fsl,pins = <IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040>,
647
+
<IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040>,
648
+
<IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040>,
649
+
<IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040>;
650
+
};
651
+
652
+
/* Colibri Audio Analogue Microphone GND */
653
+
pinctrl_sgtl5000: sgtl5000grp {
654
+
fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41>;
655
+
};
656
+
657
+
/* On-module SGTL5000 clock */
658
+
pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
659
+
fsl,pins = <IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21>;
660
+
};
661
+
662
+
/* On-module USB interrupt */
663
+
pinctrl_usb3503a: usb3503agrp {
664
+
fsl,pins = <IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61>;
665
+
};
666
+
667
+
/* Colibri USB Client Cable Detect */
668
+
pinctrl_usbc_det: usbcdetgrp {
669
+
fsl,pins = <IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040>; /* SODIMM 137 */
670
+
};
671
+
672
+
/* USB Host Power Enable */
673
+
pinctrl_usbh1_reg: usbh1reggrp {
674
+
fsl,pins = <IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040>; /* SODIMM 129 */
675
+
};
676
+
677
+
/* On-module eMMC */
678
+
pinctrl_usdhc1: usdhc1grp {
679
+
fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
680
+
<IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>,
681
+
<IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>,
682
+
<IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>,
683
+
<IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>,
684
+
<IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>,
685
+
<IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>,
686
+
<IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>,
687
+
<IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>,
688
+
<IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>,
689
+
<IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>,
690
+
<IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>;
691
+
};
692
+
693
+
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
694
+
fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
695
+
<IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>,
696
+
<IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>,
697
+
<IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>,
698
+
<IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>,
699
+
<IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>,
700
+
<IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>,
701
+
<IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>,
702
+
<IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>,
703
+
<IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>,
704
+
<IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>,
705
+
<IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>;
706
+
};
707
+
708
+
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
709
+
fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
710
+
<IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>,
711
+
<IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>,
712
+
<IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>,
713
+
<IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>,
714
+
<IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>,
715
+
<IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>,
716
+
<IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>,
717
+
<IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>,
718
+
<IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>,
719
+
<IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>,
720
+
<IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>;
721
+
};
722
+
723
+
/* Colibri SD/MMC Card Detect */
724
+
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
725
+
fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021>; /* SODIMM 43 */
726
+
};
727
+
728
+
pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
729
+
fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60>; /* SODIMM 43 */
730
+
};
731
+
732
+
/* Colibri SD/MMC Card */
733
+
pinctrl_usdhc2: usdhc2grp {
734
+
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */
735
+
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */
736
+
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */
737
+
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */
738
+
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */
739
+
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */
740
+
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
741
+
};
742
+
743
+
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
744
+
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */
745
+
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */
746
+
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */
747
+
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */
748
+
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */
749
+
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */
750
+
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
751
+
};
752
+
753
+
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
754
+
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */
755
+
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */
756
+
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */
757
+
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */
758
+
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */
759
+
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */
760
+
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
761
+
};
762
+
763
+
pinctrl_usdhc2_sleep: usdhc2slpgrp {
764
+
fsl,pins = <IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60>, /* SODIMM 47 */
765
+
<IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60>, /* SODIMM 190 */
766
+
<IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60>, /* SODIMM 192 */
767
+
<IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60>, /* SODIMM 49 */
768
+
<IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60>, /* SODIMM 51 */
769
+
<IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60>, /* SODIMM 53 */
770
+
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
771
+
};
772
+
773
+
pinctrl_wifi: wifigrp {
774
+
fsl,pins = <IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20>;
775
+
};
776
+
};
+47
arch/arm64/boot/dts/freescale/imx93.dtsi
+47
arch/arm64/boot/dts/freescale/imx93.dtsi
···
153
153
nxp,no-divider;
154
154
};
155
155
156
+
tpm1: pwm@44310000 {
157
+
compatible = "fsl,imx7ulp-pwm";
158
+
reg = <0x44310000 0x1000>;
159
+
clocks = <&clk IMX93_CLK_TPM1_GATE>;
160
+
#pwm-cells = <3>;
161
+
status = "disabled";
162
+
};
163
+
156
164
tpm2: pwm@44320000 {
157
165
compatible = "fsl,imx7ulp-pwm";
158
166
reg = <0x44320000 0x10000>;
···
251
243
status = "okay";
252
244
};
253
245
246
+
bbnsm: bbnsm@44440000 {
247
+
compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd";
248
+
reg = <0x44440000 0x10000>;
249
+
250
+
bbnsm_rtc: rtc {
251
+
compatible = "nxp,imx93-bbnsm-rtc";
252
+
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
253
+
};
254
+
255
+
bbnsm_pwrkey: pwrkey {
256
+
compatible = "nxp,imx93-bbnsm-pwrkey";
257
+
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
258
+
linux,code = <KEY_POWER>;
259
+
};
260
+
};
261
+
254
262
clk: clock-controller@44450000 {
255
263
compatible = "fsl,imx93-ccm";
256
264
reg = <0x44450000 0x10000>;
···
337
313
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
338
314
clocks = <&clk IMX93_CLK_MU2_B_GATE>;
339
315
#mbox-cells = <2>;
316
+
status = "disabled";
317
+
};
318
+
319
+
tpm3: pwm@424e0000 {
320
+
compatible = "fsl,imx7ulp-pwm";
321
+
reg = <0x424e0000 0x1000>;
322
+
clocks = <&clk IMX93_CLK_TPM3_GATE>;
323
+
#pwm-cells = <3>;
340
324
status = "disabled";
341
325
};
342
326
···
463
431
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
464
432
assigned-clock-rates = <40000000>;
465
433
fsl,clk-source = /bits/ 8 <0>;
434
+
status = "disabled";
435
+
};
436
+
437
+
flexspi1: spi@425e0000 {
438
+
compatible = "nxp,imx8mm-fspi";
439
+
reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
440
+
reg-names = "fspi_base", "fspi_mmap";
441
+
#address-cells = <1>;
442
+
#size-cells = <0>;
443
+
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
444
+
clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>,
445
+
<&clk IMX93_CLK_FLEXSPI1_GATE>;
446
+
clock-names = "fspi_en", "fspi";
447
+
assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>;
448
+
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
466
449
status = "disabled";
467
450
};
468
451