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PCI: dwc: Skip waiting for L2/L3 Ready if dw_pcie_rp::skip_l23_wait is true

In NXP i.MX6QP and i.MX7D SoCs, LTSSM registers are not accessible once
PME_Turn_Off message is broadcasted to the link. So there is no way to
verify whether the link has entered L2/L3 Ready state or not.

Hence, add a new flag 'dw_pcie_rp::skip_l23_ready' and set it to 'true' for
the above mentioned SoCs. This flag when set, will allow the DWC core to
skip polling for L2/L3 Ready state and just wait for 10ms as recommended in
the PCIe spec r6.0, sec 5.3.3.2.1.

Fixes: a528d1a72597 ("PCI: imx6: Use DWC common suspend resume method")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[mani: renamed flag to skip_l23_ready and reworded description]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260114083300.3689672-2-hongxing.zhu@nxp.com

authored by

Richard Zhu and committed by
Manivannan Sadhasivam 58a17b26 86cbb7a8

+16
+5
drivers/pci/controller/dwc/pci-imx6.c
··· 114 114 #define IMX_PCIE_FLAG_BROKEN_SUSPEND BIT(9) 115 115 #define IMX_PCIE_FLAG_HAS_LUT BIT(10) 116 116 #define IMX_PCIE_FLAG_8GT_ECN_ERR051586 BIT(11) 117 + #define IMX_PCIE_FLAG_SKIP_L23_READY BIT(12) 117 118 118 119 #define imx_check_flag(pci, val) (pci->drvdata->flags & val) 119 120 ··· 1778 1777 */ 1779 1778 imx_pcie_add_lut_by_rid(imx_pcie, 0); 1780 1779 } else { 1780 + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_SKIP_L23_READY)) 1781 + pci->pp.skip_l23_ready = true; 1781 1782 pci->pp.use_atu_msg = true; 1782 1783 ret = dw_pcie_host_init(&pci->pp); 1783 1784 if (ret < 0) ··· 1841 1838 .variant = IMX6QP, 1842 1839 .flags = IMX_PCIE_FLAG_IMX_PHY | 1843 1840 IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND | 1841 + IMX_PCIE_FLAG_SKIP_L23_READY | 1844 1842 IMX_PCIE_FLAG_SUPPORTS_SUSPEND, 1845 1843 .dbi_length = 0x200, 1846 1844 .gpr = "fsl,imx6q-iomuxc-gpr", ··· 1858 1854 .variant = IMX7D, 1859 1855 .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | 1860 1856 IMX_PCIE_FLAG_HAS_APP_RESET | 1857 + IMX_PCIE_FLAG_SKIP_L23_READY | 1861 1858 IMX_PCIE_FLAG_HAS_PHY_RESET, 1862 1859 .gpr = "fsl,imx7d-iomuxc-gpr", 1863 1860 .mode_off[0] = IOMUXC_GPR12,
+10
drivers/pci/controller/dwc/pcie-designware-host.c
··· 1199 1199 return ret; 1200 1200 } 1201 1201 1202 + /* 1203 + * Some SoCs do not support reading the LTSSM register after 1204 + * PME_Turn_Off broadcast. For those SoCs, skip waiting for L2/L3 Ready 1205 + * state and wait 10ms as recommended in PCIe spec r6.0, sec 5.3.3.2.1. 1206 + */ 1207 + if (pci->pp.skip_l23_ready) { 1208 + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); 1209 + goto stop_link; 1210 + } 1211 + 1202 1212 ret = read_poll_timeout(dw_pcie_get_ltssm, val, 1203 1213 val == DW_PCIE_LTSSM_L2_IDLE || 1204 1214 val <= DW_PCIE_LTSSM_DETECT_WAIT,
+1
drivers/pci/controller/dwc/pcie-designware.h
··· 442 442 struct pci_config_window *cfg; 443 443 bool ecam_enabled; 444 444 bool native_ecam; 445 + bool skip_l23_ready; 445 446 }; 446 447 447 448 struct dw_pcie_ep_ops {