Merge tag 'riscv-for-linus-4.19-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux

Pull RISC-V fixes from Palmer Dabbelt:
"RISC-V Fixes and Cleanups for 4.19-rc2

This contains a handful of patches that filtered their way in during
the merge window but just didn't make the deadline. It includes:

- Additional documentation in the riscv,cpu-intc device tree binding
that resulted from some feedback I missed in the original patch
set.

- A build fix that provides the definition of tlb_flush() before
including tlb.h, which fixes a RISC-V build regression introduced
during this merge window.

- A cosmetic cleanup to sys_riscv_flush_icache()"

* tag 'riscv-for-linus-4.19-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
RISC-V: Use a less ugly workaround for unused variable warnings
riscv: tlb: Provide definition of tlb_flush() before including tlb.h
dt-bindings: riscv,cpu-intc: Cleanups from a missed review

Linus Torvalds 7 years ago 58c3f14f ff69279a

+16 -17

3 changed files

expand all

Documentation

devicetree

bindings

interrupt-controller

riscv,cpu-intc.txt

arch

riscv

include

asm

tlb.h

kernel

sys_riscv.c

+11 -3

Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt

··· 11 11 attached to every HLIC: software interrupts, the timer interrupt, and external 12 12 interrupts. Software interrupts are used to send IPIs between cores. The 13 13 timer interrupt comes from an architecturally mandated real-time timer that is 14 - controller via Supervisor Binary Interface (SBI) calls and CSR reads. External 14 + controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External 15 15 interrupts connect all other device interrupts to the HLIC, which are routed 16 16 via the platform-level interrupt controller (PLIC). 17 17 ··· 25 25 26 26 Required properties: 27 27 - compatible : "riscv,cpu-intc" 28 - - #interrupt-cells : should be <1> 28 + - #interrupt-cells : should be <1>. The interrupt sources are defined by the 29 + RISC-V supervisor ISA manual, with only the following three interrupts being 30 + defined for supervisor mode: 31 + - Source 1 is the supervisor software interrupt, which can be sent by an SBI 32 + call and is reserved for use by software. 33 + - Source 5 is the supervisor timer interrupt, which can be configured by 34 + SBI calls and implements a one-shot timer. 35 + - Source 9 is the supervisor external interrupt, which chains to all other 36 + device interrupts. 29 37 - interrupt-controller : Identifies the node as an interrupt controller 30 38 31 39 Furthermore, this interrupt-controller MUST be embedded inside the cpu ··· 46 38 ... 47 39 cpu1-intc: interrupt-controller { 48 40 #interrupt-cells = <1>; 49 - compatible = "riscv,cpu-intc", "sifive,fu540-c000-cpu-intc"; 41 + compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc"; 50 42 interrupt-controller; 51 43 }; 52 44 };

arch/riscv/include/asm/tlb.h

··· 14 14 #ifndef _ASM_RISCV_TLB_H 15 15 #define _ASM_RISCV_TLB_H 16 16 17 + struct mmu_gather; 18 + 19 + static void tlb_flush(struct mmu_gather *tlb); 20 + 17 21 #include <asm-generic/tlb.h> 18 22 19 23 static inline void tlb_flush(struct mmu_gather *tlb)

+1 -14

arch/riscv/kernel/sys_riscv.c

··· 65 65 SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end, 66 66 uintptr_t, flags) 67 67 { 68 - #ifdef CONFIG_SMP 69 - struct mm_struct *mm = current->mm; 70 - bool local = (flags & SYS_RISCV_FLUSH_ICACHE_LOCAL) != 0; 71 - #endif 72 - 73 68 /* Check the reserved flags. */ 74 69 if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL)) 75 70 return -EINVAL; 76 71 77 - /* 78 - * Without CONFIG_SMP flush_icache_mm is a just a flush_icache_all(), 79 - * which generates unused variable warnings all over this function. 80 - */ 81 - #ifdef CONFIG_SMP 82 - flush_icache_mm(mm, local); 83 - #else 84 - flush_icache_all(); 85 - #endif 72 + flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL); 86 73 87 74 return 0; 88 75 }

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