Merge tag 'tty-6.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

+2 -1

Documentation/devicetree/bindings/serial/nxp,sc16is7xx.yaml

··· 23 23 maxItems: 1 24 24 25 25 interrupts: 26 + description: 27 + When missing, device driver uses polling instead. 26 28 maxItems: 1 27 29 28 30 clocks: ··· 78 76 required: 79 77 - compatible 80 78 - reg 81 - - interrupts 82 79 83 80 allOf: 84 81 - $ref: /schemas/spi/spi-peripheral-props.yaml#

+5

Documentation/devicetree/bindings/serial/renesas,scif.yaml

··· 83 83 84 84 - const: renesas,scif-r9a09g057 # RZ/V2H(P) 85 85 86 + - items: 87 + - enum: 88 + - renesas,scif-r9a09g047 # RZ/G3E 89 + - const: renesas,scif-r9a09g057 # RZ/V2H fallback 90 + 86 91 reg: 87 92 maxItems: 1 88 93

+8 -4

drivers/parport/parport_serial.c

··· 266 266 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c }, 267 267 268 268 /* WCH CARDS */ 269 - { 0x4348, 0x5053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, wch_ch353_1s1p}, 270 - { 0x4348, 0x7053, 0x4348, 0x3253, 0, 0, wch_ch353_2s1p}, 271 - { 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382_0s1p}, 272 - { 0x1c00, 0x3250, 0x1c00, 0x3250, 0, 0, wch_ch382_2s1p}, 269 + { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_1S1P, 270 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, wch_ch353_1s1p }, 271 + { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1P, 272 + 0x4348, 0x3253, 0, 0, wch_ch353_2s1p }, 273 + { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_0S1P, 274 + 0x1c00, 0x3050, 0, 0, wch_ch382_0s1p }, 275 + { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S1P, 276 + 0x1c00, 0x3250, 0, 0, wch_ch382_2s1p }, 273 277 274 278 /* BrainBoxes PX272/PX306 MIO card */ 275 279 { PCI_VENDOR_ID_INTASHIELD, 0x4100,

+2 -2

drivers/tty/mips_ejtag_fdc.c

··· 1154 1154 1155 1155 /* write buffer to allow compaction */ 1156 1156 static unsigned int kgdbfdc_wbuflen; 1157 - static char kgdbfdc_wbuf[4]; 1157 + static u8 kgdbfdc_wbuf[4]; 1158 1158 1159 1159 static void __iomem *kgdbfdc_setup(void) 1160 1160 { ··· 1215 1215 /* push an FDC word from write buffer to TX FIFO */ 1216 1216 static void kgdbfdc_push_one(void) 1217 1217 { 1218 - const char *bufs[1] = { kgdbfdc_wbuf }; 1218 + const u8 *bufs[1] = { kgdbfdc_wbuf }; 1219 1219 struct fdc_word word; 1220 1220 void __iomem *regs; 1221 1221 unsigned int i;

+27 -12

drivers/tty/n_gsm.c

··· 2224 2224 * 2225 2225 * Some control dlci can stay in ADM mode with other dlci working just 2226 2226 * fine. In that case we can just keep the control dlci open after the 2227 - * DLCI_OPENING retries time out. 2227 + * DLCI_OPENING receives DM. 2228 2228 */ 2229 2229 2230 2230 static void gsm_dlci_t1(struct timer_list *t) ··· 2243 2243 } 2244 2244 break; 2245 2245 case DLCI_OPENING: 2246 - if (dlci->retries) { 2247 - dlci->retries--; 2248 - gsm_command(dlci->gsm, dlci->addr, SABM|PF); 2249 - mod_timer(&dlci->t1, jiffies + gsm->t1 * HZ / 100); 2250 - } else if (!dlci->addr && gsm->control == (DM | PF)) { 2246 + if (!dlci->addr && gsm->control == (DM | PF)) { 2251 2247 if (debug & DBG_ERRORS) 2252 - pr_info("DLCI %d opening in ADM mode.\n", 2253 - dlci->addr); 2248 + pr_info("DLCI 0 opening in ADM mode.\n"); 2254 2249 dlci->mode = DLCI_MODE_ADM; 2255 2250 gsm_dlci_open(dlci); 2251 + } else if (dlci->retries) { 2252 + if (!dlci->addr || !gsm->dlci[0] || 2253 + gsm->dlci[0]->state != DLCI_OPENING) { 2254 + dlci->retries--; 2255 + gsm_command(dlci->gsm, dlci->addr, SABM|PF); 2256 + } 2257 + 2258 + mod_timer(&dlci->t1, jiffies + gsm->t1 * HZ / 100); 2256 2259 } else { 2257 2260 gsm->open_error++; 2258 2261 gsm_dlci_begin_close(dlci); /* prevent half open link */ ··· 2311 2308 dlci->retries = gsm->n2; 2312 2309 if (!need_pn) { 2313 2310 dlci->state = DLCI_OPENING; 2314 - gsm_command(gsm, dlci->addr, SABM|PF); 2311 + if (!dlci->addr || !gsm->dlci[0] || 2312 + gsm->dlci[0]->state != DLCI_OPENING) 2313 + gsm_command(gsm, dlci->addr, SABM|PF); 2315 2314 } else { 2316 2315 /* Configure DLCI before setup */ 2317 2316 dlci->state = DLCI_CONFIGURE; ··· 4256 4251 static int gsmtty_install(struct tty_driver *driver, struct tty_struct *tty) 4257 4252 { 4258 4253 struct gsm_mux *gsm; 4259 - struct gsm_dlci *dlci; 4254 + struct gsm_dlci *dlci, *dlci0; 4260 4255 unsigned int line = tty->index; 4261 4256 unsigned int mux = mux_line_to_num(line); 4262 4257 bool alloc = false; ··· 4279 4274 perspective as we don't have to worry about this 4280 4275 if DLCI0 is lost */ 4281 4276 mutex_lock(&gsm->mutex); 4282 - if (gsm->dlci[0] && gsm->dlci[0]->state != DLCI_OPEN) { 4277 + 4278 + dlci0 = gsm->dlci[0]; 4279 + if (dlci0 && dlci0->state != DLCI_OPEN) { 4283 4280 mutex_unlock(&gsm->mutex); 4284 - return -EL2NSYNC; 4281 + 4282 + if (dlci0->state == DLCI_OPENING) 4283 + wait_event(gsm->event, dlci0->state != DLCI_OPENING); 4284 + 4285 + if (dlci0->state != DLCI_OPEN) 4286 + return -EL2NSYNC; 4287 + 4288 + mutex_lock(&gsm->mutex); 4285 4289 } 4290 + 4286 4291 dlci = gsm->dlci[line]; 4287 4292 if (dlci == NULL) { 4288 4293 alloc = true;

+2 -2

drivers/tty/serial/8250/8250.h

··· 231 231 232 232 int serial8250_em485_config(struct uart_port *port, struct ktermios *termios, 233 233 struct serial_rs485 *rs485); 234 - void serial8250_em485_start_tx(struct uart_8250_port *p); 235 - void serial8250_em485_stop_tx(struct uart_8250_port *p); 234 + void serial8250_em485_start_tx(struct uart_8250_port *p, bool toggle_ier); 235 + void serial8250_em485_stop_tx(struct uart_8250_port *p, bool toggle_ier); 236 236 void serial8250_em485_destroy(struct uart_8250_port *p); 237 237 extern struct serial_rs485 serial8250_em485_supported; 238 238

+2 -2

drivers/tty/serial/8250/8250_bcm2835aux.c

··· 46 46 u32 cntl; 47 47 }; 48 48 49 - static void bcm2835aux_rs485_start_tx(struct uart_8250_port *up) 49 + static void bcm2835aux_rs485_start_tx(struct uart_8250_port *up, bool toggle_ier) 50 50 { 51 51 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) { 52 52 struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev); ··· 65 65 serial8250_out_MCR(up, UART_MCR_RTS); 66 66 } 67 67 68 - static void bcm2835aux_rs485_stop_tx(struct uart_8250_port *up) 68 + static void bcm2835aux_rs485_stop_tx(struct uart_8250_port *up, bool toggle_ier) 69 69 { 70 70 if (up->port.rs485.flags & SER_RS485_RTS_AFTER_SEND) 71 71 serial8250_out_MCR(up, 0);

-1

drivers/tty/serial/8250/8250_core.c

··· 675 675 676 676 uart_port_lock_irqsave(port, &flags); 677 677 up->ier |= UART_IER_RLSI | UART_IER_RDI; 678 - up->port.read_status_mask |= UART_LSR_DR; 679 678 serial_out(up, UART_IER, up->ier); 680 679 uart_port_unlock_irqrestore(port, flags); 681 680 }

+8 -3

drivers/tty/serial/8250/8250_omap.c

··· 365 365 366 366 if (up->port.rs485.flags & SER_RS485_ENABLED && 367 367 up->port.rs485_config == serial8250_em485_config) 368 - serial8250_em485_stop_tx(up); 368 + serial8250_em485_stop_tx(up, true); 369 369 } 370 370 371 371 /* ··· 412 412 */ 413 413 uart_update_timeout(port, termios->c_cflag, baud); 414 414 415 - up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 415 + /* 416 + * Specify which conditions may be considered for error 417 + * handling and the ignoring of characters. The actual 418 + * ignoring of characters only occurs if the bit is set 419 + * in @ignore_status_mask as well. 420 + */ 421 + up->port.read_status_mask = UART_LSR_OE | UART_LSR_DR; 416 422 if (termios->c_iflag & INPCK) 417 423 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 418 424 if (termios->c_iflag & (IGNBRK | PARMRK)) ··· 844 838 if (up->dma) 845 839 up->dma->rx_dma(up); 846 840 up->ier |= UART_IER_RLSI | UART_IER_RDI; 847 - port->read_status_mask |= UART_LSR_DR; 848 841 serial_out(up, UART_IER, up->ier); 849 842 uart_port_unlock_irqrestore(port, flags); 850 843

+35 -41

drivers/tty/serial/8250/8250_pci.c

··· 64 64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 65 65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 66 66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 67 - #define PCI_VENDOR_ID_WCH 0x4348 68 - #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 69 - #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 70 - #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 71 - #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 72 - #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 73 - #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 67 + 68 + #define PCI_DEVICE_ID_WCHCN_CH352_2S 0x3253 69 + #define PCI_DEVICE_ID_WCHCN_CH355_4S 0x7173 70 + 74 71 #define PCI_VENDOR_ID_AGESTAR 0x5372 75 72 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 76 73 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 77 74 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 78 75 79 - #define PCIE_VENDOR_ID_WCH 0x1c00 80 - #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 81 - #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 82 - #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 83 - #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 76 + #define PCI_DEVICE_ID_WCHIC_CH384_4S 0x3470 77 + #define PCI_DEVICE_ID_WCHIC_CH384_8S 0x3853 84 78 85 79 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 86 80 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 ··· 2811 2817 }, 2812 2818 /* WCH CH353 1S1P card (16550 clone) */ 2813 2819 { 2814 - .vendor = PCI_VENDOR_ID_WCH, 2815 - .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2820 + .vendor = PCI_VENDOR_ID_WCHCN, 2821 + .device = PCI_DEVICE_ID_WCHCN_CH353_1S1P, 2816 2822 .subvendor = PCI_ANY_ID, 2817 2823 .subdevice = PCI_ANY_ID, 2818 2824 .setup = pci_wch_ch353_setup, 2819 2825 }, 2820 2826 /* WCH CH353 2S1P card (16550 clone) */ 2821 2827 { 2822 - .vendor = PCI_VENDOR_ID_WCH, 2823 - .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2828 + .vendor = PCI_VENDOR_ID_WCHCN, 2829 + .device = PCI_DEVICE_ID_WCHCN_CH353_2S1P, 2824 2830 .subvendor = PCI_ANY_ID, 2825 2831 .subdevice = PCI_ANY_ID, 2826 2832 .setup = pci_wch_ch353_setup, 2827 2833 }, 2828 2834 /* WCH CH353 4S card (16550 clone) */ 2829 2835 { 2830 - .vendor = PCI_VENDOR_ID_WCH, 2831 - .device = PCI_DEVICE_ID_WCH_CH353_4S, 2836 + .vendor = PCI_VENDOR_ID_WCHCN, 2837 + .device = PCI_DEVICE_ID_WCHCN_CH353_4S, 2832 2838 .subvendor = PCI_ANY_ID, 2833 2839 .subdevice = PCI_ANY_ID, 2834 2840 .setup = pci_wch_ch353_setup, 2835 2841 }, 2836 2842 /* WCH CH353 2S1PF card (16550 clone) */ 2837 2843 { 2838 - .vendor = PCI_VENDOR_ID_WCH, 2839 - .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2844 + .vendor = PCI_VENDOR_ID_WCHCN, 2845 + .device = PCI_DEVICE_ID_WCHCN_CH353_2S1PF, 2840 2846 .subvendor = PCI_ANY_ID, 2841 2847 .subdevice = PCI_ANY_ID, 2842 2848 .setup = pci_wch_ch353_setup, 2843 2849 }, 2844 2850 /* WCH CH352 2S card (16550 clone) */ 2845 2851 { 2846 - .vendor = PCI_VENDOR_ID_WCH, 2847 - .device = PCI_DEVICE_ID_WCH_CH352_2S, 2852 + .vendor = PCI_VENDOR_ID_WCHCN, 2853 + .device = PCI_DEVICE_ID_WCHCN_CH352_2S, 2848 2854 .subvendor = PCI_ANY_ID, 2849 2855 .subdevice = PCI_ANY_ID, 2850 2856 .setup = pci_wch_ch353_setup, 2851 2857 }, 2852 2858 /* WCH CH355 4S card (16550 clone) */ 2853 2859 { 2854 - .vendor = PCI_VENDOR_ID_WCH, 2855 - .device = PCI_DEVICE_ID_WCH_CH355_4S, 2860 + .vendor = PCI_VENDOR_ID_WCHCN, 2861 + .device = PCI_DEVICE_ID_WCHCN_CH355_4S, 2856 2862 .subvendor = PCI_ANY_ID, 2857 2863 .subdevice = PCI_ANY_ID, 2858 2864 .setup = pci_wch_ch355_setup, 2859 2865 }, 2860 2866 /* WCH CH382 2S card (16850 clone) */ 2861 2867 { 2862 - .vendor = PCIE_VENDOR_ID_WCH, 2863 - .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2868 + .vendor = PCI_VENDOR_ID_WCHIC, 2869 + .device = PCI_DEVICE_ID_WCHIC_CH382_2S, 2864 2870 .subvendor = PCI_ANY_ID, 2865 2871 .subdevice = PCI_ANY_ID, 2866 2872 .setup = pci_wch_ch38x_setup, 2867 2873 }, 2868 2874 /* WCH CH382 2S1P card (16850 clone) */ 2869 2875 { 2870 - .vendor = PCIE_VENDOR_ID_WCH, 2871 - .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2876 + .vendor = PCI_VENDOR_ID_WCHIC, 2877 + .device = PCI_DEVICE_ID_WCHIC_CH382_2S1P, 2872 2878 .subvendor = PCI_ANY_ID, 2873 2879 .subdevice = PCI_ANY_ID, 2874 2880 .setup = pci_wch_ch38x_setup, 2875 2881 }, 2876 2882 /* WCH CH384 4S card (16850 clone) */ 2877 2883 { 2878 - .vendor = PCIE_VENDOR_ID_WCH, 2879 - .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2884 + .vendor = PCI_VENDOR_ID_WCHIC, 2885 + .device = PCI_DEVICE_ID_WCHIC_CH384_4S, 2880 2886 .subvendor = PCI_ANY_ID, 2881 2887 .subdevice = PCI_ANY_ID, 2882 2888 .setup = pci_wch_ch38x_setup, 2883 2889 }, 2884 2890 /* WCH CH384 8S card (16850 clone) */ 2885 2891 { 2886 - .vendor = PCIE_VENDOR_ID_WCH, 2887 - .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2892 + .vendor = PCI_VENDOR_ID_WCHIC, 2893 + .device = PCI_DEVICE_ID_WCHIC_CH384_8S, 2888 2894 .subvendor = PCI_ANY_ID, 2889 2895 .subdevice = PCI_ANY_ID, 2890 2896 .init = pci_wch_ch38x_init, ··· 3961 3967 3962 3968 /* multi-io cards handled by parport_serial */ 3963 3969 /* WCH CH353 2S1P */ 3964 - { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3970 + { PCI_VDEVICE(WCHCN, 0x7053), REPORT_CONFIG(PARPORT_SERIAL), }, 3965 3971 /* WCH CH353 1S1P */ 3966 - { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3972 + { PCI_VDEVICE(WCHCN, 0x5053), REPORT_CONFIG(PARPORT_SERIAL), }, 3967 3973 /* WCH CH382 2S1P */ 3968 - { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3974 + { PCI_VDEVICE(WCHIC, 0x3250), REPORT_CONFIG(PARPORT_SERIAL), }, 3969 3975 3970 3976 /* Intel platforms with MID UART */ 3971 3977 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), }, ··· 6038 6044 * WCH CH353 series devices: The 2S1P is handled by parport_serial 6039 6045 * so not listed here. 6040 6046 */ 6041 - { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 6047 + { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_4S, 6042 6048 PCI_ANY_ID, PCI_ANY_ID, 6043 6049 0, 0, pbn_b0_bt_4_115200 }, 6044 6050 6045 - { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 6051 + { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1PF, 6046 6052 PCI_ANY_ID, PCI_ANY_ID, 6047 6053 0, 0, pbn_b0_bt_2_115200 }, 6048 6054 6049 - { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 6055 + { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH355_4S, 6050 6056 PCI_ANY_ID, PCI_ANY_ID, 6051 6057 0, 0, pbn_b0_bt_4_115200 }, 6052 6058 6053 - { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 6059 + { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S, 6054 6060 PCI_ANY_ID, PCI_ANY_ID, 6055 6061 0, 0, pbn_wch382_2 }, 6056 6062 6057 - { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 6063 + { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_4S, 6058 6064 PCI_ANY_ID, PCI_ANY_ID, 6059 6065 0, 0, pbn_wch384_4 }, 6060 6066 6061 - { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 6067 + { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_8S, 6062 6068 PCI_ANY_ID, PCI_ANY_ID, 6063 6069 0, 0, pbn_wch384_8 }, 6064 6070 /*

+59 -1

drivers/tty/serial/8250/8250_pci1xxxx.c

··· 78 78 #define UART_TX_BYTE_FIFO 0x00 79 79 #define UART_FIFO_CTL 0x02 80 80 81 + #define UART_MODEM_CTL_REG 0x04 82 + #define UART_MODEM_CTL_RTS_SET BIT(1) 83 + 84 + #define UART_LINE_STAT_REG 0x05 85 + #define UART_LINE_XMIT_CHECK_MASK GENMASK(6, 5) 86 + 81 87 #define UART_ACTV_REG 0x11 82 88 #define UART_BLOCK_SET_ACTIVE BIT(0) 83 89 ··· 100 94 #define UART_BIT_SAMPLE_CNT_16 16 101 95 #define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8) 102 96 #define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8) 97 + #define FRAC_DIV_TX_END_POINT_MASK GENMASK(23, 20) 103 98 104 99 #define UART_WAKE_REG 0x8C 105 100 #define UART_WAKE_MASK_REG 0x90 ··· 140 133 #define UART_BST_STAT_LSR_PARITY_ERR 0x4000000 141 134 #define UART_BST_STAT_LSR_FRAME_ERR 0x8000000 142 135 #define UART_BST_STAT_LSR_THRE 0x20000000 136 + 137 + #define GET_MODEM_CTL_RTS_STATUS(reg) ((reg) & UART_MODEM_CTL_RTS_SET) 138 + #define GET_RTS_PIN_STATUS(val) (((val) & TIOCM_RTS) >> 1) 139 + #define RTS_TOGGLE_STATUS_MASK(val, reg) (GET_MODEM_CTL_RTS_STATUS(reg) \ 140 + != GET_RTS_PIN_STATUS(val)) 143 141 144 142 struct pci1xxxx_8250 { 145 143 unsigned int nr; ··· 264 252 265 253 writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac, 266 254 port->membase + UART_BAUD_CLK_DIVISOR_REG); 255 + } 256 + 257 + static void pci1xxxx_set_mctrl(struct uart_port *port, unsigned int mctrl) 258 + { 259 + u32 fract_div_cfg_reg; 260 + u32 line_stat_reg; 261 + u32 modem_ctl_reg; 262 + u32 adcl_cfg_reg; 263 + 264 + adcl_cfg_reg = readl(port->membase + ADCL_CFG_REG); 265 + 266 + /* HW is responsible in ADCL_EN case */ 267 + if ((adcl_cfg_reg & (ADCL_CFG_EN | ADCL_CFG_PIN_SEL))) 268 + return; 269 + 270 + modem_ctl_reg = readl(port->membase + UART_MODEM_CTL_REG); 271 + 272 + serial8250_do_set_mctrl(port, mctrl); 273 + 274 + if (RTS_TOGGLE_STATUS_MASK(mctrl, modem_ctl_reg)) { 275 + line_stat_reg = readl(port->membase + UART_LINE_STAT_REG); 276 + if (line_stat_reg & UART_LINE_XMIT_CHECK_MASK) { 277 + fract_div_cfg_reg = readl(port->membase + 278 + FRAC_DIV_CFG_REG); 279 + 280 + writel((fract_div_cfg_reg & 281 + ~(FRAC_DIV_TX_END_POINT_MASK)), 282 + port->membase + FRAC_DIV_CFG_REG); 283 + 284 + /* Enable ADC and set the nRTS pin */ 285 + writel((adcl_cfg_reg | (ADCL_CFG_EN | 286 + ADCL_CFG_PIN_SEL)), 287 + port->membase + ADCL_CFG_REG); 288 + 289 + /* Revert to the original settings */ 290 + writel(adcl_cfg_reg, port->membase + ADCL_CFG_REG); 291 + 292 + writel(fract_div_cfg_reg, port->membase + 293 + FRAC_DIV_CFG_REG); 294 + } 295 + } 267 296 } 268 297 269 298 static int pci1xxxx_rs485_config(struct uart_port *port, ··· 684 631 port->port.rs485_config = pci1xxxx_rs485_config; 685 632 port->port.rs485_supported = pci1xxxx_rs485_supported; 686 633 687 - /* From C0 rev Burst operation is supported */ 634 + /* 635 + * C0 and later revisions support Burst operation. 636 + * RTS workaround in mctrl is applicable only to B0. 637 + */ 688 638 if (rev >= 0xC0) 689 639 port->port.handle_irq = pci1xxxx_handle_irq; 640 + else if (rev == 0xB0) 641 + port->port.set_mctrl = pci1xxxx_set_mctrl; 690 642 691 643 ret = serial8250_pci_setup_port(pdev, port, 0, PORT_OFFSET * port_idx, 0); 692 644 if (ret < 0)

+70 -27

drivers/tty/serial/8250/8250_port.c

··· 578 578 579 579 deassert_rts: 580 580 if (p->em485->tx_stopped) 581 - p->rs485_stop_tx(p); 581 + p->rs485_stop_tx(p, true); 582 582 583 583 return 0; 584 584 } ··· 1390 1390 serial8250_rpm_get(up); 1391 1391 1392 1392 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1393 - up->port.read_status_mask &= ~UART_LSR_DR; 1394 1393 serial_port_out(port, UART_IER, up->ier); 1395 1394 1396 1395 serial8250_rpm_put(up); ··· 1398 1399 /** 1399 1400 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback 1400 1401 * @p: uart 8250 port 1402 + * @toggle_ier: true to allow enabling receive interrupts 1401 1403 * 1402 1404 * Generic callback usable by 8250 uart drivers to stop rs485 transmission. 1403 1405 */ 1404 - void serial8250_em485_stop_tx(struct uart_8250_port *p) 1406 + void serial8250_em485_stop_tx(struct uart_8250_port *p, bool toggle_ier) 1405 1407 { 1406 1408 unsigned char mcr = serial8250_in_MCR(p); 1407 1409 ··· 1423 1423 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) { 1424 1424 serial8250_clear_and_reinit_fifos(p); 1425 1425 1426 - p->ier |= UART_IER_RLSI | UART_IER_RDI; 1427 - serial_port_out(&p->port, UART_IER, p->ier); 1426 + if (toggle_ier) { 1427 + p->ier |= UART_IER_RLSI | UART_IER_RDI; 1428 + serial_port_out(&p->port, UART_IER, p->ier); 1429 + } 1428 1430 } 1429 1431 } 1430 1432 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx); ··· 1441 1439 serial8250_rpm_get(p); 1442 1440 uart_port_lock_irqsave(&p->port, &flags); 1443 1441 if (em485->active_timer == &em485->stop_tx_timer) { 1444 - p->rs485_stop_tx(p); 1442 + p->rs485_stop_tx(p, true); 1445 1443 em485->active_timer = NULL; 1446 1444 em485->tx_stopped = true; 1447 1445 } ··· 1473 1471 em485->active_timer = &em485->stop_tx_timer; 1474 1472 hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL); 1475 1473 } else { 1476 - p->rs485_stop_tx(p); 1474 + p->rs485_stop_tx(p, true); 1477 1475 em485->active_timer = NULL; 1478 1476 em485->tx_stopped = true; 1479 1477 } ··· 1562 1560 /** 1563 1561 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback 1564 1562 * @up: uart 8250 port 1563 + * @toggle_ier: true to allow disabling receive interrupts 1565 1564 * 1566 1565 * Generic callback usable by 8250 uart drivers to start rs485 transmission. 1567 1566 * Assumes that setting the RTS bit in the MCR register means RTS is high. ··· 1570 1567 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the 1571 1568 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.) 1572 1569 */ 1573 - void serial8250_em485_start_tx(struct uart_8250_port *up) 1570 + void serial8250_em485_start_tx(struct uart_8250_port *up, bool toggle_ier) 1574 1571 { 1575 1572 unsigned char mcr = serial8250_in_MCR(up); 1576 1573 1577 - if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) 1574 + if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX) && toggle_ier) 1578 1575 serial8250_stop_rx(&up->port); 1579 1576 1580 1577 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND) ··· 1608 1605 if (em485->tx_stopped) { 1609 1606 em485->tx_stopped = false; 1610 1607 1611 - up->rs485_start_tx(up); 1608 + up->rs485_start_tx(up, true); 1612 1609 1613 1610 if (up->port.rs485.delay_rts_before_send > 0) { 1614 1611 em485->active_timer = &em485->start_tx_timer; ··· 1934 1931 */ 1935 1932 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) && 1936 1933 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) && 1937 - !(port->read_status_mask & UART_LSR_DR)) 1934 + !(up->ier & (UART_IER_RLSI | UART_IER_RDI))) 1938 1935 skip_rx = true; 1939 1936 1940 1937 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) { ··· 2082 2079 serial8250_rpm_put(up); 2083 2080 } 2084 2081 2085 - static void wait_for_lsr(struct uart_8250_port *up, int bits) 2082 + /* Returns true if @bits were set, false on timeout */ 2083 + static bool wait_for_lsr(struct uart_8250_port *up, int bits) 2086 2084 { 2087 - unsigned int status, tmout = 10000; 2085 + unsigned int status, tmout; 2088 2086 2089 - /* Wait up to 10ms for the character(s) to be sent. */ 2087 + /* 2088 + * Wait for a character to be sent. Fallback to a safe default 2089 + * timeout value if @frame_time is not available. 2090 + */ 2091 + if (up->port.frame_time) 2092 + tmout = up->port.frame_time * 2 / NSEC_PER_USEC; 2093 + else 2094 + tmout = 10000; 2095 + 2090 2096 for (;;) { 2091 2097 status = serial_lsr_in(up); 2092 2098 ··· 2106 2094 udelay(1); 2107 2095 touch_nmi_watchdog(); 2108 2096 } 2097 + 2098 + return (tmout != 0); 2109 2099 } 2110 2100 2111 - /* 2112 - * Wait for transmitter & holding register to empty 2113 - */ 2101 + /* Wait for transmitter and holding register to empty with timeout */ 2114 2102 static void wait_for_xmitr(struct uart_8250_port *up, int bits) 2115 2103 { 2116 2104 unsigned int tmout; ··· 2798 2786 */ 2799 2787 uart_update_timeout(port, termios->c_cflag, baud); 2800 2788 2801 - port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 2789 + /* 2790 + * Specify which conditions may be considered for error 2791 + * handling and the ignoring of characters. The actual 2792 + * ignoring of characters only occurs if the bit is set 2793 + * in @ignore_status_mask as well. 2794 + */ 2795 + port->read_status_mask = UART_LSR_OE | UART_LSR_DR; 2802 2796 if (termios->c_iflag & INPCK) 2803 2797 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 2804 2798 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) ··· 3268 3250 port->ops = &serial8250_pops; 3269 3251 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 3270 3252 3271 - up->cur_iotype = 0xFF; 3253 + up->cur_iotype = UPIO_UNKNOWN; 3272 3254 } 3273 3255 EXPORT_SYMBOL_GPL(serial8250_init_port); 3274 3256 ··· 3303 3285 3304 3286 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch) 3305 3287 { 3288 + serial_port_out(port, UART_TX, ch); 3289 + } 3290 + 3291 + static void serial8250_console_wait_putchar(struct uart_port *port, unsigned char ch) 3292 + { 3306 3293 struct uart_8250_port *up = up_to_u8250p(port); 3307 3294 3308 3295 wait_for_xmitr(up, UART_LSR_THRE); 3309 - serial_port_out(port, UART_TX, ch); 3296 + serial8250_console_putchar(port, ch); 3310 3297 } 3311 3298 3312 3299 /* ··· 3340 3317 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS); 3341 3318 } 3342 3319 3320 + static void fifo_wait_for_lsr(struct uart_8250_port *up, unsigned int count) 3321 + { 3322 + unsigned int i; 3323 + 3324 + for (i = 0; i < count; i++) { 3325 + if (wait_for_lsr(up, UART_LSR_THRE)) 3326 + return; 3327 + } 3328 + } 3329 + 3343 3330 /* 3344 3331 * Print a string to the serial port using the device FIFO 3345 3332 * ··· 3359 3326 static void serial8250_console_fifo_write(struct uart_8250_port *up, 3360 3327 const char *s, unsigned int count) 3361 3328 { 3362 - int i; 3363 3329 const char *end = s + count; 3364 3330 unsigned int fifosize = up->tx_loadsz; 3331 + struct uart_port *port = &up->port; 3332 + unsigned int tx_count = 0; 3365 3333 bool cr_sent = false; 3334 + unsigned int i; 3366 3335 3367 3336 while (s != end) { 3368 - wait_for_lsr(up, UART_LSR_THRE); 3337 + /* Allow timeout for each byte of a possibly full FIFO */ 3338 + fifo_wait_for_lsr(up, fifosize); 3369 3339 3370 3340 for (i = 0; i < fifosize && s != end; ++i) { 3371 3341 if (*s == '\n' && !cr_sent) { 3372 - serial_out(up, UART_TX, '\r'); 3342 + serial8250_console_putchar(port, '\r'); 3373 3343 cr_sent = true; 3374 3344 } else { 3375 - serial_out(up, UART_TX, *s++); 3345 + serial8250_console_putchar(port, *s++); 3376 3346 cr_sent = false; 3377 3347 } 3378 3348 } 3349 + tx_count = i; 3379 3350 } 3351 + 3352 + /* 3353 + * Allow timeout for each byte written since the caller will only wait 3354 + * for UART_LSR_BOTH_EMPTY using the timeout of a single character 3355 + */ 3356 + fifo_wait_for_lsr(up, tx_count); 3380 3357 } 3381 3358 3382 3359 /* ··· 3428 3385 3429 3386 if (em485) { 3430 3387 if (em485->tx_stopped) 3431 - up->rs485_start_tx(up); 3388 + up->rs485_start_tx(up, false); 3432 3389 mdelay(port->rs485.delay_rts_before_send); 3433 3390 } 3434 3391 ··· 3455 3412 if (likely(use_fifo)) 3456 3413 serial8250_console_fifo_write(up, s, count); 3457 3414 else 3458 - uart_console_write(port, s, count, serial8250_console_putchar); 3415 + uart_console_write(port, s, count, serial8250_console_wait_putchar); 3459 3416 3460 3417 /* 3461 3418 * Finally, wait for transmitter to become empty ··· 3466 3423 if (em485) { 3467 3424 mdelay(port->rs485.delay_rts_after_send); 3468 3425 if (em485->tx_stopped) 3469 - up->rs485_stop_tx(up); 3426 + up->rs485_stop_tx(up, false); 3470 3427 } 3471 3428 3472 3429 serial_port_out(port, UART_IER, ier);

+1 -1

drivers/tty/serial/Kconfig

··· 128 128 config SERIAL_ATMEL 129 129 bool "AT91 on-chip serial port support" 130 130 depends on COMMON_CLK 131 - depends on ARCH_AT91 || COMPILE_TEST 131 + depends on ARCH_AT91 || ARCH_LAN969X || COMPILE_TEST 132 132 select SERIAL_CORE 133 133 select SERIAL_MCTRL_GPIO if GPIOLIB 134 134 select MFD_AT91_USART

+4 -6

drivers/tty/serial/altera_jtaguart.c

··· 24 24 #include <linux/io.h> 25 25 #include <linux/altera_jtaguart.h> 26 26 27 - #define DRV_NAME "altera_jtaguart" 28 - 29 27 /* 30 28 * Altera JTAG UART register definitions according to the Altera JTAG UART 31 29 * datasheet: https://www.altera.com/literature/hb/nios2/n2cpu_nii51009.pdf ··· 171 173 int ret; 172 174 173 175 ret = request_irq(port->irq, altera_jtaguart_interrupt, 0, 174 - DRV_NAME, port); 176 + dev_name(port->dev), port); 175 177 if (ret) { 176 178 dev_err(port->dev, "unable to attach Altera JTAG UART %d interrupt vector=%d\n", 177 179 port->line, port->irq); ··· 363 365 364 366 static struct uart_driver altera_jtaguart_driver = { 365 367 .owner = THIS_MODULE, 366 - .driver_name = "altera_jtaguart", 368 + .driver_name = KBUILD_MODNAME, 367 369 .dev_name = "ttyJ", 368 370 .major = ALTERA_JTAGUART_MAJOR, 369 371 .minor = ALTERA_JTAGUART_MINOR, ··· 449 451 .probe = altera_jtaguart_probe, 450 452 .remove = altera_jtaguart_remove, 451 453 .driver = { 452 - .name = DRV_NAME, 454 + .name = KBUILD_MODNAME, 453 455 .of_match_table = of_match_ptr(altera_jtaguart_match), 454 456 }, 455 457 }; ··· 479 481 MODULE_DESCRIPTION("Altera JTAG UART driver"); 480 482 MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>"); 481 483 MODULE_LICENSE("GPL"); 482 - MODULE_ALIAS("platform:" DRV_NAME); 484 + MODULE_ALIAS("platform:" KBUILD_MODNAME);

+3 -4

drivers/tty/serial/altera_uart.c

··· 24 24 #include <linux/io.h> 25 25 #include <linux/altera_uart.h> 26 26 27 - #define DRV_NAME "altera_uart" 28 27 #define SERIAL_ALTERA_MAJOR 204 29 28 #define SERIAL_ALTERA_MINOR 213 30 29 ··· 517 518 */ 518 519 static struct uart_driver altera_uart_driver = { 519 520 .owner = THIS_MODULE, 520 - .driver_name = DRV_NAME, 521 + .driver_name = KBUILD_MODNAME, 521 522 .dev_name = "ttyAL", 522 523 .major = SERIAL_ALTERA_MAJOR, 523 524 .minor = SERIAL_ALTERA_MINOR, ··· 618 619 .probe = altera_uart_probe, 619 620 .remove = altera_uart_remove, 620 621 .driver = { 621 - .name = DRV_NAME, 622 + .name = KBUILD_MODNAME, 622 623 .of_match_table = of_match_ptr(altera_uart_match), 623 624 }, 624 625 }; ··· 648 649 MODULE_DESCRIPTION("Altera UART driver"); 649 650 MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>"); 650 651 MODULE_LICENSE("GPL"); 651 - MODULE_ALIAS("platform:" DRV_NAME); 652 + MODULE_ALIAS("platform:" KBUILD_MODNAME); 652 653 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_ALTERA_MAJOR);

+96 -30

drivers/tty/serial/amba-pl011.c

··· 248 248 bool queued; 249 249 }; 250 250 251 + enum pl011_rs485_tx_state { 252 + OFF, 253 + WAIT_AFTER_RTS, 254 + SEND, 255 + WAIT_AFTER_SEND, 256 + }; 257 + 251 258 /* 252 259 * We wrap our port structure around the generic uart_port. 253 260 */ ··· 268 261 unsigned int fifosize; /* vendor-specific */ 269 262 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 270 263 char type[12]; 271 - bool rs485_tx_started; 272 - unsigned int rs485_tx_drain_interval; /* usecs */ 264 + ktime_t rs485_tx_drain_interval; /* nano */ 265 + enum pl011_rs485_tx_state rs485_tx_state; 266 + struct hrtimer trigger_start_tx; 267 + struct hrtimer trigger_stop_tx; 273 268 #ifdef CONFIG_DMA_ENGINE 274 269 /* DMA stuff */ 275 270 unsigned int dmacr; /* dma control reg */ ··· 1269 1260 1270 1261 static void pl011_rs485_tx_stop(struct uart_amba_port *uap) 1271 1262 { 1272 - /* 1273 - * To be on the safe side only time out after twice as many iterations 1274 - * as fifo size. 1275 - */ 1276 - const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2; 1277 1263 struct uart_port *port = &uap->port; 1278 - int i = 0; 1279 1264 u32 cr; 1280 1265 1281 - /* Wait until hardware tx queue is empty */ 1282 - while (!pl011_tx_empty(port)) { 1283 - if (i > MAX_TX_DRAIN_ITERS) { 1284 - dev_warn(port->dev, 1285 - "timeout while draining hardware tx queue\n"); 1286 - break; 1266 + if (uap->rs485_tx_state == SEND) 1267 + uap->rs485_tx_state = WAIT_AFTER_SEND; 1268 + 1269 + if (uap->rs485_tx_state == WAIT_AFTER_SEND) { 1270 + /* Schedule hrtimer if tx queue not empty */ 1271 + if (!pl011_tx_empty(port)) { 1272 + hrtimer_start(&uap->trigger_stop_tx, 1273 + uap->rs485_tx_drain_interval, 1274 + HRTIMER_MODE_REL); 1275 + return; 1287 1276 } 1288 - 1289 - udelay(uap->rs485_tx_drain_interval); 1290 - i++; 1277 + if (port->rs485.delay_rts_after_send > 0) { 1278 + hrtimer_start(&uap->trigger_stop_tx, 1279 + ms_to_ktime(port->rs485.delay_rts_after_send), 1280 + HRTIMER_MODE_REL); 1281 + return; 1282 + } 1283 + /* Continue without any delay */ 1284 + } else if (uap->rs485_tx_state == WAIT_AFTER_RTS) { 1285 + hrtimer_try_to_cancel(&uap->trigger_start_tx); 1291 1286 } 1292 - 1293 - if (port->rs485.delay_rts_after_send) 1294 - mdelay(port->rs485.delay_rts_after_send); 1295 1287 1296 1288 cr = pl011_read(uap, REG_CR); 1297 1289 ··· 1306 1296 cr |= UART011_CR_RXE; 1307 1297 pl011_write(cr, uap, REG_CR); 1308 1298 1309 - uap->rs485_tx_started = false; 1299 + uap->rs485_tx_state = OFF; 1310 1300 } 1311 1301 1312 1302 static void pl011_stop_tx(struct uart_port *port) ··· 1314 1304 struct uart_amba_port *uap = 1315 1305 container_of(port, struct uart_amba_port, port); 1316 1306 1307 + if (port->rs485.flags & SER_RS485_ENABLED && 1308 + uap->rs485_tx_state == WAIT_AFTER_RTS) { 1309 + pl011_rs485_tx_stop(uap); 1310 + return; 1311 + } 1312 + 1317 1313 uap->im &= ~UART011_TXIM; 1318 1314 pl011_write(uap->im, uap, REG_IMSC); 1319 1315 pl011_dma_tx_stop(uap); 1320 1316 1321 - if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) 1317 + if (port->rs485.flags & SER_RS485_ENABLED && 1318 + uap->rs485_tx_state != OFF) 1322 1319 pl011_rs485_tx_stop(uap); 1323 1320 } 1324 1321 ··· 1345 1328 struct uart_port *port = &uap->port; 1346 1329 u32 cr; 1347 1330 1331 + if (uap->rs485_tx_state == WAIT_AFTER_RTS) { 1332 + uap->rs485_tx_state = SEND; 1333 + return; 1334 + } 1335 + if (uap->rs485_tx_state == WAIT_AFTER_SEND) { 1336 + hrtimer_try_to_cancel(&uap->trigger_stop_tx); 1337 + uap->rs485_tx_state = SEND; 1338 + return; 1339 + } 1340 + /* uap->rs485_tx_state == OFF */ 1348 1341 /* Enable transmitter */ 1349 1342 cr = pl011_read(uap, REG_CR); 1350 1343 cr |= UART011_CR_TXE; 1351 - 1352 1344 /* Disable receiver if half-duplex */ 1353 1345 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1354 1346 cr &= ~UART011_CR_RXE; ··· 1369 1343 1370 1344 pl011_write(cr, uap, REG_CR); 1371 1345 1372 - if (port->rs485.delay_rts_before_send) 1373 - mdelay(port->rs485.delay_rts_before_send); 1374 - 1375 - uap->rs485_tx_started = true; 1346 + if (port->rs485.delay_rts_before_send > 0) { 1347 + uap->rs485_tx_state = WAIT_AFTER_RTS; 1348 + hrtimer_start(&uap->trigger_start_tx, 1349 + ms_to_ktime(port->rs485.delay_rts_before_send), 1350 + HRTIMER_MODE_REL); 1351 + } else { 1352 + uap->rs485_tx_state = SEND; 1353 + } 1376 1354 } 1377 1355 1378 1356 static void pl011_start_tx(struct uart_port *port) ··· 1385 1355 container_of(port, struct uart_amba_port, port); 1386 1356 1387 1357 if ((uap->port.rs485.flags & SER_RS485_ENABLED) && 1388 - !uap->rs485_tx_started) 1358 + uap->rs485_tx_state != SEND) { 1389 1359 pl011_rs485_tx_start(uap); 1360 + if (uap->rs485_tx_state == WAIT_AFTER_RTS) 1361 + return; 1362 + } 1390 1363 1391 1364 if (!pl011_dma_tx_start(uap)) 1392 1365 pl011_start_tx_pio(uap); 1366 + } 1367 + 1368 + static enum hrtimer_restart pl011_trigger_start_tx(struct hrtimer *t) 1369 + { 1370 + struct uart_amba_port *uap = 1371 + container_of(t, struct uart_amba_port, trigger_start_tx); 1372 + unsigned long flags; 1373 + 1374 + uart_port_lock_irqsave(&uap->port, &flags); 1375 + if (uap->rs485_tx_state == WAIT_AFTER_RTS) 1376 + pl011_start_tx(&uap->port); 1377 + uart_port_unlock_irqrestore(&uap->port, flags); 1378 + 1379 + return HRTIMER_NORESTART; 1380 + } 1381 + 1382 + static enum hrtimer_restart pl011_trigger_stop_tx(struct hrtimer *t) 1383 + { 1384 + struct uart_amba_port *uap = 1385 + container_of(t, struct uart_amba_port, trigger_stop_tx); 1386 + unsigned long flags; 1387 + 1388 + uart_port_lock_irqsave(&uap->port, &flags); 1389 + if (uap->rs485_tx_state == WAIT_AFTER_SEND) 1390 + pl011_rs485_tx_stop(uap); 1391 + uart_port_unlock_irqrestore(&uap->port, flags); 1392 + 1393 + return HRTIMER_NORESTART; 1393 1394 } 1394 1395 1395 1396 static void pl011_stop_rx(struct uart_port *port) ··· 2014 1953 2015 1954 pl011_dma_shutdown(uap); 2016 1955 2017 - if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) 1956 + if ((port->rs485.flags & SER_RS485_ENABLED && uap->rs485_tx_state != OFF)) 2018 1957 pl011_rs485_tx_stop(uap); 2019 1958 2020 1959 free_irq(uap->port.irq, uap); ··· 2159 2098 * with the given baud rate. We use this as the poll interval when we 2160 2099 * wait for the tx queue to empty. 2161 2100 */ 2162 - uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud); 2101 + uap->rs485_tx_drain_interval = ns_to_ktime(DIV_ROUND_UP(bits * NSEC_PER_SEC, baud)); 2163 2102 2164 2103 pl011_setup_status_masks(port, termios); 2165 2104 ··· 2867 2806 return -EINVAL; 2868 2807 } 2869 2808 } 2809 + 2810 + hrtimer_init(&uap->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2811 + hrtimer_init(&uap->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2812 + uap->trigger_start_tx.function = pl011_trigger_start_tx; 2813 + uap->trigger_stop_tx.function = pl011_trigger_stop_tx; 2870 2814 2871 2815 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 2872 2816 if (ret)

+4 -14

drivers/tty/serial/atmel_serial.c

··· 1727 1727 1728 1728 /* DMA/PDC usage specification */ 1729 1729 if (of_property_read_bool(np, "atmel,use-dma-rx")) { 1730 - if (of_property_read_bool(np, "dmas")) { 1731 - atmel_port->use_dma_rx = true; 1732 - atmel_port->use_pdc_rx = false; 1733 - } else { 1734 - atmel_port->use_dma_rx = false; 1735 - atmel_port->use_pdc_rx = true; 1736 - } 1730 + atmel_port->use_dma_rx = of_property_present(np, "dmas"); 1731 + atmel_port->use_pdc_rx = !atmel_port->use_dma_rx; 1737 1732 } else { 1738 1733 atmel_port->use_dma_rx = false; 1739 1734 atmel_port->use_pdc_rx = false; 1740 1735 } 1741 1736 1742 1737 if (of_property_read_bool(np, "atmel,use-dma-tx")) { 1743 - if (of_property_read_bool(np, "dmas")) { 1744 - atmel_port->use_dma_tx = true; 1745 - atmel_port->use_pdc_tx = false; 1746 - } else { 1747 - atmel_port->use_dma_tx = false; 1748 - atmel_port->use_pdc_tx = true; 1749 - } 1738 + atmel_port->use_dma_tx = of_property_present(np, "dmas"); 1739 + atmel_port->use_pdc_tx = !atmel_port->use_dma_tx; 1750 1740 } else { 1751 1741 atmel_port->use_dma_tx = false; 1752 1742 atmel_port->use_pdc_tx = false;

+6 -1

drivers/tty/serial/fsl_lpuart.c

··· 245 245 246 246 #define DRIVER_NAME "fsl-lpuart" 247 247 #define DEV_NAME "ttyLP" 248 - #define UART_NR 8 248 + #define UART_NR 12 249 249 250 250 /* IMX lpuart has four extra unused regs located at the beginning */ 251 251 #define IMX_REG_OFF 0x10 ··· 1964 1964 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE | 1965 1965 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK); 1966 1966 lpuart32_write(port, temp, UARTCTRL); 1967 + 1968 + /* flush Rx/Tx FIFO */ 1969 + temp = lpuart32_read(port, UARTFIFO); 1970 + temp |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1971 + lpuart32_write(port, temp, UARTFIFO); 1967 1972 1968 1973 uart_port_unlock_irqrestore(port, flags); 1969 1974

-101

drivers/tty/serial/kgdb_nmi.c

··· 27 27 #include <linux/kgdb.h> 28 28 #include <linux/kdb.h> 29 29 30 - static int kgdb_nmi_knock = 1; 31 - module_param_named(knock, kgdb_nmi_knock, int, 0600); 32 - MODULE_PARM_DESC(knock, "if set to 1 (default), the special '$3#33' command " \ 33 - "must be used to enter the debugger; when set to 0, " \ 34 - "hitting return key is enough to enter the debugger; " \ 35 - "when set to -1, the debugger is entered immediately " \ 36 - "upon NMI"); 37 - 38 - static char *kgdb_nmi_magic = "$3#33"; 39 - module_param_named(magic, kgdb_nmi_magic, charp, 0600); 40 - MODULE_PARM_DESC(magic, "magic sequence to enter NMI debugger (default $3#33)"); 41 - 42 30 static atomic_t kgdb_nmi_num_readers = ATOMIC_INIT(0); 43 31 44 32 static int kgdb_nmi_console_setup(struct console *co, char *options) ··· 82 94 }; 83 95 84 96 static struct tty_port *kgdb_nmi_port; 85 - 86 - static void kgdb_tty_recv(int ch) 87 - { 88 - struct kgdb_nmi_tty_priv *priv; 89 - char c = ch; 90 - 91 - if (!kgdb_nmi_port || ch < 0) 92 - return; 93 - /* 94 - * Can't use port->tty->driver_data as tty might be not there. Timer 95 - * will check for tty and will get the ref, but here we don't have to 96 - * do that, and actually, we can't: we're in NMI context, no locks are 97 - * possible. 98 - */ 99 - priv = container_of(kgdb_nmi_port, struct kgdb_nmi_tty_priv, port); 100 - kfifo_in(&priv->fifo, &c, 1); 101 - } 102 - 103 - static int kgdb_nmi_poll_one_knock(void) 104 - { 105 - static int n; 106 - int c; 107 - const char *magic = kgdb_nmi_magic; 108 - size_t m = strlen(magic); 109 - bool printch = false; 110 - 111 - c = dbg_io_ops->read_char(); 112 - if (c == NO_POLL_CHAR) 113 - return c; 114 - 115 - if (!kgdb_nmi_knock && (c == '\r' || c == '\n')) { 116 - return 1; 117 - } else if (c == magic[n]) { 118 - n = (n + 1) % m; 119 - if (!n) 120 - return 1; 121 - printch = true; 122 - } else { 123 - n = 0; 124 - } 125 - 126 - if (atomic_read(&kgdb_nmi_num_readers)) { 127 - kgdb_tty_recv(c); 128 - return 0; 129 - } 130 - 131 - if (printch) { 132 - kdb_printf("%c", c); 133 - return 0; 134 - } 135 - 136 - kdb_printf("\r%s %s to enter the debugger> %*s", 137 - kgdb_nmi_knock ? "Type" : "Hit", 138 - kgdb_nmi_knock ? magic : "<return>", (int)m, ""); 139 - while (m--) 140 - kdb_printf("\b"); 141 - return 0; 142 - } 143 - 144 - /** 145 - * kgdb_nmi_poll_knock - Check if it is time to enter the debugger 146 - * 147 - * "Serial ports are often noisy, especially when muxed over another port (we 148 - * often use serial over the headset connector). Noise on the async command 149 - * line just causes characters that are ignored, on a command line that blocked 150 - * execution noise would be catastrophic." -- Colin Cross 151 - * 152 - * So, this function implements KGDB/KDB knocking on the serial line: we won't 153 - * enter the debugger until we receive a known magic phrase (which is actually 154 - * "$3#33", known as "escape to KDB" command. There is also a relaxed variant 155 - * of knocking, i.e. just pressing the return key is enough to enter the 156 - * debugger. And if knocking is disabled, the function always returns 1. 157 - */ 158 - bool kgdb_nmi_poll_knock(void) 159 - { 160 - if (kgdb_nmi_knock < 0) 161 - return true; 162 - 163 - while (1) { 164 - int ret; 165 - 166 - ret = kgdb_nmi_poll_one_knock(); 167 - if (ret == NO_POLL_CHAR) 168 - return false; 169 - else if (ret == 1) 170 - break; 171 - } 172 - return true; 173 - } 174 97 175 98 /* 176 99 * The tasklet is cheap, it does not cause wakeups when reschedules itself,

+1 -1

drivers/tty/serial/mpc52xx_uart.c

··· 1621 1621 (void *)port->mapbase, port->membase, 1622 1622 port->irq, port->uartclk); 1623 1623 1624 - /* Setup the port parameters accoding to options */ 1624 + /* Setup the port parameters according to options */ 1625 1625 if (options) 1626 1626 uart_parse_options(options, &baud, &parity, &bits, &flow); 1627 1627 else

+37

drivers/tty/serial/sc16is7xx.c

··· 314 314 #define SC16IS7XX_FIFO_SIZE (64) 315 315 #define SC16IS7XX_GPIOS_PER_BANK 4 316 316 317 + #define SC16IS7XX_POLL_PERIOD_MS 10 317 318 #define SC16IS7XX_RECONF_MD BIT(0) 318 319 #define SC16IS7XX_RECONF_IER BIT(1) 319 320 #define SC16IS7XX_RECONF_RS485 BIT(2) ··· 349 348 u8 mctrl_mask; 350 349 struct kthread_worker kworker; 351 350 struct task_struct *kworker_task; 351 + struct kthread_delayed_work poll_work; 352 + bool polling; 352 353 struct sc16is7xx_one p[]; 353 354 }; 354 355 ··· 864 861 return IRQ_HANDLED; 865 862 } 866 863 864 + static void sc16is7xx_poll_proc(struct kthread_work *ws) 865 + { 866 + struct sc16is7xx_port *s = container_of(ws, struct sc16is7xx_port, poll_work.work); 867 + 868 + /* Reuse standard IRQ handler. Interrupt ID is unused in this context. */ 869 + sc16is7xx_irq(0, s); 870 + 871 + /* Setup delay based on SC16IS7XX_POLL_PERIOD_MS */ 872 + kthread_queue_delayed_work(&s->kworker, &s->poll_work, 873 + msecs_to_jiffies(SC16IS7XX_POLL_PERIOD_MS)); 874 + } 875 + 867 876 static void sc16is7xx_tx_proc(struct kthread_work *ws) 868 877 { 869 878 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); ··· 1164 1149 static int sc16is7xx_startup(struct uart_port *port) 1165 1150 { 1166 1151 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1152 + struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1167 1153 unsigned int val; 1168 1154 unsigned long flags; 1169 1155 ··· 1227 1211 sc16is7xx_enable_ms(port); 1228 1212 uart_port_unlock_irqrestore(port, flags); 1229 1213 1214 + if (s->polling) 1215 + kthread_queue_delayed_work(&s->kworker, &s->poll_work, 1216 + msecs_to_jiffies(SC16IS7XX_POLL_PERIOD_MS)); 1217 + 1230 1218 return 0; 1231 1219 } 1232 1220 ··· 1251 1231 SC16IS7XX_EFCR_TXDISABLE_BIT); 1252 1232 1253 1233 sc16is7xx_power(port, 0); 1234 + 1235 + if (s->polling) 1236 + kthread_cancel_delayed_work_sync(&s->poll_work); 1254 1237 1255 1238 kthread_flush_worker(&s->kworker); 1256 1239 } ··· 1561 1538 /* Always ask for fixed clock rate from a property. */ 1562 1539 device_property_read_u32(dev, "clock-frequency", &uartclk); 1563 1540 1541 + s->polling = !!irq; 1542 + if (s->polling) 1543 + dev_dbg(dev, 1544 + "No interrupt pin definition, falling back to polling mode\n"); 1545 + 1564 1546 s->clk = devm_clk_get_optional(dev, NULL); 1565 1547 if (IS_ERR(s->clk)) 1566 1548 return PTR_ERR(s->clk); ··· 1693 1665 goto out_ports; 1694 1666 #endif 1695 1667 1668 + if (s->polling) { 1669 + /* Initialize kernel thread for polling */ 1670 + kthread_init_delayed_work(&s->poll_work, sc16is7xx_poll_proc); 1671 + return 0; 1672 + } 1673 + 1696 1674 /* 1697 1675 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1698 1676 * If that succeeds, we can allow sharing the interrupt as well. ··· 1757 1723 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1758 1724 sc16is7xx_power(&s->p[i].port, 0); 1759 1725 } 1726 + 1727 + if (s->polling) 1728 + kthread_cancel_delayed_work_sync(&s->poll_work); 1760 1729 1761 1730 kthread_flush_worker(&s->kworker); 1762 1731 kthread_stop(s->kworker_task);

+115 -148

drivers/tty/serial/serial_core.c

··· 790 790 { 791 791 struct uart_state *state = container_of(port, struct uart_state, port); 792 792 struct uart_port *uport; 793 - int ret = -ENODEV; 794 793 795 794 /* Initialize structure in case we error out later to prevent any stack info leakage. */ 796 795 *retinfo = (struct serial_struct){}; ··· 798 799 * Ensure the state we copy is consistent and no hardware changes 799 800 * occur as we go 800 801 */ 801 - mutex_lock(&port->mutex); 802 + guard(mutex)(&port->mutex); 802 803 uport = uart_port_check(state); 803 804 if (!uport) 804 - goto out; 805 + return -ENODEV; 805 806 806 807 retinfo->type = uport->type; 807 808 retinfo->line = uport->line; ··· 822 823 retinfo->iomem_reg_shift = uport->regshift; 823 824 retinfo->iomem_base = (void *)(unsigned long)uport->mapbase; 824 825 825 - ret = 0; 826 - out: 827 - mutex_unlock(&port->mutex); 828 - return ret; 826 + return 0; 829 827 } 830 828 831 829 static int uart_get_info_user(struct tty_struct *tty, ··· 834 838 return uart_get_info(port, ss) < 0 ? -EIO : 0; 835 839 } 836 840 841 + static int uart_change_port(struct uart_port *uport, 842 + const struct serial_struct *new_info, 843 + unsigned long new_port) 844 + { 845 + unsigned long old_iobase, old_mapbase; 846 + unsigned int old_type, old_iotype, old_hub6, old_shift; 847 + int retval; 848 + 849 + old_iobase = uport->iobase; 850 + old_mapbase = uport->mapbase; 851 + old_type = uport->type; 852 + old_hub6 = uport->hub6; 853 + old_iotype = uport->iotype; 854 + old_shift = uport->regshift; 855 + 856 + if (old_type != PORT_UNKNOWN && uport->ops->release_port) 857 + uport->ops->release_port(uport); 858 + 859 + uport->iobase = new_port; 860 + uport->type = new_info->type; 861 + uport->hub6 = new_info->hub6; 862 + uport->iotype = new_info->io_type; 863 + uport->regshift = new_info->iomem_reg_shift; 864 + uport->mapbase = (unsigned long)new_info->iomem_base; 865 + 866 + if (uport->type == PORT_UNKNOWN || !uport->ops->request_port) 867 + return 0; 868 + 869 + retval = uport->ops->request_port(uport); 870 + if (retval == 0) 871 + return 0; /* succeeded => done */ 872 + 873 + /* 874 + * If we fail to request resources for the new port, try to restore the 875 + * old settings. 876 + */ 877 + uport->iobase = old_iobase; 878 + uport->type = old_type; 879 + uport->hub6 = old_hub6; 880 + uport->iotype = old_iotype; 881 + uport->regshift = old_shift; 882 + uport->mapbase = old_mapbase; 883 + 884 + if (old_type == PORT_UNKNOWN) 885 + return retval; 886 + 887 + retval = uport->ops->request_port(uport); 888 + /* If we failed to restore the old settings, we fail like this. */ 889 + if (retval) 890 + uport->type = PORT_UNKNOWN; 891 + 892 + /* We failed anyway. */ 893 + return -EBUSY; 894 + } 895 + 837 896 static int uart_set_info(struct tty_struct *tty, struct tty_port *port, 838 897 struct uart_state *state, 839 898 struct serial_struct *new_info) ··· 898 847 unsigned int change_irq, change_port, closing_wait; 899 848 unsigned int old_custom_divisor, close_delay; 900 849 upf_t old_flags, new_flags; 901 - int retval = 0; 850 + int retval; 902 851 903 852 if (!uport) 904 853 return -EIO; ··· 937 886 if (!(uport->flags & UPF_FIXED_PORT)) { 938 887 unsigned int uartclk = new_info->baud_base * 16; 939 888 /* check needs to be done here before other settings made */ 940 - if (uartclk == 0) { 941 - retval = -EINVAL; 942 - goto exit; 943 - } 889 + if (uartclk == 0) 890 + return -EINVAL; 944 891 } 945 892 if (!capable(CAP_SYS_ADMIN)) { 946 - retval = -EPERM; 947 893 if (change_irq || change_port || 948 894 (new_info->baud_base != uport->uartclk / 16) || 949 895 (close_delay != port->close_delay) || ··· 948 900 (new_info->xmit_fifo_size && 949 901 new_info->xmit_fifo_size != uport->fifosize) || 950 902 (((new_flags ^ old_flags) & ~UPF_USR_MASK) != 0)) 951 - goto exit; 903 + return -EPERM; 952 904 uport->flags = ((uport->flags & ~UPF_USR_MASK) | 953 905 (new_flags & UPF_USR_MASK)); 954 906 uport->custom_divisor = new_info->custom_divisor; ··· 958 910 if (change_irq || change_port) { 959 911 retval = security_locked_down(LOCKDOWN_TIOCSSERIAL); 960 912 if (retval) 961 - goto exit; 913 + return retval; 962 914 } 963 915 964 - /* 965 - * Ask the low level driver to verify the settings. 966 - */ 967 - if (uport->ops->verify_port) 916 + /* Ask the low level driver to verify the settings. */ 917 + if (uport->ops->verify_port) { 968 918 retval = uport->ops->verify_port(uport, new_info); 919 + if (retval) 920 + return retval; 921 + } 969 922 970 923 if ((new_info->irq >= irq_get_nr_irqs()) || (new_info->irq < 0) || 971 924 (new_info->baud_base < 9600)) 972 - retval = -EINVAL; 973 - 974 - if (retval) 975 - goto exit; 925 + return -EINVAL; 976 926 977 927 if (change_port || change_irq) { 978 - retval = -EBUSY; 979 - 980 - /* 981 - * Make sure that we are the sole user of this port. 982 - */ 928 + /* Make sure that we are the sole user of this port. */ 983 929 if (tty_port_users(port) > 1) 984 - goto exit; 930 + return -EBUSY; 985 931 986 932 /* 987 933 * We need to shutdown the serial port at the old ··· 985 943 } 986 944 987 945 if (change_port) { 988 - unsigned long old_iobase, old_mapbase; 989 - unsigned int old_type, old_iotype, old_hub6, old_shift; 990 - 991 - old_iobase = uport->iobase; 992 - old_mapbase = uport->mapbase; 993 - old_type = uport->type; 994 - old_hub6 = uport->hub6; 995 - old_iotype = uport->iotype; 996 - old_shift = uport->regshift; 997 - 998 - /* 999 - * Free and release old regions 1000 - */ 1001 - if (old_type != PORT_UNKNOWN && uport->ops->release_port) 1002 - uport->ops->release_port(uport); 1003 - 1004 - uport->iobase = new_port; 1005 - uport->type = new_info->type; 1006 - uport->hub6 = new_info->hub6; 1007 - uport->iotype = new_info->io_type; 1008 - uport->regshift = new_info->iomem_reg_shift; 1009 - uport->mapbase = (unsigned long)new_info->iomem_base; 1010 - 1011 - /* 1012 - * Claim and map the new regions 1013 - */ 1014 - if (uport->type != PORT_UNKNOWN && uport->ops->request_port) { 1015 - retval = uport->ops->request_port(uport); 1016 - } else { 1017 - /* Always success - Jean II */ 1018 - retval = 0; 1019 - } 1020 - 1021 - /* 1022 - * If we fail to request resources for the 1023 - * new port, try to restore the old settings. 1024 - */ 1025 - if (retval) { 1026 - uport->iobase = old_iobase; 1027 - uport->type = old_type; 1028 - uport->hub6 = old_hub6; 1029 - uport->iotype = old_iotype; 1030 - uport->regshift = old_shift; 1031 - uport->mapbase = old_mapbase; 1032 - 1033 - if (old_type != PORT_UNKNOWN) { 1034 - retval = uport->ops->request_port(uport); 1035 - /* 1036 - * If we failed to restore the old settings, 1037 - * we fail like this. 1038 - */ 1039 - if (retval) 1040 - uport->type = PORT_UNKNOWN; 1041 - 1042 - /* 1043 - * We failed anyway. 1044 - */ 1045 - retval = -EBUSY; 1046 - } 1047 - 1048 - /* Added to return the correct error -Ram Gupta */ 1049 - goto exit; 1050 - } 946 + retval = uart_change_port(uport, new_info, new_port); 947 + if (retval) 948 + return retval; 1051 949 } 1052 950 1053 951 if (change_irq) ··· 1003 1021 uport->fifosize = new_info->xmit_fifo_size; 1004 1022 1005 1023 check_and_exit: 1006 - retval = 0; 1007 1024 if (uport->type == PORT_UNKNOWN) 1008 - goto exit; 1025 + return 0; 1026 + 1009 1027 if (tty_port_initialized(port)) { 1010 1028 if (((old_flags ^ uport->flags) & UPF_SPD_MASK) || 1011 1029 old_custom_divisor != uport->custom_divisor) { ··· 1021 1039 } 1022 1040 uart_change_line_settings(tty, state, NULL); 1023 1041 } 1024 - } else { 1025 - retval = uart_startup(tty, state, true); 1026 - if (retval == 0) 1027 - tty_port_set_initialized(port, true); 1028 - if (retval > 0) 1029 - retval = 0; 1042 + 1043 + return 0; 1030 1044 } 1031 - exit: 1032 - return retval; 1045 + 1046 + retval = uart_startup(tty, state, true); 1047 + if (retval < 0) 1048 + return retval; 1049 + if (retval == 0) 1050 + tty_port_set_initialized(port, true); 1051 + 1052 + return 0; 1033 1053 } 1034 1054 1035 1055 static int uart_set_info_user(struct tty_struct *tty, struct serial_struct *ss) ··· 3045 3061 if (ret) 3046 3062 return ret; 3047 3063 3048 - mutex_lock(&port->mutex); 3064 + guard(mutex)(&port->mutex); 3049 3065 uport = uart_port_check(state); 3050 - if (uport) { 3051 - oldconsole = uart_console_registered(uport); 3052 - if (oldconsole && !newconsole) { 3053 - ret = unregister_console(uport->cons); 3054 - } else if (!oldconsole && newconsole) { 3055 - if (uart_console(uport)) { 3056 - uport->console_reinit = 1; 3057 - register_console(uport->cons); 3058 - } else { 3059 - ret = -ENOENT; 3060 - } 3061 - } 3062 - } else { 3063 - ret = -ENXIO; 3064 - } 3065 - mutex_unlock(&port->mutex); 3066 + if (!uport) 3067 + return -ENXIO; 3066 3068 3067 - return ret < 0 ? ret : count; 3069 + oldconsole = uart_console_registered(uport); 3070 + if (oldconsole && !newconsole) { 3071 + ret = unregister_console(uport->cons); 3072 + if (ret < 0) 3073 + return ret; 3074 + } else if (!oldconsole && newconsole) { 3075 + if (!uart_console(uport)) 3076 + return -ENOENT; 3077 + 3078 + uport->console_reinit = 1; 3079 + register_console(uport->cons); 3080 + } 3081 + 3082 + return count; 3068 3083 } 3069 3084 3070 3085 static DEVICE_ATTR_RO(uartclk); ··· 3119 3136 { 3120 3137 struct uart_state *state; 3121 3138 struct tty_port *port; 3122 - int ret = 0; 3123 3139 struct device *tty_dev; 3124 3140 int num_groups; 3125 3141 ··· 3128 3146 state = drv->state + uport->line; 3129 3147 port = &state->port; 3130 3148 3131 - mutex_lock(&port->mutex); 3132 - if (state->uart_port) { 3133 - ret = -EINVAL; 3134 - goto out; 3135 - } 3149 + guard(mutex)(&port->mutex); 3150 + if (state->uart_port) 3151 + return -EINVAL; 3136 3152 3137 3153 /* Link the port to the driver state table and vice versa */ 3138 3154 atomic_set(&state->refcount, 1); ··· 3150 3170 uport->minor = drv->tty_driver->minor_start + uport->line; 3151 3171 uport->name = kasprintf(GFP_KERNEL, "%s%d", drv->dev_name, 3152 3172 drv->tty_driver->name_base + uport->line); 3153 - if (!uport->name) { 3154 - ret = -ENOMEM; 3155 - goto out; 3156 - } 3173 + if (!uport->name) 3174 + return -ENOMEM; 3157 3175 3158 3176 if (uport->cons && uport->dev) 3159 3177 of_console_check(uport->dev->of_node, uport->cons->name, uport->line); ··· 3167 3189 3168 3190 uport->tty_groups = kcalloc(num_groups, sizeof(*uport->tty_groups), 3169 3191 GFP_KERNEL); 3170 - if (!uport->tty_groups) { 3171 - ret = -ENOMEM; 3172 - goto out; 3173 - } 3192 + if (!uport->tty_groups) 3193 + return -ENOMEM; 3194 + 3174 3195 uport->tty_groups[0] = &tty_dev_attr_group; 3175 3196 if (uport->attr_group) 3176 3197 uport->tty_groups[1] = uport->attr_group; ··· 3192 3215 uport->line); 3193 3216 } 3194 3217 3195 - out: 3196 - mutex_unlock(&port->mutex); 3197 - 3198 - return ret; 3218 + return 0; 3199 3219 } 3200 3220 3201 3221 /** ··· 3358 3384 struct serial_ctrl_device *ctrl_dev, *new_ctrl_dev = NULL; 3359 3385 int ret; 3360 3386 3361 - mutex_lock(&port_mutex); 3387 + guard(mutex)(&port_mutex); 3362 3388 3363 3389 /* 3364 3390 * Prevent serial_port_runtime_resume() from trying to use the port ··· 3370 3396 ctrl_dev = serial_core_ctrl_find(drv, port->dev, port->ctrl_id); 3371 3397 if (!ctrl_dev) { 3372 3398 new_ctrl_dev = serial_core_ctrl_device_add(port); 3373 - if (IS_ERR(new_ctrl_dev)) { 3374 - ret = PTR_ERR(new_ctrl_dev); 3375 - goto err_unlock; 3376 - } 3399 + if (IS_ERR(new_ctrl_dev)) 3400 + return PTR_ERR(new_ctrl_dev); 3377 3401 ctrl_dev = new_ctrl_dev; 3378 3402 } 3379 3403 ··· 3392 3420 if (ret) 3393 3421 goto err_unregister_port_dev; 3394 3422 3395 - mutex_unlock(&port_mutex); 3396 - 3397 3423 return 0; 3398 3424 3399 3425 err_unregister_port_dev: ··· 3399 3429 3400 3430 err_unregister_ctrl_dev: 3401 3431 serial_base_ctrl_device_remove(new_ctrl_dev); 3402 - 3403 - err_unlock: 3404 - mutex_unlock(&port_mutex); 3405 3432 3406 3433 return ret; 3407 3434 }

+75 -20

drivers/tty/serial/sh-sci.c

··· 165 165 static struct sci_port sci_ports[SCI_NPORTS]; 166 166 static unsigned long sci_ports_in_use; 167 167 static struct uart_driver sci_uart_driver; 168 + static bool sci_uart_earlycon; 169 + static bool sci_uart_earlycon_dev_probing; 168 170 169 171 static inline struct sci_port * 170 172 to_sci_port(struct uart_port *uart) ··· 3058 3056 ret = sci_init_clocks(sci_port, &dev->dev); 3059 3057 if (ret < 0) 3060 3058 return ret; 3061 - 3062 - port->dev = &dev->dev; 3063 - 3064 - pm_runtime_enable(&dev->dev); 3065 3059 } 3066 3060 3067 3061 port->type = p->type; ··· 3082 3084 port->irqflags = 0; 3083 3085 3084 3086 return 0; 3085 - } 3086 - 3087 - static void sci_cleanup_single(struct sci_port *port) 3088 - { 3089 - pm_runtime_disable(port->port.dev); 3090 3087 } 3091 3088 3092 3089 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ ··· 3253 3260 sci_ports_in_use &= ~BIT(port->port.line); 3254 3261 uart_remove_one_port(&sci_uart_driver, &port->port); 3255 3262 3256 - sci_cleanup_single(port); 3257 - 3258 3263 if (port->port.fifosize > 1) 3259 3264 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3260 3265 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) ··· 3387 3396 static int sci_probe_single(struct platform_device *dev, 3388 3397 unsigned int index, 3389 3398 struct plat_sci_port *p, 3390 - struct sci_port *sciport) 3399 + struct sci_port *sciport, 3400 + struct resource *sci_res) 3391 3401 { 3392 3402 int ret; 3393 3403 ··· 3417 3425 if (ret) 3418 3426 return ret; 3419 3427 3428 + sciport->port.dev = &dev->dev; 3429 + ret = devm_pm_runtime_enable(&dev->dev); 3430 + if (ret) 3431 + return ret; 3432 + 3420 3433 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3421 3434 if (IS_ERR(sciport->gpios)) 3422 3435 return PTR_ERR(sciport->gpios); ··· 3435 3438 sciport->port.flags |= UPF_HARD_FLOW; 3436 3439 } 3437 3440 3438 - ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3439 - if (ret) { 3440 - sci_cleanup_single(sciport); 3441 - return ret; 3441 + if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) { 3442 + /* 3443 + * In case: 3444 + * - this is the earlycon port (mapped on index 0 in sci_ports[]) and 3445 + * - it now maps to an alias other than zero and 3446 + * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is 3447 + * available in bootargs) 3448 + * 3449 + * we need to avoid disabling clocks and PM domains through the runtime 3450 + * PM APIs called in __device_attach(). For this, increment the runtime 3451 + * PM reference counter (the clocks and PM domains were already enabled 3452 + * by the bootloader). Otherwise the earlycon may access the HW when it 3453 + * has no clocks enabled leading to failures (infinite loop in 3454 + * sci_poll_put_char()). 3455 + */ 3456 + pm_runtime_get_noresume(&dev->dev); 3457 + 3458 + /* 3459 + * Skip cleanup the sci_port[0] in early_console_exit(), this 3460 + * port is the same as the earlycon one. 3461 + */ 3462 + sci_uart_earlycon_dev_probing = true; 3442 3463 } 3443 3464 3444 - return 0; 3465 + return uart_add_one_port(&sci_uart_driver, &sciport->port); 3445 3466 } 3446 3467 3447 3468 static int sci_probe(struct platform_device *dev) 3448 3469 { 3449 3470 struct plat_sci_port *p; 3471 + struct resource *res; 3450 3472 struct sci_port *sp; 3451 3473 unsigned int dev_id; 3452 3474 int ret; ··· 3495 3479 } 3496 3480 3497 3481 sp = &sci_ports[dev_id]; 3482 + 3483 + /* 3484 + * In case: 3485 + * - the probed port alias is zero (as the one used by earlycon), and 3486 + * - the earlycon is still active (e.g., "earlycon keep_bootcon" in 3487 + * bootargs) 3488 + * 3489 + * defer the probe of this serial. This is a debug scenario and the user 3490 + * must be aware of it. 3491 + * 3492 + * Except when the probed port is the same as the earlycon port. 3493 + */ 3494 + 3495 + res = platform_get_resource(dev, IORESOURCE_MEM, 0); 3496 + if (!res) 3497 + return -ENODEV; 3498 + 3499 + if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start) 3500 + return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n"); 3501 + 3498 3502 platform_set_drvdata(dev, sp); 3499 3503 3500 - ret = sci_probe_single(dev, dev_id, p, sp); 3504 + ret = sci_probe_single(dev, dev_id, p, sp, res); 3501 3505 if (ret) 3502 3506 return ret; 3503 3507 ··· 3598 3562 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3599 3563 #endif 3600 3564 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3601 - static struct plat_sci_port port_cfg __initdata; 3565 + static struct plat_sci_port port_cfg; 3566 + 3567 + static int early_console_exit(struct console *co) 3568 + { 3569 + struct sci_port *sci_port = &sci_ports[0]; 3570 + 3571 + /* 3572 + * Clean the slot used by earlycon. A new SCI device might 3573 + * map to this slot. 3574 + */ 3575 + if (!sci_uart_earlycon_dev_probing) { 3576 + memset(sci_port, 0, sizeof(*sci_port)); 3577 + sci_uart_earlycon = false; 3578 + } 3579 + 3580 + return 0; 3581 + } 3602 3582 3603 3583 static int __init early_console_setup(struct earlycon_device *device, 3604 3584 int type) ··· 3623 3571 return -ENODEV; 3624 3572 3625 3573 device->port.type = type; 3626 - memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3574 + sci_ports[0].port = device->port; 3627 3575 port_cfg.type = type; 3628 3576 sci_ports[0].cfg = &port_cfg; 3629 3577 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3578 + sci_uart_earlycon = true; 3630 3579 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3631 3580 sci_serial_out(&sci_ports[0].port, SCSCR, 3632 3581 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3633 3582 3634 3583 device->con->write = serial_console_write; 3584 + device->con->exit = early_console_exit; 3585 + 3635 3586 return 0; 3636 3587 } 3637 3588 static int __init sci_early_console_setup(struct earlycon_device *device,

+3 -5

drivers/tty/serial/xilinx_uartps.c

··· 287 287 continue; 288 288 } 289 289 290 - if (uart_handle_sysrq_char(port, data)) 290 + if (uart_prepare_sysrq_char(port, data)) 291 291 continue; 292 292 293 293 if (is_rxbs_support) { ··· 495 495 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS)) 496 496 cdns_uart_handle_rx(dev_id, isrstatus); 497 497 498 - uart_port_unlock(port); 498 + uart_unlock_and_check_sysrq(port); 499 499 return IRQ_HANDLED; 500 500 } 501 501 ··· 1380 1380 unsigned int imr, ctrl; 1381 1381 int locked = 1; 1382 1382 1383 - if (port->sysrq) 1384 - locked = 0; 1385 - else if (oops_in_progress) 1383 + if (oops_in_progress) 1386 1384 locked = uart_port_trylock_irqsave(port, &flags); 1387 1385 else 1388 1386 uart_port_lock_irqsave(port, &flags);

+1 -1

drivers/tty/tty_io.c

··· 3617 3617 sysfs_notify(&consdev->kobj, NULL, "active"); 3618 3618 } 3619 3619 3620 - static struct ctl_table tty_table[] = { 3620 + static const struct ctl_table tty_table[] = { 3621 3621 { 3622 3622 .procname = "legacy_tiocsti", 3623 3623 .data = &tty_legacy_tiocsti,

+14

drivers/tty/vt/selection.c

··· 192 192 if (copy_from_user(&v, sel, sizeof(*sel))) 193 193 return -EFAULT; 194 194 195 + /* 196 + * TIOCL_SELCLEAR, TIOCL_SELPOINTER and TIOCL_SELMOUSEREPORT are OK to 197 + * use without CAP_SYS_ADMIN as they do not modify the selection. 198 + */ 199 + switch (v.sel_mode) { 200 + case TIOCL_SELCLEAR: 201 + case TIOCL_SELPOINTER: 202 + case TIOCL_SELMOUSEREPORT: 203 + break; 204 + default: 205 + if (!capable(CAP_SYS_ADMIN)) 206 + return -EPERM; 207 + } 208 + 195 209 return set_selection_kernel(&v, tty); 196 210 } 197 211

-2

drivers/tty/vt/vt.c

··· 3345 3345 3346 3346 switch (type) { 3347 3347 case TIOCL_SETSEL: 3348 - if (!capable(CAP_SYS_ADMIN)) 3349 - return -EPERM; 3350 3348 return set_selection_user(param, tty); 3351 3349 case TIOCL_PASTESEL: 3352 3350 if (!capable(CAP_SYS_ADMIN))

-2

include/linux/kgdb.h

··· 309 309 #ifdef CONFIG_SERIAL_KGDB_NMI 310 310 extern int kgdb_register_nmi_console(void); 311 311 extern int kgdb_unregister_nmi_console(void); 312 - extern bool kgdb_nmi_poll_knock(void); 313 312 #else 314 313 static inline int kgdb_register_nmi_console(void) { return 0; } 315 314 static inline int kgdb_unregister_nmi_console(void) { return 0; } 316 - static inline bool kgdb_nmi_poll_knock(void) { return true; } 317 315 #endif 318 316 319 317 extern int kgdb_register_io_module(struct kgdb_io *local_kgdb_io_ops);

+11

include/linux/pci_ids.h

··· 2593 2593 2594 2594 #define PCI_VENDOR_ID_REDHAT 0x1b36 2595 2595 2596 + #define PCI_VENDOR_ID_WCHIC 0x1c00 2597 + #define PCI_DEVICE_ID_WCHIC_CH382_0S1P 0x3050 2598 + #define PCI_DEVICE_ID_WCHIC_CH382_2S1P 0x3250 2599 + #define PCI_DEVICE_ID_WCHIC_CH382_2S 0x3253 2600 + 2596 2601 #define PCI_VENDOR_ID_SILICOM_DENMARK 0x1c2c 2597 2602 2598 2603 #define PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS 0x1c36 ··· 2651 2646 2652 2647 #define PCI_VENDOR_ID_AKS 0x416c 2653 2648 #define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100 2649 + 2650 + #define PCI_VENDOR_ID_WCHCN 0x4348 2651 + #define PCI_DEVICE_ID_WCHCN_CH353_4S 0x3453 2652 + #define PCI_DEVICE_ID_WCHCN_CH353_2S1PF 0x5046 2653 + #define PCI_DEVICE_ID_WCHCN_CH353_1S1P 0x5053 2654 + #define PCI_DEVICE_ID_WCHCN_CH353_2S1P 0x7053 2654 2655 2655 2656 #define PCI_VENDOR_ID_ACCESSIO 0x494f 2656 2657 #define PCI_DEVICE_ID_ACCESSIO_WDG_CSM 0x22c0

+2 -2

include/linux/serial_8250.h

··· 161 161 void (*dl_write)(struct uart_8250_port *up, u32 value); 162 162 163 163 struct uart_8250_em485 *em485; 164 - void (*rs485_start_tx)(struct uart_8250_port *); 165 - void (*rs485_stop_tx)(struct uart_8250_port *); 164 + void (*rs485_start_tx)(struct uart_8250_port *up, bool toggle_ier); 165 + void (*rs485_stop_tx)(struct uart_8250_port *up, bool toggle_ier); 166 166 167 167 /* Serial port overrun backoff */ 168 168 struct delayed_work overrun_backoff;

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