Merge tag 'ti-k3-dt-for-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt

+1

Documentation/devicetree/bindings/arm/ti/k3.yaml

··· 61 61 - const: ti,j721e 62 62 - items: 63 63 - enum: 64 + - beagle,j721e-beagleboneai64 64 65 - ti,j721e-evm 65 66 - ti,j721e-sk 66 67 - const: ti,j721e

+1

arch/arm64/boot/dts/ti/Makefile

··· 12 12 dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb 13 13 dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb 14 14 15 + dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb 15 16 dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb 16 17 dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb 17 18

+122

arch/arm64/boot/dts/ti/k3-am62-main.dtsi

··· 192 192 pinctrl-single,function-mask = <0xffffffff>; 193 193 }; 194 194 195 + main_timer0: timer@2400000 { 196 + compatible = "ti,am654-timer"; 197 + reg = <0x00 0x2400000 0x00 0x400>; 198 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 199 + clocks = <&k3_clks 36 2>; 200 + clock-names = "fck"; 201 + assigned-clocks = <&k3_clks 36 2>; 202 + assigned-clock-parents = <&k3_clks 36 3>; 203 + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 204 + ti,timer-pwm; 205 + }; 206 + 207 + main_timer1: timer@2410000 { 208 + compatible = "ti,am654-timer"; 209 + reg = <0x00 0x2410000 0x00 0x400>; 210 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 211 + clocks = <&k3_clks 37 2>; 212 + clock-names = "fck"; 213 + assigned-clocks = <&k3_clks 37 2>; 214 + assigned-clock-parents = <&k3_clks 37 3>; 215 + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 216 + ti,timer-pwm; 217 + }; 218 + 219 + main_timer2: timer@2420000 { 220 + compatible = "ti,am654-timer"; 221 + reg = <0x00 0x2420000 0x00 0x400>; 222 + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 223 + clocks = <&k3_clks 38 2>; 224 + clock-names = "fck"; 225 + assigned-clocks = <&k3_clks 38 2>; 226 + assigned-clock-parents = <&k3_clks 38 3>; 227 + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 228 + ti,timer-pwm; 229 + }; 230 + 231 + main_timer3: timer@2430000 { 232 + compatible = "ti,am654-timer"; 233 + reg = <0x00 0x2430000 0x00 0x400>; 234 + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 235 + clocks = <&k3_clks 39 2>; 236 + clock-names = "fck"; 237 + assigned-clocks = <&k3_clks 39 2>; 238 + assigned-clock-parents = <&k3_clks 39 3>; 239 + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 240 + ti,timer-pwm; 241 + }; 242 + 243 + main_timer4: timer@2440000 { 244 + compatible = "ti,am654-timer"; 245 + reg = <0x00 0x2440000 0x00 0x400>; 246 + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 247 + clocks = <&k3_clks 40 2>; 248 + clock-names = "fck"; 249 + assigned-clocks = <&k3_clks 40 2>; 250 + assigned-clock-parents = <&k3_clks 40 3>; 251 + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 252 + ti,timer-pwm; 253 + }; 254 + 255 + main_timer5: timer@2450000 { 256 + compatible = "ti,am654-timer"; 257 + reg = <0x00 0x2450000 0x00 0x400>; 258 + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 259 + clocks = <&k3_clks 41 2>; 260 + clock-names = "fck"; 261 + assigned-clocks = <&k3_clks 41 2>; 262 + assigned-clock-parents = <&k3_clks 41 3>; 263 + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 264 + ti,timer-pwm; 265 + }; 266 + 267 + main_timer6: timer@2460000 { 268 + compatible = "ti,am654-timer"; 269 + reg = <0x00 0x2460000 0x00 0x400>; 270 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 271 + clocks = <&k3_clks 42 2>; 272 + clock-names = "fck"; 273 + assigned-clocks = <&k3_clks 42 2>; 274 + assigned-clock-parents = <&k3_clks 42 3>; 275 + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 276 + ti,timer-pwm; 277 + }; 278 + 279 + main_timer7: timer@2470000 { 280 + compatible = "ti,am654-timer"; 281 + reg = <0x00 0x2470000 0x00 0x400>; 282 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 283 + clocks = <&k3_clks 43 2>; 284 + clock-names = "fck"; 285 + assigned-clocks = <&k3_clks 43 2>; 286 + assigned-clock-parents = <&k3_clks 43 3>; 287 + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 288 + ti,timer-pwm; 289 + }; 290 + 195 291 main_uart0: serial@2800000 { 196 292 compatible = "ti,am64-uart", "ti,am654-uart"; 197 293 reg = <0x00 0x02800000 0x00 0x100>; ··· 295 199 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 296 200 clocks = <&k3_clks 146 0>; 297 201 clock-names = "fclk"; 202 + status = "disabled"; 298 203 }; 299 204 300 205 main_uart1: serial@2810000 { ··· 305 208 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 306 209 clocks = <&k3_clks 152 0>; 307 210 clock-names = "fclk"; 211 + status = "disabled"; 308 212 }; 309 213 310 214 main_uart2: serial@2820000 { ··· 315 217 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 316 218 clocks = <&k3_clks 153 0>; 317 219 clock-names = "fclk"; 220 + status = "disabled"; 318 221 }; 319 222 320 223 main_uart3: serial@2830000 { ··· 325 226 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 326 227 clocks = <&k3_clks 154 0>; 327 228 clock-names = "fclk"; 229 + status = "disabled"; 328 230 }; 329 231 330 232 main_uart4: serial@2840000 { ··· 335 235 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 336 236 clocks = <&k3_clks 155 0>; 337 237 clock-names = "fclk"; 238 + status = "disabled"; 338 239 }; 339 240 340 241 main_uart5: serial@2850000 { ··· 345 244 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 346 245 clocks = <&k3_clks 156 0>; 347 246 clock-names = "fclk"; 247 + status = "disabled"; 348 248 }; 349 249 350 250 main_uart6: serial@2860000 { ··· 355 253 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 356 254 clocks = <&k3_clks 158 0>; 357 255 clock-names = "fclk"; 256 + status = "disabled"; 358 257 }; 359 258 360 259 main_i2c0: i2c@20000000 { ··· 367 264 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 368 265 clocks = <&k3_clks 102 2>; 369 266 clock-names = "fck"; 267 + status = "disabled"; 370 268 }; 371 269 372 270 main_i2c1: i2c@20010000 { ··· 379 275 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 380 276 clocks = <&k3_clks 103 2>; 381 277 clock-names = "fck"; 278 + status = "disabled"; 382 279 }; 383 280 384 281 main_i2c2: i2c@20020000 { ··· 391 286 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 392 287 clocks = <&k3_clks 104 2>; 393 288 clock-names = "fck"; 289 + status = "disabled"; 394 290 }; 395 291 396 292 main_i2c3: i2c@20030000 { ··· 403 297 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 404 298 clocks = <&k3_clks 105 2>; 405 299 clock-names = "fck"; 300 + status = "disabled"; 406 301 }; 407 302 408 303 main_spi0: spi@20100000 { ··· 414 307 #size-cells = <0>; 415 308 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 416 309 clocks = <&k3_clks 172 0>; 310 + status = "disabled"; 417 311 }; 418 312 419 313 main_spi1: spi@20110000 { ··· 425 317 #size-cells = <0>; 426 318 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 427 319 clocks = <&k3_clks 173 0>; 320 + status = "disabled"; 428 321 }; 429 322 430 323 main_spi2: spi@20120000 { ··· 436 327 #size-cells = <0>; 437 328 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 438 329 clocks = <&k3_clks 174 0>; 330 + status = "disabled"; 439 331 }; 440 332 441 333 main_gpio_intr: interrupt-controller@a00000 { ··· 503 393 ti,otap-del-sel-mmc-hs = <0x0>; 504 394 ti,otap-del-sel-ddr52 = <0x9>; 505 395 ti,otap-del-sel-hs200 = <0x6>; 396 + status = "disabled"; 506 397 }; 507 398 508 399 sdhci1: mmc@fa00000 { ··· 527 416 ti,itap-del-sel-sdr25 = <0x0>; 528 417 ti,clkbuf-sel = <0x7>; 529 418 bus-width = <4>; 419 + status = "disabled"; 530 420 }; 531 421 532 422 sdhci2: mmc@fa20000 { ··· 550 438 ti,itap-del-sel-sdr12 = <0x0>; 551 439 ti,itap-del-sel-sdr25 = <0x0>; 552 440 ti,clkbuf-sel = <0x7>; 441 + status = "disabled"; 553 442 }; 554 443 555 444 fss: bus@fc00000 { ··· 575 462 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 576 463 #address-cells = <1>; 577 464 #size-cells = <0>; 465 + status = "disabled"; 578 466 }; 579 467 }; 580 468 ··· 634 520 clocks = <&k3_clks 13 0>; 635 521 clock-names = "fck"; 636 522 bus_freq = <1000000>; 523 + status = "disabled"; 637 524 }; 638 525 639 526 cpts@3d000 { ··· 672 557 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 673 558 clocks = <&k3_clks 51 0>; 674 559 clock-names = "fck"; 560 + status = "disabled"; 675 561 }; 676 562 677 563 ecap1: pwm@23110000 { ··· 682 566 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 683 567 clocks = <&k3_clks 52 0>; 684 568 clock-names = "fck"; 569 + status = "disabled"; 685 570 }; 686 571 687 572 ecap2: pwm@23120000 { ··· 692 575 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 693 576 clocks = <&k3_clks 53 0>; 694 577 clock-names = "fck"; 578 + status = "disabled"; 695 579 }; 696 580 697 581 main_mcan0: can@20701000 { ··· 707 589 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 708 590 interrupt-names = "int0", "int1"; 709 591 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 592 + status = "disabled"; 710 593 }; 711 594 712 595 epwm0: pwm@23000000 { ··· 717 598 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 718 599 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 719 600 clock-names = "tbclk", "fck"; 601 + status = "disabled"; 720 602 }; 721 603 722 604 epwm1: pwm@23010000 { ··· 727 607 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 728 608 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 729 609 clock-names = "tbclk", "fck"; 610 + status = "disabled"; 730 611 }; 731 612 732 613 epwm2: pwm@23020000 { ··· 737 616 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 738 617 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 739 618 clock-names = "tbclk", "fck"; 619 + status = "disabled"; 740 620 }; 741 621 };

+49

arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi

··· 14 14 pinctrl-single,function-mask = <0xffffffff>; 15 15 }; 16 16 17 + /* 18 + * The MCU domain timer interrupts are routed only to the ESM module, 19 + * and not currently available for Linux. The MCU domain timers are 20 + * of limited use without interrupts, and likely reserved by the ESM. 21 + */ 22 + mcu_timer0: timer@4800000 { 23 + compatible = "ti,am654-timer"; 24 + reg = <0x00 0x4800000 0x00 0x400>; 25 + clocks = <&k3_clks 35 2>; 26 + clock-names = "fck"; 27 + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 28 + ti,timer-pwm; 29 + status = "reserved"; 30 + }; 31 + 32 + mcu_timer1: timer@4810000 { 33 + compatible = "ti,am654-timer"; 34 + reg = <0x00 0x4810000 0x00 0x400>; 35 + clocks = <&k3_clks 48 2>; 36 + clock-names = "fck"; 37 + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 38 + ti,timer-pwm; 39 + status = "reserved"; 40 + }; 41 + 42 + mcu_timer2: timer@4820000 { 43 + compatible = "ti,am654-timer"; 44 + reg = <0x00 0x4820000 0x00 0x400>; 45 + clocks = <&k3_clks 49 2>; 46 + clock-names = "fck"; 47 + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 48 + ti,timer-pwm; 49 + status = "reserved"; 50 + }; 51 + 52 + mcu_timer3: timer@4830000 { 53 + compatible = "ti,am654-timer"; 54 + reg = <0x00 0x4830000 0x00 0x400>; 55 + clocks = <&k3_clks 50 2>; 56 + clock-names = "fck"; 57 + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 58 + ti,timer-pwm; 59 + status = "reserved"; 60 + }; 61 + 17 62 mcu_uart0: serial@4a00000 { 18 63 compatible = "ti,am64-uart", "ti,am654-uart"; 19 64 reg = <0x00 0x04a00000 0x00 0x100>; ··· 66 21 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 67 22 clocks = <&k3_clks 149 0>; 68 23 clock-names = "fclk"; 24 + status = "disabled"; 69 25 }; 70 26 71 27 mcu_i2c0: i2c@4900000 { ··· 78 32 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 79 33 clocks = <&k3_clks 106 2>; 80 34 clock-names = "fck"; 35 + status = "disabled"; 81 36 }; 82 37 83 38 mcu_spi0: spi@4b00000 { ··· 89 42 #size-cells = <0>; 90 43 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 91 44 clocks = <&k3_clks 147 0>; 45 + status = "disabled"; 92 46 }; 93 47 94 48 mcu_spi1: spi@4b10000 { ··· 100 52 #size-cells = <0>; 101 53 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 102 54 clocks = <&k3_clks 148 0>; 55 + status = "disabled"; 103 56 }; 104 57 105 58 mcu_gpio_intr: interrupt-controller@4210000 {

+3 -1

arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi

··· 26 26 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 27 27 clocks = <&k3_clks 114 0>; 28 28 clock-names = "fclk"; 29 + status = "disabled"; 29 30 }; 30 31 31 32 wkup_i2c0: i2c@2b200000 { 32 33 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 33 - reg = <0x00 0x02b200000 0x00 0x100>; 34 + reg = <0x00 0x2b200000 0x00 0x100>; 34 35 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 35 36 #address-cells = <1>; 36 37 #size-cells = <0>; 37 38 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 38 39 clocks = <&k3_clks 107 4>; 39 40 clock-names = "fck"; 41 + status = "disabled"; 40 42 }; 41 43 };

+11 -70

arch/arm64/boot/dts/ti/k3-am625-sk.dts

··· 282 282 status = "reserved"; 283 283 }; 284 284 285 - &mcu_uart0 { 286 - status = "disabled"; 287 - }; 288 - 289 285 &main_uart0 { 286 + status = "okay"; 290 287 pinctrl-names = "default"; 291 288 pinctrl-0 = <&main_uart0_pins_default>; 292 289 }; ··· 293 296 status = "reserved"; 294 297 }; 295 298 296 - &main_uart2 { 297 - status = "disabled"; 298 - }; 299 - 300 - &main_uart3 { 301 - status = "disabled"; 302 - }; 303 - 304 - &main_uart4 { 305 - status = "disabled"; 306 - }; 307 - 308 - &main_uart5 { 309 - status = "disabled"; 310 - }; 311 - 312 - &main_uart6 { 313 - status = "disabled"; 314 - }; 315 - 316 - &mcu_i2c0 { 317 - status = "disabled"; 318 - }; 319 - 320 - &wkup_i2c0 { 321 - status = "disabled"; 322 - }; 323 - 324 299 &main_i2c0 { 300 + status = "okay"; 325 301 pinctrl-names = "default"; 326 302 pinctrl-0 = <&main_i2c0_pins_default>; 327 303 clock-frequency = <400000>; 328 304 }; 329 305 330 306 &main_i2c1 { 307 + status = "okay"; 331 308 pinctrl-names = "default"; 332 309 pinctrl-0 = <&main_i2c1_pins_default>; 333 310 clock-frequency = <400000>; ··· 334 363 }; 335 364 }; 336 365 337 - &main_i2c2 { 338 - status = "disabled"; 339 - }; 340 - 341 - &main_i2c3 { 342 - status = "disabled"; 343 - }; 344 - 345 366 &sdhci0 { 367 + status = "okay"; 346 368 pinctrl-names = "default"; 347 369 pinctrl-0 = <&main_mmc0_pins_default>; 348 370 ti,driver-strength-ohm = <50>; ··· 344 380 345 381 &sdhci1 { 346 382 /* SD/MMC */ 383 + status = "okay"; 347 384 vmmc-supply = <&vdd_mmc1>; 348 385 vqmmc-supply = <&vdd_sd_dv>; 349 386 pinctrl-names = "default"; ··· 355 390 356 391 &cpsw3g { 357 392 pinctrl-names = "default"; 358 - pinctrl-0 = <&main_mdio1_pins_default 359 - &main_rgmii1_pins_default 393 + pinctrl-0 = <&main_rgmii1_pins_default 360 394 &main_rgmii2_pins_default>; 361 395 }; 362 396 ··· 370 406 }; 371 407 372 408 &cpsw3g_mdio { 409 + status = "okay"; 410 + pinctrl-names = "default"; 411 + pinctrl-0 = <&main_mdio1_pins_default>; 412 + 373 413 cpsw3g_phy0: ethernet-phy@0 { 374 414 reg = <0>; 375 415 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ··· 397 429 }; 398 430 399 431 &ospi0 { 432 + status = "okay"; 400 433 pinctrl-names = "default"; 401 434 pinctrl-0 = <&ospi0_pins_default>; 402 435 ··· 454 485 }; 455 486 }; 456 487 }; 457 - }; 458 - 459 - &ecap0 { 460 - status = "disabled"; 461 - }; 462 - 463 - &ecap1 { 464 - status = "disabled"; 465 - }; 466 - 467 - &ecap2 { 468 - status = "disabled"; 469 - }; 470 - 471 - &main_mcan0 { 472 - status = "disabled"; 473 - }; 474 - 475 - &epwm0 { 476 - status = "disabled"; 477 - }; 478 - 479 - &epwm1 { 480 - status = "disabled"; 481 - }; 482 - 483 - &epwm2 { 484 - status = "disabled"; 485 488 };

+1 -1

arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi

··· 31 31 32 32 wkup_i2c0: i2c@2b200000 { 33 33 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 34 - reg = <0x00 0x02b200000 0x00 0x100>; 34 + reg = <0x00 0x2b200000 0x00 0x100>; 35 35 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 36 36 #address-cells = <1>; 37 37 #size-cells = <0>;

+40 -4

arch/arm64/boot/dts/ti/k3-am64-main.dtsi

··· 237 237 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 238 238 clocks = <&k3_clks 146 0>; 239 239 clock-names = "fclk"; 240 + status = "disabled"; 240 241 }; 241 242 242 243 main_uart1: serial@2810000 { ··· 249 248 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 250 249 clocks = <&k3_clks 152 0>; 251 250 clock-names = "fclk"; 251 + status = "disabled"; 252 252 }; 253 253 254 254 main_uart2: serial@2820000 { ··· 261 259 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 262 260 clocks = <&k3_clks 153 0>; 263 261 clock-names = "fclk"; 262 + status = "disabled"; 264 263 }; 265 264 266 265 main_uart3: serial@2830000 { ··· 273 270 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 274 271 clocks = <&k3_clks 154 0>; 275 272 clock-names = "fclk"; 273 + status = "disabled"; 276 274 }; 277 275 278 276 main_uart4: serial@2840000 { ··· 285 281 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 286 282 clocks = <&k3_clks 155 0>; 287 283 clock-names = "fclk"; 284 + status = "disabled"; 288 285 }; 289 286 290 287 main_uart5: serial@2850000 { ··· 297 292 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 298 293 clocks = <&k3_clks 156 0>; 299 294 clock-names = "fclk"; 295 + status = "disabled"; 300 296 }; 301 297 302 298 main_uart6: serial@2860000 { ··· 309 303 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 310 304 clocks = <&k3_clks 158 0>; 311 305 clock-names = "fclk"; 306 + status = "disabled"; 312 307 }; 313 308 314 309 main_i2c0: i2c@20000000 { ··· 321 314 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 322 315 clocks = <&k3_clks 102 2>; 323 316 clock-names = "fck"; 317 + status = "disabled"; 324 318 }; 325 319 326 320 main_i2c1: i2c@20010000 { ··· 333 325 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 334 326 clocks = <&k3_clks 103 2>; 335 327 clock-names = "fck"; 328 + status = "disabled"; 336 329 }; 337 330 338 331 main_i2c2: i2c@20020000 { ··· 345 336 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 346 337 clocks = <&k3_clks 104 2>; 347 338 clock-names = "fck"; 339 + status = "disabled"; 348 340 }; 349 341 350 342 main_i2c3: i2c@20030000 { ··· 357 347 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 358 348 clocks = <&k3_clks 105 2>; 359 349 clock-names = "fck"; 350 + status = "disabled"; 360 351 }; 361 352 362 353 main_spi0: spi@20100000 { ··· 370 359 clocks = <&k3_clks 141 0>; 371 360 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 372 361 dma-names = "tx0", "rx0"; 362 + status = "disabled"; 373 363 }; 374 364 375 365 main_spi1: spi@20110000 { ··· 381 369 #size-cells = <0>; 382 370 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 383 371 clocks = <&k3_clks 142 0>; 372 + status = "disabled"; 384 373 }; 385 374 386 375 main_spi2: spi@20120000 { ··· 392 379 #size-cells = <0>; 393 380 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 394 381 clocks = <&k3_clks 143 0>; 382 + status = "disabled"; 395 383 }; 396 384 397 385 main_spi3: spi@20130000 { ··· 403 389 #size-cells = <0>; 404 390 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 405 391 clocks = <&k3_clks 144 0>; 392 + status = "disabled"; 406 393 }; 407 394 408 395 main_spi4: spi@20140000 { ··· 414 399 #size-cells = <0>; 415 400 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 416 401 clocks = <&k3_clks 145 0>; 402 + status = "disabled"; 417 403 }; 418 404 419 405 main_gpio_intr: interrupt-controller@a00000 { ··· 552 536 clocks = <&k3_clks 13 0>; 553 537 clock-names = "fck"; 554 538 bus_freq = <1000000>; 539 + status = "disabled"; 555 540 }; 556 541 557 542 cpts@3d000 { ··· 629 612 assigned-clocks = <&k3_clks 0 0>; 630 613 assigned-clock-parents = <&k3_clks 0 3>; 631 614 assigned-clock-rates = <60000000>; 632 - clock-names = "adc_tsc_fck"; 615 + clock-names = "fck"; 633 616 634 617 adc { 635 618 #io-channel-cells = <1>; ··· 872 855 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, 873 856 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; 874 857 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 858 + status = "disabled"; 875 859 }; 876 860 877 861 pcie0_ep: pcie-ep@f102000 { ··· 891 873 clocks = <&k3_clks 114 0>; 892 874 clock-names = "fck"; 893 875 max-functions = /bits/ 8 <1>; 876 + status = "disabled"; 894 877 }; 895 878 896 879 epwm0: pwm@23000000 { ··· 901 882 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 902 883 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 903 884 clock-names = "tbclk", "fck"; 885 + status = "disabled"; 904 886 }; 905 887 906 888 epwm1: pwm@23010000 { ··· 911 891 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 912 892 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 913 893 clock-names = "tbclk", "fck"; 894 + status = "disabled"; 914 895 }; 915 896 916 897 epwm2: pwm@23020000 { ··· 921 900 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 922 901 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 923 902 clock-names = "tbclk", "fck"; 903 + status = "disabled"; 924 904 }; 925 905 926 906 epwm3: pwm@23030000 { ··· 931 909 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 932 910 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; 933 911 clock-names = "tbclk", "fck"; 912 + status = "disabled"; 934 913 }; 935 914 936 915 epwm4: pwm@23040000 { ··· 941 918 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 942 919 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; 943 920 clock-names = "tbclk", "fck"; 921 + status = "disabled"; 944 922 }; 945 923 946 924 epwm5: pwm@23050000 { ··· 951 927 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 952 928 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; 953 929 clock-names = "tbclk", "fck"; 930 + status = "disabled"; 954 931 }; 955 932 956 933 epwm6: pwm@23060000 { ··· 961 936 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 962 937 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; 963 938 clock-names = "tbclk", "fck"; 939 + status = "disabled"; 964 940 }; 965 941 966 942 epwm7: pwm@23070000 { ··· 971 945 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 972 946 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; 973 947 clock-names = "tbclk", "fck"; 948 + status = "disabled"; 974 949 }; 975 950 976 951 epwm8: pwm@23080000 { ··· 981 954 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; 982 955 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; 983 956 clock-names = "tbclk", "fck"; 957 + status = "disabled"; 984 958 }; 985 959 986 960 ecap0: pwm@23100000 { ··· 991 963 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 992 964 clocks = <&k3_clks 51 0>; 993 965 clock-names = "fck"; 966 + status = "disabled"; 994 967 }; 995 968 996 969 ecap1: pwm@23110000 { ··· 1001 972 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1002 973 clocks = <&k3_clks 52 0>; 1003 974 clock-names = "fck"; 975 + status = "disabled"; 1004 976 }; 1005 977 1006 978 ecap2: pwm@23120000 { ··· 1011 981 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1012 982 clocks = <&k3_clks 53 0>; 1013 983 clock-names = "fck"; 984 + status = "disabled"; 1014 985 }; 1015 986 1016 987 main_rti0: watchdog@e000000 { ··· 1169 1138 #address-cells = <1>; 1170 1139 #size-cells = <0>; 1171 1140 bus_freq = <1000000>; 1141 + status = "disabled"; 1172 1142 }; 1173 1143 }; 1174 1144 ··· 1310 1278 clocks = <&k3_clks 82 0>; 1311 1279 clock-names = "fck"; 1312 1280 bus_freq = <1000000>; 1281 + status = "disabled"; 1313 1282 }; 1314 1283 }; 1315 1284 ··· 1326 1293 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1327 1294 interrupt-names = "int0", "int1"; 1328 1295 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1296 + status = "disabled"; 1329 1297 }; 1330 1298 1331 1299 main_mcan1: can@20711000 { ··· 1341 1307 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1342 1308 interrupt-names = "int0", "int1"; 1343 1309 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1310 + status = "disabled"; 1344 1311 }; 1345 1312 1346 1313 crypto: crypto@40900000 { ··· 1359 1324 compatible = "inside-secure,safexcel-eip76"; 1360 1325 reg = <0x00 0x40910000 0x00 0x7d>; 1361 1326 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1362 - clocks = <&k3_clks 133 1>; 1363 1327 status = "disabled"; /* Used by OP-TEE */ 1364 1328 }; 1365 1329 }; ··· 1368 1334 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 1369 1335 clocks = <&k3_clks 80 0>; 1370 1336 clock-names = "fck"; 1371 - reg = <0x00 0x03b000000 0x00 0x400>, 1372 - <0x00 0x050000000 0x00 0x8000000>; 1337 + reg = <0x00 0x3b000000 0x00 0x400>, 1338 + <0x00 0x50000000 0x00 0x8000000>; 1373 1339 reg-names = "cfg", "data"; 1374 1340 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1375 1341 gpmc,num-cs = <3>; ··· 1380 1346 #interrupt-cells = <2>; 1381 1347 gpio-controller; 1382 1348 #gpio-cells = <2>; 1349 + status = "disabled"; 1383 1350 }; 1384 1351 1385 1352 elm0: ecc@25010000 { ··· 1390 1355 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1391 1356 clocks = <&k3_clks 54 0>; 1392 1357 clock-names = "fck"; 1358 + status = "disabled"; 1393 1359 }; 1394 1360 };

+6

arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi

··· 14 14 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 15 15 clocks = <&k3_clks 149 0>; 16 16 clock-names = "fclk"; 17 + status = "disabled"; 17 18 }; 18 19 19 20 mcu_uart1: serial@4a10000 { ··· 25 24 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 26 25 clocks = <&k3_clks 160 0>; 27 26 clock-names = "fclk"; 27 + status = "disabled"; 28 28 }; 29 29 30 30 mcu_i2c0: i2c@4900000 { ··· 37 35 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 38 36 clocks = <&k3_clks 106 2>; 39 37 clock-names = "fck"; 38 + status = "disabled"; 40 39 }; 41 40 42 41 mcu_i2c1: i2c@4910000 { ··· 49 46 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 50 47 clocks = <&k3_clks 107 2>; 51 48 clock-names = "fck"; 49 + status = "disabled"; 52 50 }; 53 51 54 52 mcu_spi0: spi@4b00000 { ··· 60 56 #size-cells = <0>; 61 57 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 62 58 clocks = <&k3_clks 147 0>; 59 + status = "disabled"; 63 60 }; 64 61 65 62 mcu_spi1: spi@4b10000 { ··· 71 66 #size-cells = <0>; 72 67 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 73 68 clocks = <&k3_clks 148 0>; 69 + status = "disabled"; 74 70 }; 75 71 76 72 mcu_gpio_intr: interrupt-controller@4210000 {

+12 -107

arch/arm64/boot/dts/ti/k3-am642-evm.dts

··· 325 325 }; 326 326 327 327 &main_uart0 { 328 + status = "okay"; 328 329 pinctrl-names = "default"; 329 330 pinctrl-0 = <&main_uart0_pins_default>; 330 331 }; ··· 335 334 status = "reserved"; 336 335 }; 337 336 338 - &main_uart2 { 339 - status = "disabled"; 340 - }; 341 - 342 - &main_uart3 { 343 - status = "disabled"; 344 - }; 345 - 346 - &main_uart4 { 347 - status = "disabled"; 348 - }; 349 - 350 - &main_uart5 { 351 - status = "disabled"; 352 - }; 353 - 354 - &main_uart6 { 355 - status = "disabled"; 356 - }; 357 - 358 - &mcu_uart0 { 359 - status = "disabled"; 360 - }; 361 - 362 - &mcu_uart1 { 363 - status = "disabled"; 364 - }; 365 - 366 337 &main_i2c1 { 338 + status = "okay"; 367 339 pinctrl-names = "default"; 368 340 pinctrl-0 = <&main_i2c1_pins_default>; 369 341 clock-frequency = <400000>; ··· 379 405 status = "reserved"; 380 406 }; 381 407 382 - &mcu_i2c0 { 383 - status = "disabled"; 384 - }; 385 - 386 - &mcu_i2c1 { 387 - status = "disabled"; 388 - }; 389 - 390 - &mcu_spi0 { 391 - status = "disabled"; 392 - }; 393 - 394 - &mcu_spi1 { 395 - status = "disabled"; 396 - }; 397 - 398 408 &main_spi0 { 409 + status = "okay"; 399 410 pinctrl-names = "default"; 400 411 pinctrl-0 = <&main_spi0_pins_default>; 401 412 ti,pindir-d0-out-d1-in; ··· 425 466 426 467 &cpsw3g { 427 468 pinctrl-names = "default"; 428 - pinctrl-0 = <&mdio1_pins_default 429 - &rgmii1_pins_default 469 + pinctrl-0 = <&rgmii1_pins_default 430 470 &rgmii2_pins_default>; 431 471 }; 432 472 ··· 440 482 }; 441 483 442 484 &cpsw3g_mdio { 485 + status = "okay"; 486 + pinctrl-names = "default"; 487 + pinctrl-0 = <&mdio1_pins_default>; 488 + 443 489 cpsw3g_phy0: ethernet-phy@0 { 444 490 reg = <0>; 445 491 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ··· 556 594 }; 557 595 558 596 &pcie0_rc { 597 + status = "okay"; 559 598 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; 560 599 phys = <&serdes0_pcie_link>; 561 600 phy-names = "pcie-phy"; ··· 567 604 phys = <&serdes0_pcie_link>; 568 605 phy-names = "pcie-phy"; 569 606 num-lanes = <1>; 570 - status = "disabled"; 571 607 }; 572 608 573 609 &ecap0 { 610 + status = "okay"; 574 611 /* PWM is available on Pin 1 of header J12 */ 575 612 pinctrl-names = "default"; 576 613 pinctrl-0 = <&main_ecap0_pins_default>; 577 614 }; 578 615 579 - &ecap1 { 580 - status = "disabled"; 581 - }; 582 - 583 - &ecap2 { 584 - status = "disabled"; 585 - }; 586 - 587 - &epwm0 { 588 - status = "disabled"; 589 - }; 590 - 591 - &epwm1 { 592 - status = "disabled"; 593 - }; 594 - 595 - &epwm2 { 596 - status = "disabled"; 597 - }; 598 - 599 - &epwm3 { 600 - status = "disabled"; 601 - }; 602 - 603 - &epwm4 { 604 - status = "disabled"; 605 - }; 606 - 607 - &epwm5 { 608 - status = "disabled"; 609 - }; 610 - 611 - &epwm6 { 612 - status = "disabled"; 613 - }; 614 - 615 - &epwm7 { 616 - status = "disabled"; 617 - }; 618 - 619 - &epwm8 { 620 - status = "disabled"; 621 - }; 622 - 623 - &icssg0_mdio { 624 - status = "disabled"; 625 - }; 626 - 627 - &icssg1_mdio { 628 - status = "disabled"; 629 - }; 630 - 631 616 &main_mcan0 { 617 + status = "okay"; 632 618 pinctrl-names = "default"; 633 619 pinctrl-0 = <&main_mcan0_pins_default>; 634 620 phys = <&transceiver1>; 635 621 }; 636 622 637 623 &main_mcan1 { 624 + status = "okay"; 638 625 pinctrl-names = "default"; 639 626 pinctrl-0 = <&main_mcan1_pins_default>; 640 627 phys = <&transceiver2>; 641 - }; 642 - 643 - &gpmc0 { 644 - status = "disabled"; 645 - }; 646 - 647 - &elm0 { 648 - status = "disabled"; 649 628 };

+8 -134

arch/arm64/boot/dts/ti/k3-am642-sk.dts

··· 338 338 }; 339 339 }; 340 340 341 - &mcu_uart0 { 342 - status = "disabled"; 343 - }; 344 - 345 - &mcu_uart1 { 346 - status = "disabled"; 347 - }; 348 - 349 341 &main_uart0 { 342 + status = "okay"; 350 343 pinctrl-names = "default"; 351 344 pinctrl-0 = <&main_uart0_pins_default>; 352 345 }; ··· 349 356 status = "reserved"; 350 357 }; 351 358 352 - &main_uart2 { 353 - status = "disabled"; 354 - }; 355 - 356 - &main_uart3 { 357 - status = "disabled"; 358 - }; 359 - 360 - &main_uart4 { 361 - status = "disabled"; 362 - }; 363 - 364 - &main_uart5 { 365 - status = "disabled"; 366 - }; 367 - 368 - &main_uart6 { 369 - status = "disabled"; 370 - }; 371 - 372 - &mcu_i2c0 { 373 - status = "disabled"; 374 - }; 375 - 376 - &mcu_i2c1 { 377 - status = "disabled"; 378 - }; 379 - 380 359 &main_i2c1 { 360 + status = "okay"; 381 361 pinctrl-names = "default"; 382 362 pinctrl-0 = <&main_i2c1_pins_default>; 383 363 clock-frequency = <400000>; ··· 373 407 #gpio-cells = <2>; 374 408 gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8"; 375 409 }; 376 - }; 377 - 378 - &main_i2c3 { 379 - status = "disabled"; 380 - }; 381 - 382 - &mcu_spi0 { 383 - status = "disabled"; 384 - }; 385 - 386 - &mcu_spi1 { 387 - status = "disabled"; 388 410 }; 389 411 390 412 /* mcu_gpio0 is reserved for mcu firmware usage */ ··· 439 485 440 486 &cpsw3g { 441 487 pinctrl-names = "default"; 442 - pinctrl-0 = <&mdio1_pins_default 443 - &rgmii1_pins_default 488 + pinctrl-0 = <&rgmii1_pins_default 444 489 &rgmii2_pins_default>; 445 490 }; 446 491 ··· 454 501 }; 455 502 456 503 &cpsw3g_mdio { 504 + status = "okay"; 505 + pinctrl-names = "default"; 506 + pinctrl-0 = <&mdio1_pins_default>; 507 + 457 508 cpsw3g_phy0: ethernet-phy@0 { 458 509 reg = <0>; 459 510 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ··· 560 603 <&main_r5fss1_core1_memory_region>; 561 604 }; 562 605 563 - &pcie0_rc { 564 - status = "disabled"; 565 - }; 566 - 567 - &pcie0_ep { 568 - status = "disabled"; 569 - }; 570 - 571 606 &ecap0 { 607 + status = "okay"; 572 608 /* PWM is available on Pin 1 of header J3 */ 573 609 pinctrl-names = "default"; 574 610 pinctrl-0 = <&main_ecap0_pins_default>; 575 - }; 576 - 577 - &ecap1 { 578 - status = "disabled"; 579 - }; 580 - 581 - &ecap2 { 582 - status = "disabled"; 583 - }; 584 - 585 - &epwm0 { 586 - status = "disabled"; 587 - }; 588 - 589 - &epwm1 { 590 - status = "disabled"; 591 - }; 592 - 593 - &epwm2 { 594 - status = "disabled"; 595 - }; 596 - 597 - &epwm3 { 598 - status = "disabled"; 599 - }; 600 - 601 - &epwm4 { 602 - /* 603 - * EPWM4_A, EPWM4_B is available on Pin 32 and 33 on J4 (RPi hat) 604 - * But RPi Hat will be used for other use cases, so marking epwm4 as disabled. 605 - */ 606 - status = "disabled"; 607 - }; 608 - 609 - &epwm5 { 610 - /* 611 - * EPWM5_A, EPWM5_B is available on Pin 29 and 31 on J4 (RPi hat) 612 - * But RPi Hat will be used for other use cases, so marking epwm5 as disabled. 613 - */ 614 - status = "disabled"; 615 - }; 616 - 617 - &epwm6 { 618 - status = "disabled"; 619 - }; 620 - 621 - &epwm7 { 622 - status = "disabled"; 623 - }; 624 - 625 - &epwm8 { 626 - status = "disabled"; 627 - }; 628 - 629 - &icssg0_mdio { 630 - status = "disabled"; 631 - }; 632 - 633 - &icssg1_mdio { 634 - status = "disabled"; 635 - }; 636 - 637 - &main_mcan0 { 638 - status = "disabled"; 639 - }; 640 - 641 - &main_mcan1 { 642 - status = "disabled"; 643 - }; 644 - 645 - &gpmc0 { 646 - status = "disabled"; 647 - }; 648 - 649 - &elm0 { 650 - status = "disabled"; 651 611 };

+13 -88

arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi

··· 360 360 }; 361 361 362 362 &main_uart1 { 363 + status = "okay"; 363 364 pinctrl-names = "default"; 364 365 pinctrl-0 = <&main_uart1_pins_default>; 365 366 }; 366 367 367 - &main_uart2 { 368 - status = "disabled"; 369 - }; 370 - 371 368 &mcu_uart0 { 369 + status = "okay"; 372 370 pinctrl-names = "default"; 373 371 pinctrl-0 = <&arduino_uart_pins_default>; 374 372 }; ··· 411 413 }; 412 414 413 415 &wkup_i2c0 { 416 + status = "okay"; 414 417 pinctrl-names = "default"; 415 418 pinctrl-0 = <&wkup_i2c0_pins_default>; 416 419 clock-frequency = <400000>; 417 420 }; 418 421 419 422 &mcu_i2c0 { 423 + status = "okay"; 420 424 pinctrl-names = "default"; 421 425 pinctrl-0 = <&mcu_i2c0_pins_default>; 422 426 clock-frequency = <400000>; ··· 478 478 }; 479 479 480 480 &main_i2c0 { 481 + status = "okay"; 481 482 pinctrl-names = "default"; 482 483 pinctrl-0 = <&main_i2c0_pins_default>; 483 484 clock-frequency = <400000>; ··· 496 495 }; 497 496 498 497 &main_i2c1 { 498 + status = "okay"; 499 499 pinctrl-names = "default"; 500 500 pinctrl-0 = <&main_i2c1_pins_default>; 501 501 clock-frequency = <400000>; 502 502 }; 503 503 504 504 &main_i2c2 { 505 + status = "okay"; 505 506 pinctrl-names = "default"; 506 507 pinctrl-0 = <&main_i2c2_pins_default>; 507 508 clock-frequency = <400000>; 508 509 }; 509 510 510 511 &main_i2c3 { 512 + status = "okay"; 511 513 pinctrl-names = "default"; 512 514 pinctrl-0 = <&main_i2c3_pins_default>; 513 515 clock-frequency = <400000>; ··· 550 546 }; 551 547 552 548 &ecap0 { 549 + status = "okay"; 553 550 pinctrl-names = "default"; 554 551 pinctrl-0 = <&ecap0_pins_default>; 555 552 }; ··· 575 570 }; 576 571 577 572 &mcu_spi0 { 573 + status = "okay"; 578 574 pinctrl-names = "default"; 579 575 pinctrl-0 = <&mcu_spi0_pins_default>; 580 576 ··· 632 626 }; 633 627 }; 634 628 635 - &pcie0_rc { 636 - status = "disabled"; 637 - }; 638 - 639 - &pcie0_ep { 640 - status = "disabled"; 641 - }; 642 - 643 629 &pcie1_rc { 630 + status = "okay"; 644 631 pinctrl-names = "default"; 645 632 pinctrl-0 = <&minipcie_pins_default>; 646 633 ··· 643 644 reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; 644 645 }; 645 646 646 - &m_can0 { 647 - status = "disabled"; 648 - }; 649 - 650 - &m_can1 { 651 - status = "disabled"; 652 - }; 653 - 654 - &pcie1_ep { 655 - status = "disabled"; 656 - }; 657 - 658 647 &mailbox0_cluster0 { 648 + status = "okay"; 659 649 interrupts = <436>; 660 650 661 651 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { ··· 654 666 }; 655 667 656 668 &mailbox0_cluster1 { 669 + status = "okay"; 657 670 interrupts = <432>; 658 671 659 672 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 660 673 ti,mbox-tx = <1 0 0>; 661 674 ti,mbox-rx = <0 0 0>; 662 675 }; 663 - }; 664 - 665 - &mailbox0_cluster2 { 666 - status = "disabled"; 667 - }; 668 - 669 - &mailbox0_cluster3 { 670 - status = "disabled"; 671 - }; 672 - 673 - &mailbox0_cluster4 { 674 - status = "disabled"; 675 - }; 676 - 677 - &mailbox0_cluster5 { 678 - status = "disabled"; 679 - }; 680 - 681 - &mailbox0_cluster6 { 682 - status = "disabled"; 683 - }; 684 - 685 - &mailbox0_cluster7 { 686 - status = "disabled"; 687 - }; 688 - 689 - &mailbox0_cluster8 { 690 - status = "disabled"; 691 - }; 692 - 693 - &mailbox0_cluster9 { 694 - status = "disabled"; 695 - }; 696 - 697 - &mailbox0_cluster10 { 698 - status = "disabled"; 699 - }; 700 - 701 - &mailbox0_cluster11 { 702 - status = "disabled"; 703 676 }; 704 677 705 678 &mcu_r5fss0_core0 { ··· 673 724 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 674 725 <&mcu_r5fss0_core1_memory_region>; 675 726 mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; 676 - }; 677 - 678 - &icssg0_mdio { 679 - status = "disabled"; 680 - }; 681 - 682 - &icssg1_mdio { 683 - status = "disabled"; 684 - }; 685 - 686 - &icssg2_mdio { 687 - status = "disabled"; 688 - }; 689 - 690 - &mcasp0 { 691 - status = "disabled"; 692 - }; 693 - 694 - &mcasp1 { 695 - status = "disabled"; 696 - }; 697 - 698 - &mcasp2 { 699 - status = "disabled"; 700 727 };

+204 -3

arch/arm64/boot/dts/ti/k3-am65-main.dtsi

··· 91 91 clock-frequency = <48000000>; 92 92 current-speed = <115200>; 93 93 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 94 + status = "disabled"; 94 95 }; 95 96 96 97 main_uart1: serial@2810000 { ··· 100 99 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 101 100 clock-frequency = <48000000>; 102 101 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 102 + status = "disabled"; 103 103 }; 104 104 105 105 main_uart2: serial@2820000 { ··· 109 107 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 110 108 clock-frequency = <48000000>; 111 109 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 110 + status = "disabled"; 112 111 }; 113 112 114 113 crypto: crypto@4e00000 { ··· 123 120 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>, 124 121 <&main_udmap 0x4003>; 125 122 dma-names = "tx", "rx1", "rx2"; 126 - dma-coherent; 127 123 128 124 rng: rng@4e10000 { 129 125 compatible = "inside-secure,safexcel-eip76"; 130 126 reg = <0x0 0x4e10000 0x0 0x7d>; 131 127 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 132 - clocks = <&k3_clks 136 1>; 133 128 status = "disabled"; /* Used by OP-TEE */ 134 129 }; 130 + }; 131 + 132 + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 133 + main_timerio_input: pinctrl@104200 { 134 + compatible = "pinctrl-single"; 135 + reg = <0x0 0x104200 0x0 0x30>; 136 + #pinctrl-cells = <1>; 137 + pinctrl-single,register-width = <32>; 138 + pinctrl-single,function-mask = <0x0000001ff>; 139 + }; 140 + 141 + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 142 + main_timerio_output: pinctrl@104280 { 143 + compatible = "pinctrl-single"; 144 + reg = <0x0 0x104280 0x0 0x20>; 145 + #pinctrl-cells = <1>; 146 + pinctrl-single,register-width = <32>; 147 + pinctrl-single,function-mask = <0x0000000f>; 135 148 }; 136 149 137 150 main_pmx0: pinctrl@11c000 { ··· 175 156 clock-names = "fck"; 176 157 clocks = <&k3_clks 110 1>; 177 158 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 159 + status = "disabled"; 178 160 }; 179 161 180 162 main_i2c1: i2c@2010000 { ··· 187 167 clock-names = "fck"; 188 168 clocks = <&k3_clks 111 1>; 189 169 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 170 + status = "disabled"; 190 171 }; 191 172 192 173 main_i2c2: i2c@2020000 { ··· 199 178 clock-names = "fck"; 200 179 clocks = <&k3_clks 112 1>; 201 180 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 181 + status = "disabled"; 202 182 }; 203 183 204 184 main_i2c3: i2c@2030000 { ··· 211 189 clock-names = "fck"; 212 190 clocks = <&k3_clks 113 1>; 213 191 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 192 + status = "disabled"; 214 193 }; 215 194 216 195 ecap0: pwm@3100000 { ··· 221 198 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 222 199 clocks = <&k3_clks 39 0>; 223 200 clock-names = "fck"; 201 + status = "disabled"; 224 202 }; 225 203 226 204 main_spi0: spi@2100000 { ··· 234 210 #size-cells = <0>; 235 211 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 236 212 dma-names = "tx0", "rx0"; 213 + status = "disabled"; 237 214 }; 238 215 239 216 main_spi1: spi@2110000 { ··· 247 222 #size-cells = <0>; 248 223 assigned-clocks = <&k3_clks 137 1>; 249 224 assigned-clock-rates = <48000000>; 225 + status = "disabled"; 250 226 }; 251 227 252 228 main_spi2: spi@2120000 { ··· 258 232 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 259 233 #address-cells = <1>; 260 234 #size-cells = <0>; 235 + status = "disabled"; 261 236 }; 262 237 263 238 main_spi3: spi@2130000 { ··· 269 242 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 270 243 #address-cells = <1>; 271 244 #size-cells = <0>; 245 + status = "disabled"; 272 246 }; 273 247 274 248 main_spi4: spi@2140000 { ··· 280 252 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 281 253 #address-cells = <1>; 282 254 #size-cells = <0>; 255 + status = "disabled"; 256 + }; 257 + 258 + main_timer0: timer@2400000 { 259 + compatible = "ti,am654-timer"; 260 + reg = <0x00 0x2400000 0x00 0x400>; 261 + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 262 + clocks = <&k3_clks 23 0>; 263 + clock-names = "fck"; 264 + assigned-clocks = <&k3_clks 23 0>; 265 + assigned-clock-parents = <&k3_clks 23 1>; 266 + power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>; 267 + ti,timer-pwm; 268 + }; 269 + 270 + main_timer1: timer@2410000 { 271 + compatible = "ti,am654-timer"; 272 + reg = <0x00 0x2410000 0x00 0x400>; 273 + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 274 + clocks = <&k3_clks 24 0>; 275 + clock-names = "fck"; 276 + assigned-clocks = <&k3_clks 24 0>; 277 + assigned-clock-parents = <&k3_clks 24 1>; 278 + power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>; 279 + ti,timer-pwm; 280 + }; 281 + 282 + main_timer2: timer@2420000 { 283 + compatible = "ti,am654-timer"; 284 + reg = <0x00 0x2420000 0x00 0x400>; 285 + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 286 + clocks = <&k3_clks 27 0>; 287 + clock-names = "fck"; 288 + assigned-clocks = <&k3_clks 27 0>; 289 + assigned-clock-parents = <&k3_clks 27 1>; 290 + power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; 291 + ti,timer-pwm; 292 + }; 293 + 294 + main_timer3: timer@2430000 { 295 + compatible = "ti,am654-timer"; 296 + reg = <0x00 0x2430000 0x00 0x400>; 297 + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 298 + clocks = <&k3_clks 28 0>; 299 + clock-names = "fck"; 300 + assigned-clocks = <&k3_clks 28 0>; 301 + assigned-clock-parents = <&k3_clks 28 1>; 302 + power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; 303 + ti,timer-pwm; 304 + }; 305 + 306 + main_timer4: timer@2440000 { 307 + compatible = "ti,am654-timer"; 308 + reg = <0x00 0x2440000 0x00 0x400>; 309 + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 310 + clocks = <&k3_clks 29 0>; 311 + clock-names = "fck"; 312 + assigned-clocks = <&k3_clks 29 0>; 313 + assigned-clock-parents = <&k3_clks 29 1>; 314 + power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; 315 + ti,timer-pwm; 316 + }; 317 + 318 + main_timer5: timer@2450000 { 319 + compatible = "ti,am654-timer"; 320 + reg = <0x00 0x2450000 0x00 0x400>; 321 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 322 + clocks = <&k3_clks 30 0>; 323 + clock-names = "fck"; 324 + assigned-clocks = <&k3_clks 30 0>; 325 + assigned-clock-parents = <&k3_clks 30 1>; 326 + power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>; 327 + ti,timer-pwm; 328 + }; 329 + 330 + main_timer6: timer@2460000 { 331 + compatible = "ti,am654-timer"; 332 + reg = <0x00 0x2460000 0x00 0x400>; 333 + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 334 + clocks = <&k3_clks 31 0>; 335 + assigned-clocks = <&k3_clks 31 0>; 336 + assigned-clock-parents = <&k3_clks 31 1>; 337 + clock-names = "fck"; 338 + power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>; 339 + ti,timer-pwm; 340 + }; 341 + 342 + main_timer7: timer@2470000 { 343 + compatible = "ti,am654-timer"; 344 + reg = <0x00 0x2470000 0x00 0x400>; 345 + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 346 + clocks = <&k3_clks 32 0>; 347 + clock-names = "fck"; 348 + assigned-clocks = <&k3_clks 32 0>; 349 + assigned-clock-parents = <&k3_clks 32 1>; 350 + power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>; 351 + ti,timer-pwm; 352 + }; 353 + 354 + main_timer8: timer@2480000 { 355 + compatible = "ti,am654-timer"; 356 + reg = <0x00 0x2480000 0x00 0x400>; 357 + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 358 + clocks = <&k3_clks 33 0>; 359 + clock-names = "fck"; 360 + assigned-clocks = <&k3_clks 33 0>; 361 + assigned-clock-parents = <&k3_clks 33 1>; 362 + power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>; 363 + ti,timer-pwm; 364 + }; 365 + 366 + main_timer9: timer@2490000 { 367 + compatible = "ti,am654-timer"; 368 + reg = <0x00 0x2490000 0x00 0x400>; 369 + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 370 + clocks = <&k3_clks 34 0>; 371 + clock-names = "fck"; 372 + assigned-clocks = <&k3_clks 34 0>; 373 + assigned-clock-parents = <&k3_clks 34 1>; 374 + power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>; 375 + ti,timer-pwm; 376 + }; 377 + 378 + main_timer10: timer@24a0000 { 379 + compatible = "ti,am654-timer"; 380 + reg = <0x00 0x24a0000 0x00 0x400>; 381 + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 382 + clocks = <&k3_clks 25 0>; 383 + clock-names = "fck"; 384 + assigned-clocks = <&k3_clks 25 0>; 385 + assigned-clock-parents = <&k3_clks 25 1>; 386 + power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>; 387 + ti,timer-pwm; 388 + }; 389 + 390 + main_timer11: timer@24b0000 { 391 + compatible = "ti,am654-timer"; 392 + reg = <0x00 0x24b0000 0x00 0x400>; 393 + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 394 + clocks = <&k3_clks 26 0>; 395 + clock-names = "fck"; 396 + assigned-clocks = <&k3_clks 26 0>; 397 + assigned-clock-parents = <&k3_clks 26 1>; 398 + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; 399 + ti,timer-pwm; 283 400 }; 284 401 285 402 sdhci0: mmc@4f80000 { ··· 515 342 516 343 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { 517 344 compatible = "syscon"; 518 - reg = <0x0000041e0 0x14>; 345 + reg = <0x000041e0 0x14>; 519 346 }; 520 347 521 348 ehrpwm_tbclk: clock@4140 { ··· 674 501 ti,mbox-num-users = <4>; 675 502 ti,mbox-num-fifos = <16>; 676 503 interrupt-parent = <&intr_main_navss>; 504 + status = "disabled"; 677 505 }; 678 506 679 507 mailbox0_cluster1: mailbox@31f81000 { ··· 684 510 ti,mbox-num-users = <4>; 685 511 ti,mbox-num-fifos = <16>; 686 512 interrupt-parent = <&intr_main_navss>; 513 + status = "disabled"; 687 514 }; 688 515 689 516 mailbox0_cluster2: mailbox@31f82000 { ··· 694 519 ti,mbox-num-users = <4>; 695 520 ti,mbox-num-fifos = <16>; 696 521 interrupt-parent = <&intr_main_navss>; 522 + status = "disabled"; 697 523 }; 698 524 699 525 mailbox0_cluster3: mailbox@31f83000 { ··· 704 528 ti,mbox-num-users = <4>; 705 529 ti,mbox-num-fifos = <16>; 706 530 interrupt-parent = <&intr_main_navss>; 531 + status = "disabled"; 707 532 }; 708 533 709 534 mailbox0_cluster4: mailbox@31f84000 { ··· 714 537 ti,mbox-num-users = <4>; 715 538 ti,mbox-num-fifos = <16>; 716 539 interrupt-parent = <&intr_main_navss>; 540 + status = "disabled"; 717 541 }; 718 542 719 543 mailbox0_cluster5: mailbox@31f85000 { ··· 724 546 ti,mbox-num-users = <4>; 725 547 ti,mbox-num-fifos = <16>; 726 548 interrupt-parent = <&intr_main_navss>; 549 + status = "disabled"; 727 550 }; 728 551 729 552 mailbox0_cluster6: mailbox@31f86000 { ··· 734 555 ti,mbox-num-users = <4>; 735 556 ti,mbox-num-fifos = <16>; 736 557 interrupt-parent = <&intr_main_navss>; 558 + status = "disabled"; 737 559 }; 738 560 739 561 mailbox0_cluster7: mailbox@31f87000 { ··· 744 564 ti,mbox-num-users = <4>; 745 565 ti,mbox-num-fifos = <16>; 746 566 interrupt-parent = <&intr_main_navss>; 567 + status = "disabled"; 747 568 }; 748 569 749 570 mailbox0_cluster8: mailbox@31f88000 { ··· 754 573 ti,mbox-num-users = <4>; 755 574 ti,mbox-num-fifos = <16>; 756 575 interrupt-parent = <&intr_main_navss>; 576 + status = "disabled"; 757 577 }; 758 578 759 579 mailbox0_cluster9: mailbox@31f89000 { ··· 764 582 ti,mbox-num-users = <4>; 765 583 ti,mbox-num-fifos = <16>; 766 584 interrupt-parent = <&intr_main_navss>; 585 + status = "disabled"; 767 586 }; 768 587 769 588 mailbox0_cluster10: mailbox@31f8a000 { ··· 774 591 ti,mbox-num-users = <4>; 775 592 ti,mbox-num-fifos = <16>; 776 593 interrupt-parent = <&intr_main_navss>; 594 + status = "disabled"; 777 595 }; 778 596 779 597 mailbox0_cluster11: mailbox@31f8b000 { ··· 784 600 ti,mbox-num-users = <4>; 785 601 ti,mbox-num-fifos = <16>; 786 602 interrupt-parent = <&intr_main_navss>; 603 + status = "disabled"; 787 604 }; 788 605 789 606 ringacc: ringacc@3c000000 { ··· 892 707 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 893 708 msi-map = <0x0 &gic_its 0x0 0x10000>; 894 709 device_type = "pci"; 710 + status = "disabled"; 895 711 }; 896 712 897 713 pcie0_ep: pcie-ep@5500000 { ··· 906 720 max-link-speed = <2>; 907 721 dma-coherent; 908 722 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 723 + status = "disabled"; 909 724 }; 910 725 911 726 pcie1_rc: pcie@5600000 { ··· 927 740 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 928 741 msi-map = <0x0 &gic_its 0x10000 0x10000>; 929 742 device_type = "pci"; 743 + status = "disabled"; 930 744 }; 931 745 932 746 pcie1_ep: pcie-ep@5600000 { ··· 941 753 max-link-speed = <2>; 942 754 dma-coherent; 943 755 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 756 + status = "disabled"; 944 757 }; 945 758 946 759 mcasp0: mcasp@2b00000 { ··· 959 770 clocks = <&k3_clks 104 0>; 960 771 clock-names = "fck"; 961 772 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 773 + status = "disabled"; 962 774 }; 963 775 964 776 mcasp1: mcasp@2b10000 { ··· 977 787 clocks = <&k3_clks 105 0>; 978 788 clock-names = "fck"; 979 789 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 790 + status = "disabled"; 980 791 }; 981 792 982 793 mcasp2: mcasp@2b20000 { ··· 995 804 clocks = <&k3_clks 106 0>; 996 805 clock-names = "fck"; 997 806 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 807 + status = "disabled"; 998 808 }; 999 809 1000 810 cal: cal@6f03000 { ··· 1066 874 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 1067 875 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; 1068 876 clock-names = "tbclk", "fck"; 877 + status = "disabled"; 1069 878 }; 1070 879 1071 880 ehrpwm1: pwm@3010000 { ··· 1076 883 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 1077 884 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; 1078 885 clock-names = "tbclk", "fck"; 886 + status = "disabled"; 1079 887 }; 1080 888 1081 889 ehrpwm2: pwm@3020000 { ··· 1086 892 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 1087 893 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; 1088 894 clock-names = "tbclk", "fck"; 895 + status = "disabled"; 1089 896 }; 1090 897 1091 898 ehrpwm3: pwm@3030000 { ··· 1096 901 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 1097 902 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; 1098 903 clock-names = "tbclk", "fck"; 904 + status = "disabled"; 1099 905 }; 1100 906 1101 907 ehrpwm4: pwm@3040000 { ··· 1106 910 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 1107 911 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; 1108 912 clock-names = "tbclk", "fck"; 913 + status = "disabled"; 1109 914 }; 1110 915 1111 916 ehrpwm5: pwm@3050000 { ··· 1116 919 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 1117 920 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; 1118 921 clock-names = "tbclk", "fck"; 922 + status = "disabled"; 1119 923 }; 1120 924 1121 925 icssg0: icssg@b000000 { ··· 1257 1059 #address-cells = <1>; 1258 1060 #size-cells = <0>; 1259 1061 bus_freq = <1000000>; 1062 + status = "disabled"; 1260 1063 }; 1261 1064 }; 1262 1065 ··· 1399 1200 #address-cells = <1>; 1400 1201 #size-cells = <0>; 1401 1202 bus_freq = <1000000>; 1203 + status = "disabled"; 1402 1204 }; 1403 1205 }; 1404 1206 ··· 1541 1341 #address-cells = <1>; 1542 1342 #size-cells = <0>; 1543 1343 bus_freq = <1000000>; 1344 + status = "disabled"; 1544 1345 }; 1545 1346 }; 1546 1347 };

+78 -7

arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi

··· 20 20 }; 21 21 }; 22 22 23 + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 24 + mcu_timerio_input: pinctrl@40f04200 { 25 + compatible = "pinctrl-single"; 26 + reg = <0x0 0x40f04200 0x0 0x10>; 27 + #pinctrl-cells = <1>; 28 + pinctrl-single,register-width = <32>; 29 + pinctrl-single,function-mask = <0x00000101>; 30 + }; 31 + 32 + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 33 + mcu_timerio_output: pinctrl@40f04280 { 34 + compatible = "pinctrl-single"; 35 + reg = <0x0 0x40f04280 0x0 0x8>; 36 + #pinctrl-cells = <1>; 37 + pinctrl-single,register-width = <32>; 38 + pinctrl-single,function-mask = <0x00000003>; 39 + }; 40 + 23 41 mcu_uart0: serial@40a00000 { 24 42 compatible = "ti,am654-uart"; 25 - reg = <0x00 0x40a00000 0x00 0x100>; 26 - interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 27 - clock-frequency = <96000000>; 28 - current-speed = <115200>; 29 - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 43 + reg = <0x00 0x40a00000 0x00 0x100>; 44 + interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 45 + clock-frequency = <96000000>; 46 + current-speed = <115200>; 47 + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 48 + status = "disabled"; 30 49 }; 31 50 32 51 mcu_ram: sram@41c00000 { ··· 65 46 clock-names = "fck"; 66 47 clocks = <&k3_clks 114 1>; 67 48 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 49 + status = "disabled"; 68 50 }; 69 51 70 52 mcu_spi0: spi@40300000 { ··· 76 56 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 77 57 #address-cells = <1>; 78 58 #size-cells = <0>; 59 + status = "disabled"; 79 60 }; 80 61 81 62 mcu_spi1: spi@40310000 { ··· 87 66 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 88 67 #address-cells = <1>; 89 68 #size-cells = <0>; 69 + status = "disabled"; 90 70 }; 91 71 92 72 mcu_spi2: spi@40320000 { ··· 98 76 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 99 77 #address-cells = <1>; 100 78 #size-cells = <0>; 79 + status = "disabled"; 101 80 }; 102 81 103 82 tscadc0: tscadc@40200000 { ··· 108 85 clocks = <&k3_clks 0 2>; 109 86 assigned-clocks = <&k3_clks 0 2>; 110 87 assigned-clock-rates = <60000000>; 111 - clock-names = "adc_tsc_fck"; 88 + clock-names = "fck"; 112 89 dmas = <&mcu_udmap 0x7100>, 113 90 <&mcu_udmap 0x7101 >; 114 91 dma-names = "fifo0", "fifo1"; ··· 126 103 clocks = <&k3_clks 1 2>; 127 104 assigned-clocks = <&k3_clks 1 2>; 128 105 assigned-clock-rates = <60000000>; 129 - clock-names = "adc_tsc_fck"; 106 + clock-names = "fck"; 130 107 dmas = <&mcu_udmap 0x7102>, 131 108 <&mcu_udmap 0x7103>; 132 109 dma-names = "fifo0", "fifo1"; ··· 135 112 #io-channel-cells = <1>; 136 113 compatible = "ti,am654-adc", "ti,am3359-adc"; 137 114 }; 115 + }; 116 + 117 + /* 118 + * The MCU domain timer interrupts are routed only to the ESM module, 119 + * and not currently available for Linux. The MCU domain timers are 120 + * of limited use without interrupts, and likely reserved by the ESM. 121 + */ 122 + mcu_timer0: timer@40400000 { 123 + compatible = "ti,am654-timer"; 124 + reg = <0x00 0x40400000 0x00 0x400>; 125 + clocks = <&k3_clks 35 0>; 126 + clock-names = "fck"; 127 + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 128 + ti,timer-pwm; 129 + status = "reserved"; 130 + }; 131 + 132 + mcu_timer1: timer@40410000 { 133 + compatible = "ti,am654-timer"; 134 + reg = <0x00 0x40410000 0x00 0x400>; 135 + clocks = <&k3_clks 36 0>; 136 + clock-names = "fck"; 137 + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 138 + ti,timer-pwm; 139 + status = "reserved"; 140 + }; 141 + 142 + mcu_timer2: timer@40420000 { 143 + compatible = "ti,am654-timer"; 144 + reg = <0x00 0x40420000 0x00 0x400>; 145 + clocks = <&k3_clks 37 0>; 146 + clock-names = "fck"; 147 + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 148 + ti,timer-pwm; 149 + status = "reserved"; 150 + }; 151 + 152 + mcu_timer3: timer@40430000 { 153 + compatible = "ti,am654-timer"; 154 + reg = <0x00 0x40430000 0x00 0x400>; 155 + clocks = <&k3_clks 38 0>; 156 + clock-names = "fck"; 157 + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 158 + ti,timer-pwm; 159 + status = "reserved"; 138 160 }; 139 161 140 162 mcu_navss: bus@28380000 { ··· 240 172 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 241 173 interrupt-names = "int0", "int1"; 242 174 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 175 + status = "disabled"; 243 176 }; 244 177 245 178 m_can1: mcan@40568000 { ··· 256 187 <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 257 188 interrupt-names = "int0", "int1"; 258 189 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 190 + status = "disabled"; 259 191 }; 260 192 261 193 fss: fss@47000000 { ··· 343 273 clocks = <&k3_clks 5 10>; 344 274 clock-names = "fck"; 345 275 bus_freq = <1000000>; 276 + status = "disabled"; 346 277 }; 347 278 348 279 cpts@3d000 {

+2

arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi

··· 54 54 clock-frequency = <48000000>; 55 55 current-speed = <115200>; 56 56 power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; 57 + status = "disabled"; 57 58 }; 58 59 59 60 wkup_i2c0: i2c@42120000 { ··· 66 65 clock-names = "fck"; 67 66 clocks = <&k3_clks 115 1>; 68 67 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 68 + status = "disabled"; 69 69 }; 70 70 71 71 intr_wkup_gpio: interrupt-controller@42200000 {

+1

arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi

··· 50 50 }; 51 51 52 52 &main_uart0 { 53 + status = "okay"; 53 54 pinctrl-names = "default"; 54 55 pinctrl-0 = <&main_uart0_pins_default>; 55 56 };

+24 -89

arch/arm64/boot/dts/ti/k3-am654-base-board.dts

··· 271 271 status = "reserved"; 272 272 }; 273 273 274 + &mcu_uart0 { 275 + status = "okay"; 276 + /* Default pinmux */ 277 + }; 278 + 274 279 &main_uart0 { 280 + status = "okay"; 275 281 pinctrl-names = "default"; 276 282 pinctrl-0 = <&main_uart0_pins_default>; 277 283 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 278 284 }; 279 285 280 286 &wkup_i2c0 { 287 + status = "okay"; 281 288 pinctrl-names = "default"; 282 289 pinctrl-0 = <&wkup_i2c0_pins_default>; 283 290 clock-frequency = <400000>; ··· 303 296 }; 304 297 }; 305 298 299 + &mcu_i2c0 { 300 + status = "okay"; 301 + /* Default pinmux */ 302 + }; 303 + 306 304 &main_i2c0 { 305 + status = "okay"; 307 306 pinctrl-names = "default"; 308 307 pinctrl-0 = <&main_i2c0_pins_default>; 309 308 clock-frequency = <400000>; ··· 323 310 }; 324 311 325 312 &main_i2c1 { 313 + status = "okay"; 326 314 pinctrl-names = "default"; 327 315 pinctrl-0 = <&main_i2c1_pins_default>; 328 316 clock-frequency = <400000>; 329 317 }; 330 318 331 319 &main_i2c2 { 320 + status = "okay"; 332 321 pinctrl-names = "default"; 333 322 pinctrl-0 = <&main_i2c2_pins_default>; 334 323 clock-frequency = <400000>; 335 324 }; 336 325 337 326 &ecap0 { 327 + status = "okay"; 338 328 pinctrl-names = "default"; 339 329 pinctrl-0 = <&ecap0_pins_default>; 340 330 }; 341 331 342 332 &main_spi0 { 333 + status = "okay"; 343 334 pinctrl-names = "default"; 344 335 pinctrl-0 = <&main_spi0_pins_default>; 345 336 #address-cells = <1>; ··· 415 398 status = "disabled"; 416 399 }; 417 400 418 - &pcie0_rc { 419 - status = "disabled"; 420 - }; 421 - 422 - &pcie0_ep { 423 - status = "disabled"; 424 - }; 425 - 426 - &pcie1_rc { 427 - status = "disabled"; 428 - }; 429 - 430 - &pcie1_ep { 431 - status = "disabled"; 432 - }; 433 - 434 - &m_can0 { 435 - status = "disabled"; 436 - }; 437 - 438 - &m_can1 { 439 - status = "disabled"; 440 - }; 441 - 442 401 &mailbox0_cluster0 { 402 + status = "okay"; 443 403 interrupts = <436>; 444 404 445 405 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { ··· 426 432 }; 427 433 428 434 &mailbox0_cluster1 { 435 + status = "okay"; 429 436 interrupts = <432>; 430 437 431 438 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 432 439 ti,mbox-tx = <1 0 0>; 433 440 ti,mbox-rx = <0 0 0>; 434 441 }; 435 - }; 436 - 437 - &mailbox0_cluster2 { 438 - status = "disabled"; 439 - }; 440 - 441 - &mailbox0_cluster3 { 442 - status = "disabled"; 443 - }; 444 - 445 - &mailbox0_cluster4 { 446 - status = "disabled"; 447 - }; 448 - 449 - &mailbox0_cluster5 { 450 - status = "disabled"; 451 - }; 452 - 453 - &mailbox0_cluster6 { 454 - status = "disabled"; 455 - }; 456 - 457 - &mailbox0_cluster7 { 458 - status = "disabled"; 459 - }; 460 - 461 - &mailbox0_cluster8 { 462 - status = "disabled"; 463 - }; 464 - 465 - &mailbox0_cluster9 { 466 - status = "disabled"; 467 - }; 468 - 469 - &mailbox0_cluster10 { 470 - status = "disabled"; 471 - }; 472 - 473 - &mailbox0_cluster11 { 474 - status = "disabled"; 475 442 }; 476 443 477 444 &mcu_r5fss0_core0 { ··· 467 512 468 513 &mcu_cpsw { 469 514 pinctrl-names = "default"; 470 - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 515 + pinctrl-0 = <&mcu_cpsw_pins_default>; 471 516 }; 472 517 473 518 &davinci_mdio { 519 + status = "okay"; 520 + pinctrl-names = "default"; 521 + pinctrl-0 = <&mcu_mdio_pins_default>; 522 + 474 523 phy0: ethernet-phy@0 { 475 524 reg = <0>; 476 525 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ··· 487 528 phy-handle = <&phy0>; 488 529 }; 489 530 490 - &mcasp0 { 491 - status = "disabled"; 492 - }; 493 - 494 - &mcasp1 { 495 - status = "disabled"; 496 - }; 497 - 498 - &mcasp2 { 499 - status = "disabled"; 500 - }; 501 - 502 531 &dss { 503 - status = "disabled"; 504 - }; 505 - 506 - &icssg0_mdio { 507 - status = "disabled"; 508 - }; 509 - 510 - &icssg1_mdio { 511 - status = "disabled"; 512 - }; 513 - 514 - &icssg2_mdio { 515 532 status = "disabled"; 516 533 };

-4

arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi

··· 50 50 ti,driver-strength-ohm = <50>; 51 51 disable-wp; 52 52 }; 53 - 54 - &main_uart0 { 55 - status = "disabled"; 56 - };

+13 -35

arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts

··· 154 154 status = "reserved"; 155 155 }; 156 156 157 + &mcu_uart0 { 158 + status = "okay"; 159 + /* Default pinmux */ 160 + }; 161 + 157 162 &main_uart0 { 163 + status = "okay"; 158 164 /* Shared with ATF on this platform */ 159 165 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 166 + }; 167 + 168 + &main_uart1 { 169 + status = "okay"; 170 + /* Default pinmux */ 160 171 }; 161 172 162 173 &main_uart2 { 163 174 /* MAIN UART 2 is used by R5F firmware */ 164 175 status = "reserved"; 165 - }; 166 - 167 - &main_uart3 { 168 - /* UART not brought out */ 169 - status = "disabled"; 170 - }; 171 - 172 - &main_uart4 { 173 - /* UART not brought out */ 174 - status = "disabled"; 175 - }; 176 - 177 - &main_uart5 { 178 - /* UART not brought out */ 179 - status = "disabled"; 180 - }; 181 - 182 - &main_uart6 { 183 - /* UART not brought out */ 184 - status = "disabled"; 185 - }; 186 - 187 - &main_uart7 { 188 - /* UART not brought out */ 189 - status = "disabled"; 190 - }; 191 - 192 - &main_uart8 { 193 - /* UART not brought out */ 194 - status = "disabled"; 195 - }; 196 - 197 - &main_uart9 { 198 - /* UART not brought out */ 199 - status = "disabled"; 200 176 }; 201 177 202 178 &main_gpio2 { ··· 210 234 }; 211 235 212 236 &main_i2c0 { 237 + status = "okay"; 213 238 pinctrl-names = "default"; 214 239 pinctrl-0 = <&main_i2c0_pins_default>; 215 240 clock-frequency = <400000>; ··· 238 261 * The i2c1 of the CPB (as it is labeled) is not connected to j7200. 239 262 */ 240 263 &main_i2c1 { 264 + status = "okay"; 241 265 pinctrl-names = "default"; 242 266 pinctrl-0 = <&main_i2c1_pins_default>; 243 267 clock-frequency = <400000>;

+29

arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

··· 142 142 ti,mbox-num-users = <4>; 143 143 ti,mbox-num-fifos = <16>; 144 144 interrupt-parent = <&main_navss_intr>; 145 + status = "disabled"; 145 146 }; 146 147 147 148 mailbox0_cluster1: mailbox@31f81000 { ··· 152 151 ti,mbox-num-users = <4>; 153 152 ti,mbox-num-fifos = <16>; 154 153 interrupt-parent = <&main_navss_intr>; 154 + status = "disabled"; 155 155 }; 156 156 157 157 mailbox0_cluster2: mailbox@31f82000 { ··· 162 160 ti,mbox-num-users = <4>; 163 161 ti,mbox-num-fifos = <16>; 164 162 interrupt-parent = <&main_navss_intr>; 163 + status = "disabled"; 165 164 }; 166 165 167 166 mailbox0_cluster3: mailbox@31f83000 { ··· 172 169 ti,mbox-num-users = <4>; 173 170 ti,mbox-num-fifos = <16>; 174 171 interrupt-parent = <&main_navss_intr>; 172 + status = "disabled"; 175 173 }; 176 174 177 175 mailbox0_cluster4: mailbox@31f84000 { ··· 182 178 ti,mbox-num-users = <4>; 183 179 ti,mbox-num-fifos = <16>; 184 180 interrupt-parent = <&main_navss_intr>; 181 + status = "disabled"; 185 182 }; 186 183 187 184 mailbox0_cluster5: mailbox@31f85000 { ··· 192 187 ti,mbox-num-users = <4>; 193 188 ti,mbox-num-fifos = <16>; 194 189 interrupt-parent = <&main_navss_intr>; 190 + status = "disabled"; 195 191 }; 196 192 197 193 mailbox0_cluster6: mailbox@31f86000 { ··· 202 196 ti,mbox-num-users = <4>; 203 197 ti,mbox-num-fifos = <16>; 204 198 interrupt-parent = <&main_navss_intr>; 199 + status = "disabled"; 205 200 }; 206 201 207 202 mailbox0_cluster7: mailbox@31f87000 { ··· 212 205 ti,mbox-num-users = <4>; 213 206 ti,mbox-num-fifos = <16>; 214 207 interrupt-parent = <&main_navss_intr>; 208 + status = "disabled"; 215 209 }; 216 210 217 211 mailbox0_cluster8: mailbox@31f88000 { ··· 222 214 ti,mbox-num-users = <4>; 223 215 ti,mbox-num-fifos = <16>; 224 216 interrupt-parent = <&main_navss_intr>; 217 + status = "disabled"; 225 218 }; 226 219 227 220 mailbox0_cluster9: mailbox@31f89000 { ··· 232 223 ti,mbox-num-users = <4>; 233 224 ti,mbox-num-fifos = <16>; 234 225 interrupt-parent = <&main_navss_intr>; 226 + status = "disabled"; 235 227 }; 236 228 237 229 mailbox0_cluster10: mailbox@31f8a000 { ··· 242 232 ti,mbox-num-users = <4>; 243 233 ti,mbox-num-fifos = <16>; 244 234 interrupt-parent = <&main_navss_intr>; 235 + status = "disabled"; 245 236 }; 246 237 247 238 mailbox0_cluster11: mailbox@31f8b000 { ··· 252 241 ti,mbox-num-users = <4>; 253 242 ti,mbox-num-fifos = <16>; 254 243 interrupt-parent = <&main_navss_intr>; 244 + status = "disabled"; 255 245 }; 256 246 257 247 main_ringacc: ringacc@3c000000 { ··· 331 319 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 332 320 clocks = <&k3_clks 146 2>; 333 321 clock-names = "fclk"; 322 + status = "disabled"; 334 323 }; 335 324 336 325 main_uart1: serial@2810000 { ··· 343 330 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 344 331 clocks = <&k3_clks 278 2>; 345 332 clock-names = "fclk"; 333 + status = "disabled"; 346 334 }; 347 335 348 336 main_uart2: serial@2820000 { ··· 355 341 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 356 342 clocks = <&k3_clks 279 2>; 357 343 clock-names = "fclk"; 344 + status = "disabled"; 358 345 }; 359 346 360 347 main_uart3: serial@2830000 { ··· 367 352 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 368 353 clocks = <&k3_clks 280 2>; 369 354 clock-names = "fclk"; 355 + status = "disabled"; 370 356 }; 371 357 372 358 main_uart4: serial@2840000 { ··· 379 363 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 380 364 clocks = <&k3_clks 281 2>; 381 365 clock-names = "fclk"; 366 + status = "disabled"; 382 367 }; 383 368 384 369 main_uart5: serial@2850000 { ··· 391 374 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 392 375 clocks = <&k3_clks 282 2>; 393 376 clock-names = "fclk"; 377 + status = "disabled"; 394 378 }; 395 379 396 380 main_uart6: serial@2860000 { ··· 403 385 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 404 386 clocks = <&k3_clks 283 2>; 405 387 clock-names = "fclk"; 388 + status = "disabled"; 406 389 }; 407 390 408 391 main_uart7: serial@2870000 { ··· 415 396 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 416 397 clocks = <&k3_clks 284 2>; 417 398 clock-names = "fclk"; 399 + status = "disabled"; 418 400 }; 419 401 420 402 main_uart8: serial@2880000 { ··· 427 407 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 428 408 clocks = <&k3_clks 285 2>; 429 409 clock-names = "fclk"; 410 + status = "disabled"; 430 411 }; 431 412 432 413 main_uart9: serial@2890000 { ··· 439 418 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 440 419 clocks = <&k3_clks 286 2>; 441 420 clock-names = "fclk"; 421 + status = "disabled"; 442 422 }; 443 423 444 424 main_i2c0: i2c@2000000 { ··· 451 429 clock-names = "fck"; 452 430 clocks = <&k3_clks 187 1>; 453 431 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 432 + status = "disabled"; 454 433 }; 455 434 456 435 main_i2c1: i2c@2010000 { ··· 463 440 clock-names = "fck"; 464 441 clocks = <&k3_clks 188 1>; 465 442 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 443 + status = "disabled"; 466 444 }; 467 445 468 446 main_i2c2: i2c@2020000 { ··· 475 451 clock-names = "fck"; 476 452 clocks = <&k3_clks 189 1>; 477 453 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 454 + status = "disabled"; 478 455 }; 479 456 480 457 main_i2c3: i2c@2030000 { ··· 487 462 clock-names = "fck"; 488 463 clocks = <&k3_clks 190 1>; 489 464 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 465 + status = "disabled"; 490 466 }; 491 467 492 468 main_i2c4: i2c@2040000 { ··· 499 473 clock-names = "fck"; 500 474 clocks = <&k3_clks 191 1>; 501 475 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 476 + status = "disabled"; 502 477 }; 503 478 504 479 main_i2c5: i2c@2050000 { ··· 511 484 clock-names = "fck"; 512 485 clocks = <&k3_clks 192 1>; 513 486 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 487 + status = "disabled"; 514 488 }; 515 489 516 490 main_i2c6: i2c@2060000 { ··· 523 495 clock-names = "fck"; 524 496 clocks = <&k3_clks 193 1>; 525 497 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 498 + status = "disabled"; 526 499 }; 527 500 528 501 main_sdhci0: mmc@4f80000 {

+6 -2

arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi

··· 79 79 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 80 80 clocks = <&k3_clks 287 2>; 81 81 clock-names = "fclk"; 82 + status = "disabled"; 82 83 }; 83 84 84 85 mcu_uart0: serial@40a00000 { ··· 91 90 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 92 91 clocks = <&k3_clks 149 2>; 93 92 clock-names = "fclk"; 93 + status = "disabled"; 94 94 }; 95 95 96 96 wkup_gpio_intr: interrupt-controller@42200000 { ··· 251 249 clock-names = "fck"; 252 250 clocks = <&k3_clks 194 1>; 253 251 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 252 + status = "disabled"; 254 253 }; 255 254 256 255 mcu_i2c1: i2c@40b10000 { ··· 263 260 clock-names = "fck"; 264 261 clocks = <&k3_clks 195 1>; 265 262 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 263 + status = "disabled"; 266 264 }; 267 265 268 266 wkup_i2c0: i2c@42120000 { ··· 275 271 clock-names = "fck"; 276 272 clocks = <&k3_clks 197 1>; 277 273 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 274 + status = "disabled"; 278 275 }; 279 276 280 277 fss: syscon@47000000 { ··· 330 325 clocks = <&k3_clks 0 1>; 331 326 assigned-clocks = <&k3_clks 0 3>; 332 327 assigned-clock-rates = <60000000>; 333 - clock-names = "adc_tsc_fck"; 328 + clock-names = "fck"; 334 329 dmas = <&main_udmap 0x7400>, 335 330 <&main_udmap 0x7401>; 336 331 dma-names = "fifo0", "fifo1"; ··· 391 386 dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, 392 387 <&mcu_udmap 0x7503>; 393 388 dma-names = "tx", "rx1", "rx2"; 394 - dma-coherent; 395 389 396 390 rng: rng@40910000 { 397 391 compatible = "inside-secure,safexcel-eip76";

+2 -40

arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi

··· 144 144 }; 145 145 146 146 &mailbox0_cluster0 { 147 + status = "okay"; 147 148 interrupts = <436>; 148 149 149 150 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { ··· 159 158 }; 160 159 161 160 &mailbox0_cluster1 { 161 + status = "okay"; 162 162 interrupts = <432>; 163 163 164 164 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { ··· 171 169 ti,mbox-rx = <2 0 0>; 172 170 ti,mbox-tx = <3 0 0>; 173 171 }; 174 - }; 175 - 176 - &mailbox0_cluster2 { 177 - status = "disabled"; 178 - }; 179 - 180 - &mailbox0_cluster3 { 181 - status = "disabled"; 182 - }; 183 - 184 - &mailbox0_cluster4 { 185 - status = "disabled"; 186 - }; 187 - 188 - &mailbox0_cluster5 { 189 - status = "disabled"; 190 - }; 191 - 192 - &mailbox0_cluster6 { 193 - status = "disabled"; 194 - }; 195 - 196 - &mailbox0_cluster7 { 197 - status = "disabled"; 198 - }; 199 - 200 - &mailbox0_cluster8 { 201 - status = "disabled"; 202 - }; 203 - 204 - &mailbox0_cluster9 { 205 - status = "disabled"; 206 - }; 207 - 208 - &mailbox0_cluster10 { 209 - status = "disabled"; 210 - }; 211 - 212 - &mailbox0_cluster11 { 213 - status = "disabled"; 214 172 }; 215 173 216 174 &mcu_r5fss0_core0 {

+1055

arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * https://beagleboard.org/ai-64 4 + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 5 + * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation 6 + * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation 7 + */ 8 + 9 + /dts-v1/; 10 + 11 + #include "k3-j721e.dtsi" 12 + #include <dt-bindings/gpio/gpio.h> 13 + #include <dt-bindings/input/input.h> 14 + #include <dt-bindings/leds/common.h> 15 + #include <dt-bindings/net/ti-dp83867.h> 16 + #include <dt-bindings/phy/phy-cadence.h> 17 + 18 + / { 19 + compatible = "beagle,j721e-beagleboneai64", "ti,j721e"; 20 + model = "BeagleBoard.org BeagleBone AI-64"; 21 + 22 + aliases { 23 + serial2 = &main_uart0; 24 + mmc0 = &main_sdhci0; 25 + mmc1 = &main_sdhci1; 26 + i2c0 = &wkup_i2c0; 27 + i2c1 = &main_i2c6; 28 + i2c2 = &main_i2c2; 29 + i2c3 = &main_i2c4; 30 + }; 31 + 32 + chosen { 33 + stdout-path = "serial2:115200n8"; 34 + }; 35 + 36 + memory@80000000 { 37 + device_type = "memory"; 38 + /* 4G RAM */ 39 + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 40 + <0x00000008 0x80000000 0x00000000 0x80000000>; 41 + }; 42 + 43 + reserved_memory: reserved-memory { 44 + #address-cells = <2>; 45 + #size-cells = <2>; 46 + ranges; 47 + 48 + secure_ddr: optee@9e800000 { 49 + reg = <0x00 0x9e800000 0x00 0x01800000>; 50 + no-map; 51 + }; 52 + 53 + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 54 + compatible = "shared-dma-pool"; 55 + reg = <0x00 0xa0000000 0x00 0x100000>; 56 + no-map; 57 + }; 58 + 59 + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 60 + compatible = "shared-dma-pool"; 61 + reg = <0x00 0xa0100000 0x00 0xf00000>; 62 + no-map; 63 + }; 64 + 65 + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 66 + compatible = "shared-dma-pool"; 67 + reg = <0x00 0xa1000000 0x00 0x100000>; 68 + no-map; 69 + }; 70 + 71 + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 72 + compatible = "shared-dma-pool"; 73 + reg = <0x00 0xa1100000 0x00 0xf00000>; 74 + no-map; 75 + }; 76 + 77 + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 78 + compatible = "shared-dma-pool"; 79 + reg = <0x00 0xa2000000 0x00 0x100000>; 80 + no-map; 81 + }; 82 + 83 + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 84 + compatible = "shared-dma-pool"; 85 + reg = <0x00 0xa2100000 0x00 0xf00000>; 86 + no-map; 87 + }; 88 + 89 + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 90 + compatible = "shared-dma-pool"; 91 + reg = <0x00 0xa3000000 0x00 0x100000>; 92 + no-map; 93 + }; 94 + 95 + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 96 + compatible = "shared-dma-pool"; 97 + reg = <0x00 0xa3100000 0x00 0xf00000>; 98 + no-map; 99 + }; 100 + 101 + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 102 + compatible = "shared-dma-pool"; 103 + reg = <0x00 0xa4000000 0x00 0x100000>; 104 + no-map; 105 + }; 106 + 107 + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 108 + compatible = "shared-dma-pool"; 109 + reg = <0x00 0xa4100000 0x00 0xf00000>; 110 + no-map; 111 + }; 112 + 113 + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 114 + compatible = "shared-dma-pool"; 115 + reg = <0x00 0xa5000000 0x00 0x100000>; 116 + no-map; 117 + }; 118 + 119 + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 120 + compatible = "shared-dma-pool"; 121 + reg = <0x00 0xa5100000 0x00 0xf00000>; 122 + no-map; 123 + }; 124 + 125 + c66_1_dma_memory_region: c66-dma-memory@a6000000 { 126 + compatible = "shared-dma-pool"; 127 + reg = <0x00 0xa6000000 0x00 0x100000>; 128 + no-map; 129 + }; 130 + 131 + c66_0_memory_region: c66-memory@a6100000 { 132 + compatible = "shared-dma-pool"; 133 + reg = <0x00 0xa6100000 0x00 0xf00000>; 134 + no-map; 135 + }; 136 + 137 + c66_0_dma_memory_region: c66-dma-memory@a7000000 { 138 + compatible = "shared-dma-pool"; 139 + reg = <0x00 0xa7000000 0x00 0x100000>; 140 + no-map; 141 + }; 142 + 143 + c66_1_memory_region: c66-memory@a7100000 { 144 + compatible = "shared-dma-pool"; 145 + reg = <0x00 0xa7100000 0x00 0xf00000>; 146 + no-map; 147 + }; 148 + 149 + c71_0_dma_memory_region: c71-dma-memory@a8000000 { 150 + compatible = "shared-dma-pool"; 151 + reg = <0x00 0xa8000000 0x00 0x100000>; 152 + no-map; 153 + }; 154 + 155 + c71_0_memory_region: c71-memory@a8100000 { 156 + compatible = "shared-dma-pool"; 157 + reg = <0x00 0xa8100000 0x00 0xf00000>; 158 + no-map; 159 + }; 160 + 161 + rtos_ipc_memory_region: ipc-memories@aa000000 { 162 + reg = <0x00 0xaa000000 0x00 0x01c00000>; 163 + alignment = <0x1000>; 164 + no-map; 165 + }; 166 + }; 167 + 168 + gpio_keys: gpio-keys { 169 + compatible = "gpio-keys"; 170 + pinctrl-names = "default"; 171 + pinctrl-0 = <&sw_pwr_pins_default>; 172 + 173 + button-1 { 174 + label = "BOOT"; 175 + linux,code = <BTN_0>; 176 + gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>; 177 + }; 178 + 179 + button-2 { 180 + label = "POWER"; 181 + linux,code = <KEY_POWER>; 182 + gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>; 183 + }; 184 + }; 185 + 186 + leds { 187 + compatible = "gpio-leds"; 188 + pinctrl-names = "default"; 189 + pinctrl-0 = <&led_pins_default>; 190 + 191 + led-0 { 192 + gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>; 193 + function = LED_FUNCTION_HEARTBEAT; 194 + linux,default-trigger = "heartbeat"; 195 + }; 196 + 197 + led-1 { 198 + gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>; 199 + function = LED_FUNCTION_DISK_ACTIVITY; 200 + linux,default-trigger = "mmc0"; 201 + }; 202 + 203 + led-2 { 204 + gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>; 205 + function = LED_FUNCTION_CPU; 206 + linux,default-trigger = "cpu"; 207 + }; 208 + 209 + led-3 { 210 + gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>; 211 + function = LED_FUNCTION_DISK_ACTIVITY; 212 + linux,default-trigger = "mmc1"; 213 + }; 214 + 215 + led-4 { 216 + gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>; 217 + function = LED_FUNCTION_WLAN; 218 + default-state = "off"; 219 + }; 220 + }; 221 + 222 + evm_12v0: regulator-0 { 223 + /* main supply */ 224 + compatible = "regulator-fixed"; 225 + regulator-name = "evm_12v0"; 226 + regulator-min-microvolt = <12000000>; 227 + regulator-max-microvolt = <12000000>; 228 + regulator-always-on; 229 + regulator-boot-on; 230 + }; 231 + 232 + vsys_3v3: regulator-1 { 233 + /* Output of LMS140 */ 234 + compatible = "regulator-fixed"; 235 + regulator-name = "vsys_3v3"; 236 + regulator-min-microvolt = <3300000>; 237 + regulator-max-microvolt = <3300000>; 238 + vin-supply = <&evm_12v0>; 239 + regulator-always-on; 240 + regulator-boot-on; 241 + }; 242 + 243 + vsys_5v0: regulator-2 { 244 + /* Output of LM5140 */ 245 + compatible = "regulator-fixed"; 246 + regulator-name = "vsys_5v0"; 247 + regulator-min-microvolt = <5000000>; 248 + regulator-max-microvolt = <5000000>; 249 + vin-supply = <&evm_12v0>; 250 + regulator-always-on; 251 + regulator-boot-on; 252 + }; 253 + 254 + vdd_mmc1: regulator-3 { 255 + compatible = "regulator-fixed"; 256 + pinctrl-names = "default"; 257 + pinctrl-0 = <&sd_pwr_en_pins_default>; 258 + regulator-name = "vdd_mmc1"; 259 + regulator-min-microvolt = <3300000>; 260 + regulator-max-microvolt = <3300000>; 261 + regulator-boot-on; 262 + enable-active-high; 263 + vin-supply = <&vsys_3v3>; 264 + gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>; 265 + }; 266 + 267 + vdd_sd_dv_alt: regulator-4 { 268 + compatible = "regulator-gpio"; 269 + pinctrl-names = "default"; 270 + pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 271 + regulator-name = "tlv71033"; 272 + regulator-min-microvolt = <1800000>; 273 + regulator-max-microvolt = <3300000>; 274 + regulator-boot-on; 275 + vin-supply = <&vsys_5v0>; 276 + gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; 277 + states = <1800000 0x0>, 278 + <3300000 0x1>; 279 + }; 280 + 281 + dp_pwr_3v3: regulator-5 { 282 + compatible = "regulator-fixed"; 283 + pinctrl-names = "default"; 284 + pinctrl-0 = <&dp0_3v3_en_pins_default>; 285 + regulator-name = "dp-pwr"; 286 + regulator-min-microvolt = <3300000>; 287 + regulator-max-microvolt = <3300000>; 288 + gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */ 289 + enable-active-high; 290 + }; 291 + 292 + dp0: connector { 293 + compatible = "dp-connector"; 294 + label = "DP0"; 295 + type = "full-size"; 296 + dp-pwr-supply = <&dp_pwr_3v3>; 297 + 298 + port { 299 + dp_connector_in: endpoint { 300 + remote-endpoint = <&dp0_out>; 301 + }; 302 + }; 303 + }; 304 + }; 305 + 306 + &main_pmx0 { 307 + led_pins_default: led-pins-default { 308 + pinctrl-single,pins = < 309 + J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */ 310 + J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */ 311 + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ 312 + J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */ 313 + J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */ 314 + >; 315 + }; 316 + 317 + main_mmc1_pins_default: main-mmc1-pins-default { 318 + pinctrl-single,pins = < 319 + J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 320 + J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 321 + J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 322 + J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 323 + J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 324 + J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 325 + J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 326 + J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 327 + >; 328 + }; 329 + 330 + main_uart0_pins_default: main-uart0-pins-default { 331 + pinctrl-single,pins = < 332 + J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 333 + J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 334 + >; 335 + }; 336 + 337 + sd_pwr_en_pins_default: sd-pwr-en-pins-default { 338 + pinctrl-single,pins = < 339 + J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ 340 + >; 341 + }; 342 + 343 + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { 344 + pinctrl-single,pins = < 345 + J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ 346 + >; 347 + }; 348 + 349 + main_usbss0_pins_default: main-usbss0-pins-default { 350 + pinctrl-single,pins = < 351 + J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */ 352 + >; 353 + }; 354 + 355 + main_usbss1_pins_default: main-usbss1-pins-default { 356 + pinctrl-single,pins = < 357 + J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */ 358 + >; 359 + }; 360 + 361 + dp0_3v3_en_pins_default:dp0-3v3-en-pins-default { 362 + pinctrl-single,pins = < 363 + J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */ 364 + >; 365 + }; 366 + 367 + dp0_pins_default: dp0-pins-default { 368 + pinctrl-single,pins = < 369 + J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */ 370 + >; 371 + }; 372 + 373 + main_i2c0_pins_default: main-i2c0-pins-default { 374 + pinctrl-single,pins = < 375 + J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 376 + J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 377 + >; 378 + }; 379 + 380 + main_i2c1_pins_default: main-i2c1-pins-default { 381 + pinctrl-single,pins = < 382 + J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 383 + J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 384 + >; 385 + }; 386 + 387 + main_i2c2_pins_default: main-i2c2-pins-default { 388 + pinctrl-single,pins = < 389 + J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */ 390 + J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */ 391 + J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */ 392 + J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */ 393 + >; 394 + }; 395 + 396 + main_i2c3_pins_default: main-i2c3-pins-default { 397 + pinctrl-single,pins = < 398 + J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 399 + J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 400 + >; 401 + }; 402 + 403 + main_i2c4_pins_default: main-i2c4-pins-default { 404 + pinctrl-single,pins = < 405 + J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */ 406 + J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */ 407 + J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */ 408 + J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */ 409 + >; 410 + }; 411 + 412 + main_i2c5_pins_default: main-i2c5-pins-default { 413 + pinctrl-single,pins = < 414 + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ 415 + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ 416 + >; 417 + }; 418 + 419 + main_i2c6_pins_default: main-i2c6-pins-default { 420 + pinctrl-single,pins = < 421 + J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ 422 + J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ 423 + J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */ 424 + J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */ 425 + >; 426 + }; 427 + 428 + csi0_gpio_pins_default: csi0-gpio-pins-default { 429 + pinctrl-single,pins = < 430 + J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ 431 + J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ 432 + >; 433 + }; 434 + 435 + csi1_gpio_pins_default: csi1-gpio-pins-default { 436 + pinctrl-single,pins = < 437 + J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ 438 + J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ 439 + >; 440 + }; 441 + 442 + pcie1_rst_pins_default: pcie1-rst-pins-default { 443 + pinctrl-single,pins = < 444 + J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ 445 + >; 446 + }; 447 + }; 448 + 449 + &wkup_pmx0 { 450 + eeprom_wp_pins_default: eeprom-wp-pins-default { 451 + pinctrl-single,pins = < 452 + J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */ 453 + >; 454 + }; 455 + 456 + mcu_adc0_pins_default: mcu-adc0-pins-default { 457 + pinctrl-single,pins = < 458 + J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */ 459 + J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */ 460 + J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */ 461 + J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */ 462 + J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */ 463 + J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */ 464 + J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */ 465 + >; 466 + }; 467 + 468 + mcu_adc1_pins_default: mcu-adc1-pins-default { 469 + pinctrl-single,pins = < 470 + J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */ 471 + >; 472 + }; 473 + 474 + mikro_bus_pins_default: mikro-bus-pins-default { 475 + pinctrl-single,pins = < 476 + J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */ 477 + J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */ 478 + J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */ 479 + J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */ 480 + J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */ 481 + 482 + J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */ 483 + J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */ 484 + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */ 485 + J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */ 486 + 487 + J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */ 488 + J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */ 489 + 490 + J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */ 491 + J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */ 492 + J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */ 493 + J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */ 494 + >; 495 + }; 496 + 497 + mcu_cpsw_pins_default: mcu-cpsw-pins-default { 498 + pinctrl-single,pins = < 499 + J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 500 + J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 501 + J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 502 + J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 503 + J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 504 + J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 505 + J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 506 + J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 507 + J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 508 + J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 509 + J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 510 + J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 511 + >; 512 + }; 513 + 514 + mcu_mdio_pins_default: mcu-mdio1-pins-default { 515 + pinctrl-single,pins = < 516 + J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 517 + J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 518 + >; 519 + }; 520 + 521 + sw_pwr_pins_default: sw-pwr-pins-default { 522 + pinctrl-single,pins = < 523 + J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */ 524 + >; 525 + }; 526 + 527 + wkup_i2c0_pins_default: wkup-i2c0-pins-default { 528 + pinctrl-single,pins = < 529 + J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 530 + J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 531 + >; 532 + }; 533 + 534 + mcu_usbss1_pins_default: mcu-usbss1-pins-default { 535 + pinctrl-single,pins = < 536 + J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ 537 + >; 538 + }; 539 + }; 540 + 541 + &wkup_uart0 { 542 + /* Wakeup UART is used by TIFS firmware. */ 543 + status = "reserved"; 544 + }; 545 + 546 + &main_uart0 { 547 + status = "okay"; 548 + pinctrl-names = "default"; 549 + pinctrl-0 = <&main_uart0_pins_default>; 550 + /* Shared with ATF on this platform */ 551 + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 552 + }; 553 + 554 + &main_sdhci0 { 555 + /* eMMC */ 556 + non-removable; 557 + ti,driver-strength-ohm = <50>; 558 + disable-wp; 559 + }; 560 + 561 + &main_sdhci1 { 562 + /* SD Card */ 563 + vmmc-supply = <&vdd_mmc1>; 564 + vqmmc-supply = <&vdd_sd_dv_alt>; 565 + pinctrl-names = "default"; 566 + pinctrl-0 = <&main_mmc1_pins_default>; 567 + ti,driver-strength-ohm = <50>; 568 + disable-wp; 569 + }; 570 + 571 + &main_sdhci2 { 572 + /* Unused */ 573 + status = "disabled"; 574 + }; 575 + 576 + &ospi0 { 577 + /* Unused */ 578 + status = "disabled"; 579 + }; 580 + 581 + &ospi1 { 582 + /* Unused */ 583 + status = "disabled"; 584 + }; 585 + 586 + &main_i2c0 { 587 + status = "okay"; 588 + pinctrl-names = "default"; 589 + pinctrl-0 = <&main_i2c0_pins_default>; 590 + clock-frequency = <400000>; 591 + }; 592 + 593 + &main_i2c1 { 594 + status = "okay"; 595 + pinctrl-names = "default"; 596 + pinctrl-0 = <&main_i2c1_pins_default &csi1_gpio_pins_default>; 597 + clock-frequency = <400000>; 598 + }; 599 + 600 + &main_i2c2 { 601 + /* BBB Header: P9.19 and P9.20 */ 602 + status = "okay"; 603 + pinctrl-names = "default"; 604 + pinctrl-0 = <&main_i2c2_pins_default>; 605 + clock-frequency = <100000>; 606 + }; 607 + 608 + &main_i2c3 { 609 + status = "okay"; 610 + pinctrl-names = "default"; 611 + pinctrl-0 = <&main_i2c3_pins_default>; 612 + clock-frequency = <400000>; 613 + }; 614 + 615 + &main_i2c4 { 616 + /* BBB Header: P9.24 and P9.26 */ 617 + status = "okay"; 618 + pinctrl-names = "default"; 619 + pinctrl-0 = <&main_i2c4_pins_default>; 620 + clock-frequency = <100000>; 621 + }; 622 + 623 + &main_i2c5 { 624 + status = "okay"; 625 + pinctrl-names = "default"; 626 + pinctrl-0 = <&main_i2c5_pins_default &csi0_gpio_pins_default>; 627 + clock-frequency = <400000>; 628 + }; 629 + 630 + &main_i2c6 { 631 + /* BBB Header: P9.17 and P9.18 */ 632 + status = "okay"; 633 + pinctrl-names = "default"; 634 + pinctrl-0 = <&main_i2c6_pins_default>; 635 + clock-frequency = <100000>; 636 + status = "okay"; 637 + }; 638 + 639 + &wkup_i2c0 { 640 + status = "okay"; 641 + pinctrl-names = "default"; 642 + pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>; 643 + clock-frequency = <400000>; 644 + 645 + eeprom@50 { 646 + compatible = "atmel,24c04"; 647 + reg = <0x50>; 648 + }; 649 + }; 650 + 651 + &main_gpio2 { 652 + /* Unused */ 653 + status = "disabled"; 654 + }; 655 + 656 + &main_gpio3 { 657 + /* Unused */ 658 + status = "disabled"; 659 + }; 660 + 661 + &main_gpio4 { 662 + /* Unused */ 663 + status = "disabled"; 664 + }; 665 + 666 + &main_gpio5 { 667 + /* Unused */ 668 + status = "disabled"; 669 + }; 670 + 671 + &main_gpio6 { 672 + /* Unused */ 673 + status = "disabled"; 674 + }; 675 + 676 + &main_gpio7 { 677 + /* Unused */ 678 + status = "disabled"; 679 + }; 680 + 681 + &wkup_gpio0 { 682 + pinctrl-names = "default"; 683 + pinctrl-0 = <&mcu_adc0_pins_default &mcu_adc1_pins_default &mikro_bus_pins_default>; 684 + }; 685 + 686 + &wkup_gpio1 { 687 + /* Unused */ 688 + status = "disabled"; 689 + }; 690 + 691 + &usb_serdes_mux { 692 + idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 693 + }; 694 + 695 + &serdes_ln_ctrl { 696 + idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 697 + <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 698 + <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 699 + <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 700 + <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 701 + <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 702 + }; 703 + 704 + &serdes_wiz3 { 705 + typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>; 706 + typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 707 + }; 708 + 709 + &serdes3 { 710 + serdes3_usb_link: phy@0 { 711 + reg = <0>; 712 + cdns,num-lanes = <2>; 713 + #phy-cells = <0>; 714 + cdns,phy-type = <PHY_TYPE_USB3>; 715 + resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 716 + }; 717 + }; 718 + 719 + &serdes4 { 720 + torrent_phy_dp: phy@0 { 721 + reg = <0>; 722 + resets = <&serdes_wiz4 1>; 723 + cdns,phy-type = <PHY_TYPE_DP>; 724 + cdns,num-lanes = <4>; 725 + cdns,max-bit-rate = <5400>; 726 + #phy-cells = <0>; 727 + }; 728 + }; 729 + 730 + &mhdp { 731 + phys = <&torrent_phy_dp>; 732 + phy-names = "dpphy"; 733 + pinctrl-names = "default"; 734 + pinctrl-0 = <&dp0_pins_default>; 735 + }; 736 + 737 + &usbss0 { 738 + pinctrl-names = "default"; 739 + pinctrl-0 = <&main_usbss0_pins_default>; 740 + ti,vbus-divider; 741 + }; 742 + 743 + &usb0 { 744 + dr_mode = "peripheral"; 745 + maximum-speed = "super-speed"; 746 + phys = <&serdes3_usb_link>; 747 + phy-names = "cdns3,usb3-phy"; 748 + }; 749 + 750 + &serdes2 { 751 + serdes2_usb_link: phy@1 { 752 + reg = <1>; 753 + cdns,num-lanes = <1>; 754 + #phy-cells = <0>; 755 + cdns,phy-type = <PHY_TYPE_USB3>; 756 + resets = <&serdes_wiz2 2>; 757 + }; 758 + }; 759 + 760 + &usbss1 { 761 + pinctrl-names = "default"; 762 + pinctrl-0 = <&main_usbss1_pins_default &mcu_usbss1_pins_default>; 763 + ti,vbus-divider; 764 + }; 765 + 766 + &usb1 { 767 + dr_mode = "host"; 768 + maximum-speed = "super-speed"; 769 + phys = <&serdes2_usb_link>; 770 + phy-names = "cdns3,usb3-phy"; 771 + }; 772 + 773 + &tscadc0 { 774 + /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ 775 + adc { 776 + ti,adc-channels = <0 1 2 3 4 5 6>; 777 + }; 778 + }; 779 + 780 + &tscadc1 { 781 + /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ 782 + adc { 783 + ti,adc-channels = <0>; 784 + }; 785 + }; 786 + 787 + &mcu_cpsw { 788 + pinctrl-names = "default"; 789 + pinctrl-0 = <&mcu_cpsw_pins_default>; 790 + }; 791 + 792 + &davinci_mdio { 793 + pinctrl-names = "default"; 794 + pinctrl-0 = <&mcu_mdio_pins_default>; 795 + 796 + phy0: ethernet-phy@0 { 797 + reg = <0>; 798 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 799 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 800 + }; 801 + }; 802 + 803 + &cpsw_port1 { 804 + phy-mode = "rgmii-rxid"; 805 + phy-handle = <&phy0>; 806 + }; 807 + 808 + &dss { 809 + /* 810 + * These clock assignments are chosen to enable the following outputs: 811 + * 812 + * VP0 - DisplayPort SST 813 + * VP1 - DPI0 814 + * VP2 - DSI 815 + * VP3 - DPI1 816 + */ 817 + 818 + assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 819 + <&k3_clks 152 4>, /* VP 2 pixel clock */ 820 + <&k3_clks 152 9>, /* VP 3 pixel clock */ 821 + <&k3_clks 152 13>; /* VP 4 pixel clock */ 822 + assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 823 + <&k3_clks 152 6>, /* PLL19_HSDIV0 */ 824 + <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 825 + <&k3_clks 152 18>; /* PLL23_HSDIV0 */ 826 + }; 827 + 828 + &dss_ports { 829 + port { 830 + dpi0_out: endpoint { 831 + remote-endpoint = <&dp0_in>; 832 + }; 833 + }; 834 + }; 835 + 836 + &dp0_ports { 837 + #address-cells = <1>; 838 + #size-cells = <0>; 839 + 840 + port@0 { 841 + reg = <0>; 842 + dp0_in: endpoint { 843 + remote-endpoint = <&dpi0_out>; 844 + }; 845 + }; 846 + 847 + port@4 { 848 + reg = <4>; 849 + dp0_out: endpoint { 850 + remote-endpoint = <&dp_connector_in>; 851 + }; 852 + }; 853 + }; 854 + 855 + &serdes0 { 856 + serdes0_pcie_link: phy@0 { 857 + reg = <0>; 858 + cdns,num-lanes = <1>; 859 + #phy-cells = <0>; 860 + cdns,phy-type = <PHY_TYPE_PCIE>; 861 + resets = <&serdes_wiz0 1>; 862 + }; 863 + }; 864 + 865 + &serdes1 { 866 + serdes1_pcie_link: phy@0 { 867 + reg = <0>; 868 + cdns,num-lanes = <2>; 869 + #phy-cells = <0>; 870 + cdns,phy-type = <PHY_TYPE_PCIE>; 871 + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 872 + }; 873 + }; 874 + 875 + &pcie0_rc { 876 + /* Unused */ 877 + status = "disabled"; 878 + }; 879 + 880 + &pcie1_rc { 881 + pinctrl-names = "default"; 882 + pinctrl-0 = <&pcie1_rst_pins_default>; 883 + phys = <&serdes1_pcie_link>; 884 + phy-names = "pcie-phy"; 885 + num-lanes = <2>; 886 + max-link-speed = <3>; 887 + reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; 888 + }; 889 + 890 + &pcie2_rc { 891 + /* Unused */ 892 + status = "disabled"; 893 + }; 894 + 895 + &pcie0_ep { 896 + status = "disabled"; 897 + phys = <&serdes0_pcie_link>; 898 + phy-names = "pcie-phy"; 899 + num-lanes = <1>; 900 + }; 901 + 902 + &pcie1_ep { 903 + status = "disabled"; 904 + phys = <&serdes1_pcie_link>; 905 + phy-names = "pcie-phy"; 906 + num-lanes = <2>; 907 + }; 908 + 909 + &pcie2_ep { 910 + /* Unused */ 911 + status = "disabled"; 912 + }; 913 + 914 + &pcie3_rc { 915 + /* Unused */ 916 + status = "disabled"; 917 + }; 918 + 919 + &pcie3_ep { 920 + /* Unused */ 921 + status = "disabled"; 922 + }; 923 + 924 + &icssg0_mdio { 925 + /* Unused */ 926 + status = "disabled"; 927 + }; 928 + 929 + &icssg1_mdio { 930 + /* Unused */ 931 + status = "disabled"; 932 + }; 933 + 934 + &ufs_wrapper { 935 + status = "disabled"; 936 + }; 937 + 938 + &mailbox0_cluster0 { 939 + interrupts = <436>; 940 + 941 + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 942 + ti,mbox-rx = <0 0 0>; 943 + ti,mbox-tx = <1 0 0>; 944 + }; 945 + 946 + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 947 + ti,mbox-rx = <2 0 0>; 948 + ti,mbox-tx = <3 0 0>; 949 + }; 950 + }; 951 + 952 + &mailbox0_cluster1 { 953 + interrupts = <432>; 954 + 955 + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 956 + ti,mbox-rx = <0 0 0>; 957 + ti,mbox-tx = <1 0 0>; 958 + }; 959 + 960 + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 961 + ti,mbox-rx = <2 0 0>; 962 + ti,mbox-tx = <3 0 0>; 963 + }; 964 + }; 965 + 966 + &mailbox0_cluster2 { 967 + interrupts = <428>; 968 + 969 + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 970 + ti,mbox-rx = <0 0 0>; 971 + ti,mbox-tx = <1 0 0>; 972 + }; 973 + 974 + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 975 + ti,mbox-rx = <2 0 0>; 976 + ti,mbox-tx = <3 0 0>; 977 + }; 978 + }; 979 + 980 + &mailbox0_cluster3 { 981 + interrupts = <424>; 982 + 983 + mbox_c66_0: mbox-c66-0 { 984 + ti,mbox-rx = <0 0 0>; 985 + ti,mbox-tx = <1 0 0>; 986 + }; 987 + 988 + mbox_c66_1: mbox-c66-1 { 989 + ti,mbox-rx = <2 0 0>; 990 + ti,mbox-tx = <3 0 0>; 991 + }; 992 + }; 993 + 994 + &mailbox0_cluster4 { 995 + interrupts = <420>; 996 + 997 + mbox_c71_0: mbox-c71-0 { 998 + ti,mbox-rx = <0 0 0>; 999 + ti,mbox-tx = <1 0 0>; 1000 + }; 1001 + }; 1002 + 1003 + &mcu_r5fss0_core0 { 1004 + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 1005 + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1006 + <&mcu_r5fss0_core0_memory_region>; 1007 + }; 1008 + 1009 + &mcu_r5fss0_core1 { 1010 + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 1011 + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1012 + <&mcu_r5fss0_core1_memory_region>; 1013 + }; 1014 + 1015 + &main_r5fss0_core0 { 1016 + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1017 + memory-region = <&main_r5fss0_core0_dma_memory_region>, 1018 + <&main_r5fss0_core0_memory_region>; 1019 + }; 1020 + 1021 + &main_r5fss0_core1 { 1022 + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1023 + memory-region = <&main_r5fss0_core1_dma_memory_region>, 1024 + <&main_r5fss0_core1_memory_region>; 1025 + }; 1026 + 1027 + &main_r5fss1_core0 { 1028 + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1029 + memory-region = <&main_r5fss1_core0_dma_memory_region>, 1030 + <&main_r5fss1_core0_memory_region>; 1031 + }; 1032 + 1033 + &main_r5fss1_core1 { 1034 + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1035 + memory-region = <&main_r5fss1_core1_dma_memory_region>, 1036 + <&main_r5fss1_core1_memory_region>; 1037 + }; 1038 + 1039 + &c66_0 { 1040 + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 1041 + memory-region = <&c66_0_dma_memory_region>, 1042 + <&c66_0_memory_region>; 1043 + }; 1044 + 1045 + &c66_1 { 1046 + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; 1047 + memory-region = <&c66_1_dma_memory_region>, 1048 + <&c66_1_memory_region>; 1049 + }; 1050 + 1051 + &c71_0 { 1052 + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1053 + memory-region = <&c71_0_dma_memory_region>, 1054 + <&c71_0_memory_region>; 1055 + };

+26 -117

arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts

··· 96 96 <3300000 0x1>; 97 97 }; 98 98 99 - sound0: sound@0 { 99 + sound0: sound-0 { 100 100 compatible = "ti,j721e-cpb-audio"; 101 101 model = "j721e-cpb"; 102 102 ··· 370 370 status = "reserved"; 371 371 }; 372 372 373 + &mcu_uart0 { 374 + status = "okay"; 375 + /* Default pinmux */ 376 + }; 377 + 373 378 &main_uart0 { 379 + status = "okay"; 380 + /* Shared with ATF on this platform */ 374 381 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 375 382 }; 376 383 377 - &main_uart3 { 378 - /* UART not brought out */ 379 - status = "disabled"; 384 + &main_uart1 { 385 + status = "okay"; 386 + /* Default pinmux */ 380 387 }; 381 388 382 - &main_uart5 { 383 - /* UART not brought out */ 384 - status = "disabled"; 389 + &main_uart2 { 390 + status = "okay"; 391 + /* Default pinmux */ 385 392 }; 386 393 387 - &main_uart6 { 388 - /* UART not brought out */ 389 - status = "disabled"; 390 - }; 391 - 392 - &main_uart7 { 393 - /* UART not brought out */ 394 - status = "disabled"; 395 - }; 396 - 397 - &main_uart8 { 398 - /* UART not brought out */ 399 - status = "disabled"; 400 - }; 401 - 402 - &main_uart9 { 403 - /* UART not brought out */ 404 - status = "disabled"; 394 + &main_uart4 { 395 + status = "okay"; 396 + /* Default pinmux */ 405 397 }; 406 398 407 399 &main_gpio2 { ··· 529 537 }; 530 538 531 539 &main_i2c0 { 540 + status = "okay"; 532 541 pinctrl-names = "default"; 533 542 pinctrl-0 = <&main_i2c0_pins_default>; 534 543 clock-frequency = <400000>; ··· 566 573 }; 567 574 568 575 &main_i2c1 { 576 + status = "okay"; 569 577 pinctrl-names = "default"; 570 578 pinctrl-0 = <&main_i2c1_pins_default>; 571 579 clock-frequency = <400000>; ··· 592 598 }; 593 599 594 600 &main_i2c3 { 601 + status = "okay"; 595 602 pinctrl-names = "default"; 596 603 pinctrl-0 = <&main_i2c3_pins_default>; 597 604 clock-frequency = <400000>; ··· 631 636 }; 632 637 633 638 &main_i2c6 { 639 + status = "okay"; 634 640 pinctrl-names = "default"; 635 641 pinctrl-0 = <&main_i2c6_pins_default>; 636 642 clock-frequency = <400000>; ··· 709 713 }; 710 714 }; 711 715 712 - &mcasp0 { 713 - status = "disabled"; 714 - }; 715 - 716 - &mcasp1 { 717 - status = "disabled"; 718 - }; 719 - 720 - &mcasp2 { 721 - status = "disabled"; 722 - }; 723 - 724 - &mcasp3 { 725 - status = "disabled"; 726 - }; 727 - 728 - &mcasp4 { 729 - status = "disabled"; 730 - }; 731 - 732 - &mcasp5 { 733 - status = "disabled"; 734 - }; 735 - 736 - &mcasp6 { 737 - status = "disabled"; 738 - }; 739 - 740 - &mcasp7 { 741 - status = "disabled"; 742 - }; 743 - 744 - &mcasp8 { 745 - status = "disabled"; 746 - }; 747 - 748 - &mcasp9 { 749 - status = "disabled"; 750 - }; 751 - 752 716 &mcasp10 { 717 + status = "okay"; 753 718 #sound-dai-cells = <0>; 754 719 755 720 pinctrl-names = "default"; ··· 726 769 >; 727 770 tx-num-evt = <0>; 728 771 rx-num-evt = <0>; 729 - }; 730 - 731 - &mcasp11 { 732 - status = "disabled"; 733 772 }; 734 773 735 774 &cmn_refclk1 { ··· 878 925 }; 879 926 880 927 &mcu_mcan0 { 928 + status = "okay"; 881 929 pinctrl-names = "default"; 882 930 pinctrl-0 = <&mcu_mcan0_pins_default>; 883 931 phys = <&transceiver1>; 884 932 }; 885 933 886 934 &mcu_mcan1 { 935 + status = "okay"; 887 936 pinctrl-names = "default"; 888 937 pinctrl-0 = <&mcu_mcan1_pins_default>; 889 938 phys = <&transceiver2>; 890 939 }; 891 940 892 941 &main_mcan0 { 942 + status = "okay"; 893 943 pinctrl-names = "default"; 894 944 pinctrl-0 = <&main_mcan0_pins_default>; 895 945 phys = <&transceiver3>; 896 946 }; 897 947 898 - &main_mcan1 { 899 - status = "disabled"; 900 - }; 901 - 902 948 &main_mcan2 { 949 + status = "okay"; 903 950 pinctrl-names = "default"; 904 951 pinctrl-0 = <&main_mcan2_pins_default>; 905 952 phys = <&transceiver4>; 906 - }; 907 - 908 - &main_mcan3 { 909 - status = "disabled"; 910 - }; 911 - 912 - &main_mcan4 { 913 - status = "disabled"; 914 - }; 915 - 916 - &main_mcan5 { 917 - status = "disabled"; 918 - }; 919 - 920 - &main_mcan6 { 921 - status = "disabled"; 922 - }; 923 - 924 - &main_mcan7 { 925 - status = "disabled"; 926 - }; 927 - 928 - &main_mcan8 { 929 - status = "disabled"; 930 - }; 931 - 932 - &main_mcan9 { 933 - status = "disabled"; 934 - }; 935 - 936 - &main_mcan10 { 937 - status = "disabled"; 938 - }; 939 - 940 - &main_mcan11 { 941 - status = "disabled"; 942 - }; 943 - 944 - &main_mcan12 { 945 - status = "disabled"; 946 - }; 947 - 948 - &main_mcan13 { 949 - status = "disabled"; 950 953 };

+122 -3

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

··· 66 66 #mux-control-cells = <1>; 67 67 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 68 68 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 69 - }; 69 + }; 70 + 71 + ehrpwm_tbclk: clock-controller@4140 { 72 + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 73 + reg = <0x4140 0x18>; 74 + #clock-cells = <1>; 75 + }; 76 + }; 77 + 78 + main_ehrpwm0: pwm@3000000 { 79 + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 80 + #pwm-cells = <3>; 81 + reg = <0x00 0x3000000 0x00 0x100>; 82 + power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 83 + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; 84 + clock-names = "tbclk", "fck"; 85 + status = "disabled"; 86 + }; 87 + 88 + main_ehrpwm1: pwm@3010000 { 89 + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 90 + #pwm-cells = <3>; 91 + reg = <0x00 0x3010000 0x00 0x100>; 92 + power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 93 + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; 94 + clock-names = "tbclk", "fck"; 95 + status = "disabled"; 96 + }; 97 + 98 + main_ehrpwm2: pwm@3020000 { 99 + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 100 + #pwm-cells = <3>; 101 + reg = <0x00 0x3020000 0x00 0x100>; 102 + power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 103 + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; 104 + clock-names = "tbclk", "fck"; 105 + status = "disabled"; 106 + }; 107 + 108 + main_ehrpwm3: pwm@3030000 { 109 + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 110 + #pwm-cells = <3>; 111 + reg = <0x00 0x3030000 0x00 0x100>; 112 + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 113 + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; 114 + clock-names = "tbclk", "fck"; 115 + status = "disabled"; 116 + }; 117 + 118 + main_ehrpwm4: pwm@3040000 { 119 + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 120 + #pwm-cells = <3>; 121 + reg = <0x00 0x3040000 0x00 0x100>; 122 + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 123 + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; 124 + clock-names = "tbclk", "fck"; 125 + status = "disabled"; 126 + }; 127 + 128 + main_ehrpwm5: pwm@3050000 { 129 + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 130 + #pwm-cells = <3>; 131 + reg = <0x00 0x3050000 0x00 0x100>; 132 + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 133 + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; 134 + clock-names = "tbclk", "fck"; 135 + status = "disabled"; 70 136 }; 71 137 72 138 gic500: interrupt-controller@1800000 { ··· 242 176 ti,mbox-num-users = <4>; 243 177 ti,mbox-num-fifos = <16>; 244 178 interrupt-parent = <&main_navss_intr>; 179 + status = "disabled"; 245 180 }; 246 181 247 182 mailbox0_cluster1: mailbox@31f81000 { ··· 252 185 ti,mbox-num-users = <4>; 253 186 ti,mbox-num-fifos = <16>; 254 187 interrupt-parent = <&main_navss_intr>; 188 + status = "disabled"; 255 189 }; 256 190 257 191 mailbox0_cluster2: mailbox@31f82000 { ··· 262 194 ti,mbox-num-users = <4>; 263 195 ti,mbox-num-fifos = <16>; 264 196 interrupt-parent = <&main_navss_intr>; 197 + status = "disabled"; 265 198 }; 266 199 267 200 mailbox0_cluster3: mailbox@31f83000 { ··· 272 203 ti,mbox-num-users = <4>; 273 204 ti,mbox-num-fifos = <16>; 274 205 interrupt-parent = <&main_navss_intr>; 206 + status = "disabled"; 275 207 }; 276 208 277 209 mailbox0_cluster4: mailbox@31f84000 { ··· 282 212 ti,mbox-num-users = <4>; 283 213 ti,mbox-num-fifos = <16>; 284 214 interrupt-parent = <&main_navss_intr>; 215 + status = "disabled"; 285 216 }; 286 217 287 218 mailbox0_cluster5: mailbox@31f85000 { ··· 292 221 ti,mbox-num-users = <4>; 293 222 ti,mbox-num-fifos = <16>; 294 223 interrupt-parent = <&main_navss_intr>; 224 + status = "disabled"; 295 225 }; 296 226 297 227 mailbox0_cluster6: mailbox@31f86000 { ··· 302 230 ti,mbox-num-users = <4>; 303 231 ti,mbox-num-fifos = <16>; 304 232 interrupt-parent = <&main_navss_intr>; 233 + status = "disabled"; 305 234 }; 306 235 307 236 mailbox0_cluster7: mailbox@31f87000 { ··· 312 239 ti,mbox-num-users = <4>; 313 240 ti,mbox-num-fifos = <16>; 314 241 interrupt-parent = <&main_navss_intr>; 242 + status = "disabled"; 315 243 }; 316 244 317 245 mailbox0_cluster8: mailbox@31f88000 { ··· 322 248 ti,mbox-num-users = <4>; 323 249 ti,mbox-num-fifos = <16>; 324 250 interrupt-parent = <&main_navss_intr>; 251 + status = "disabled"; 325 252 }; 326 253 327 254 mailbox0_cluster9: mailbox@31f89000 { ··· 332 257 ti,mbox-num-users = <4>; 333 258 ti,mbox-num-fifos = <16>; 334 259 interrupt-parent = <&main_navss_intr>; 260 + status = "disabled"; 335 261 }; 336 262 337 263 mailbox0_cluster10: mailbox@31f8a000 { ··· 342 266 ti,mbox-num-users = <4>; 343 267 ti,mbox-num-fifos = <16>; 344 268 interrupt-parent = <&main_navss_intr>; 269 + status = "disabled"; 345 270 }; 346 271 347 272 mailbox0_cluster11: mailbox@31f8b000 { ··· 352 275 ti,mbox-num-users = <4>; 353 276 ti,mbox-num-fifos = <16>; 354 277 interrupt-parent = <&main_navss_intr>; 278 + status = "disabled"; 355 279 }; 356 280 357 281 main_ringacc: ringacc@3c000000 { ··· 415 337 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 416 338 <&main_udmap 0x4001>; 417 339 dma-names = "tx", "rx1", "rx2"; 418 - dma-coherent; 419 340 420 341 rng: rng@4e10000 { 421 342 compatible = "inside-secure,safexcel-eip76"; 422 343 reg = <0x0 0x4e10000 0x0 0x7d>; 423 344 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 424 - clocks = <&k3_clks 264 2>; 425 345 }; 426 346 }; 427 347 ··· 916 840 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 917 841 clocks = <&k3_clks 146 0>; 918 842 clock-names = "fclk"; 843 + status = "disabled"; 919 844 }; 920 845 921 846 main_uart1: serial@2810000 { ··· 928 851 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 929 852 clocks = <&k3_clks 278 0>; 930 853 clock-names = "fclk"; 854 + status = "disabled"; 931 855 }; 932 856 933 857 main_uart2: serial@2820000 { ··· 940 862 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 941 863 clocks = <&k3_clks 279 0>; 942 864 clock-names = "fclk"; 865 + status = "disabled"; 943 866 }; 944 867 945 868 main_uart3: serial@2830000 { ··· 952 873 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 953 874 clocks = <&k3_clks 280 0>; 954 875 clock-names = "fclk"; 876 + status = "disabled"; 955 877 }; 956 878 957 879 main_uart4: serial@2840000 { ··· 964 884 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 965 885 clocks = <&k3_clks 281 0>; 966 886 clock-names = "fclk"; 887 + status = "disabled"; 967 888 }; 968 889 969 890 main_uart5: serial@2850000 { ··· 976 895 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 977 896 clocks = <&k3_clks 282 0>; 978 897 clock-names = "fclk"; 898 + status = "disabled"; 979 899 }; 980 900 981 901 main_uart6: serial@2860000 { ··· 988 906 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 989 907 clocks = <&k3_clks 283 0>; 990 908 clock-names = "fclk"; 909 + status = "disabled"; 991 910 }; 992 911 993 912 main_uart7: serial@2870000 { ··· 1000 917 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 1001 918 clocks = <&k3_clks 284 0>; 1002 919 clock-names = "fclk"; 920 + status = "disabled"; 1003 921 }; 1004 922 1005 923 main_uart8: serial@2880000 { ··· 1012 928 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 1013 929 clocks = <&k3_clks 285 0>; 1014 930 clock-names = "fclk"; 931 + status = "disabled"; 1015 932 }; 1016 933 1017 934 main_uart9: serial@2890000 { ··· 1024 939 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 1025 940 clocks = <&k3_clks 286 0>; 1026 941 clock-names = "fclk"; 942 + status = "disabled"; 1027 943 }; 1028 944 1029 945 main_gpio0: gpio@600000 { ··· 1305 1219 clock-names = "fck"; 1306 1220 clocks = <&k3_clks 187 0>; 1307 1221 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1222 + status = "disabled"; 1308 1223 }; 1309 1224 1310 1225 main_i2c1: i2c@2010000 { ··· 1317 1230 clock-names = "fck"; 1318 1231 clocks = <&k3_clks 188 0>; 1319 1232 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1233 + status = "disabled"; 1320 1234 }; 1321 1235 1322 1236 main_i2c2: i2c@2020000 { ··· 1329 1241 clock-names = "fck"; 1330 1242 clocks = <&k3_clks 189 0>; 1331 1243 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1244 + status = "disabled"; 1332 1245 }; 1333 1246 1334 1247 main_i2c3: i2c@2030000 { ··· 1341 1252 clock-names = "fck"; 1342 1253 clocks = <&k3_clks 190 0>; 1343 1254 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1255 + status = "disabled"; 1344 1256 }; 1345 1257 1346 1258 main_i2c4: i2c@2040000 { ··· 1353 1263 clock-names = "fck"; 1354 1264 clocks = <&k3_clks 191 0>; 1355 1265 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1266 + status = "disabled"; 1356 1267 }; 1357 1268 1358 1269 main_i2c5: i2c@2050000 { ··· 1365 1274 clock-names = "fck"; 1366 1275 clocks = <&k3_clks 192 0>; 1367 1276 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1277 + status = "disabled"; 1368 1278 }; 1369 1279 1370 1280 main_i2c6: i2c@2060000 { ··· 1377 1285 clock-names = "fck"; 1378 1286 clocks = <&k3_clks 193 0>; 1379 1287 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1288 + status = "disabled"; 1380 1289 }; 1381 1290 1382 1291 ufs_wrapper: ufs-wrapper@4e80000 { ··· 1501 1408 clocks = <&k3_clks 174 1>; 1502 1409 clock-names = "fck"; 1503 1410 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1411 + status = "disabled"; 1504 1412 }; 1505 1413 1506 1414 mcasp1: mcasp@2b10000 { ··· 1519 1425 clocks = <&k3_clks 175 1>; 1520 1426 clock-names = "fck"; 1521 1427 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1428 + status = "disabled"; 1522 1429 }; 1523 1430 1524 1431 mcasp2: mcasp@2b20000 { ··· 1537 1442 clocks = <&k3_clks 176 1>; 1538 1443 clock-names = "fck"; 1539 1444 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1445 + status = "disabled"; 1540 1446 }; 1541 1447 1542 1448 mcasp3: mcasp@2b30000 { ··· 1555 1459 clocks = <&k3_clks 177 1>; 1556 1460 clock-names = "fck"; 1557 1461 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1462 + status = "disabled"; 1558 1463 }; 1559 1464 1560 1465 mcasp4: mcasp@2b40000 { ··· 1573 1476 clocks = <&k3_clks 178 1>; 1574 1477 clock-names = "fck"; 1575 1478 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1479 + status = "disabled"; 1576 1480 }; 1577 1481 1578 1482 mcasp5: mcasp@2b50000 { ··· 1591 1493 clocks = <&k3_clks 179 1>; 1592 1494 clock-names = "fck"; 1593 1495 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1496 + status = "disabled"; 1594 1497 }; 1595 1498 1596 1499 mcasp6: mcasp@2b60000 { ··· 1609 1510 clocks = <&k3_clks 180 1>; 1610 1511 clock-names = "fck"; 1611 1512 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1513 + status = "disabled"; 1612 1514 }; 1613 1515 1614 1516 mcasp7: mcasp@2b70000 { ··· 1627 1527 clocks = <&k3_clks 181 1>; 1628 1528 clock-names = "fck"; 1629 1529 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1530 + status = "disabled"; 1630 1531 }; 1631 1532 1632 1533 mcasp8: mcasp@2b80000 { ··· 1645 1544 clocks = <&k3_clks 182 1>; 1646 1545 clock-names = "fck"; 1647 1546 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1547 + status = "disabled"; 1648 1548 }; 1649 1549 1650 1550 mcasp9: mcasp@2b90000 { ··· 1663 1561 clocks = <&k3_clks 183 1>; 1664 1562 clock-names = "fck"; 1665 1563 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1564 + status = "disabled"; 1666 1565 }; 1667 1566 1668 1567 mcasp10: mcasp@2ba0000 { ··· 1681 1578 clocks = <&k3_clks 184 1>; 1682 1579 clock-names = "fck"; 1683 1580 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1581 + status = "disabled"; 1684 1582 }; 1685 1583 1686 1584 mcasp11: mcasp@2bb0000 { ··· 1699 1595 clocks = <&k3_clks 185 1>; 1700 1596 clock-names = "fck"; 1701 1597 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1598 + status = "disabled"; 1702 1599 }; 1703 1600 1704 1601 watchdog0: watchdog@2200000 { ··· 2132 2027 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2133 2028 interrupt-names = "int0", "int1"; 2134 2029 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2030 + status = "disabled"; 2135 2031 }; 2136 2032 2137 2033 main_mcan1: can@2711000 { ··· 2147 2041 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 2148 2042 interrupt-names = "int0", "int1"; 2149 2043 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2044 + status = "disabled"; 2150 2045 }; 2151 2046 2152 2047 main_mcan2: can@2721000 { ··· 2162 2055 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2163 2056 interrupt-names = "int0", "int1"; 2164 2057 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2058 + status = "disabled"; 2165 2059 }; 2166 2060 2167 2061 main_mcan3: can@2731000 { ··· 2177 2069 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2178 2070 interrupt-names = "int0", "int1"; 2179 2071 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2072 + status = "disabled"; 2180 2073 }; 2181 2074 2182 2075 main_mcan4: can@2741000 { ··· 2192 2083 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2193 2084 interrupt-names = "int0", "int1"; 2194 2085 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2086 + status = "disabled"; 2195 2087 }; 2196 2088 2197 2089 main_mcan5: can@2751000 { ··· 2207 2097 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2208 2098 interrupt-names = "int0", "int1"; 2209 2099 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2100 + status = "disabled"; 2210 2101 }; 2211 2102 2212 2103 main_mcan6: can@2761000 { ··· 2222 2111 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 2223 2112 interrupt-names = "int0", "int1"; 2224 2113 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2114 + status = "disabled"; 2225 2115 }; 2226 2116 2227 2117 main_mcan7: can@2771000 { ··· 2237 2125 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2238 2126 interrupt-names = "int0", "int1"; 2239 2127 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2128 + status = "disabled"; 2240 2129 }; 2241 2130 2242 2131 main_mcan8: can@2781000 { ··· 2252 2139 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 2253 2140 interrupt-names = "int0", "int1"; 2254 2141 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2142 + status = "disabled"; 2255 2143 }; 2256 2144 2257 2145 main_mcan9: can@2791000 { ··· 2267 2153 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2268 2154 interrupt-names = "int0", "int1"; 2269 2155 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2156 + status = "disabled"; 2270 2157 }; 2271 2158 2272 2159 main_mcan10: can@27a1000 { ··· 2282 2167 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2283 2168 interrupt-names = "int0", "int1"; 2284 2169 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2170 + status = "disabled"; 2285 2171 }; 2286 2172 2287 2173 main_mcan11: can@27b1000 { ··· 2297 2181 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2298 2182 interrupt-names = "int0", "int1"; 2299 2183 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2184 + status = "disabled"; 2300 2185 }; 2301 2186 2302 2187 main_mcan12: can@27c1000 { ··· 2312 2195 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 2313 2196 interrupt-names = "int0", "int1"; 2314 2197 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2198 + status = "disabled"; 2315 2199 }; 2316 2200 2317 2201 main_mcan13: can@27d1000 { ··· 2327 2209 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 2328 2210 interrupt-names = "int0", "int1"; 2329 2211 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2212 + status = "disabled"; 2330 2213 }; 2331 2214 };

+9 -2

arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi

··· 79 79 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 80 80 clocks = <&k3_clks 287 0>; 81 81 clock-names = "fclk"; 82 + status = "disabled"; 82 83 }; 83 84 84 85 mcu_uart0: serial@40a00000 { ··· 91 90 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 92 91 clocks = <&k3_clks 149 0>; 93 92 clock-names = "fclk"; 93 + status = "disabled"; 94 94 }; 95 95 96 96 wkup_gpio_intr: interrupt-controller@42200000 { ··· 147 145 clock-names = "fck"; 148 146 clocks = <&k3_clks 194 0>; 149 147 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 148 + status = "disabled"; 150 149 }; 151 150 152 151 mcu_i2c1: i2c@40b10000 { ··· 159 156 clock-names = "fck"; 160 157 clocks = <&k3_clks 195 0>; 161 158 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 159 + status = "disabled"; 162 160 }; 163 161 164 162 wkup_i2c0: i2c@42120000 { ··· 171 167 clock-names = "fck"; 172 168 clocks = <&k3_clks 197 0>; 173 169 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 170 + status = "disabled"; 174 171 }; 175 172 176 173 fss: fss@47000000 { ··· 221 216 clocks = <&k3_clks 0 1>; 222 217 assigned-clocks = <&k3_clks 0 3>; 223 218 assigned-clock-rates = <60000000>; 224 - clock-names = "adc_tsc_fck"; 219 + clock-names = "fck"; 225 220 dmas = <&main_udmap 0x7400>, 226 221 <&main_udmap 0x7401>; 227 222 dma-names = "fifo0", "fifo1"; ··· 240 235 clocks = <&k3_clks 1 1>; 241 236 assigned-clocks = <&k3_clks 1 3>; 242 237 assigned-clock-rates = <60000000>; 243 - clock-names = "adc_tsc_fck"; 238 + clock-names = "fck"; 244 239 dmas = <&main_udmap 0x7402>, 245 240 <&main_udmap 0x7403>; 246 241 dma-names = "fifo0", "fifo1"; ··· 408 403 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 409 404 interrupt-names = "int0", "int1"; 410 405 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 406 + status = "disabled"; 411 407 }; 412 408 413 409 mcu_mcan1: can@40568000 { ··· 423 417 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 424 418 interrupt-names = "int0", "int1"; 425 419 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 420 + status = "disabled"; 426 421 }; 427 422 };

+70 -135

arch/arm64/boot/dts/ti/k3-j721e-sk.dts

··· 400 400 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ 401 401 >; 402 402 }; 403 + 404 + main_i2c5_pins_default: main-i2c5-pins-default { 405 + pinctrl-single,pins = < 406 + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ 407 + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ 408 + >; 409 + }; 410 + 411 + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { 412 + pinctrl-single,pins = < 413 + J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ 414 + J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ 415 + J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ 416 + J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ 417 + J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ 418 + J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ 419 + J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ 420 + J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ 421 + J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ 422 + J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ 423 + J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ 424 + J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ 425 + J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ 426 + J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ 427 + J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ 428 + J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ 429 + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ 430 + J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ 431 + J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ 432 + J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ 433 + J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ 434 + J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ 435 + J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ 436 + >; 437 + }; 438 + 439 + rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { 440 + pinctrl-single,pins = < 441 + J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ 442 + >; 443 + }; 403 444 }; 404 445 405 446 &wkup_pmx0 { ··· 516 475 status = "reserved"; 517 476 }; 518 477 478 + &mcu_uart0 { 479 + status = "okay"; 480 + /* Default pinmux */ 481 + }; 482 + 519 483 &main_uart0 { 484 + status = "okay"; 520 485 pinctrl-names = "default"; 521 486 pinctrl-0 = <&main_uart0_pins_default>; 522 487 /* Shared with ATF on this platform */ 523 488 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 524 489 }; 525 490 526 - &main_uart2 { 527 - /* Brought out on RPi header */ 528 - status = "disabled"; 529 - }; 530 - 531 - &main_uart3 { 532 - /* UART not brought out */ 533 - status = "disabled"; 534 - }; 535 - 536 - &main_uart5 { 537 - /* UART not brought out */ 538 - status = "disabled"; 539 - }; 540 - 541 - &main_uart6 { 542 - /* UART not brought out */ 543 - status = "disabled"; 544 - }; 545 - 546 - &main_uart7 { 547 - /* UART not brought out */ 548 - status = "disabled"; 549 - }; 550 - 551 - &main_uart8 { 552 - /* UART not brought out */ 553 - status = "disabled"; 554 - }; 555 - 556 - &main_uart9 { 557 - /* Brought out on M.2 E Key */ 558 - status = "disabled"; 491 + &main_uart1 { 492 + status = "okay"; 493 + /* Default pinmux */ 559 494 }; 560 495 561 496 &main_sdhci0 { ··· 578 561 }; 579 562 580 563 &main_i2c0 { 564 + status = "okay"; 581 565 pinctrl-names = "default"; 582 566 pinctrl-0 = <&main_i2c0_pins_default>; 583 567 clock-frequency = <400000>; ··· 606 588 }; 607 589 608 590 &main_i2c1 { 591 + status = "okay"; 609 592 pinctrl-names = "default"; 610 593 pinctrl-0 = <&main_i2c1_pins_default>; 611 594 /* i2c1 is used for DVI DDC, so we need to use 100kHz */ 612 595 clock-frequency = <100000>; 613 596 }; 614 597 615 - &main_i2c2 { 616 - /* Unused */ 617 - status = "disabled"; 618 - }; 619 - 620 598 &main_i2c3 { 599 + status = "okay"; 621 600 pinctrl-names = "default"; 622 601 pinctrl-0 = <&main_i2c3_pins_default>; 623 602 clock-frequency = <400000>; ··· 641 626 }; 642 627 }; 643 628 644 - &main_i2c4 { 645 - /* Unused */ 646 - status = "disabled"; 647 - }; 648 - 649 629 &main_i2c5 { 650 630 /* Brought out on RPi Header */ 651 - status = "disabled"; 631 + status = "okay"; 632 + pinctrl-names = "default"; 633 + pinctrl-0 = <&main_i2c5_pins_default>; 634 + clock-frequency = <400000>; 652 635 }; 653 636 654 - &main_i2c6 { 655 - /* Unused */ 656 - status = "disabled"; 637 + &main_gpio0 { 638 + pinctrl-names = "default"; 639 + pinctrl-0 = <&rpi_header_gpio0_pins_default>; 640 + }; 641 + 642 + &main_gpio1 { 643 + pinctrl-names = "default"; 644 + pinctrl-0 = <&rpi_header_gpio1_pins_default>; 657 645 }; 658 646 659 647 &main_gpio2 { ··· 855 837 }; 856 838 }; 857 839 858 - &mcasp0 { 859 - /* Unused */ 860 - status = "disabled"; 861 - }; 862 - 863 - &mcasp1 { 864 - /* Unused */ 865 - status = "disabled"; 866 - }; 867 - 868 - &mcasp2 { 869 - /* Unused */ 870 - status = "disabled"; 871 - }; 872 - 873 - &mcasp3 { 874 - /* Unused */ 875 - status = "disabled"; 876 - }; 877 - 878 - &mcasp4 { 879 - /* Unused */ 880 - status = "disabled"; 881 - }; 882 - 883 - &mcasp5 { 884 - /* Unused */ 885 - status = "disabled"; 886 - }; 887 - 888 - &mcasp6 { 889 - /* Brought out on RPi header */ 890 - status = "disabled"; 891 - }; 892 - 893 - &mcasp7 { 894 - /* Unused */ 895 - status = "disabled"; 896 - }; 897 - 898 - &mcasp8 { 899 - /* Unused */ 900 - status = "disabled"; 901 - }; 902 - 903 - &mcasp9 { 904 - /* Unused */ 905 - status = "disabled"; 906 - }; 907 - 908 - &mcasp10 { 909 - /* Unused */ 910 - status = "disabled"; 911 - }; 912 - 913 - &mcasp11 { 914 - /* Brought out on M.2 E Key */ 915 - status = "disabled"; 916 - }; 917 - 918 840 &serdes0 { 919 841 serdes0_pcie_link: phy@0 { 920 842 reg = <0>; ··· 942 984 }; 943 985 944 986 &mailbox0_cluster0 { 987 + status = "okay"; 945 988 interrupts = <436>; 946 989 947 990 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { ··· 957 998 }; 958 999 959 1000 &mailbox0_cluster1 { 1001 + status = "okay"; 960 1002 interrupts = <432>; 961 1003 962 1004 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { ··· 972 1012 }; 973 1013 974 1014 &mailbox0_cluster2 { 1015 + status = "okay"; 975 1016 interrupts = <428>; 976 1017 977 1018 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { ··· 987 1026 }; 988 1027 989 1028 &mailbox0_cluster3 { 1029 + status = "okay"; 990 1030 interrupts = <424>; 991 1031 992 1032 mbox_c66_0: mbox-c66-0 { ··· 1002 1040 }; 1003 1041 1004 1042 &mailbox0_cluster4 { 1043 + status = "okay"; 1005 1044 interrupts = <420>; 1006 1045 1007 1046 mbox_c71_0: mbox-c71-0 { 1008 1047 ti,mbox-rx = <0 0 0>; 1009 1048 ti,mbox-tx = <1 0 0>; 1010 1049 }; 1011 - }; 1012 - 1013 - &mailbox0_cluster5 { 1014 - status = "disabled"; 1015 - }; 1016 - 1017 - &mailbox0_cluster6 { 1018 - status = "disabled"; 1019 - }; 1020 - 1021 - &mailbox0_cluster7 { 1022 - status = "disabled"; 1023 - }; 1024 - 1025 - &mailbox0_cluster8 { 1026 - status = "disabled"; 1027 - }; 1028 - 1029 - &mailbox0_cluster9 { 1030 - status = "disabled"; 1031 - }; 1032 - 1033 - &mailbox0_cluster10 { 1034 - status = "disabled"; 1035 - }; 1036 - 1037 - &mailbox0_cluster11 { 1038 - status = "disabled"; 1039 1050 }; 1040 1051 1041 1052 &mcu_r5fss0_core0 {

+5 -28

arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi

··· 186 186 }; 187 187 188 188 &mailbox0_cluster0 { 189 + status = "okay"; 189 190 interrupts = <436>; 190 191 191 192 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { ··· 201 200 }; 202 201 203 202 &mailbox0_cluster1 { 203 + status = "okay"; 204 204 interrupts = <432>; 205 205 206 206 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { ··· 216 214 }; 217 215 218 216 &mailbox0_cluster2 { 217 + status = "okay"; 219 218 interrupts = <428>; 220 219 221 220 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { ··· 231 228 }; 232 229 233 230 &mailbox0_cluster3 { 231 + status = "okay"; 234 232 interrupts = <424>; 235 233 236 234 mbox_c66_0: mbox-c66-0 { ··· 246 242 }; 247 243 248 244 &mailbox0_cluster4 { 245 + status = "okay"; 249 246 interrupts = <420>; 250 247 251 248 mbox_c71_0: mbox-c71-0 { 252 249 ti,mbox-rx = <0 0 0>; 253 250 ti,mbox-tx = <1 0 0>; 254 251 }; 255 - }; 256 - 257 - &mailbox0_cluster5 { 258 - status = "disabled"; 259 - }; 260 - 261 - &mailbox0_cluster6 { 262 - status = "disabled"; 263 - }; 264 - 265 - &mailbox0_cluster7 { 266 - status = "disabled"; 267 - }; 268 - 269 - &mailbox0_cluster8 { 270 - status = "disabled"; 271 - }; 272 - 273 - &mailbox0_cluster9 { 274 - status = "disabled"; 275 - }; 276 - 277 - &mailbox0_cluster10 { 278 - status = "disabled"; 279 - }; 280 - 281 - &mailbox0_cluster11 { 282 - status = "disabled"; 283 252 }; 284 253 285 254 &mcu_r5fss0_core0 {

+6 -126

arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts

··· 219 219 status = "reserved"; 220 220 }; 221 221 222 - &main_uart0 { 223 - status = "disabled"; 224 - }; 225 - 226 - &main_uart1 { 227 - status = "disabled"; 228 - }; 229 - 230 - &main_uart2 { 231 - status = "disabled"; 232 - }; 233 - 234 - &main_uart3 { 235 - status = "disabled"; 236 - }; 237 - 238 - &main_uart4 { 239 - status = "disabled"; 240 - }; 241 - 242 - &main_uart5 { 243 - status = "disabled"; 244 - }; 245 - 246 - &main_uart6 { 247 - status = "disabled"; 248 - }; 249 - 250 - &main_uart7 { 251 - status = "disabled"; 222 + &mcu_uart0 { 223 + status = "okay"; 224 + /* Default pinmux */ 252 225 }; 253 226 254 227 &main_uart8 { 228 + status = "okay"; 255 229 pinctrl-names = "default"; 256 230 pinctrl-0 = <&main_uart8_pins_default>; 257 231 /* Shared with TFA on this platform */ 258 232 power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; 259 - }; 260 - 261 - &main_uart9 { 262 - status = "disabled"; 263 233 }; 264 234 265 235 &main_i2c0 { ··· 259 289 "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL", 260 290 "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2"; 261 291 }; 262 - }; 263 - 264 - &main_i2c1 { 265 - status = "disabled"; 266 - }; 267 - 268 - &main_i2c2 { 269 - status = "disabled"; 270 - }; 271 - 272 - &main_i2c3 { 273 - status = "disabled"; 274 - }; 275 - 276 - &main_i2c4 { 277 - status = "disabled"; 278 - }; 279 - 280 - &main_i2c5 { 281 - status = "disabled"; 282 - }; 283 - 284 - &main_i2c6 { 285 - status = "disabled"; 286 292 }; 287 293 288 294 &main_sdhci0 { ··· 297 351 }; 298 352 299 353 &mcu_mcan0 { 354 + status = "okay"; 300 355 pinctrl-names = "default"; 301 356 pinctrl-0 = <&mcu_mcan0_pins_default>; 302 357 phys = <&transceiver1>; 303 358 }; 304 359 305 360 &mcu_mcan1 { 361 + status = "okay"; 306 362 pinctrl-names = "default"; 307 363 pinctrl-0 = <&mcu_mcan1_pins_default>; 308 364 phys = <&transceiver2>; 309 - }; 310 - 311 - &main_mcan0 { 312 - status = "disabled"; 313 - }; 314 - 315 - &main_mcan1 { 316 - status = "disabled"; 317 - }; 318 - 319 - &main_mcan2 { 320 - status = "disabled"; 321 - }; 322 - 323 - &main_mcan3 { 324 - status = "disabled"; 325 - }; 326 - 327 - &main_mcan4 { 328 - status = "disabled"; 329 - }; 330 - 331 - &main_mcan5 { 332 - status = "disabled"; 333 - }; 334 - 335 - &main_mcan6 { 336 - status = "disabled"; 337 - }; 338 - 339 - &main_mcan7 { 340 - status = "disabled"; 341 - }; 342 - 343 - &main_mcan8 { 344 - status = "disabled"; 345 - }; 346 - 347 - &main_mcan9 { 348 - status = "disabled"; 349 - }; 350 - 351 - &main_mcan10 { 352 - status = "disabled"; 353 - }; 354 - 355 - &main_mcan11 { 356 - status = "disabled"; 357 - }; 358 - 359 - &main_mcan12 { 360 - status = "disabled"; 361 - }; 362 - 363 - &main_mcan13 { 364 - status = "disabled"; 365 - }; 366 - 367 - &main_mcan14 { 368 - status = "disabled"; 369 - }; 370 - 371 - &main_mcan15 { 372 - status = "disabled"; 373 - }; 374 - 375 - &main_mcan17 { 376 - status = "disabled"; 377 365 };

+78 -1

arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

··· 60 60 #interrupt-cells = <1>; 61 61 ti,sci = <&sms>; 62 62 ti,sci-dev-id = <148>; 63 - ti,interrupt-ranges = <8 360 56>; 63 + ti,interrupt-ranges = <8 392 56>; 64 64 }; 65 65 66 66 main_pmx0: pinctrl@11c000 { ··· 72 72 pinctrl-single,function-mask = <0xffffffff>; 73 73 }; 74 74 75 + main_crypto: crypto@4e00000 { 76 + compatible = "ti,j721e-sa2ul"; 77 + reg = <0x00 0x04e00000 0x00 0x1200>; 78 + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 79 + #address-cells = <2>; 80 + #size-cells = <2>; 81 + ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 82 + 83 + dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 84 + <&main_udmap 0x4a41>; 85 + dma-names = "tx", "rx1", "rx2"; 86 + 87 + rng: rng@4e10000 { 88 + compatible = "inside-secure,safexcel-eip76"; 89 + reg = <0x00 0x04e10000 0x00 0x7d>; 90 + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 91 + }; 92 + }; 93 + 75 94 main_uart0: serial@2800000 { 76 95 compatible = "ti,j721e-uart", "ti,am654-uart"; 77 96 reg = <0x00 0x02800000 0x00 0x200>; ··· 99 80 clocks = <&k3_clks 146 3>; 100 81 clock-names = "fclk"; 101 82 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 83 + status = "disabled"; 102 84 }; 103 85 104 86 main_uart1: serial@2810000 { ··· 110 90 clocks = <&k3_clks 350 3>; 111 91 clock-names = "fclk"; 112 92 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 93 + status = "disabled"; 113 94 }; 114 95 115 96 main_uart2: serial@2820000 { ··· 121 100 clocks = <&k3_clks 351 3>; 122 101 clock-names = "fclk"; 123 102 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 103 + status = "disabled"; 124 104 }; 125 105 126 106 main_uart3: serial@2830000 { ··· 132 110 clocks = <&k3_clks 352 3>; 133 111 clock-names = "fclk"; 134 112 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 113 + status = "disabled"; 135 114 }; 136 115 137 116 main_uart4: serial@2840000 { ··· 143 120 clocks = <&k3_clks 353 3>; 144 121 clock-names = "fclk"; 145 122 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 123 + status = "disabled"; 146 124 }; 147 125 148 126 main_uart5: serial@2850000 { ··· 154 130 clocks = <&k3_clks 354 3>; 155 131 clock-names = "fclk"; 156 132 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 133 + status = "disabled"; 157 134 }; 158 135 159 136 main_uart6: serial@2860000 { ··· 165 140 clocks = <&k3_clks 355 3>; 166 141 clock-names = "fclk"; 167 142 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 143 + status = "disabled"; 168 144 }; 169 145 170 146 main_uart7: serial@2870000 { ··· 176 150 clocks = <&k3_clks 356 3>; 177 151 clock-names = "fclk"; 178 152 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 153 + status = "disabled"; 179 154 }; 180 155 181 156 main_uart8: serial@2880000 { ··· 187 160 clocks = <&k3_clks 357 3>; 188 161 clock-names = "fclk"; 189 162 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 163 + status = "disabled"; 190 164 }; 191 165 192 166 main_uart9: serial@2890000 { ··· 198 170 clocks = <&k3_clks 358 3>; 199 171 clock-names = "fclk"; 200 172 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 173 + status = "disabled"; 201 174 }; 202 175 203 176 main_gpio0: gpio@600000 { ··· 285 256 clocks = <&k3_clks 215 1>; 286 257 clock-names = "fck"; 287 258 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; 259 + status = "disabled"; 288 260 }; 289 261 290 262 main_i2c2: i2c@2020000 { ··· 297 267 clocks = <&k3_clks 216 1>; 298 268 clock-names = "fck"; 299 269 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; 270 + status = "disabled"; 300 271 }; 301 272 302 273 main_i2c3: i2c@2030000 { ··· 309 278 clocks = <&k3_clks 217 1>; 310 279 clock-names = "fck"; 311 280 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 281 + status = "disabled"; 312 282 }; 313 283 314 284 main_i2c4: i2c@2040000 { ··· 321 289 clocks = <&k3_clks 218 1>; 322 290 clock-names = "fck"; 323 291 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 292 + status = "disabled"; 324 293 }; 325 294 326 295 main_i2c5: i2c@2050000 { ··· 333 300 clocks = <&k3_clks 219 1>; 334 301 clock-names = "fck"; 335 302 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 303 + status = "disabled"; 336 304 }; 337 305 338 306 main_i2c6: i2c@2060000 { ··· 345 311 clocks = <&k3_clks 220 1>; 346 312 clock-names = "fck"; 347 313 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 314 + status = "disabled"; 348 315 }; 349 316 350 317 main_sdhci0: mmc@4f80000 { ··· 463 428 ti,mbox-num-users = <4>; 464 429 ti,mbox-num-fifos = <16>; 465 430 interrupt-parent = <&main_navss_intr>; 431 + status = "disabled"; 466 432 }; 467 433 468 434 mailbox0_cluster1: mailbox@31f81000 { ··· 473 437 ti,mbox-num-users = <4>; 474 438 ti,mbox-num-fifos = <16>; 475 439 interrupt-parent = <&main_navss_intr>; 440 + status = "disabled"; 476 441 }; 477 442 478 443 mailbox0_cluster2: mailbox@31f82000 { ··· 483 446 ti,mbox-num-users = <4>; 484 447 ti,mbox-num-fifos = <16>; 485 448 interrupt-parent = <&main_navss_intr>; 449 + status = "disabled"; 486 450 }; 487 451 488 452 mailbox0_cluster3: mailbox@31f83000 { ··· 493 455 ti,mbox-num-users = <4>; 494 456 ti,mbox-num-fifos = <16>; 495 457 interrupt-parent = <&main_navss_intr>; 458 + status = "disabled"; 496 459 }; 497 460 498 461 mailbox0_cluster4: mailbox@31f84000 { ··· 503 464 ti,mbox-num-users = <4>; 504 465 ti,mbox-num-fifos = <16>; 505 466 interrupt-parent = <&main_navss_intr>; 467 + status = "disabled"; 506 468 }; 507 469 508 470 mailbox0_cluster5: mailbox@31f85000 { ··· 513 473 ti,mbox-num-users = <4>; 514 474 ti,mbox-num-fifos = <16>; 515 475 interrupt-parent = <&main_navss_intr>; 476 + status = "disabled"; 516 477 }; 517 478 518 479 mailbox0_cluster6: mailbox@31f86000 { ··· 523 482 ti,mbox-num-users = <4>; 524 483 ti,mbox-num-fifos = <16>; 525 484 interrupt-parent = <&main_navss_intr>; 485 + status = "disabled"; 526 486 }; 527 487 528 488 mailbox0_cluster7: mailbox@31f87000 { ··· 533 491 ti,mbox-num-users = <4>; 534 492 ti,mbox-num-fifos = <16>; 535 493 interrupt-parent = <&main_navss_intr>; 494 + status = "disabled"; 536 495 }; 537 496 538 497 mailbox0_cluster8: mailbox@31f88000 { ··· 543 500 ti,mbox-num-users = <4>; 544 501 ti,mbox-num-fifos = <16>; 545 502 interrupt-parent = <&main_navss_intr>; 503 + status = "disabled"; 546 504 }; 547 505 548 506 mailbox0_cluster9: mailbox@31f89000 { ··· 553 509 ti,mbox-num-users = <4>; 554 510 ti,mbox-num-fifos = <16>; 555 511 interrupt-parent = <&main_navss_intr>; 512 + status = "disabled"; 556 513 }; 557 514 558 515 mailbox0_cluster10: mailbox@31f8a000 { ··· 563 518 ti,mbox-num-users = <4>; 564 519 ti,mbox-num-fifos = <16>; 565 520 interrupt-parent = <&main_navss_intr>; 521 + status = "disabled"; 566 522 }; 567 523 568 524 mailbox0_cluster11: mailbox@31f8b000 { ··· 573 527 ti,mbox-num-users = <4>; 574 528 ti,mbox-num-fifos = <16>; 575 529 interrupt-parent = <&main_navss_intr>; 530 + status = "disabled"; 576 531 }; 577 532 578 533 mailbox1_cluster0: mailbox@31f90000 { ··· 583 536 ti,mbox-num-users = <4>; 584 537 ti,mbox-num-fifos = <16>; 585 538 interrupt-parent = <&main_navss_intr>; 539 + status = "disabled"; 586 540 }; 587 541 588 542 mailbox1_cluster1: mailbox@31f91000 { ··· 593 545 ti,mbox-num-users = <4>; 594 546 ti,mbox-num-fifos = <16>; 595 547 interrupt-parent = <&main_navss_intr>; 548 + status = "disabled"; 596 549 }; 597 550 598 551 mailbox1_cluster2: mailbox@31f92000 { ··· 603 554 ti,mbox-num-users = <4>; 604 555 ti,mbox-num-fifos = <16>; 605 556 interrupt-parent = <&main_navss_intr>; 557 + status = "disabled"; 606 558 }; 607 559 608 560 mailbox1_cluster3: mailbox@31f93000 { ··· 613 563 ti,mbox-num-users = <4>; 614 564 ti,mbox-num-fifos = <16>; 615 565 interrupt-parent = <&main_navss_intr>; 566 + status = "disabled"; 616 567 }; 617 568 618 569 mailbox1_cluster4: mailbox@31f94000 { ··· 623 572 ti,mbox-num-users = <4>; 624 573 ti,mbox-num-fifos = <16>; 625 574 interrupt-parent = <&main_navss_intr>; 575 + status = "disabled"; 626 576 }; 627 577 628 578 mailbox1_cluster5: mailbox@31f95000 { ··· 633 581 ti,mbox-num-users = <4>; 634 582 ti,mbox-num-fifos = <16>; 635 583 interrupt-parent = <&main_navss_intr>; 584 + status = "disabled"; 636 585 }; 637 586 638 587 mailbox1_cluster6: mailbox@31f96000 { ··· 643 590 ti,mbox-num-users = <4>; 644 591 ti,mbox-num-fifos = <16>; 645 592 interrupt-parent = <&main_navss_intr>; 593 + status = "disabled"; 646 594 }; 647 595 648 596 mailbox1_cluster7: mailbox@31f97000 { ··· 653 599 ti,mbox-num-users = <4>; 654 600 ti,mbox-num-fifos = <16>; 655 601 interrupt-parent = <&main_navss_intr>; 602 + status = "disabled"; 656 603 }; 657 604 658 605 mailbox1_cluster8: mailbox@31f98000 { ··· 663 608 ti,mbox-num-users = <4>; 664 609 ti,mbox-num-fifos = <16>; 665 610 interrupt-parent = <&main_navss_intr>; 611 + status = "disabled"; 666 612 }; 667 613 668 614 mailbox1_cluster9: mailbox@31f99000 { ··· 673 617 ti,mbox-num-users = <4>; 674 618 ti,mbox-num-fifos = <16>; 675 619 interrupt-parent = <&main_navss_intr>; 620 + status = "disabled"; 676 621 }; 677 622 678 623 mailbox1_cluster10: mailbox@31f9a000 { ··· 683 626 ti,mbox-num-users = <4>; 684 627 ti,mbox-num-fifos = <16>; 685 628 interrupt-parent = <&main_navss_intr>; 629 + status = "disabled"; 686 630 }; 687 631 688 632 mailbox1_cluster11: mailbox@31f9b000 { ··· 693 635 ti,mbox-num-users = <4>; 694 636 ti,mbox-num-fifos = <16>; 695 637 interrupt-parent = <&main_navss_intr>; 638 + status = "disabled"; 696 639 }; 697 640 698 641 main_ringacc: ringacc@3c000000 { ··· 757 698 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 758 699 interrupt-names = "int0", "int1"; 759 700 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 701 + status = "disabled"; 760 702 }; 761 703 762 704 main_mcan1: can@2711000 { ··· 772 712 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 773 713 interrupt-names = "int0", "int1"; 774 714 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 715 + status = "disabled"; 775 716 }; 776 717 777 718 main_mcan2: can@2721000 { ··· 787 726 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 788 727 interrupt-names = "int0", "int1"; 789 728 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 729 + status = "disabled"; 790 730 }; 791 731 792 732 main_mcan3: can@2731000 { ··· 802 740 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 803 741 interrupt-names = "int0", "int1"; 804 742 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 743 + status = "disabled"; 805 744 }; 806 745 807 746 main_mcan4: can@2741000 { ··· 817 754 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 818 755 interrupt-names = "int0", "int1"; 819 756 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 757 + status = "disabled"; 820 758 }; 821 759 822 760 main_mcan5: can@2751000 { ··· 832 768 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 833 769 interrupt-names = "int0", "int1"; 834 770 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 771 + status = "disabled"; 835 772 }; 836 773 837 774 main_mcan6: can@2761000 { ··· 847 782 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 848 783 interrupt-names = "int0", "int1"; 849 784 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 785 + status = "disabled"; 850 786 }; 851 787 852 788 main_mcan7: can@2771000 { ··· 862 796 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 863 797 interrupt-names = "int0", "int1"; 864 798 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 799 + status = "disabled"; 865 800 }; 866 801 867 802 main_mcan8: can@2781000 { ··· 877 810 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 878 811 interrupt-names = "int0", "int1"; 879 812 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 813 + status = "disabled"; 880 814 }; 881 815 882 816 main_mcan9: can@2791000 { ··· 892 824 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 893 825 interrupt-names = "int0", "int1"; 894 826 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 827 + status = "disabled"; 895 828 }; 896 829 897 830 main_mcan10: can@27a1000 { ··· 907 838 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 908 839 interrupt-names = "int0", "int1"; 909 840 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 841 + status = "disabled"; 910 842 }; 911 843 912 844 main_mcan11: can@27b1000 { ··· 922 852 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 923 853 interrupt-names = "int0", "int1"; 924 854 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 855 + status = "disabled"; 925 856 }; 926 857 927 858 main_mcan12: can@27c1000 { ··· 937 866 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 938 867 interrupt-names = "int0", "int1"; 939 868 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 869 + status = "disabled"; 940 870 }; 941 871 942 872 main_mcan13: can@27d1000 { ··· 952 880 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 953 881 interrupt-names = "int0", "int1"; 954 882 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 883 + status = "disabled"; 955 884 }; 956 885 957 886 main_mcan14: can@2681000 { ··· 967 894 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 968 895 interrupt-names = "int0", "int1"; 969 896 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 897 + status = "disabled"; 970 898 }; 971 899 972 900 main_mcan15: can@2691000 { ··· 982 908 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 983 909 interrupt-names = "int0", "int1"; 984 910 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 911 + status = "disabled"; 985 912 }; 986 913 987 914 main_mcan16: can@26a1000 { ··· 997 922 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 998 923 interrupt-names = "int0", "int1"; 999 924 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 925 + status = "disabled"; 1000 926 }; 1001 927 1002 928 main_mcan17: can@26b1000 { ··· 1012 936 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1013 937 interrupt-names = "int0", "int1"; 1014 938 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 939 + status = "disabled"; 1015 940 }; 1016 941 };

+8 -1

arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi

··· 65 65 #interrupt-cells = <1>; 66 66 ti,sci = <&sms>; 67 67 ti,sci-dev-id = <125>; 68 - ti,interrupt-ranges = <16 928 16>; 68 + ti,interrupt-ranges = <16 960 16>; 69 69 }; 70 70 71 71 mcu_conf: syscon@40f00000 { ··· 91 91 clocks = <&k3_clks 359 3>; 92 92 clock-names = "fclk"; 93 93 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 94 + status = "disabled"; 94 95 }; 95 96 96 97 mcu_uart0: serial@40a00000 { ··· 102 101 clocks = <&k3_clks 149 3>; 103 102 clock-names = "fclk"; 104 103 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 104 + status = "disabled"; 105 105 }; 106 106 107 107 wkup_gpio0: gpio@42110000 { ··· 146 144 clocks = <&k3_clks 223 1>; 147 145 clock-names = "fck"; 148 146 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; 147 + status = "disabled"; 149 148 }; 150 149 151 150 mcu_i2c0: i2c@40b00000 { ··· 158 155 clocks = <&k3_clks 221 1>; 159 156 clock-names = "fck"; 160 157 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; 158 + status = "disabled"; 161 159 }; 162 160 163 161 mcu_i2c1: i2c@40b10000 { ··· 170 166 clocks = <&k3_clks 222 1>; 171 167 clock-names = "fck"; 172 168 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; 169 + status = "disabled"; 173 170 }; 174 171 175 172 mcu_mcan0: can@40528000 { ··· 185 180 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 186 181 interrupt-names = "int0", "int1"; 187 182 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 183 + status = "disabled"; 188 184 }; 189 185 190 186 mcu_mcan1: can@40568000 { ··· 200 194 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 201 195 interrupt-names = "int0", "int1"; 202 196 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 197 + status = "disabled"; 203 198 }; 204 199 205 200 mcu_navss: bus@28380000{

+2 -96

arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi

··· 56 56 }; 57 57 58 58 &main_i2c0 { 59 + status = "okay"; 59 60 pinctrl-names = "default"; 60 61 pinctrl-0 = <&main_i2c0_pins_default>; 61 62 clock-frequency = <400000>; ··· 74 73 }; 75 74 76 75 &main_mcan16 { 76 + status = "okay"; 77 77 pinctrl-0 = <&main_mcan16_pins_default>; 78 78 pinctrl-names = "default"; 79 79 phys = <&transceiver0>; 80 - }; 81 - 82 - &mailbox0_cluster0 { 83 - status = "disabled"; 84 - }; 85 - 86 - &mailbox0_cluster1 { 87 - status = "disabled"; 88 - }; 89 - 90 - &mailbox0_cluster2 { 91 - status = "disabled"; 92 - }; 93 - 94 - &mailbox0_cluster3 { 95 - status = "disabled"; 96 - }; 97 - 98 - &mailbox0_cluster4 { 99 - status = "disabled"; 100 - }; 101 - 102 - &mailbox0_cluster5 { 103 - status = "disabled"; 104 - }; 105 - 106 - &mailbox0_cluster6 { 107 - status = "disabled"; 108 - }; 109 - 110 - &mailbox0_cluster7 { 111 - status = "disabled"; 112 - }; 113 - 114 - &mailbox0_cluster8 { 115 - status = "disabled"; 116 - }; 117 - 118 - &mailbox0_cluster9 { 119 - status = "disabled"; 120 - }; 121 - 122 - &mailbox0_cluster10 { 123 - status = "disabled"; 124 - }; 125 - 126 - &mailbox0_cluster11 { 127 - status = "disabled"; 128 - }; 129 - 130 - &mailbox1_cluster0 { 131 - status = "disabled"; 132 - }; 133 - 134 - &mailbox1_cluster1 { 135 - status = "disabled"; 136 - }; 137 - 138 - &mailbox1_cluster2 { 139 - status = "disabled"; 140 - }; 141 - 142 - &mailbox1_cluster3 { 143 - status = "disabled"; 144 - }; 145 - 146 - &mailbox1_cluster4 { 147 - status = "disabled"; 148 - }; 149 - 150 - &mailbox1_cluster5 { 151 - status = "disabled"; 152 - }; 153 - 154 - &mailbox1_cluster6 { 155 - status = "disabled"; 156 - }; 157 - 158 - &mailbox1_cluster7 { 159 - status = "disabled"; 160 - }; 161 - 162 - &mailbox1_cluster8 { 163 - status = "disabled"; 164 - }; 165 - 166 - &mailbox1_cluster9 { 167 - status = "disabled"; 168 - }; 169 - 170 - &mailbox1_cluster10 { 171 - status = "disabled"; 172 - }; 173 - 174 - &mailbox1_cluster11 { 175 - status = "disabled"; 176 80 };

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