Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Add smuio v15_0_8 support v4
v15_0_8 is a new generation smuio ip block
v2: Add smuio callbacks for interface id
v3: Add smuio callback to identify custom hbm
v4: comment out unused functions (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Hawking Zhang
and committed by
Alex Deucher
591689cc
c3cd568d
+248
-1
+2
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+2
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h
···
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AMDGPU_PKG_TYPE_APU = 2,
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AMDGPU_PKG_TYPE_CEM = 3,
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AMDGPU_PKG_TYPE_OAM = 4,
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AMDGPU_PKG_TYPE_BB = 5,
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AMDGPU_PKG_TYPE_UNKNOWN,
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};
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···
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u32 (*get_socket_id)(struct amdgpu_device *adev);
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enum amdgpu_pkg_type (*get_pkg_type)(struct amdgpu_device *adev);
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bool (*is_host_gpu_xgmi_supported)(struct amdgpu_device *adev);
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bool (*is_connected_with_ethernet_switch)(struct amdgpu_device *adev);
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bool (*is_custom_hbm_supported)(struct amdgpu_device *adev);
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u64 (*get_gpu_clock_counter)(struct amdgpu_device *adev);
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};
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+213
drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c
+213
drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c
···
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "smuio_v15_0_8.h"
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#include "smuio/smuio_15_0_8_offset.h"
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#include "smuio/smuio_15_0_8_sh_mask.h"
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+
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#define SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK 0x00000001L
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#define SMUIO_MCM_CONFIG__ETHERNET_SWITCH_MASK 0x00000008L
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#define SMUIO_MCM_CONFIG__CUSTOM_HBM_MASK 0x00000001L
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+
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static u32 smuio_v15_0_8_get_rom_index_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(SMUIO, 0, regROM_INDEX);
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}
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+
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static u32 smuio_v15_0_8_get_rom_data_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(SMUIO, 0, regROM_DATA);
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}
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static void smuio_v15_0_8_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
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{
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return;
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}
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+
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static u64 smuio_v15_0_8_get_gpu_clock_counter(struct amdgpu_device *adev)
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{
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u64 clock;
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u64 clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;
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+
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preempt_disable();
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clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
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clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
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/* the clock counter may be udpated during polling the counters */
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clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
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if (clock_counter_hi_pre != clock_counter_hi_after)
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clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
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preempt_enable();
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+
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clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);
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return clock;
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}
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static void smuio_v15_0_8_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)
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{
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u32 data;
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+
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/* CGTT_ROM_CLK_CTRL0 is not available for APU */
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if (adev->flags & AMD_IS_APU)
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return;
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data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0);
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if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
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*flags |= AMD_CG_SUPPORT_ROM_MGCG;
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}
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+
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/**
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* smuio_v15_0_8_get_die_id - query die id from FCH.
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*
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* @adev: amdgpu device pointer
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*
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* Returns die id
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*/
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static u32 smuio_v15_0_8_get_die_id(struct amdgpu_device *adev)
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{
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u32 data, die_id;
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data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
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die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID);
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return die_id;
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}
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/**
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* smuio_v15_0_8_get_socket_id - query socket id from FCH
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*
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* @adev: amdgpu device pointer
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*
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* Returns socket id
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*/
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static u32 smuio_v15_0_8_get_socket_id(struct amdgpu_device *adev)
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{
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u32 data, socket_id;
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data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
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socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID);
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return socket_id;
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}
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/**
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* smuio_v15_0_8_is_host_gpu_xgmi_supported - detect xgmi interface between cpu and gpu/s.
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*
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* @adev: amdgpu device pointer
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*
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* Returns true on success or false otherwise.
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*/
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static bool smuio_v15_0_8_is_host_gpu_xgmi_supported(struct amdgpu_device *adev)
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{
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u32 data;
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data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
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data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID);
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/* data[4:0]
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* bit 0 == 0 host-gpu interface is PCIE
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* bit 0 == 1 host-gpu interface is Alternate Protocal
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* for AMD, this is XGMI
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*/
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data &= SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK;
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return data ? true : false;
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}
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#if 0
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/*
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* smuio_v15_0_8_is_connected_with_ethernet_switch - detect systems connected with ethernet switch
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*
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* @adev: amdgpu device pointer
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*
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* Returns true on success or false otherwise.
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*/
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static bool smuio_v15_0_8_is_connected_with_ethernet_switch(struct amdgpu_device *adev)
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{
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u32 data;
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if (!(adev->flags & AMD_IS_APU))
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return false;
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data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
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data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID);
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/* data[4:0]
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* bit 3 == 0 systems connected with ethernet switch
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*/
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data &= SMUIO_MCM_CONFIG__ETHERNET_SWITCH_MASK;
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return data ? false : true;
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}
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#endif
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static enum amdgpu_pkg_type smuio_v15_0_8_get_pkg_type(struct amdgpu_device *adev)
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{
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enum amdgpu_pkg_type pkg_type;
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u32 data;
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data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
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data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, PKG_TYPE);
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/* data [3:0]
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bit 2 and bit 3 identifies the pkg type */
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switch (data & 0xC) {
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case 0x0:
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pkg_type = AMDGPU_PKG_TYPE_BB;
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break;
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case 0x8:
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pkg_type = AMDGPU_PKG_TYPE_CEM;
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break;
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default:
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pkg_type = AMDGPU_PKG_TYPE_UNKNOWN;
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break;
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}
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return pkg_type;
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}
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#if 0
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static bool smuio_v15_0_8_is_custom_hbm_supported(struct amdgpu_device *adev)
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{
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u32 data;
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data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
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data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, PKG_TYPE);
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/* data [3:0]
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* bit 0 identifies custom HBM module */
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data &= SMUIO_MCM_CONFIG__CUSTOM_HBM_MASK;
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return data ? true : false;
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}
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#endif
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const struct amdgpu_smuio_funcs smuio_v15_0_8_funcs = {
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.get_rom_index_offset = smuio_v15_0_8_get_rom_index_offset,
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.get_rom_data_offset = smuio_v15_0_8_get_rom_data_offset,
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.get_gpu_clock_counter = smuio_v15_0_8_get_gpu_clock_counter,
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.get_die_id = smuio_v15_0_8_get_die_id,
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.get_socket_id = smuio_v15_0_8_get_socket_id,
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.is_host_gpu_xgmi_supported = smuio_v15_0_8_is_host_gpu_xgmi_supported,
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.update_rom_clock_gating = smuio_v15_0_8_update_rom_clock_gating,
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.get_clock_gating_state = smuio_v15_0_8_get_clock_gating_state,
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.get_pkg_type = smuio_v15_0_8_get_pkg_type,
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};
+30
drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.h
+30
drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.h
···
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
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+
*
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*/
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#ifndef __SMUIO_V15_0_8_H__
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#define __SMUIO_V15_0_8_H__
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#include "soc15_common.h"
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extern const struct amdgpu_smuio_funcs smuio_v15_0_8_funcs;
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#endif /* __SMUIO_V15_0_8_H__ */