Merge branch 'i2c/for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

-62

Documentation/devicetree/bindings/i2c/i2c-mpc.txt

··· 1 - * I2C 2 - 3 - Required properties : 4 - 5 - - reg : Offset and length of the register set for the device 6 - - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a 7 - compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121, 8 - mpc5200 or mpc5200b. For the mpc5121, an additional node 9 - "fsl,mpc5121-i2c-ctrl" is required as shown in the example below. 10 - 11 - Recommended properties : 12 - 13 - - interrupts : <a b> where a is the interrupt number and b is a 14 - field that represents an encoding of the sense and level 15 - information for the interrupt. This should be encoded based on 16 - the information in section 2) depending on the type of interrupt 17 - controller you have. 18 - - fsl,preserve-clocking : boolean; if defined, the clock settings 19 - from the bootloader are preserved (not touched). 20 - - clock-frequency : desired I2C bus clock frequency in Hz. 21 - - fsl,timeout : I2C bus timeout in microseconds. 22 - 23 - Examples : 24 - 25 - /* MPC5121 based board */ 26 - i2c@1740 { 27 - #address-cells = <1>; 28 - #size-cells = <0>; 29 - compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 30 - reg = <0x1740 0x20>; 31 - interrupts = <11 0x8>; 32 - interrupt-parent = <&ipic>; 33 - clock-frequency = <100000>; 34 - }; 35 - 36 - i2ccontrol@1760 { 37 - compatible = "fsl,mpc5121-i2c-ctrl"; 38 - reg = <0x1760 0x8>; 39 - }; 40 - 41 - /* MPC5200B based board */ 42 - i2c@3d00 { 43 - #address-cells = <1>; 44 - #size-cells = <0>; 45 - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 46 - reg = <0x3d00 0x40>; 47 - interrupts = <2 15 0>; 48 - interrupt-parent = <&mpc5200_pic>; 49 - fsl,preserve-clocking; 50 - }; 51 - 52 - /* MPC8544 base board */ 53 - i2c@3100 { 54 - #address-cells = <1>; 55 - #size-cells = <0>; 56 - compatible = "fsl,mpc8544-i2c", "fsl-i2c"; 57 - reg = <0x3100 0x100>; 58 - interrupts = <43 2>; 59 - interrupt-parent = <&mpic>; 60 - clock-frequency = <400000>; 61 - fsl,timeout = <10000>; 62 - };

+91

Documentation/devicetree/bindings/i2c/i2c-mpc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i2c/i2c-mpc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: I2C-Bus adapter for MPC824x/83xx/85xx/86xx/512x/52xx SoCs 8 + 9 + maintainers: 10 + - Chris Packham <chris.packham@alliedtelesis.co.nz> 11 + 12 + allOf: 13 + - $ref: /schemas/i2c/i2c-controller.yaml# 14 + 15 + properties: 16 + compatible: 17 + oneOf: 18 + - items: 19 + - enum: 20 + - mpc5200-i2c 21 + - fsl,mpc5200-i2c 22 + - fsl,mpc5121-i2c 23 + - fsl,mpc8313-i2c 24 + - fsl,mpc8543-i2c 25 + - fsl,mpc8544-i2c 26 + - const: fsl-i2c 27 + - items: 28 + - const: fsl,mpc5200b-i2c 29 + - const: fsl,mpc5200-i2c 30 + - const: fsl-i2c 31 + 32 + reg: 33 + maxItems: 1 34 + 35 + interrupts: 36 + maxItems: 1 37 + 38 + fsl,preserve-clocking: 39 + $ref: /schemas/types.yaml#/definitions/flag 40 + description: | 41 + if defined, the clock settings from the bootloader are 42 + preserved (not touched) 43 + 44 + fsl,timeout: 45 + $ref: /schemas/types.yaml#/definitions/uint32 46 + description: | 47 + I2C bus timeout in microseconds 48 + 49 + required: 50 + - compatible 51 + - reg 52 + - interrupts 53 + 54 + unevaluatedProperties: false 55 + 56 + examples: 57 + - | 58 + /* MPC5121 based board */ 59 + i2c@1740 { 60 + #address-cells = <1>; 61 + #size-cells = <0>; 62 + compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 63 + reg = <0x1740 0x20>; 64 + interrupts = <11 0x8>; 65 + interrupt-parent = <&ipic>; 66 + clock-frequency = <100000>; 67 + }; 68 + 69 + /* MPC5200B based board */ 70 + i2c@3d00 { 71 + #address-cells = <1>; 72 + #size-cells = <0>; 73 + compatible = "fsl,mpc5200b-i2c", "fsl,mpc5200-i2c", "fsl-i2c"; 74 + reg = <0x3d00 0x40>; 75 + interrupts = <2 15 0>; 76 + interrupt-parent = <&mpc5200_pic>; 77 + fsl,preserve-clocking; 78 + }; 79 + 80 + /* MPC8544 base board */ 81 + i2c@3100 { 82 + #address-cells = <1>; 83 + #size-cells = <0>; 84 + compatible = "fsl,mpc8544-i2c", "fsl-i2c"; 85 + reg = <0x3100 0x100>; 86 + interrupts = <43 2>; 87 + interrupt-parent = <&mpic>; 88 + clock-frequency = <400000>; 89 + fsl,timeout = <10000>; 90 + }; 91 + ...

+19

MAINTAINERS

··· 4662 4662 F: include/linux/counter.h 4663 4663 F: include/linux/counter_enum.h 4664 4664 4665 + CP2615 I2C DRIVER 4666 + M: Bence Csókás <bence98@sch.bme.hu> 4667 + S: Maintained 4668 + F: drivers/i2c/busses/i2c-cp2615.c 4669 + 4665 4670 CPMAC ETHERNET DRIVER 4666 4671 M: Florian Fainelli <f.fainelli@gmail.com> 4667 4672 L: netdev@vger.kernel.org ··· 7240 7235 F: Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml 7241 7236 F: drivers/i2c/busses/i2c-imx-lpi2c.c 7242 7237 7238 + FREESCALE MPC I2C DRIVER 7239 + M: Chris Packham <chris.packham@alliedtelesis.co.nz> 7240 + L: linux-i2c@vger.kernel.org 7241 + S: Maintained 7242 + F: Documentation/devicetree/bindings/i2c/i2c-mpc.yaml 7243 + F: drivers/i2c/busses/i2c-mpc.c 7244 + 7243 7245 FREESCALE QORIQ DPAA ETHERNET DRIVER 7244 7246 M: Madalin Bucur <madalin.bucur@nxp.com> 7245 7247 L: netdev@vger.kernel.org ··· 8168 8156 F: drivers/crypto/hisilicon/hpre/hpre.h 8169 8157 F: drivers/crypto/hisilicon/hpre/hpre_crypto.c 8170 8158 F: drivers/crypto/hisilicon/hpre/hpre_main.c 8159 + 8160 + HISILICON I2C CONTROLLER DRIVER 8161 + M: Yicong Yang <yangyicong@hisilicon.com> 8162 + L: linux-i2c@vger.kernel.org 8163 + S: Maintained 8164 + W: https://www.hisilicon.com 8165 + F: drivers/i2c/busses/i2c-hisi.c 8171 8166 8172 8167 HISILICON LPC BUS DRIVER 8173 8168 M: john.garry@huawei.com

+5 -1

arch/arm/mach-davinci/board-da830-evm.c

··· 454 454 { } 455 455 }; 456 456 457 + static const struct software_node da830_evm_i2c_eeprom_node = { 458 + .properties = da830_evm_i2c_eeprom_properties, 459 + }; 460 + 457 461 static int __init da830_evm_ui_expander_setup(struct i2c_client *client, 458 462 int gpio, unsigned ngpio, void *context) 459 463 { ··· 489 485 static struct i2c_board_info __initdata da830_evm_i2c_devices[] = { 490 486 { 491 487 I2C_BOARD_INFO("24c256", 0x50), 492 - .properties = da830_evm_i2c_eeprom_properties, 488 + .swnode = &da830_evm_i2c_eeprom_node, 493 489 }, 494 490 { 495 491 I2C_BOARD_INFO("tlv320aic3x", 0x18),

+5 -1

arch/arm/mach-davinci/board-dm365-evm.c

··· 232 232 { } 233 233 }; 234 234 235 + static const struct software_node eeprom_node = { 236 + .properties = eeprom_properties, 237 + }; 238 + 235 239 static struct i2c_board_info i2c_info[] = { 236 240 { 237 241 I2C_BOARD_INFO("24c256", 0x50), 238 - .properties = eeprom_properties, 242 + .swnode = &eeprom_node, 239 243 }, 240 244 { 241 245 I2C_BOARD_INFO("tlv320aic3x", 0x18),

+5 -1

arch/arm/mach-davinci/board-dm644x-evm.c

··· 541 541 { } 542 542 }; 543 543 544 + static const struct software_node eeprom_node = { 545 + .properties = eeprom_properties, 546 + }; 547 + 544 548 /* 545 549 * MSP430 supports RTC, card detection, input from IR remote, and 546 550 * a bit more. It triggers interrupts on GPIO(7) from pressing ··· 651 647 }, 652 648 { 653 649 I2C_BOARD_INFO("24c256", 0x50), 654 - .properties = eeprom_properties, 650 + .swnode = &eeprom_node, 655 651 }, 656 652 { 657 653 I2C_BOARD_INFO("tlv320aic33", 0x1b),

+5 -1

arch/arm/mach-davinci/board-dm646x-evm.c

··· 362 362 PROPERTY_ENTRY_U32("pagesize", 64), 363 363 { } 364 364 }; 365 + 366 + static const struct software_node eeprom_node = { 367 + .properties = eeprom_properties, 368 + }; 365 369 #endif 366 370 367 371 static u8 dm646x_iis_serializer_direction[] = { ··· 434 430 static struct i2c_board_info __initdata i2c_info[] = { 435 431 { 436 432 I2C_BOARD_INFO("24c256", 0x50), 437 - .properties = eeprom_properties, 433 + .swnode = &eeprom_node, 438 434 }, 439 435 { 440 436 I2C_BOARD_INFO("pcf8574a", 0x38),

+5 -1

arch/arm/mach-davinci/board-mityomapl138.c

··· 197 197 { } 198 198 }; 199 199 200 + static const struct software_node mityomapl138_fd_chip_node = { 201 + .properties = mityomapl138_fd_chip_properties, 202 + }; 203 + 200 204 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { 201 205 .bus_freq = 100, /* kHz */ 202 206 .bus_delay = 0, /* usec */ ··· 327 323 }, 328 324 { 329 325 I2C_BOARD_INFO("24c02", 0x50), 330 - .properties = mityomapl138_fd_chip_properties, 326 + .swnode = &mityomapl138_fd_chip_node, 331 327 }, 332 328 }; 333 329

+5 -1

arch/arm/mach-davinci/board-sffsdr.c

··· 84 84 { } 85 85 }; 86 86 87 + static const struct software_node eeprom_node = { 88 + .properties = eeprom_properties, 89 + }; 90 + 87 91 static struct i2c_board_info __initdata i2c_info[] = { 88 92 { 89 93 I2C_BOARD_INFO("24c64", 0x50), 90 - .properties = eeprom_properties, 94 + .swnode = &eeprom_node, 91 95 }, 92 96 /* Other I2C devices: 93 97 * MSP430, addr 0x23 (not used)

+5 -1

arch/arm/mach-omap1/board-osk.c

··· 332 332 { } 333 333 }; 334 334 335 + static const struct software_node mistral_at24_node = { 336 + .properties = mistral_at24_properties, 337 + }; 338 + 335 339 static struct i2c_board_info __initdata mistral_i2c_board_info[] = { 336 340 { 337 341 /* NOTE: powered from LCD supply */ 338 342 I2C_BOARD_INFO("24c04", 0x50), 339 - .properties = mistral_at24_properties, 343 + .swnode = &mistral_at24_node, 340 344 }, 341 345 /* TODO when driver support is ready: 342 346 * - optionally ov9640 camera sensor at 0x30

+5 -1

arch/arm/mach-pxa/stargate2.c

··· 794 794 { } 795 795 }; 796 796 797 + static const struct software_node pca9500_eeprom_node = { 798 + .properties = pca9500_eeprom_properties, 799 + }; 800 + 797 801 /** 798 802 * stargate2_reset_bluetooth() reset the bluecore to ensure consistent state 799 803 **/ ··· 933 929 }, { 934 930 .type = "24c02", 935 931 .addr = 0x57, 936 - .properties = pca9500_eeprom_properties, 932 + .swnode = &pca9500_eeprom_node, 937 933 }, { 938 934 .type = "max1238", 939 935 .addr = 0x35,

+5 -1

arch/arm/mach-s3c/mach-mini2440.c

··· 542 542 { } 543 543 }; 544 544 545 + static const struct software_node mini2440_at24_node = { 546 + .properties = mini2440_at24_properties, 547 + }; 548 + 545 549 static struct i2c_board_info mini2440_i2c_devs[] __initdata = { 546 550 { 547 551 I2C_BOARD_INFO("24c08", 0x50), 548 - .properties = mini2440_at24_properties, 552 + .swnode = &mini2440_at24_node, 549 553 }, 550 554 }; 551 555

+20

drivers/i2c/busses/Kconfig

··· 645 645 This driver can also be built as a module. If so, the module 646 646 will be called i2c-highlander. 647 647 648 + config I2C_HISI 649 + tristate "HiSilicon I2C controller" 650 + depends on ARM64 || COMPILE_TEST 651 + help 652 + Say Y here if you want to have Hisilicon I2C controller support 653 + available on the Kunpeng Server. 654 + 655 + This driver can also be built as a module. If so, the module 656 + will be called i2c-hisi. 657 + 648 658 config I2C_IBM_IIC 649 659 tristate "IBM PPC 4xx on-chip I2C interface" 650 660 depends on 4xx ··· 1208 1198 1209 1199 This driver can also be built as a module. If so, the module 1210 1200 will be called i2c-dln2. 1201 + 1202 + config I2C_CP2615 1203 + tristate "Silicon Labs CP2615 USB sound card and I2C adapter" 1204 + depends on USB 1205 + help 1206 + If you say yes to this option, support will be included for Silicon 1207 + Labs CP2615's I2C interface. 1208 + 1209 + This driver can also be built as a module. If so, the module 1210 + will be called i2c-cp2615. 1211 1211 1212 1212 config I2C_PARPORT 1213 1213 tristate "Parallel port adapter"

+2

drivers/i2c/busses/Makefile

··· 63 63 obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o 64 64 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o 65 65 obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o 66 + obj-$(CONFIG_I2C_HISI) += i2c-hisi.o 66 67 obj-$(CONFIG_I2C_HIX5HD2) += i2c-hix5hd2.o 67 68 obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o 68 69 obj-$(CONFIG_I2C_IMG) += i2c-img-scb.o ··· 124 123 # External I2C/SMBus adapter drivers 125 124 obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o 126 125 obj-$(CONFIG_I2C_DLN2) += i2c-dln2.o 126 + obj-$(CONFIG_I2C_CP2615) += i2c-cp2615.o 127 127 obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o 128 128 obj-$(CONFIG_I2C_ROBOTFUZZ_OSIF) += i2c-robotfuzz-osif.o 129 129 obj-$(CONFIG_I2C_TAOS_EVM) += i2c-taos-evm.o

+136 -136

drivers/i2c/busses/i2c-amd8111.c

··· 186 186 #define AMD_SMB_PRTCL_PEC 0x80 187 187 188 188 189 - static s32 amd8111_access(struct i2c_adapter * adap, u16 addr, 189 + static s32 amd8111_access(struct i2c_adapter *adap, u16 addr, 190 190 unsigned short flags, char read_write, u8 command, int size, 191 - union i2c_smbus_data * data) 191 + union i2c_smbus_data *data) 192 192 { 193 193 struct amd_smbus *smbus = adap->algo_data; 194 194 unsigned char protocol, len, pec, temp[2]; ··· 199 199 pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0; 200 200 201 201 switch (size) { 202 - case I2C_SMBUS_QUICK: 203 - protocol |= AMD_SMB_PRTCL_QUICK; 204 - read_write = I2C_SMBUS_WRITE; 205 - break; 202 + case I2C_SMBUS_QUICK: 203 + protocol |= AMD_SMB_PRTCL_QUICK; 204 + read_write = I2C_SMBUS_WRITE; 205 + break; 206 206 207 - case I2C_SMBUS_BYTE: 208 - if (read_write == I2C_SMBUS_WRITE) { 209 - status = amd_ec_write(smbus, AMD_SMB_CMD, 210 - command); 211 - if (status) 212 - return status; 213 - } 214 - protocol |= AMD_SMB_PRTCL_BYTE; 215 - break; 216 - 217 - case I2C_SMBUS_BYTE_DATA: 218 - status = amd_ec_write(smbus, AMD_SMB_CMD, command); 207 + case I2C_SMBUS_BYTE: 208 + if (read_write == I2C_SMBUS_WRITE) { 209 + status = amd_ec_write(smbus, AMD_SMB_CMD, 210 + command); 219 211 if (status) 220 212 return status; 221 - if (read_write == I2C_SMBUS_WRITE) { 222 - status = amd_ec_write(smbus, AMD_SMB_DATA, 223 - data->byte); 224 - if (status) 225 - return status; 226 - } 227 - protocol |= AMD_SMB_PRTCL_BYTE_DATA; 228 - break; 213 + } 214 + protocol |= AMD_SMB_PRTCL_BYTE; 215 + break; 229 216 230 - case I2C_SMBUS_WORD_DATA: 231 - status = amd_ec_write(smbus, AMD_SMB_CMD, command); 232 - if (status) 233 - return status; 234 - if (read_write == I2C_SMBUS_WRITE) { 235 - status = amd_ec_write(smbus, AMD_SMB_DATA, 236 - data->word & 0xff); 237 - if (status) 238 - return status; 239 - status = amd_ec_write(smbus, AMD_SMB_DATA + 1, 240 - data->word >> 8); 241 - if (status) 242 - return status; 243 - } 244 - protocol |= AMD_SMB_PRTCL_WORD_DATA | pec; 245 - break; 246 - 247 - case I2C_SMBUS_BLOCK_DATA: 248 - status = amd_ec_write(smbus, AMD_SMB_CMD, command); 249 - if (status) 250 - return status; 251 - if (read_write == I2C_SMBUS_WRITE) { 252 - len = min_t(u8, data->block[0], 253 - I2C_SMBUS_BLOCK_MAX); 254 - status = amd_ec_write(smbus, AMD_SMB_BCNT, len); 255 - if (status) 256 - return status; 257 - for (i = 0; i < len; i++) { 258 - status = 259 - amd_ec_write(smbus, AMD_SMB_DATA + i, 260 - data->block[i + 1]); 261 - if (status) 262 - return status; 263 - } 264 - } 265 - protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec; 266 - break; 267 - 268 - case I2C_SMBUS_I2C_BLOCK_DATA: 269 - len = min_t(u8, data->block[0], 270 - I2C_SMBUS_BLOCK_MAX); 271 - status = amd_ec_write(smbus, AMD_SMB_CMD, command); 272 - if (status) 273 - return status; 274 - status = amd_ec_write(smbus, AMD_SMB_BCNT, len); 275 - if (status) 276 - return status; 277 - if (read_write == I2C_SMBUS_WRITE) 278 - for (i = 0; i < len; i++) { 279 - status = 280 - amd_ec_write(smbus, AMD_SMB_DATA + i, 281 - data->block[i + 1]); 282 - if (status) 283 - return status; 284 - } 285 - protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA; 286 - break; 287 - 288 - case I2C_SMBUS_PROC_CALL: 289 - status = amd_ec_write(smbus, AMD_SMB_CMD, command); 290 - if (status) 291 - return status; 217 + case I2C_SMBUS_BYTE_DATA: 218 + status = amd_ec_write(smbus, AMD_SMB_CMD, command); 219 + if (status) 220 + return status; 221 + if (read_write == I2C_SMBUS_WRITE) { 292 222 status = amd_ec_write(smbus, AMD_SMB_DATA, 293 - data->word & 0xff); 223 + data->byte); 224 + if (status) 225 + return status; 226 + } 227 + protocol |= AMD_SMB_PRTCL_BYTE_DATA; 228 + break; 229 + 230 + case I2C_SMBUS_WORD_DATA: 231 + status = amd_ec_write(smbus, AMD_SMB_CMD, command); 232 + if (status) 233 + return status; 234 + if (read_write == I2C_SMBUS_WRITE) { 235 + status = amd_ec_write(smbus, AMD_SMB_DATA, 236 + data->word & 0xff); 294 237 if (status) 295 238 return status; 296 239 status = amd_ec_write(smbus, AMD_SMB_DATA + 1, 297 - data->word >> 8); 240 + data->word >> 8); 298 241 if (status) 299 242 return status; 300 - protocol = AMD_SMB_PRTCL_PROC_CALL | pec; 301 - read_write = I2C_SMBUS_READ; 302 - break; 243 + } 244 + protocol |= AMD_SMB_PRTCL_WORD_DATA | pec; 245 + break; 303 246 304 - case I2C_SMBUS_BLOCK_PROC_CALL: 247 + case I2C_SMBUS_BLOCK_DATA: 248 + status = amd_ec_write(smbus, AMD_SMB_CMD, command); 249 + if (status) 250 + return status; 251 + if (read_write == I2C_SMBUS_WRITE) { 305 252 len = min_t(u8, data->block[0], 306 - I2C_SMBUS_BLOCK_MAX - 1); 307 - status = amd_ec_write(smbus, AMD_SMB_CMD, command); 308 - if (status) 309 - return status; 253 + I2C_SMBUS_BLOCK_MAX); 310 254 status = amd_ec_write(smbus, AMD_SMB_BCNT, len); 311 255 if (status) 312 256 return status; 313 257 for (i = 0; i < len; i++) { 314 - status = amd_ec_write(smbus, AMD_SMB_DATA + i, 315 - data->block[i + 1]); 258 + status = 259 + amd_ec_write(smbus, AMD_SMB_DATA + i, 260 + data->block[i + 1]); 316 261 if (status) 317 262 return status; 318 263 } 319 - protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec; 320 - read_write = I2C_SMBUS_READ; 321 - break; 264 + } 265 + protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec; 266 + break; 322 267 323 - default: 324 - dev_warn(&adap->dev, "Unsupported transaction %d\n", size); 325 - return -EOPNOTSUPP; 268 + case I2C_SMBUS_I2C_BLOCK_DATA: 269 + len = min_t(u8, data->block[0], 270 + I2C_SMBUS_BLOCK_MAX); 271 + status = amd_ec_write(smbus, AMD_SMB_CMD, command); 272 + if (status) 273 + return status; 274 + status = amd_ec_write(smbus, AMD_SMB_BCNT, len); 275 + if (status) 276 + return status; 277 + if (read_write == I2C_SMBUS_WRITE) 278 + for (i = 0; i < len; i++) { 279 + status = 280 + amd_ec_write(smbus, AMD_SMB_DATA + i, 281 + data->block[i + 1]); 282 + if (status) 283 + return status; 284 + } 285 + protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA; 286 + break; 287 + 288 + case I2C_SMBUS_PROC_CALL: 289 + status = amd_ec_write(smbus, AMD_SMB_CMD, command); 290 + if (status) 291 + return status; 292 + status = amd_ec_write(smbus, AMD_SMB_DATA, 293 + data->word & 0xff); 294 + if (status) 295 + return status; 296 + status = amd_ec_write(smbus, AMD_SMB_DATA + 1, 297 + data->word >> 8); 298 + if (status) 299 + return status; 300 + protocol = AMD_SMB_PRTCL_PROC_CALL | pec; 301 + read_write = I2C_SMBUS_READ; 302 + break; 303 + 304 + case I2C_SMBUS_BLOCK_PROC_CALL: 305 + len = min_t(u8, data->block[0], 306 + I2C_SMBUS_BLOCK_MAX - 1); 307 + status = amd_ec_write(smbus, AMD_SMB_CMD, command); 308 + if (status) 309 + return status; 310 + status = amd_ec_write(smbus, AMD_SMB_BCNT, len); 311 + if (status) 312 + return status; 313 + for (i = 0; i < len; i++) { 314 + status = amd_ec_write(smbus, AMD_SMB_DATA + i, 315 + data->block[i + 1]); 316 + if (status) 317 + return status; 318 + } 319 + protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec; 320 + read_write = I2C_SMBUS_READ; 321 + break; 322 + 323 + default: 324 + dev_warn(&adap->dev, "Unsupported transaction %d\n", size); 325 + return -EOPNOTSUPP; 326 326 } 327 327 328 328 status = amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1); ··· 357 357 return 0; 358 358 359 359 switch (size) { 360 - case I2C_SMBUS_BYTE: 361 - case I2C_SMBUS_BYTE_DATA: 362 - status = amd_ec_read(smbus, AMD_SMB_DATA, &data->byte); 363 - if (status) 364 - return status; 365 - break; 360 + case I2C_SMBUS_BYTE: 361 + case I2C_SMBUS_BYTE_DATA: 362 + status = amd_ec_read(smbus, AMD_SMB_DATA, &data->byte); 363 + if (status) 364 + return status; 365 + break; 366 366 367 - case I2C_SMBUS_WORD_DATA: 368 - case I2C_SMBUS_PROC_CALL: 369 - status = amd_ec_read(smbus, AMD_SMB_DATA, temp + 0); 370 - if (status) 371 - return status; 372 - status = amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1); 373 - if (status) 374 - return status; 375 - data->word = (temp[1] << 8) | temp[0]; 376 - break; 367 + case I2C_SMBUS_WORD_DATA: 368 + case I2C_SMBUS_PROC_CALL: 369 + status = amd_ec_read(smbus, AMD_SMB_DATA, temp + 0); 370 + if (status) 371 + return status; 372 + status = amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1); 373 + if (status) 374 + return status; 375 + data->word = (temp[1] << 8) | temp[0]; 376 + break; 377 377 378 - case I2C_SMBUS_BLOCK_DATA: 379 - case I2C_SMBUS_BLOCK_PROC_CALL: 380 - status = amd_ec_read(smbus, AMD_SMB_BCNT, &len); 378 + case I2C_SMBUS_BLOCK_DATA: 379 + case I2C_SMBUS_BLOCK_PROC_CALL: 380 + status = amd_ec_read(smbus, AMD_SMB_BCNT, &len); 381 + if (status) 382 + return status; 383 + len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX); 384 + fallthrough; 385 + case I2C_SMBUS_I2C_BLOCK_DATA: 386 + for (i = 0; i < len; i++) { 387 + status = amd_ec_read(smbus, AMD_SMB_DATA + i, 388 + data->block + i + 1); 381 389 if (status) 382 390 return status; 383 - len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX); 384 - fallthrough; 385 - case I2C_SMBUS_I2C_BLOCK_DATA: 386 - for (i = 0; i < len; i++) { 387 - status = amd_ec_read(smbus, AMD_SMB_DATA + i, 388 - data->block + i + 1); 389 - if (status) 390 - return status; 391 - } 392 - data->block[0] = len; 393 - break; 391 + } 392 + data->block[0] = len; 393 + break; 394 394 } 395 395 396 396 return 0;

-1

drivers/i2c/busses/i2c-brcmstb.c

··· 22 22 #include <linux/platform_device.h> 23 23 #include <linux/sched.h> 24 24 #include <linux/slab.h> 25 - #include <linux/version.h> 26 25 27 26 #define N_DATA_REGS 8 28 27

+6 -3

drivers/i2c/busses/i2c-cadence.c

··· 789 789 bool change_role = false; 790 790 #endif 791 791 792 - ret = pm_runtime_get_sync(id->dev); 792 + ret = pm_runtime_resume_and_get(id->dev); 793 793 if (ret < 0) 794 794 return ret; 795 795 ··· 911 911 if (slave->flags & I2C_CLIENT_TEN) 912 912 return -EAFNOSUPPORT; 913 913 914 - ret = pm_runtime_get_sync(id->dev); 914 + ret = pm_runtime_resume_and_get(id->dev); 915 915 if (ret < 0) 916 916 return ret; 917 917 ··· 1200 1200 if (IS_ERR(id->membase)) 1201 1201 return PTR_ERR(id->membase); 1202 1202 1203 - id->irq = platform_get_irq(pdev, 0); 1203 + ret = platform_get_irq(pdev, 0); 1204 + if (ret < 0) 1205 + return ret; 1206 + id->irq = ret; 1204 1207 1205 1208 id->adap.owner = THIS_MODULE; 1206 1209 id->adap.dev.of_node = pdev->dev.of_node;

+5 -1

drivers/i2c/busses/i2c-cht-wc.c

··· 280 280 { } 281 281 }; 282 282 283 + static const struct software_node bq24190_node = { 284 + .properties = bq24190_props, 285 + }; 286 + 283 287 static struct regulator_consumer_supply fusb302_consumer = { 284 288 .supply = "vbus", 285 289 /* Must match fusb302 dev_name in intel_cht_int33fe.c */ ··· 312 308 .type = "bq24190", 313 309 .addr = 0x6b, 314 310 .dev_name = "bq24190", 315 - .properties = bq24190_props, 311 + .swnode = &bq24190_node, 316 312 .platform_data = &bq24190_pdata, 317 313 }; 318 314 int ret, reg, irq;

+330

drivers/i2c/busses/i2c-cp2615.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 + /* 3 + * i2c support for Silicon Labs' CP2615 Digital Audio Bridge 4 + * 5 + * (c) 2021, Bence Csókás <bence98@sch.bme.hu> 6 + */ 7 + 8 + #include <linux/errno.h> 9 + #include <linux/i2c.h> 10 + #include <linux/kernel.h> 11 + #include <linux/module.h> 12 + #include <linux/string.h> 13 + #include <linux/usb.h> 14 + 15 + /** CP2615 I/O Protocol implementation */ 16 + 17 + #define CP2615_VID 0x10c4 18 + #define CP2615_PID 0xeac1 19 + 20 + #define IOP_EP_IN 0x82 21 + #define IOP_EP_OUT 0x02 22 + #define IOP_IFN 1 23 + #define IOP_ALTSETTING 2 24 + 25 + #define MAX_IOP_SIZE 64 26 + #define MAX_IOP_PAYLOAD_SIZE (MAX_IOP_SIZE - 6) 27 + #define MAX_I2C_SIZE (MAX_IOP_PAYLOAD_SIZE - 4) 28 + 29 + enum cp2615_iop_msg_type { 30 + iop_GetAccessoryInfo = 0xD100, 31 + iop_AccessoryInfo = 0xA100, 32 + iop_GetPortConfiguration = 0xD203, 33 + iop_PortConfiguration = 0xA203, 34 + iop_DoI2cTransfer = 0xD400, 35 + iop_I2cTransferResult = 0xA400, 36 + iop_GetSerialState = 0xD501, 37 + iop_SerialState = 0xA501 38 + }; 39 + 40 + struct __packed cp2615_iop_msg { 41 + __be16 preamble, length, msg; 42 + u8 data[MAX_IOP_PAYLOAD_SIZE]; 43 + }; 44 + 45 + #define PART_ID_A01 0x1400 46 + #define PART_ID_A02 0x1500 47 + 48 + struct __packed cp2615_iop_accessory_info { 49 + __be16 part_id, option_id, proto_ver; 50 + }; 51 + 52 + struct __packed cp2615_i2c_transfer { 53 + u8 tag, i2caddr, read_len, write_len; 54 + u8 data[MAX_I2C_SIZE]; 55 + }; 56 + 57 + /* Possible values for struct cp2615_i2c_transfer_result.status */ 58 + enum cp2615_i2c_status { 59 + /* Writing to the internal EEPROM failed, because it is locked */ 60 + CP2615_CFG_LOCKED = -6, 61 + /* read_len or write_len out of range */ 62 + CP2615_INVALID_PARAM = -4, 63 + /* I2C slave did not ACK in time */ 64 + CP2615_TIMEOUT, 65 + /* I2C bus busy */ 66 + CP2615_BUS_BUSY, 67 + /* I2C bus error (ie. device NAK'd the request) */ 68 + CP2615_BUS_ERROR, 69 + CP2615_SUCCESS 70 + }; 71 + 72 + struct __packed cp2615_i2c_transfer_result { 73 + u8 tag, i2caddr; 74 + s8 status; 75 + u8 read_len; 76 + u8 data[MAX_I2C_SIZE]; 77 + }; 78 + 79 + static int cp2615_init_iop_msg(struct cp2615_iop_msg *ret, enum cp2615_iop_msg_type msg, 80 + const void *data, size_t data_len) 81 + { 82 + if (data_len > MAX_IOP_PAYLOAD_SIZE) 83 + return -EFBIG; 84 + 85 + if (!ret) 86 + return -EINVAL; 87 + 88 + ret->preamble = 0x2A2A; 89 + ret->length = htons(data_len + 6); 90 + ret->msg = htons(msg); 91 + if (data && data_len) 92 + memcpy(&ret->data, data, data_len); 93 + return 0; 94 + } 95 + 96 + static int cp2615_init_i2c_msg(struct cp2615_iop_msg *ret, const struct cp2615_i2c_transfer *data) 97 + { 98 + return cp2615_init_iop_msg(ret, iop_DoI2cTransfer, data, 4 + data->write_len); 99 + } 100 + 101 + /* Translates status codes to Linux errno's */ 102 + static int cp2615_check_status(enum cp2615_i2c_status status) 103 + { 104 + switch (status) { 105 + case CP2615_SUCCESS: 106 + return 0; 107 + case CP2615_BUS_ERROR: 108 + return -ENXIO; 109 + case CP2615_BUS_BUSY: 110 + return -EAGAIN; 111 + case CP2615_TIMEOUT: 112 + return -ETIMEDOUT; 113 + case CP2615_INVALID_PARAM: 114 + return -EINVAL; 115 + case CP2615_CFG_LOCKED: 116 + return -EPERM; 117 + } 118 + /* Unknown error code */ 119 + return -EPROTO; 120 + } 121 + 122 + /** Driver code */ 123 + 124 + static int 125 + cp2615_i2c_send(struct usb_interface *usbif, struct cp2615_i2c_transfer *i2c_w) 126 + { 127 + struct cp2615_iop_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL); 128 + struct usb_device *usbdev = interface_to_usbdev(usbif); 129 + int res = cp2615_init_i2c_msg(msg, i2c_w); 130 + 131 + if (!res) 132 + res = usb_bulk_msg(usbdev, usb_sndbulkpipe(usbdev, IOP_EP_OUT), 133 + msg, ntohs(msg->length), NULL, 0); 134 + kfree(msg); 135 + return res; 136 + } 137 + 138 + static int 139 + cp2615_i2c_recv(struct usb_interface *usbif, unsigned char tag, void *buf) 140 + { 141 + struct cp2615_iop_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL); 142 + struct cp2615_i2c_transfer_result *i2c_r = (struct cp2615_i2c_transfer_result *)&msg->data; 143 + struct usb_device *usbdev = interface_to_usbdev(usbif); 144 + int res = usb_bulk_msg(usbdev, usb_rcvbulkpipe(usbdev, IOP_EP_IN), 145 + msg, sizeof(struct cp2615_iop_msg), NULL, 0); 146 + 147 + if (res < 0) { 148 + kfree(msg); 149 + return res; 150 + } 151 + 152 + if (msg->msg != htons(iop_I2cTransferResult) || i2c_r->tag != tag) { 153 + kfree(msg); 154 + return -EIO; 155 + } 156 + 157 + res = cp2615_check_status(i2c_r->status); 158 + if (!res) 159 + memcpy(buf, &i2c_r->data, i2c_r->read_len); 160 + 161 + kfree(msg); 162 + return res; 163 + } 164 + 165 + /* Checks if the IOP is functional by querying the part's ID */ 166 + static int cp2615_check_iop(struct usb_interface *usbif) 167 + { 168 + struct cp2615_iop_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL); 169 + struct cp2615_iop_accessory_info *info = (struct cp2615_iop_accessory_info *)&msg->data; 170 + struct usb_device *usbdev = interface_to_usbdev(usbif); 171 + int res = cp2615_init_iop_msg(msg, iop_GetAccessoryInfo, NULL, 0); 172 + 173 + if (res) 174 + goto out; 175 + 176 + res = usb_bulk_msg(usbdev, usb_sndbulkpipe(usbdev, IOP_EP_OUT), 177 + msg, ntohs(msg->length), NULL, 0); 178 + if (res) 179 + goto out; 180 + 181 + res = usb_bulk_msg(usbdev, usb_rcvbulkpipe(usbdev, IOP_EP_IN), 182 + msg, sizeof(struct cp2615_iop_msg), NULL, 0); 183 + if (res) 184 + goto out; 185 + 186 + if (msg->msg != htons(iop_AccessoryInfo)) { 187 + res = -EIO; 188 + goto out; 189 + } 190 + 191 + switch (ntohs(info->part_id)) { 192 + case PART_ID_A01: 193 + dev_dbg(&usbif->dev, "Found A01 part. (WARNING: errata exists!)\n"); 194 + break; 195 + case PART_ID_A02: 196 + dev_dbg(&usbif->dev, "Found good A02 part.\n"); 197 + break; 198 + default: 199 + dev_warn(&usbif->dev, "Unknown part ID %04X\n", ntohs(info->part_id)); 200 + } 201 + 202 + out: 203 + kfree(msg); 204 + return res; 205 + } 206 + 207 + static int 208 + cp2615_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 209 + { 210 + struct usb_interface *usbif = adap->algo_data; 211 + int i = 0, ret = 0; 212 + struct i2c_msg *msg; 213 + struct cp2615_i2c_transfer i2c_w = {0}; 214 + 215 + dev_dbg(&usbif->dev, "Doing %d I2C transactions\n", num); 216 + 217 + for (; !ret && i < num; i++) { 218 + msg = &msgs[i]; 219 + 220 + i2c_w.tag = 0xdd; 221 + i2c_w.i2caddr = i2c_8bit_addr_from_msg(msg); 222 + if (msg->flags & I2C_M_RD) { 223 + i2c_w.read_len = msg->len; 224 + i2c_w.write_len = 0; 225 + } else { 226 + i2c_w.read_len = 0; 227 + i2c_w.write_len = msg->len; 228 + memcpy(&i2c_w.data, msg->buf, i2c_w.write_len); 229 + } 230 + ret = cp2615_i2c_send(usbif, &i2c_w); 231 + if (ret) 232 + break; 233 + ret = cp2615_i2c_recv(usbif, i2c_w.tag, msg->buf); 234 + } 235 + if (ret < 0) 236 + return ret; 237 + return i; 238 + } 239 + 240 + static u32 241 + cp2615_i2c_func(struct i2c_adapter *adap) 242 + { 243 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 244 + } 245 + 246 + static const struct i2c_algorithm cp2615_i2c_algo = { 247 + .master_xfer = cp2615_i2c_master_xfer, 248 + .functionality = cp2615_i2c_func, 249 + }; 250 + 251 + /* 252 + * This chip has some limitations: one is that the USB endpoint 253 + * can only receive 64 bytes/transfer, that leaves 54 bytes for 254 + * the I2C transfer. On top of that, EITHER read_len OR write_len 255 + * may be zero, but not both. If both are non-zero, the adapter 256 + * issues a write followed by a read. And the chip does not 257 + * support repeated START between the write and read phases. 258 + */ 259 + static struct i2c_adapter_quirks cp2615_i2c_quirks = { 260 + .max_write_len = MAX_I2C_SIZE, 261 + .max_read_len = MAX_I2C_SIZE, 262 + .flags = I2C_AQ_COMB_WRITE_THEN_READ | I2C_AQ_NO_ZERO_LEN | I2C_AQ_NO_REP_START, 263 + .max_comb_1st_msg_len = MAX_I2C_SIZE, 264 + .max_comb_2nd_msg_len = MAX_I2C_SIZE 265 + }; 266 + 267 + static void 268 + cp2615_i2c_remove(struct usb_interface *usbif) 269 + { 270 + struct i2c_adapter *adap = usb_get_intfdata(usbif); 271 + 272 + usb_set_intfdata(usbif, NULL); 273 + i2c_del_adapter(adap); 274 + } 275 + 276 + static int 277 + cp2615_i2c_probe(struct usb_interface *usbif, const struct usb_device_id *id) 278 + { 279 + int ret = 0; 280 + struct i2c_adapter *adap; 281 + struct usb_device *usbdev = interface_to_usbdev(usbif); 282 + 283 + ret = usb_set_interface(usbdev, IOP_IFN, IOP_ALTSETTING); 284 + if (ret) 285 + return ret; 286 + 287 + ret = cp2615_check_iop(usbif); 288 + if (ret) 289 + return ret; 290 + 291 + adap = devm_kzalloc(&usbif->dev, sizeof(struct i2c_adapter), GFP_KERNEL); 292 + if (!adap) 293 + return -ENOMEM; 294 + 295 + strncpy(adap->name, usbdev->serial, sizeof(adap->name) - 1); 296 + adap->owner = THIS_MODULE; 297 + adap->dev.parent = &usbif->dev; 298 + adap->dev.of_node = usbif->dev.of_node; 299 + adap->timeout = HZ; 300 + adap->algo = &cp2615_i2c_algo; 301 + adap->quirks = &cp2615_i2c_quirks; 302 + adap->algo_data = usbif; 303 + 304 + ret = i2c_add_adapter(adap); 305 + if (ret) 306 + return ret; 307 + 308 + usb_set_intfdata(usbif, adap); 309 + return 0; 310 + } 311 + 312 + static const struct usb_device_id id_table[] = { 313 + { USB_DEVICE_INTERFACE_NUMBER(CP2615_VID, CP2615_PID, IOP_IFN) }, 314 + { } 315 + }; 316 + 317 + MODULE_DEVICE_TABLE(usb, id_table); 318 + 319 + static struct usb_driver cp2615_i2c_driver = { 320 + .name = "i2c-cp2615", 321 + .probe = cp2615_i2c_probe, 322 + .disconnect = cp2615_i2c_remove, 323 + .id_table = id_table, 324 + }; 325 + 326 + module_usb_driver(cp2615_i2c_driver); 327 + 328 + MODULE_AUTHOR("Bence Csókás <bence98@sch.bme.hu>"); 329 + MODULE_DESCRIPTION("CP2615 I2C bus driver"); 330 + MODULE_LICENSE("GPL");

+3

drivers/i2c/busses/i2c-designware-common.c

··· 150 150 reg = readl(dev->base + DW_IC_COMP_TYPE); 151 151 i2c_dw_release_lock(dev); 152 152 153 + if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) 154 + map_cfg.max_register = AMD_UCSI_INTR_REG; 155 + 153 156 if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) { 154 157 map_cfg.reg_read = dw_reg_read_swab; 155 158 map_cfg.reg_write = dw_reg_write_swab;

+8

drivers/i2c/busses/i2c-designware-core.h

··· 295 295 296 296 #define MODEL_MSCC_OCELOT BIT(8) 297 297 #define MODEL_BAIKAL_BT1 BIT(9) 298 + #define MODEL_AMD_NAVI_GPU BIT(10) 298 299 #define MODEL_MASK GENMASK(11, 8) 300 + 301 + /* 302 + * Enable UCSI interrupt by writing 0xd at register 303 + * offset 0x474 specified in hardware specification. 304 + */ 305 + #define AMD_UCSI_INTR_REG 0x474 306 + #define AMD_UCSI_INTR_EN 0xd 299 307 300 308 int i2c_dw_init_regmap(struct dw_i2c_dev *dev); 301 309 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);

+138 -17

drivers/i2c/busses/i2c-designware-master.c

··· 23 23 24 24 #include "i2c-designware-core.h" 25 25 26 + #define AMD_TIMEOUT_MIN_US 25 27 + #define AMD_TIMEOUT_MAX_US 250 28 + #define AMD_MASTERCFG_MASK GENMASK(15, 0) 29 + 26 30 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev) 27 31 { 28 32 /* Configure Tx/Rx FIFO threshold levels */ ··· 39 35 40 36 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) 41 37 { 42 - const char *mode_str, *fp_str = ""; 43 38 u32 comp_param1; 44 39 u32 sda_falling_time, scl_falling_time; 45 40 struct i2c_timings *t = &dev->timings; 41 + const char *fp_str = ""; 46 42 u32 ic_clk; 47 43 int ret; 48 44 ··· 82 78 * difference is the timing parameter values since the registers are 83 79 * the same. 84 80 */ 85 - if (t->bus_freq_hz == 1000000) { 81 + if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) { 86 82 /* 87 83 * Check are Fast Mode Plus parameters available. Calculate 88 84 * SCL timing parameters for Fast Mode Plus if not set. ··· 158 154 159 155 ret = i2c_dw_set_sda_hold(dev); 160 156 if (ret) 161 - goto out; 157 + return ret; 162 158 163 - switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) { 164 - case DW_IC_CON_SPEED_STD: 165 - mode_str = "Standard Mode"; 166 - break; 167 - case DW_IC_CON_SPEED_HIGH: 168 - mode_str = "High Speed Mode"; 169 - break; 170 - default: 171 - mode_str = "Fast Mode"; 172 - } 173 - dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str); 174 - 175 - out: 176 - return ret; 159 + dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); 160 + return 0; 177 161 } 178 162 179 163 /** ··· 250 258 /* Clear and enable interrupts */ 251 259 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); 252 260 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK); 261 + } 262 + 263 + static int i2c_dw_check_stopbit(struct dw_i2c_dev *dev) 264 + { 265 + u32 val; 266 + int ret; 267 + 268 + ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val, 269 + !(val & DW_IC_INTR_STOP_DET), 270 + 1100, 20000); 271 + if (ret) 272 + dev_err(dev->dev, "i2c timeout error %d\n", ret); 273 + 274 + return ret; 275 + } 276 + 277 + static int i2c_dw_status(struct dw_i2c_dev *dev) 278 + { 279 + int status; 280 + 281 + status = i2c_dw_wait_bus_not_busy(dev); 282 + if (status) 283 + return status; 284 + 285 + return i2c_dw_check_stopbit(dev); 286 + } 287 + 288 + /* 289 + * Initiate and continue master read/write transaction with polling 290 + * based transfer routine afterward write messages into the Tx buffer. 291 + */ 292 + static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs) 293 + { 294 + struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 295 + int msg_wrt_idx, msg_itr_lmt, buf_len, data_idx; 296 + int cmd = 0, status; 297 + u8 *tx_buf; 298 + u32 val; 299 + 300 + /* 301 + * In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card, 302 + * it is mandatory to set the right value in specific register 303 + * (offset:0x474) as per the hardware IP specification. 304 + */ 305 + regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN); 306 + 307 + dev->msgs = msgs; 308 + dev->msgs_num = num_msgs; 309 + i2c_dw_xfer_init(dev); 310 + i2c_dw_disable_int(dev); 311 + 312 + /* Initiate messages read/write transaction */ 313 + for (msg_wrt_idx = 0; msg_wrt_idx < num_msgs; msg_wrt_idx++) { 314 + tx_buf = msgs[msg_wrt_idx].buf; 315 + buf_len = msgs[msg_wrt_idx].len; 316 + 317 + if (!(msgs[msg_wrt_idx].flags & I2C_M_RD)) 318 + regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1); 319 + /* 320 + * Initiate the i2c read/write transaction of buffer length, 321 + * and poll for bus busy status. For the last message transfer, 322 + * update the command with stopbit enable. 323 + */ 324 + for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) { 325 + if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1) 326 + cmd |= BIT(9); 327 + 328 + if (msgs[msg_wrt_idx].flags & I2C_M_RD) { 329 + /* Due to hardware bug, need to write the same command twice. */ 330 + regmap_write(dev->map, DW_IC_DATA_CMD, 0x100); 331 + regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd); 332 + if (cmd) { 333 + regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1)); 334 + regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1)); 335 + /* 336 + * Need to check the stop bit. However, it cannot be 337 + * detected from the registers so we check it always 338 + * when read/write the last byte. 339 + */ 340 + status = i2c_dw_status(dev); 341 + if (status) 342 + return status; 343 + 344 + for (data_idx = 0; data_idx < buf_len; data_idx++) { 345 + regmap_read(dev->map, DW_IC_DATA_CMD, &val); 346 + tx_buf[data_idx] = val; 347 + } 348 + status = i2c_dw_check_stopbit(dev); 349 + if (status) 350 + return status; 351 + } 352 + } else { 353 + regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd); 354 + usleep_range(AMD_TIMEOUT_MIN_US, AMD_TIMEOUT_MAX_US); 355 + } 356 + } 357 + status = i2c_dw_check_stopbit(dev); 358 + if (status) 359 + return status; 360 + } 361 + 362 + return 0; 253 363 } 254 364 255 365 /* ··· 556 462 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 557 463 558 464 pm_runtime_get_sync(dev->dev); 465 + 466 + /* 467 + * Initiate I2C message transfer when AMD NAVI GPU card is enabled, 468 + * As it is polling based transfer mechanism, which does not support 469 + * interrupt based functionalities of existing DesignWare driver. 470 + */ 471 + if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) { 472 + ret = amd_i2c_dw_xfer_quirk(adap, msgs, num); 473 + goto done_nolock; 474 + } 559 475 560 476 if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) { 561 477 ret = -ESHUTDOWN; ··· 843 739 return 0; 844 740 } 845 741 742 + static int amd_i2c_adap_quirk(struct dw_i2c_dev *dev) 743 + { 744 + struct i2c_adapter *adap = &dev->adapter; 745 + int ret; 746 + 747 + pm_runtime_get_noresume(dev->dev); 748 + ret = i2c_add_numbered_adapter(adap); 749 + if (ret) 750 + dev_err(dev->dev, "Failed to add adapter: %d\n", ret); 751 + pm_runtime_put_noidle(dev->dev); 752 + 753 + return ret; 754 + } 755 + 846 756 int i2c_dw_probe_master(struct dw_i2c_dev *dev) 847 757 { 848 758 struct i2c_adapter *adap = &dev->adapter; ··· 892 774 adap->quirks = &i2c_dw_quirks; 893 775 adap->dev.parent = dev->dev; 894 776 i2c_set_adapdata(adap, dev); 777 + 778 + if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) 779 + return amd_i2c_adap_quirk(dev); 895 780 896 781 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { 897 782 irq_flags = IRQF_NO_SUSPEND;

+61

drivers/i2c/busses/i2c-designware-pcidrv.c

··· 26 26 #include "i2c-designware-core.h" 27 27 28 28 #define DRIVER_NAME "i2c-designware-pci" 29 + #define AMD_CLK_RATE_HZ 100000 29 30 30 31 enum dw_pci_ctl_id_t { 31 32 medfield, ··· 35 34 cherrytrail, 36 35 haswell, 37 36 elkhartlake, 37 + navi_amd, 38 38 }; 39 39 40 40 struct dw_scl_sda_cfg { ··· 80 78 .sda_hold = 0x9, 81 79 }; 82 80 81 + /* NAVI-AMD HCNT/LCNT/SDA hold time */ 82 + static struct dw_scl_sda_cfg navi_amd_config = { 83 + .ss_hcnt = 0x1ae, 84 + .ss_lcnt = 0x23a, 85 + .sda_hold = 0x9, 86 + }; 87 + 83 88 static u32 mfld_get_clk_rate_khz(struct dw_i2c_dev *dev) 84 89 { 85 90 return 25000; 91 + } 92 + 93 + static u32 navi_amd_get_clk_rate_khz(struct dw_i2c_dev *dev) 94 + { 95 + return AMD_CLK_RATE_HZ; 86 96 } 87 97 88 98 static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c) ··· 116 102 return 0; 117 103 } 118 104 return -ENODEV; 105 + } 106 + 107 + /* 108 + * TODO find a better way how to deduplicate instantiation 109 + * of USB PD slave device from nVidia GPU driver. 110 + */ 111 + static int navi_amd_register_client(struct dw_i2c_dev *dev) 112 + { 113 + struct i2c_board_info info; 114 + 115 + memset(&info, 0, sizeof(struct i2c_board_info)); 116 + strscpy(info.type, "ccgx-ucsi", I2C_NAME_SIZE); 117 + info.addr = 0x08; 118 + info.irq = dev->irq; 119 + 120 + dev->slave = i2c_new_client_device(&dev->adapter, &info); 121 + if (IS_ERR(dev->slave)) 122 + return PTR_ERR(dev->slave); 123 + 124 + return 0; 125 + } 126 + 127 + static int navi_amd_setup(struct pci_dev *pdev, struct dw_pci_controller *c) 128 + { 129 + struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev); 130 + 131 + dev->flags |= MODEL_AMD_NAVI_GPU; 132 + dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 133 + return 0; 119 134 } 120 135 121 136 static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c) ··· 197 154 [elkhartlake] = { 198 155 .bus_num = -1, 199 156 .get_clk_rate_khz = ehl_get_clk_rate_khz, 157 + }, 158 + [navi_amd] = { 159 + .bus_num = -1, 160 + .scl_sda_cfg = &navi_amd_config, 161 + .setup = navi_amd_setup, 162 + .get_clk_rate_khz = navi_amd_get_clk_rate_khz, 200 163 }, 201 164 }; 202 165 ··· 323 274 return r; 324 275 } 325 276 277 + if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) { 278 + r = navi_amd_register_client(dev); 279 + if (r) { 280 + dev_err(dev->dev, "register client failed with %d\n", r); 281 + return r; 282 + } 283 + } 284 + 326 285 pm_runtime_set_autosuspend_delay(&pdev->dev, 1000); 327 286 pm_runtime_use_autosuspend(&pdev->dev); 328 287 pm_runtime_put_autosuspend(&pdev->dev); ··· 394 337 { PCI_VDEVICE(INTEL, 0x4bbe), elkhartlake }, 395 338 { PCI_VDEVICE(INTEL, 0x4bbf), elkhartlake }, 396 339 { PCI_VDEVICE(INTEL, 0x4bc0), elkhartlake }, 340 + { PCI_VDEVICE(ATI, 0x7314), navi_amd }, 341 + { PCI_VDEVICE(ATI, 0x73a4), navi_amd }, 342 + { PCI_VDEVICE(ATI, 0x73e4), navi_amd }, 343 + { PCI_VDEVICE(ATI, 0x73c4), navi_amd }, 397 344 { 0,} 398 345 }; 399 346 MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);

+4 -1

drivers/i2c/busses/i2c-emev2.c

··· 395 395 396 396 em_i2c_reset(&priv->adap); 397 397 398 - priv->irq = platform_get_irq(pdev, 0); 398 + ret = platform_get_irq(pdev, 0); 399 + if (ret < 0) 400 + goto err_clk; 401 + priv->irq = ret; 399 402 ret = devm_request_irq(&pdev->dev, priv->irq, em_i2c_irq_handler, 0, 400 403 "em_i2c", priv); 401 404 if (ret)

+504

drivers/i2c/busses/i2c-hisi.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * HiSilicon I2C Controller Driver for Kunpeng SoC 4 + * 5 + * Copyright (c) 2021 HiSilicon Technologies Co., Ltd. 6 + */ 7 + 8 + #include <linux/bits.h> 9 + #include <linux/bitfield.h> 10 + #include <linux/completion.h> 11 + #include <linux/i2c.h> 12 + #include <linux/interrupt.h> 13 + #include <linux/io.h> 14 + #include <linux/module.h> 15 + #include <linux/mod_devicetable.h> 16 + #include <linux/platform_device.h> 17 + #include <linux/property.h> 18 + 19 + #define HISI_I2C_FRAME_CTRL 0x0000 20 + #define HISI_I2C_FRAME_CTRL_SPEED_MODE GENMASK(1, 0) 21 + #define HISI_I2C_FRAME_CTRL_ADDR_TEN BIT(2) 22 + #define HISI_I2C_SLV_ADDR 0x0004 23 + #define HISI_I2C_SLV_ADDR_VAL GENMASK(9, 0) 24 + #define HISI_I2C_SLV_ADDR_GC_S_MODE BIT(10) 25 + #define HISI_I2C_SLV_ADDR_GC_S_EN BIT(11) 26 + #define HISI_I2C_CMD_TXDATA 0x0008 27 + #define HISI_I2C_CMD_TXDATA_DATA GENMASK(7, 0) 28 + #define HISI_I2C_CMD_TXDATA_RW BIT(8) 29 + #define HISI_I2C_CMD_TXDATA_P_EN BIT(9) 30 + #define HISI_I2C_CMD_TXDATA_SR_EN BIT(10) 31 + #define HISI_I2C_RXDATA 0x000c 32 + #define HISI_I2C_RXDATA_DATA GENMASK(7, 0) 33 + #define HISI_I2C_SS_SCL_HCNT 0x0010 34 + #define HISI_I2C_SS_SCL_LCNT 0x0014 35 + #define HISI_I2C_FS_SCL_HCNT 0x0018 36 + #define HISI_I2C_FS_SCL_LCNT 0x001c 37 + #define HISI_I2C_HS_SCL_HCNT 0x0020 38 + #define HISI_I2C_HS_SCL_LCNT 0x0024 39 + #define HISI_I2C_FIFO_CTRL 0x0028 40 + #define HISI_I2C_FIFO_RX_CLR BIT(0) 41 + #define HISI_I2C_FIFO_TX_CLR BIT(1) 42 + #define HISI_I2C_FIFO_RX_AF_THRESH GENMASK(7, 2) 43 + #define HISI_I2C_FIFO_TX_AE_THRESH GENMASK(13, 8) 44 + #define HISI_I2C_FIFO_STATE 0x002c 45 + #define HISI_I2C_FIFO_STATE_RX_RERR BIT(0) 46 + #define HISI_I2C_FIFO_STATE_RX_WERR BIT(1) 47 + #define HISI_I2C_FIFO_STATE_RX_EMPTY BIT(3) 48 + #define HISI_I2C_FIFO_STATE_TX_RERR BIT(6) 49 + #define HISI_I2C_FIFO_STATE_TX_WERR BIT(7) 50 + #define HISI_I2C_FIFO_STATE_TX_FULL BIT(11) 51 + #define HISI_I2C_SDA_HOLD 0x0030 52 + #define HISI_I2C_SDA_HOLD_TX GENMASK(15, 0) 53 + #define HISI_I2C_SDA_HOLD_RX GENMASK(23, 16) 54 + #define HISI_I2C_FS_SPK_LEN 0x0038 55 + #define HISI_I2C_FS_SPK_LEN_CNT GENMASK(7, 0) 56 + #define HISI_I2C_HS_SPK_LEN 0x003c 57 + #define HISI_I2C_HS_SPK_LEN_CNT GENMASK(7, 0) 58 + #define HISI_I2C_INT_MSTAT 0x0044 59 + #define HISI_I2C_INT_CLR 0x0048 60 + #define HISI_I2C_INT_MASK 0x004C 61 + #define HISI_I2C_TRANS_STATE 0x0050 62 + #define HISI_I2C_TRANS_ERR 0x0054 63 + #define HISI_I2C_VERSION 0x0058 64 + 65 + #define HISI_I2C_INT_ALL GENMASK(4, 0) 66 + #define HISI_I2C_INT_TRANS_CPLT BIT(0) 67 + #define HISI_I2C_INT_TRANS_ERR BIT(1) 68 + #define HISI_I2C_INT_FIFO_ERR BIT(2) 69 + #define HISI_I2C_INT_RX_FULL BIT(3) 70 + #define HISI_I2C_INT_TX_EMPTY BIT(4) 71 + #define HISI_I2C_INT_ERR \ 72 + (HISI_I2C_INT_TRANS_ERR | HISI_I2C_INT_FIFO_ERR) 73 + 74 + #define HISI_I2C_STD_SPEED_MODE 0 75 + #define HISI_I2C_FAST_SPEED_MODE 1 76 + #define HISI_I2C_HIGH_SPEED_MODE 2 77 + 78 + #define HISI_I2C_TX_FIFO_DEPTH 64 79 + #define HISI_I2C_RX_FIFO_DEPTH 64 80 + #define HISI_I2C_TX_F_AE_THRESH 1 81 + #define HISI_I2C_RX_F_AF_THRESH 60 82 + 83 + #define HZ_PER_KHZ 1000 84 + 85 + #define NSEC_TO_CYCLES(ns, clk_rate_khz) \ 86 + DIV_ROUND_UP_ULL((clk_rate_khz) * (ns), NSEC_PER_MSEC) 87 + 88 + struct hisi_i2c_controller { 89 + struct i2c_adapter adapter; 90 + void __iomem *iobase; 91 + struct device *dev; 92 + int irq; 93 + 94 + /* Intermediates for recording the transfer process */ 95 + struct completion *completion; 96 + struct i2c_msg *msgs; 97 + int msg_num; 98 + int msg_tx_idx; 99 + int buf_tx_idx; 100 + int msg_rx_idx; 101 + int buf_rx_idx; 102 + u16 tar_addr; 103 + u32 xfer_err; 104 + 105 + /* I2C bus configuration */ 106 + struct i2c_timings t; 107 + u32 clk_rate_khz; 108 + u32 spk_len; 109 + }; 110 + 111 + static void hisi_i2c_enable_int(struct hisi_i2c_controller *ctlr, u32 mask) 112 + { 113 + writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); 114 + } 115 + 116 + static void hisi_i2c_disable_int(struct hisi_i2c_controller *ctlr, u32 mask) 117 + { 118 + writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); 119 + } 120 + 121 + static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask) 122 + { 123 + writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); 124 + } 125 + 126 + static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr) 127 + { 128 + u32 int_err = ctlr->xfer_err, reg; 129 + 130 + if (int_err & HISI_I2C_INT_FIFO_ERR) { 131 + reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 132 + 133 + if (reg & HISI_I2C_FIFO_STATE_RX_RERR) 134 + dev_err(ctlr->dev, "rx fifo error read\n"); 135 + 136 + if (reg & HISI_I2C_FIFO_STATE_RX_WERR) 137 + dev_err(ctlr->dev, "rx fifo error write\n"); 138 + 139 + if (reg & HISI_I2C_FIFO_STATE_TX_RERR) 140 + dev_err(ctlr->dev, "tx fifo error read\n"); 141 + 142 + if (reg & HISI_I2C_FIFO_STATE_TX_WERR) 143 + dev_err(ctlr->dev, "tx fifo error write\n"); 144 + } 145 + } 146 + 147 + static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) 148 + { 149 + struct i2c_msg *msg = ctlr->msgs; 150 + u32 reg; 151 + 152 + reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); 153 + reg &= ~HISI_I2C_FRAME_CTRL_ADDR_TEN; 154 + if (msg->flags & I2C_M_TEN) 155 + reg |= HISI_I2C_FRAME_CTRL_ADDR_TEN; 156 + writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); 157 + 158 + reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR); 159 + reg &= ~HISI_I2C_SLV_ADDR_VAL; 160 + reg |= FIELD_PREP(HISI_I2C_SLV_ADDR_VAL, msg->addr); 161 + writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR); 162 + 163 + reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL); 164 + reg |= HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR; 165 + writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 166 + reg &= ~(HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR); 167 + writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 168 + 169 + hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); 170 + hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL); 171 + 172 + return 0; 173 + } 174 + 175 + static void hisi_i2c_reset_xfer(struct hisi_i2c_controller *ctlr) 176 + { 177 + ctlr->msg_num = 0; 178 + ctlr->xfer_err = 0; 179 + ctlr->msg_tx_idx = 0; 180 + ctlr->msg_rx_idx = 0; 181 + ctlr->buf_tx_idx = 0; 182 + ctlr->buf_rx_idx = 0; 183 + } 184 + 185 + /* 186 + * Initialize the transfer information and start the I2C bus transfer. 187 + * We only configure the transfer and do some pre/post works here, and 188 + * wait for the transfer done. The major transfer process is performed 189 + * in the IRQ handler. 190 + */ 191 + static int hisi_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 192 + int num) 193 + { 194 + struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); 195 + DECLARE_COMPLETION_ONSTACK(done); 196 + int ret = num; 197 + 198 + hisi_i2c_reset_xfer(ctlr); 199 + ctlr->completion = &done; 200 + ctlr->msg_num = num; 201 + ctlr->msgs = msgs; 202 + 203 + hisi_i2c_start_xfer(ctlr); 204 + 205 + if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) { 206 + hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 207 + synchronize_irq(ctlr->irq); 208 + i2c_recover_bus(&ctlr->adapter); 209 + dev_err(ctlr->dev, "bus transfer timeout\n"); 210 + ret = -EIO; 211 + } 212 + 213 + if (ctlr->xfer_err) { 214 + hisi_i2c_handle_errors(ctlr); 215 + ret = -EIO; 216 + } 217 + 218 + hisi_i2c_reset_xfer(ctlr); 219 + ctlr->completion = NULL; 220 + 221 + return ret; 222 + } 223 + 224 + static u32 hisi_i2c_functionality(struct i2c_adapter *adap) 225 + { 226 + return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; 227 + } 228 + 229 + static const struct i2c_algorithm hisi_i2c_algo = { 230 + .master_xfer = hisi_i2c_master_xfer, 231 + .functionality = hisi_i2c_functionality, 232 + }; 233 + 234 + static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr) 235 + { 236 + struct i2c_msg *cur_msg; 237 + u32 fifo_state; 238 + 239 + while (ctlr->msg_rx_idx < ctlr->msg_num) { 240 + cur_msg = ctlr->msgs + ctlr->msg_rx_idx; 241 + 242 + if (!(cur_msg->flags & I2C_M_RD)) { 243 + ctlr->msg_rx_idx++; 244 + continue; 245 + } 246 + 247 + fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 248 + while (!(fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) && 249 + ctlr->buf_rx_idx < cur_msg->len) { 250 + cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA); 251 + fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 252 + } 253 + 254 + if (ctlr->buf_rx_idx == cur_msg->len) { 255 + ctlr->buf_rx_idx = 0; 256 + ctlr->msg_rx_idx++; 257 + } 258 + 259 + if (fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) 260 + break; 261 + } 262 + 263 + return 0; 264 + } 265 + 266 + static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) 267 + { 268 + int max_write = HISI_I2C_TX_FIFO_DEPTH; 269 + bool need_restart = false, last_msg; 270 + struct i2c_msg *cur_msg; 271 + u32 cmd, fifo_state; 272 + 273 + while (ctlr->msg_tx_idx < ctlr->msg_num) { 274 + cur_msg = ctlr->msgs + ctlr->msg_tx_idx; 275 + last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1); 276 + 277 + /* Signal the SR bit when we start transferring a new message */ 278 + if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx) 279 + need_restart = true; 280 + 281 + fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 282 + while (!(fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) && 283 + ctlr->buf_tx_idx < cur_msg->len && max_write) { 284 + cmd = 0; 285 + 286 + if (need_restart) { 287 + cmd |= HISI_I2C_CMD_TXDATA_SR_EN; 288 + need_restart = false; 289 + } 290 + 291 + /* Signal the STOP bit at the last frame of the last message */ 292 + if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg) 293 + cmd |= HISI_I2C_CMD_TXDATA_P_EN; 294 + 295 + if (cur_msg->flags & I2C_M_RD) 296 + cmd |= HISI_I2C_CMD_TXDATA_RW; 297 + else 298 + cmd |= FIELD_PREP(HISI_I2C_CMD_TXDATA_DATA, 299 + cur_msg->buf[ctlr->buf_tx_idx]); 300 + 301 + writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA); 302 + ctlr->buf_tx_idx++; 303 + max_write--; 304 + 305 + fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 306 + } 307 + 308 + /* Update the transfer index after per message transfer is done. */ 309 + if (ctlr->buf_tx_idx == cur_msg->len) { 310 + ctlr->buf_tx_idx = 0; 311 + ctlr->msg_tx_idx++; 312 + } 313 + 314 + if ((fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) || 315 + max_write == 0) 316 + break; 317 + } 318 + } 319 + 320 + static irqreturn_t hisi_i2c_irq(int irq, void *context) 321 + { 322 + struct hisi_i2c_controller *ctlr = context; 323 + u32 int_stat; 324 + 325 + int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT); 326 + hisi_i2c_clear_int(ctlr, int_stat); 327 + if (!(int_stat & HISI_I2C_INT_ALL)) 328 + return IRQ_NONE; 329 + 330 + if (int_stat & HISI_I2C_INT_TX_EMPTY) 331 + hisi_i2c_xfer_msg(ctlr); 332 + 333 + if (int_stat & HISI_I2C_INT_ERR) { 334 + ctlr->xfer_err = int_stat; 335 + goto out; 336 + } 337 + 338 + /* Drain the rx fifo before finish the transfer */ 339 + if (int_stat & (HISI_I2C_INT_TRANS_CPLT | HISI_I2C_INT_RX_FULL)) 340 + hisi_i2c_read_rx_fifo(ctlr); 341 + 342 + out: 343 + if (int_stat & HISI_I2C_INT_TRANS_CPLT || ctlr->xfer_err) { 344 + hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 345 + hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); 346 + complete(ctlr->completion); 347 + } 348 + 349 + return IRQ_HANDLED; 350 + } 351 + 352 + /* 353 + * Helper function for calculating and configuring the HIGH and LOW 354 + * periods of SCL clock. The caller will pass the ratio of the 355 + * counts (divide / divisor) according to the target speed mode, 356 + * and the target registers. 357 + */ 358 + static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr, 359 + u32 divide, u32 divisor, 360 + u32 reg_hcnt, u32 reg_lcnt) 361 + { 362 + u32 total_cnt, t_scl_hcnt, t_scl_lcnt, scl_fall_cnt, scl_rise_cnt; 363 + u32 scl_hcnt, scl_lcnt; 364 + 365 + /* Total SCL clock cycles per speed period */ 366 + total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz); 367 + /* Total HIGH level SCL clock cycles including edges */ 368 + t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor); 369 + /* Total LOW level SCL clock cycles including edges */ 370 + t_scl_lcnt = total_cnt - t_scl_hcnt; 371 + /* Fall edge SCL clock cycles */ 372 + scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz); 373 + /* Rise edge SCL clock cycles */ 374 + scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz); 375 + 376 + /* Calculated HIGH and LOW periods of SCL clock */ 377 + scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt; 378 + scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt; 379 + 380 + writel(scl_hcnt, ctlr->iobase + reg_hcnt); 381 + writel(scl_lcnt, ctlr->iobase + reg_lcnt); 382 + } 383 + 384 + static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr) 385 + { 386 + u32 reg, sda_hold_cnt, speed_mode; 387 + 388 + i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true); 389 + ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz); 390 + 391 + switch (ctlr->t.bus_freq_hz) { 392 + case I2C_MAX_FAST_MODE_FREQ: 393 + speed_mode = HISI_I2C_FAST_SPEED_MODE; 394 + hisi_i2c_set_scl(ctlr, 26, 76, HISI_I2C_FS_SCL_HCNT, HISI_I2C_FS_SCL_LCNT); 395 + break; 396 + case I2C_MAX_HIGH_SPEED_MODE_FREQ: 397 + speed_mode = HISI_I2C_HIGH_SPEED_MODE; 398 + hisi_i2c_set_scl(ctlr, 6, 22, HISI_I2C_HS_SCL_HCNT, HISI_I2C_HS_SCL_LCNT); 399 + break; 400 + case I2C_MAX_STANDARD_MODE_FREQ: 401 + default: 402 + speed_mode = HISI_I2C_STD_SPEED_MODE; 403 + 404 + /* For default condition force the bus speed to standard mode. */ 405 + ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 406 + hisi_i2c_set_scl(ctlr, 40, 87, HISI_I2C_SS_SCL_HCNT, HISI_I2C_SS_SCL_LCNT); 407 + break; 408 + } 409 + 410 + reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); 411 + reg &= ~HISI_I2C_FRAME_CTRL_SPEED_MODE; 412 + reg |= FIELD_PREP(HISI_I2C_FRAME_CTRL_SPEED_MODE, speed_mode); 413 + writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); 414 + 415 + sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz); 416 + 417 + reg = FIELD_PREP(HISI_I2C_SDA_HOLD_TX, sda_hold_cnt); 418 + writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD); 419 + 420 + writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN); 421 + 422 + reg = FIELD_PREP(HISI_I2C_FIFO_RX_AF_THRESH, HISI_I2C_RX_F_AF_THRESH); 423 + reg |= FIELD_PREP(HISI_I2C_FIFO_TX_AE_THRESH, HISI_I2C_TX_F_AE_THRESH); 424 + writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 425 + } 426 + 427 + static int hisi_i2c_probe(struct platform_device *pdev) 428 + { 429 + struct hisi_i2c_controller *ctlr; 430 + struct device *dev = &pdev->dev; 431 + struct i2c_adapter *adapter; 432 + u64 clk_rate_hz; 433 + u32 hw_version; 434 + int ret; 435 + 436 + ctlr = devm_kzalloc(dev, sizeof(*ctlr), GFP_KERNEL); 437 + if (!ctlr) 438 + return -ENOMEM; 439 + 440 + ctlr->iobase = devm_platform_ioremap_resource(pdev, 0); 441 + if (IS_ERR(ctlr->iobase)) 442 + return PTR_ERR(ctlr->iobase); 443 + 444 + ctlr->irq = platform_get_irq(pdev, 0); 445 + if (ctlr->irq < 0) 446 + return ctlr->irq; 447 + 448 + ctlr->dev = dev; 449 + 450 + hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 451 + 452 + ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr); 453 + if (ret) { 454 + dev_err(dev, "failed to request irq handler, ret = %d\n", ret); 455 + return ret; 456 + } 457 + 458 + ret = device_property_read_u64(dev, "clk_rate", &clk_rate_hz); 459 + if (ret) { 460 + dev_err(dev, "failed to get clock frequency, ret = %d\n", ret); 461 + return ret; 462 + } 463 + 464 + ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); 465 + 466 + hisi_i2c_configure_bus(ctlr); 467 + 468 + adapter = &ctlr->adapter; 469 + snprintf(adapter->name, sizeof(adapter->name), 470 + "HiSilicon I2C Controller %s", dev_name(dev)); 471 + adapter->owner = THIS_MODULE; 472 + adapter->algo = &hisi_i2c_algo; 473 + adapter->dev.parent = dev; 474 + i2c_set_adapdata(adapter, ctlr); 475 + 476 + ret = devm_i2c_add_adapter(dev, adapter); 477 + if (ret) 478 + return ret; 479 + 480 + hw_version = readl(ctlr->iobase + HISI_I2C_VERSION); 481 + dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n", 482 + i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version); 483 + 484 + return 0; 485 + } 486 + 487 + static const struct acpi_device_id hisi_i2c_acpi_ids[] = { 488 + { "HISI03D1", 0 }, 489 + { } 490 + }; 491 + MODULE_DEVICE_TABLE(acpi, hisi_i2c_acpi_ids); 492 + 493 + static struct platform_driver hisi_i2c_driver = { 494 + .probe = hisi_i2c_probe, 495 + .driver = { 496 + .name = "hisi-i2c", 497 + .acpi_match_table = hisi_i2c_acpi_ids, 498 + }, 499 + }; 500 + module_platform_driver(hisi_i2c_driver); 501 + 502 + MODULE_AUTHOR("Yicong Yang <yangyicong@hisilicon.com>"); 503 + MODULE_DESCRIPTION("HiSilicon I2C Controller Driver"); 504 + MODULE_LICENSE("GPL");

+4

drivers/i2c/busses/i2c-i801.c

··· 73 73 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 74 74 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 75 75 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 76 + * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 76 77 * 77 78 * Features supported by this driver: 78 79 * Software PEC no ··· 231 230 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 232 231 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 233 232 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 233 + #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 234 234 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 235 235 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 236 236 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 ··· 1089 1087 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) }, 1090 1088 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) }, 1091 1089 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS) }, 1090 + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS) }, 1092 1091 { 0, } 1093 1092 }; 1094 1093 ··· 1774 1771 case PCI_DEVICE_ID_INTEL_EBG_SMBUS: 1775 1772 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS: 1776 1773 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS: 1774 + case PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS: 1777 1775 priv->features |= FEATURE_BLOCK_PROC; 1778 1776 priv->features |= FEATURE_I2C_BLOCK_READ; 1779 1777 priv->features |= FEATURE_IRQ;

+9 -23

drivers/i2c/busses/i2c-icy.c

··· 54 54 55 55 void __iomem *reg_s0; 56 56 void __iomem *reg_s1; 57 - struct fwnode_handle *ltc2990_fwnode; 58 57 struct i2c_client *ltc2990_client; 59 58 }; 60 59 ··· 114 115 { } 115 116 }; 116 117 118 + static const struct software_node icy_ltc2990_node = { 119 + .properties = icy_ltc2990_props, 120 + }; 121 + 117 122 static int icy_probe(struct zorro_dev *z, 118 123 const struct zorro_device_id *ent) 119 124 { ··· 126 123 struct fwnode_handle *new_fwnode; 127 124 struct i2c_board_info ltc2990_info = { 128 125 .type = "ltc2990", 126 + .swnode = &icy_ltc2990_node, 129 127 }; 130 128 131 129 i2c = devm_kzalloc(&z->dev, sizeof(*i2c), GFP_KERNEL); ··· 178 174 * 179 175 * See property_entry above for in1, in2, temp3. 180 176 */ 181 - new_fwnode = fwnode_create_software_node(icy_ltc2990_props, NULL); 182 - if (IS_ERR(new_fwnode)) { 183 - dev_info(&z->dev, "Failed to create fwnode for LTC2990, error: %ld\n", 184 - PTR_ERR(new_fwnode)); 185 - } else { 186 - /* 187 - * Store the fwnode so we can destroy it on .remove(). 188 - * Only store it on success, as fwnode_remove_software_node() 189 - * is NULL safe, but not PTR_ERR safe. 190 - */ 191 - i2c->ltc2990_fwnode = new_fwnode; 192 - ltc2990_info.fwnode = new_fwnode; 193 - 194 - i2c->ltc2990_client = 195 - i2c_new_scanned_device(&i2c->adapter, 196 - &ltc2990_info, 197 - icy_ltc2990_addresses, 198 - NULL); 199 - } 200 - 177 + i2c->ltc2990_client = i2c_new_scanned_device(&i2c->adapter, 178 + &ltc2990_info, 179 + icy_ltc2990_addresses, 180 + NULL); 201 181 return 0; 202 182 } 203 183 ··· 190 202 struct icy_i2c *i2c = dev_get_drvdata(&z->dev); 191 203 192 204 i2c_unregister_device(i2c->ltc2990_client); 193 - fwnode_remove_software_node(i2c->ltc2990_fwnode); 194 - 195 205 i2c_del_adapter(&i2c->adapter); 196 206 } 197 207

+2 -2

drivers/i2c/busses/i2c-img-scb.c

··· 1057 1057 atomic = true; 1058 1058 } 1059 1059 1060 - ret = pm_runtime_get_sync(adap->dev.parent); 1060 + ret = pm_runtime_resume_and_get(adap->dev.parent); 1061 1061 if (ret < 0) 1062 1062 return ret; 1063 1063 ··· 1158 1158 u32 rev; 1159 1159 int ret; 1160 1160 1161 - ret = pm_runtime_get_sync(i2c->adap.dev.parent); 1161 + ret = pm_runtime_resume_and_get(i2c->adap.dev.parent); 1162 1162 if (ret < 0) 1163 1163 return ret; 1164 1164

+1 -1

drivers/i2c/busses/i2c-imx-lpi2c.c

··· 259 259 unsigned int temp; 260 260 int ret; 261 261 262 - ret = pm_runtime_get_sync(lpi2c_imx->adapter.dev.parent); 262 + ret = pm_runtime_resume_and_get(lpi2c_imx->adapter.dev.parent); 263 263 if (ret < 0) 264 264 return ret; 265 265

+3 -3

drivers/i2c/busses/i2c-imx.c

··· 801 801 i2c_imx->last_slave_event = I2C_SLAVE_STOP; 802 802 803 803 /* Resume */ 804 - ret = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 804 + ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 805 805 if (ret < 0) { 806 806 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 807 807 return ret; ··· 1253 1253 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1254 1254 int result; 1255 1255 1256 - result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 1256 + result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 1257 1257 if (result < 0) 1258 1258 return result; 1259 1259 ··· 1496 1496 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1497 1497 int irq, ret; 1498 1498 1499 - ret = pm_runtime_get_sync(&pdev->dev); 1499 + ret = pm_runtime_resume_and_get(&pdev->dev); 1500 1500 if (ret < 0) 1501 1501 return ret; 1502 1502

+15 -13

drivers/i2c/busses/i2c-iop3xx.c

··· 125 125 int rc = 0; 126 126 127 127 if ((sr & IOP3XX_ISR_BERRD)) { 128 - if ( !rc ) rc = -I2C_ERR_BERR; 128 + if (!rc) 129 + rc = -I2C_ERR_BERR; 129 130 } 130 131 if ((sr & IOP3XX_ISR_ALD)) { 131 - if ( !rc ) rc = -I2C_ERR_ALD; 132 + if (!rc) 133 + rc = -I2C_ERR_ALD; 132 134 } 133 135 return rc; 134 136 } ··· 153 151 * sleep until interrupted, then recover and analyse the SR 154 152 * saved by handler 155 153 */ 156 - typedef int (* compare_func)(unsigned test, unsigned mask); 154 + typedef int (*compare_func)(unsigned test, unsigned mask); 157 155 /* returns 1 on correct comparison */ 158 156 159 157 static int 160 158 iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, 161 - unsigned flags, unsigned* status, 159 + unsigned flags, unsigned *status, 162 160 compare_func compare) 163 161 { 164 162 unsigned sr = 0; ··· 169 167 do { 170 168 interrupted = wait_event_interruptible_timeout ( 171 169 iop3xx_adap->waitq, 172 - (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )), 170 + (done = compare(sr = iop3xx_i2c_get_srstat(iop3xx_adap), flags)), 173 171 1 * HZ 174 172 ); 175 173 if ((rc = iop3xx_i2c_error(sr)) < 0) { ··· 179 177 *status = sr; 180 178 return -ETIMEDOUT; 181 179 } 182 - } while(!done); 180 + } while (!done); 183 181 184 182 *status = sr; 185 183 ··· 206 204 { 207 205 return iop3xx_i2c_wait_event( 208 206 iop3xx_adap, 209 - IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD, 207 + IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD, 210 208 status, any_bits_set); 211 209 } 212 210 ··· 228 226 229 227 static int 230 228 iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, 231 - struct i2c_msg* msg) 229 + struct i2c_msg *msg) 232 230 { 233 231 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 234 232 int status; ··· 275 273 } 276 274 277 275 static int 278 - iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, 276 + iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char *byte, 279 277 int stop) 280 278 { 281 279 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); ··· 307 305 int rc = 0; 308 306 309 307 for (ii = 0; rc == 0 && ii != count; ++ii) 310 - rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1); 308 + rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii == count-1); 311 309 return rc; 312 310 } 313 311 ··· 319 317 int rc = 0; 320 318 321 319 for (ii = 0; rc == 0 && ii != count; ++ii) 322 - rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1); 320 + rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii == count-1); 323 321 324 322 return rc; 325 323 } ··· 332 330 * condition. 333 331 */ 334 332 static int 335 - iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) 333 + iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg *pmsg) 336 334 { 337 335 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 338 336 int rc; ··· 371 369 372 370 iop3xx_i2c_transaction_cleanup(iop3xx_adap); 373 371 374 - if(ret) 372 + if (ret) 375 373 return ret; 376 374 377 375 return im;

+4 -1

drivers/i2c/busses/i2c-jz4780.c

··· 825 825 826 826 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0x0); 827 827 828 - i2c->irq = platform_get_irq(pdev, 0); 828 + ret = platform_get_irq(pdev, 0); 829 + if (ret < 0) 830 + goto err; 831 + i2c->irq = ret; 829 832 ret = devm_request_irq(&pdev->dev, i2c->irq, jz4780_i2c_irq, 0, 830 833 dev_name(&pdev->dev), i2c); 831 834 if (ret)

+6 -10

drivers/i2c/busses/i2c-mlxbf.c

··· 172 172 #define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14 173 173 #define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18 174 174 175 - enum { 176 - MLXBF_I2C_TIMING_100KHZ = 100000, 177 - MLXBF_I2C_TIMING_400KHZ = 400000, 178 - MLXBF_I2C_TIMING_1000KHZ = 1000000, 179 - }; 180 - 181 175 /* 182 176 * Defines SMBus operating frequency and core clock frequency. 183 177 * According to ADB files, default values are compliant to 100KHz SMBus ··· 1196 1202 1197 1203 ret = device_property_read_u32(dev, "clock-frequency", &config_khz); 1198 1204 if (ret < 0) 1199 - config_khz = MLXBF_I2C_TIMING_100KHZ; 1205 + config_khz = I2C_MAX_STANDARD_MODE_FREQ; 1200 1206 1201 1207 switch (config_khz) { 1202 1208 default: ··· 1204 1210 pr_warn("Illegal value %d: defaulting to 100 KHz\n", 1205 1211 config_khz); 1206 1212 fallthrough; 1207 - case MLXBF_I2C_TIMING_100KHZ: 1213 + case I2C_MAX_STANDARD_MODE_FREQ: 1208 1214 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ; 1209 1215 break; 1210 1216 1211 - case MLXBF_I2C_TIMING_400KHZ: 1217 + case I2C_MAX_FAST_MODE_FREQ: 1212 1218 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ; 1213 1219 break; 1214 1220 1215 - case MLXBF_I2C_TIMING_1000KHZ: 1221 + case I2C_MAX_FAST_MODE_PLUS_FREQ: 1216 1222 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ; 1217 1223 break; 1218 1224 } ··· 2370 2376 mlxbf_i2c_init_slave(pdev, priv); 2371 2377 2372 2378 irq = platform_get_irq(pdev, 0); 2379 + if (irq < 0) 2380 + return irq; 2373 2381 ret = devm_request_irq(dev, irq, mlxbf_smbus_irq, 2374 2382 IRQF_ONESHOT | IRQF_SHARED | IRQF_PROBE_SHARED, 2375 2383 dev_name(dev), priv);

+298 -281

drivers/i2c/busses/i2c-mpc.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 - * (C) Copyright 2003-2004 3 - * Humboldt Solutions Ltd, adrian@humboldt.co.uk. 4 - 5 3 * This is a combined i2c adapter and algorithm driver for the 6 4 * MPC107/Tsi107 PowerPC northbridge and processors that include 7 5 * the same I2C unit (8240, 8245, 85xx). 8 6 * 9 - * Release 0.8 10 - * 11 - * This file is licensed under the terms of the GNU General Public 12 - * License version 2. This program is licensed "as is" without any 13 - * warranty of any kind, whether express or implied. 7 + * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk 8 + * Copyright (C) 2021 Allied Telesis Labs 14 9 */ 15 10 16 11 #include <linux/kernel.h> ··· 14 19 #include <linux/of_address.h> 15 20 #include <linux/of_irq.h> 16 21 #include <linux/of_platform.h> 22 + #include <linux/property.h> 17 23 #include <linux/slab.h> 18 24 19 25 #include <linux/clk.h> ··· 54 58 #define CSR_MIF 0x02 55 59 #define CSR_RXAK 0x01 56 60 61 + enum mpc_i2c_action { 62 + MPC_I2C_ACTION_START = 1, 63 + MPC_I2C_ACTION_RESTART, 64 + MPC_I2C_ACTION_READ_BEGIN, 65 + MPC_I2C_ACTION_READ_BYTE, 66 + MPC_I2C_ACTION_WRITE, 67 + MPC_I2C_ACTION_STOP, 68 + 69 + __MPC_I2C_ACTION_CNT 70 + }; 71 + 72 + static const char * const action_str[] = { 73 + "invalid", 74 + "start", 75 + "restart", 76 + "read begin", 77 + "read", 78 + "write", 79 + "stop", 80 + }; 81 + 82 + static_assert(ARRAY_SIZE(action_str) == __MPC_I2C_ACTION_CNT); 83 + 57 84 struct mpc_i2c { 58 85 struct device *dev; 59 86 void __iomem *base; 60 87 u32 interrupt; 61 - wait_queue_head_t queue; 88 + wait_queue_head_t waitq; 89 + spinlock_t lock; 62 90 struct i2c_adapter adap; 63 91 int irq; 64 92 u32 real_clk; 65 - #ifdef CONFIG_PM_SLEEP 66 93 u8 fdr, dfsrr; 67 - #endif 68 94 struct clk *clk_per; 95 + u32 cntl_bits; 96 + enum mpc_i2c_action action; 97 + struct i2c_msg *msgs; 98 + int num_msgs; 99 + int curr_msg; 100 + u32 byte_posn; 101 + u32 block; 102 + int rc; 103 + int expect_rxack; 104 + 69 105 }; 70 106 71 107 struct mpc_i2c_divider { ··· 112 84 static inline void writeccr(struct mpc_i2c *i2c, u32 x) 113 85 { 114 86 writeb(x, i2c->base + MPC_I2C_CR); 115 - } 116 - 117 - static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) 118 - { 119 - struct mpc_i2c *i2c = dev_id; 120 - if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) { 121 - /* Read again to allow register to stabilise */ 122 - i2c->interrupt = readb(i2c->base + MPC_I2C_SR); 123 - writeb(0, i2c->base + MPC_I2C_SR); 124 - wake_up(&i2c->queue); 125 - return IRQ_HANDLED; 126 - } 127 - return IRQ_NONE; 128 87 } 129 88 130 89 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release ··· 134 119 writeccr(i2c, CCR_MEN); 135 120 udelay(delay_val << 1); 136 121 } 137 - } 138 - 139 - static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing) 140 - { 141 - unsigned long orig_jiffies = jiffies; 142 - u32 cmd_err; 143 - int result = 0; 144 - 145 - if (!i2c->irq) { 146 - while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) { 147 - schedule(); 148 - if (time_after(jiffies, orig_jiffies + timeout)) { 149 - dev_dbg(i2c->dev, "timeout\n"); 150 - writeccr(i2c, 0); 151 - result = -ETIMEDOUT; 152 - break; 153 - } 154 - } 155 - cmd_err = readb(i2c->base + MPC_I2C_SR); 156 - writeb(0, i2c->base + MPC_I2C_SR); 157 - } else { 158 - /* Interrupt mode */ 159 - result = wait_event_timeout(i2c->queue, 160 - (i2c->interrupt & CSR_MIF), timeout); 161 - 162 - if (unlikely(!(i2c->interrupt & CSR_MIF))) { 163 - dev_dbg(i2c->dev, "wait timeout\n"); 164 - writeccr(i2c, 0); 165 - result = -ETIMEDOUT; 166 - } 167 - 168 - cmd_err = i2c->interrupt; 169 - i2c->interrupt = 0; 170 - } 171 - 172 - if (result < 0) 173 - return result; 174 - 175 - if (!(cmd_err & CSR_MCF)) { 176 - dev_dbg(i2c->dev, "unfinished\n"); 177 - return -EIO; 178 - } 179 - 180 - if (cmd_err & CSR_MAL) { 181 - dev_dbg(i2c->dev, "MAL\n"); 182 - return -EAGAIN; 183 - } 184 - 185 - if (writing && (cmd_err & CSR_RXAK)) { 186 - dev_dbg(i2c->dev, "No RXAK\n"); 187 - /* generate stop */ 188 - writeccr(i2c, CCR_MEN); 189 - return -ENXIO; 190 - } 191 - return 0; 192 122 } 193 123 194 124 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x) ··· 375 415 } 376 416 377 417 *real_clk = fsl_get_sys_freq() / prescaler / div->divider; 378 - return div ? (int)div->fdr : -EINVAL; 418 + return (int)div->fdr; 379 419 } 380 420 381 421 static void mpc_i2c_setup_8xxx(struct device_node *node, ··· 410 450 } 411 451 #endif /* CONFIG_FSL_SOC */ 412 452 413 - static void mpc_i2c_start(struct mpc_i2c *i2c) 453 + static void mpc_i2c_finish(struct mpc_i2c *i2c, int rc) 414 454 { 415 - /* Clear arbitration */ 416 - writeb(0, i2c->base + MPC_I2C_SR); 417 - /* Start with MEN */ 418 - writeccr(i2c, CCR_MEN); 455 + i2c->rc = rc; 456 + i2c->block = 0; 457 + i2c->cntl_bits = CCR_MEN; 458 + writeccr(i2c, i2c->cntl_bits); 459 + wake_up(&i2c->waitq); 419 460 } 420 461 421 - static void mpc_i2c_stop(struct mpc_i2c *i2c) 462 + static void mpc_i2c_do_action(struct mpc_i2c *i2c) 422 463 { 423 - writeccr(i2c, CCR_MEN); 424 - } 464 + struct i2c_msg *msg = &i2c->msgs[i2c->curr_msg]; 465 + int dir = 0; 466 + int recv_len = 0; 467 + u8 byte; 425 468 426 - static int mpc_write(struct mpc_i2c *i2c, int target, 427 - const u8 *data, int length, int restart) 428 - { 429 - int i, result; 430 - unsigned timeout = i2c->adap.timeout; 431 - u32 flags = restart ? CCR_RSTA : 0; 469 + dev_dbg(i2c->dev, "action = %s\n", action_str[i2c->action]); 432 470 433 - /* Start as master */ 434 - writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags); 435 - /* Write target byte */ 436 - writeb((target << 1), i2c->base + MPC_I2C_DR); 471 + i2c->cntl_bits &= ~(CCR_RSTA | CCR_MTX | CCR_TXAK); 437 472 438 - result = i2c_wait(i2c, timeout, 1); 439 - if (result < 0) 440 - return result; 473 + if (msg->flags & I2C_M_RD) 474 + dir = 1; 475 + if (msg->flags & I2C_M_RECV_LEN) 476 + recv_len = 1; 441 477 442 - for (i = 0; i < length; i++) { 443 - /* Write data byte */ 444 - writeb(data[i], i2c->base + MPC_I2C_DR); 478 + switch (i2c->action) { 479 + case MPC_I2C_ACTION_RESTART: 480 + i2c->cntl_bits |= CCR_RSTA; 481 + fallthrough; 445 482 446 - result = i2c_wait(i2c, timeout, 1); 447 - if (result < 0) 448 - return result; 449 - } 483 + case MPC_I2C_ACTION_START: 484 + i2c->cntl_bits |= CCR_MSTA | CCR_MTX; 485 + writeccr(i2c, i2c->cntl_bits); 486 + writeb((msg->addr << 1) | dir, i2c->base + MPC_I2C_DR); 487 + i2c->expect_rxack = 1; 488 + i2c->action = dir ? MPC_I2C_ACTION_READ_BEGIN : MPC_I2C_ACTION_WRITE; 489 + break; 450 490 451 - return 0; 452 - } 491 + case MPC_I2C_ACTION_READ_BEGIN: 492 + if (msg->len) { 493 + if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN)) 494 + i2c->cntl_bits |= CCR_TXAK; 453 495 454 - static int mpc_read(struct mpc_i2c *i2c, int target, 455 - u8 *data, int length, int restart, bool recv_len) 456 - { 457 - unsigned timeout = i2c->adap.timeout; 458 - int i, result; 459 - u32 flags = restart ? CCR_RSTA : 0; 496 + writeccr(i2c, i2c->cntl_bits); 497 + /* Dummy read */ 498 + readb(i2c->base + MPC_I2C_DR); 499 + } 500 + i2c->action = MPC_I2C_ACTION_READ_BYTE; 501 + break; 460 502 461 - /* Switch to read - restart */ 462 - writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags); 463 - /* Write target address byte - this time with the read flag set */ 464 - writeb((target << 1) | 1, i2c->base + MPC_I2C_DR); 465 - 466 - result = i2c_wait(i2c, timeout, 1); 467 - if (result < 0) 468 - return result; 469 - 470 - if (length) { 471 - if (length == 1 && !recv_len) 472 - writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK); 473 - else 474 - writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA); 475 - /* Dummy read */ 476 - readb(i2c->base + MPC_I2C_DR); 477 - } 478 - 479 - for (i = 0; i < length; i++) { 480 - u8 byte; 481 - 482 - result = i2c_wait(i2c, timeout, 0); 483 - if (result < 0) 484 - return result; 485 - 486 - /* 487 - * For block reads, we have to know the total length (1st byte) 488 - * before we can determine if we are done. 489 - */ 490 - if (i || !recv_len) { 491 - /* Generate txack on next to last byte */ 492 - if (i == length - 2) 493 - writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA 494 - | CCR_TXAK); 503 + case MPC_I2C_ACTION_READ_BYTE: 504 + if (i2c->byte_posn || !recv_len) { 505 + /* Generate Tx ACK on next to last byte */ 506 + if (i2c->byte_posn == msg->len - 2) 507 + i2c->cntl_bits |= CCR_TXAK; 495 508 /* Do not generate stop on last byte */ 496 - if (i == length - 1) 497 - writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA 498 - | CCR_MTX); 509 + if (i2c->byte_posn == msg->len - 1) 510 + i2c->cntl_bits |= CCR_MTX; 511 + 512 + writeccr(i2c, i2c->cntl_bits); 499 513 } 500 514 501 515 byte = readb(i2c->base + MPC_I2C_DR); 502 516 503 - /* 504 - * Adjust length if first received byte is length. 505 - * The length is 1 length byte plus actually data length 506 - */ 507 - if (i == 0 && recv_len) { 508 - if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) 509 - return -EPROTO; 510 - length += byte; 517 + if (i2c->byte_posn == 0 && recv_len) { 518 + if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) { 519 + mpc_i2c_finish(i2c, -EPROTO); 520 + return; 521 + } 522 + msg->len += byte; 511 523 /* 512 - * For block reads, generate txack here if data length 524 + * For block reads, generate Tx ACK here if data length 513 525 * is 1 byte (total length is 2 bytes). 514 526 */ 515 - if (length == 2) 516 - writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA 517 - | CCR_TXAK); 527 + if (msg->len == 2) { 528 + i2c->cntl_bits |= CCR_TXAK; 529 + writeccr(i2c, i2c->cntl_bits); 530 + } 518 531 } 519 - data[i] = byte; 532 + 533 + dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], byte); 534 + msg->buf[i2c->byte_posn++] = byte; 535 + break; 536 + 537 + case MPC_I2C_ACTION_WRITE: 538 + dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], 539 + msg->buf[i2c->byte_posn]); 540 + writeb(msg->buf[i2c->byte_posn++], i2c->base + MPC_I2C_DR); 541 + i2c->expect_rxack = 1; 542 + break; 543 + 544 + case MPC_I2C_ACTION_STOP: 545 + mpc_i2c_finish(i2c, 0); 546 + break; 547 + 548 + default: 549 + WARN(1, "Unexpected action %d\n", i2c->action); 550 + break; 520 551 } 521 552 522 - return length; 553 + if (msg->len == i2c->byte_posn) { 554 + i2c->curr_msg++; 555 + i2c->byte_posn = 0; 556 + 557 + if (i2c->curr_msg == i2c->num_msgs) { 558 + i2c->action = MPC_I2C_ACTION_STOP; 559 + /* 560 + * We don't get another interrupt on read so 561 + * finish the transfer now 562 + */ 563 + if (dir) 564 + mpc_i2c_finish(i2c, 0); 565 + } else { 566 + i2c->action = MPC_I2C_ACTION_RESTART; 567 + } 568 + } 523 569 } 524 570 525 - static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 571 + static void mpc_i2c_do_intr(struct mpc_i2c *i2c, u8 status) 526 572 { 527 - struct i2c_msg *pmsg; 528 - int i; 529 - int ret = 0; 530 - unsigned long orig_jiffies = jiffies; 531 - struct mpc_i2c *i2c = i2c_get_adapdata(adap); 573 + spin_lock(&i2c->lock); 532 574 533 - mpc_i2c_start(i2c); 534 - 535 - /* Allow bus up to 1s to become not busy */ 536 - while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { 537 - if (signal_pending(current)) { 538 - dev_dbg(i2c->dev, "Interrupted\n"); 539 - writeccr(i2c, 0); 540 - return -EINTR; 541 - } 542 - if (time_after(jiffies, orig_jiffies + HZ)) { 543 - u8 status = readb(i2c->base + MPC_I2C_SR); 544 - 545 - dev_dbg(i2c->dev, "timeout\n"); 546 - if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) { 547 - writeb(status & ~CSR_MAL, 548 - i2c->base + MPC_I2C_SR); 549 - mpc_i2c_fixup(i2c); 550 - } 551 - return -EIO; 552 - } 553 - schedule(); 575 + if (!(status & CSR_MCF)) { 576 + dev_dbg(i2c->dev, "unfinished\n"); 577 + mpc_i2c_finish(i2c, -EIO); 578 + goto out; 554 579 } 555 580 556 - for (i = 0; ret >= 0 && i < num; i++) { 557 - pmsg = &msgs[i]; 558 - dev_dbg(i2c->dev, 559 - "Doing %s %d bytes to 0x%02x - %d of %d messages\n", 560 - pmsg->flags & I2C_M_RD ? "read" : "write", 561 - pmsg->len, pmsg->addr, i + 1, num); 562 - if (pmsg->flags & I2C_M_RD) { 563 - bool recv_len = pmsg->flags & I2C_M_RECV_LEN; 564 - 565 - ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i, 566 - recv_len); 567 - if (recv_len && ret > 0) 568 - pmsg->len = ret; 569 - } else { 570 - ret = 571 - mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i); 572 - } 581 + if (status & CSR_MAL) { 582 + dev_dbg(i2c->dev, "arbitration lost\n"); 583 + mpc_i2c_finish(i2c, -EAGAIN); 584 + goto out; 573 585 } 574 - mpc_i2c_stop(i2c); /* Initiate STOP */ 586 + 587 + if (i2c->expect_rxack && (status & CSR_RXAK)) { 588 + dev_dbg(i2c->dev, "no Rx ACK\n"); 589 + mpc_i2c_finish(i2c, -ENXIO); 590 + goto out; 591 + } 592 + i2c->expect_rxack = 0; 593 + 594 + mpc_i2c_do_action(i2c); 595 + 596 + out: 597 + spin_unlock(&i2c->lock); 598 + } 599 + 600 + static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) 601 + { 602 + struct mpc_i2c *i2c = dev_id; 603 + u8 status; 604 + 605 + status = readb(i2c->base + MPC_I2C_SR); 606 + if (status & CSR_MIF) { 607 + writeb(0, i2c->base + MPC_I2C_SR); 608 + mpc_i2c_do_intr(i2c, status); 609 + return IRQ_HANDLED; 610 + } 611 + return IRQ_NONE; 612 + } 613 + 614 + static int mpc_i2c_wait_for_completion(struct mpc_i2c *i2c) 615 + { 616 + long time_left; 617 + 618 + time_left = wait_event_timeout(i2c->waitq, !i2c->block, i2c->adap.timeout); 619 + if (!time_left) 620 + return -ETIMEDOUT; 621 + if (time_left < 0) 622 + return time_left; 623 + 624 + return 0; 625 + } 626 + 627 + static int mpc_i2c_execute_msg(struct mpc_i2c *i2c) 628 + { 629 + unsigned long orig_jiffies; 630 + unsigned long flags; 631 + int ret; 632 + 633 + spin_lock_irqsave(&i2c->lock, flags); 634 + 635 + i2c->curr_msg = 0; 636 + i2c->rc = 0; 637 + i2c->byte_posn = 0; 638 + i2c->block = 1; 639 + i2c->action = MPC_I2C_ACTION_START; 640 + 641 + i2c->cntl_bits = CCR_MEN | CCR_MIEN; 642 + writeb(0, i2c->base + MPC_I2C_SR); 643 + writeccr(i2c, i2c->cntl_bits); 644 + 645 + mpc_i2c_do_action(i2c); 646 + 647 + spin_unlock_irqrestore(&i2c->lock, flags); 648 + 649 + ret = mpc_i2c_wait_for_completion(i2c); 650 + if (ret) 651 + i2c->rc = ret; 652 + 653 + if (i2c->rc == -EIO || i2c->rc == -EAGAIN || i2c->rc == -ETIMEDOUT) 654 + i2c_recover_bus(&i2c->adap); 655 + 575 656 orig_jiffies = jiffies; 576 657 /* Wait until STOP is seen, allow up to 1 s */ 577 658 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { ··· 623 622 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) { 624 623 writeb(status & ~CSR_MAL, 625 624 i2c->base + MPC_I2C_SR); 626 - mpc_i2c_fixup(i2c); 625 + i2c_recover_bus(&i2c->adap); 627 626 } 628 627 return -EIO; 629 628 } 630 629 cond_resched(); 631 630 } 632 - return (ret < 0) ? ret : num; 631 + 632 + return i2c->rc; 633 + } 634 + 635 + static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 636 + { 637 + int rc, ret = num; 638 + struct mpc_i2c *i2c = i2c_get_adapdata(adap); 639 + int i; 640 + 641 + dev_dbg(i2c->dev, "num = %d\n", num); 642 + for (i = 0; i < num; i++) 643 + dev_dbg(i2c->dev, " addr = %02x, flags = %02x, len = %d, %*ph\n", 644 + msgs[i].addr, msgs[i].flags, msgs[i].len, 645 + msgs[i].flags & I2C_M_RD ? 0 : msgs[i].len, 646 + msgs[i].buf); 647 + 648 + WARN_ON(i2c->msgs != NULL); 649 + i2c->msgs = msgs; 650 + i2c->num_msgs = num; 651 + 652 + rc = mpc_i2c_execute_msg(i2c); 653 + if (rc < 0) 654 + ret = rc; 655 + 656 + i2c->num_msgs = 0; 657 + i2c->msgs = NULL; 658 + 659 + return ret; 633 660 } 634 661 635 662 static u32 mpc_functionality(struct i2c_adapter *adap) 636 663 { 637 664 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 638 665 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL; 666 + } 667 + 668 + static int fsl_i2c_bus_recovery(struct i2c_adapter *adap) 669 + { 670 + struct mpc_i2c *i2c = i2c_get_adapdata(adap); 671 + 672 + mpc_i2c_fixup(i2c); 673 + 674 + return 0; 639 675 } 640 676 641 677 static const struct i2c_algorithm mpc_algo = { ··· 686 648 .timeout = HZ, 687 649 }; 688 650 689 - static const struct of_device_id mpc_i2c_of_match[]; 651 + static struct i2c_bus_recovery_info fsl_i2c_recovery_info = { 652 + .recover_bus = fsl_i2c_bus_recovery, 653 + }; 654 + 690 655 static int fsl_i2c_probe(struct platform_device *op) 691 656 { 692 - const struct of_device_id *match; 657 + const struct mpc_i2c_data *data; 693 658 struct mpc_i2c *i2c; 694 659 const u32 *prop; 695 660 u32 clock = MPC_I2C_CLOCK_LEGACY; 696 661 int result = 0; 697 662 int plen; 698 - struct resource res; 699 663 struct clk *clk; 700 664 int err; 701 665 702 - match = of_match_device(mpc_i2c_of_match, &op->dev); 703 - if (!match) 704 - return -EINVAL; 705 - 706 - i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); 666 + i2c = devm_kzalloc(&op->dev, sizeof(*i2c), GFP_KERNEL); 707 667 if (!i2c) 708 668 return -ENOMEM; 709 669 710 670 i2c->dev = &op->dev; /* for debug and error output */ 711 671 712 - init_waitqueue_head(&i2c->queue); 672 + init_waitqueue_head(&i2c->waitq); 673 + spin_lock_init(&i2c->lock); 713 674 714 - i2c->base = of_iomap(op->dev.of_node, 0); 715 - if (!i2c->base) { 716 - dev_err(i2c->dev, "failed to map controller\n"); 717 - result = -ENOMEM; 718 - goto fail_map; 719 - } 675 + i2c->base = devm_platform_ioremap_resource(op, 0); 676 + if (IS_ERR(i2c->base)) 677 + return PTR_ERR(i2c->base); 720 678 721 - i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0); 722 - if (i2c->irq) { /* no i2c->irq implies polling */ 723 - result = request_irq(i2c->irq, mpc_i2c_isr, 724 - IRQF_SHARED, "i2c-mpc", i2c); 725 - if (result < 0) { 726 - dev_err(i2c->dev, "failed to attach interrupt\n"); 727 - goto fail_request; 728 - } 679 + i2c->irq = platform_get_irq(op, 0); 680 + if (i2c->irq < 0) 681 + return i2c->irq; 682 + 683 + result = devm_request_irq(&op->dev, i2c->irq, mpc_i2c_isr, 684 + IRQF_SHARED, "i2c-mpc", i2c); 685 + if (result < 0) { 686 + dev_err(i2c->dev, "failed to attach interrupt\n"); 687 + return result; 729 688 } 730 689 731 690 /* 732 691 * enable clock for the I2C peripheral (non fatal), 733 692 * keep a reference upon successful allocation 734 693 */ 735 - clk = devm_clk_get(&op->dev, NULL); 736 - if (!IS_ERR(clk)) { 737 - err = clk_prepare_enable(clk); 738 - if (err) { 739 - dev_err(&op->dev, "failed to enable clock\n"); 740 - goto fail_request; 741 - } else { 742 - i2c->clk_per = clk; 743 - } 694 + clk = devm_clk_get_optional(&op->dev, NULL); 695 + if (IS_ERR(clk)) 696 + return PTR_ERR(clk); 697 + 698 + err = clk_prepare_enable(clk); 699 + if (err) { 700 + dev_err(&op->dev, "failed to enable clock\n"); 701 + return err; 744 702 } 703 + 704 + i2c->clk_per = clk; 745 705 746 706 if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) { 747 707 clock = MPC_I2C_CLOCK_PRESERVE; ··· 750 714 clock = *prop; 751 715 } 752 716 753 - if (match->data) { 754 - const struct mpc_i2c_data *data = match->data; 717 + data = device_get_match_data(&op->dev); 718 + if (data) { 755 719 data->setup(op->dev.of_node, i2c, clock); 756 720 } else { 757 721 /* Backwards compatibility */ ··· 767 731 } 768 732 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ); 769 733 770 - platform_set_drvdata(op, i2c); 771 - 772 734 i2c->adap = mpc_ops; 773 - of_address_to_resource(op->dev.of_node, 0, &res); 774 735 scnprintf(i2c->adap.name, sizeof(i2c->adap.name), 775 - "MPC adapter at 0x%llx", (unsigned long long)res.start); 776 - i2c_set_adapdata(&i2c->adap, i2c); 736 + "MPC adapter (%s)", of_node_full_name(op->dev.of_node)); 777 737 i2c->adap.dev.parent = &op->dev; 738 + i2c->adap.nr = op->id; 778 739 i2c->adap.dev.of_node = of_node_get(op->dev.of_node); 740 + i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info; 741 + platform_set_drvdata(op, i2c); 742 + i2c_set_adapdata(&i2c->adap, i2c); 779 743 780 - result = i2c_add_adapter(&i2c->adap); 781 - if (result < 0) 744 + result = i2c_add_numbered_adapter(&i2c->adap); 745 + if (result) 782 746 goto fail_add; 783 747 784 - return result; 748 + return 0; 785 749 786 750 fail_add: 787 - if (i2c->clk_per) 788 - clk_disable_unprepare(i2c->clk_per); 789 - free_irq(i2c->irq, i2c); 790 - fail_request: 791 - irq_dispose_mapping(i2c->irq); 792 - iounmap(i2c->base); 793 - fail_map: 794 - kfree(i2c); 751 + clk_disable_unprepare(i2c->clk_per); 752 + 795 753 return result; 796 754 }; 797 755 ··· 795 765 796 766 i2c_del_adapter(&i2c->adap); 797 767 798 - if (i2c->clk_per) 799 - clk_disable_unprepare(i2c->clk_per); 768 + clk_disable_unprepare(i2c->clk_per); 800 769 801 - if (i2c->irq) 802 - free_irq(i2c->irq, i2c); 803 - 804 - irq_dispose_mapping(i2c->irq); 805 - iounmap(i2c->base); 806 - kfree(i2c); 807 770 return 0; 808 771 }; 809 772 810 - #ifdef CONFIG_PM_SLEEP 811 - static int mpc_i2c_suspend(struct device *dev) 773 + static int __maybe_unused mpc_i2c_suspend(struct device *dev) 812 774 { 813 775 struct mpc_i2c *i2c = dev_get_drvdata(dev); 814 776 ··· 810 788 return 0; 811 789 } 812 790 813 - static int mpc_i2c_resume(struct device *dev) 791 + static int __maybe_unused mpc_i2c_resume(struct device *dev) 814 792 { 815 793 struct mpc_i2c *i2c = dev_get_drvdata(dev); 816 794 ··· 819 797 820 798 return 0; 821 799 } 822 - 823 800 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume); 824 - #define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops) 825 - #else 826 - #define MPC_I2C_PM_OPS NULL 827 - #endif 828 801 829 802 static const struct mpc_i2c_data mpc_i2c_data_512x = { 830 803 .setup = mpc_i2c_setup_512x, ··· 862 845 .driver = { 863 846 .name = DRV_NAME, 864 847 .of_match_table = mpc_i2c_of_match, 865 - .pm = MPC_I2C_PM_OPS, 848 + .pm = &mpc_i2c_pm_ops, 866 849 }, 867 850 }; 868 851

+11 -6

drivers/i2c/busses/i2c-mt65xx.c

··· 231 231 struct i2c_adapter adap; /* i2c host adapter */ 232 232 struct device *dev; 233 233 struct completion msg_complete; 234 + struct i2c_timings timing_info; 234 235 235 236 /* set in i2c probe */ 236 237 void __iomem *base; /* i2c base addr */ ··· 480 479 { 481 480 u16 control_reg; 482 481 483 - if (i2c->dev_comp->dma_sync) { 482 + if (i2c->dev_comp->apdma_sync) { 484 483 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); 485 484 udelay(10); 486 485 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); ··· 565 564 566 565 static int mtk_i2c_max_step_cnt(unsigned int target_speed) 567 566 { 568 - if (target_speed > I2C_MAX_FAST_MODE_FREQ) 567 + if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) 569 568 return MAX_HS_STEP_CNT_DIV; 570 569 else 571 570 return MAX_STEP_CNT_DIV; ··· 608 607 else 609 608 clk_ns = sample_ns / 2; 610 609 611 - su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns); 610 + su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns + 611 + i2c->timing_info.scl_int_delay_ns, clk_ns); 612 612 if (su_sta_cnt > max_sta_cnt) 613 613 return -1; 614 614 ··· 637 635 if (sda_min > sda_max) 638 636 return -3; 639 637 640 - if (check_speed > I2C_MAX_FAST_MODE_FREQ) { 638 + if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { 641 639 if (i2c->dev_comp->ltiming_adjust) { 642 640 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | 643 641 (sample_cnt << 12) | (high_cnt << 8); ··· 852 850 853 851 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & 854 852 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 855 - if ((i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) || (left_num >= 1)) 853 + if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) 856 854 control_reg |= I2C_CONTROL_RS; 857 855 858 856 if (i2c->op == I2C_MASTER_WRRD) ··· 1069 1067 } 1070 1068 } 1071 1069 1072 - if (i2c->auto_restart && num >= 2 && i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) 1070 + if (i2c->auto_restart && num >= 2 && 1071 + i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) 1073 1072 /* ignore the first restart irq after the master code, 1074 1073 * otherwise the first transfer will be discarded. 1075 1074 */ ··· 1177 1174 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 1178 1175 i2c->use_push_pull = 1179 1176 of_property_read_bool(np, "mediatek,use-push-pull"); 1177 + 1178 + i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true); 1180 1179 1181 1180 return 0; 1182 1181 }

+2 -2

drivers/i2c/busses/i2c-nomadik.c

··· 277 277 goto exit; 278 278 279 279 /* disable the controller */ 280 - i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 280 + i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 281 281 282 282 disable_all_interrupts(dev); 283 283 ··· 525 525 dev->virtbase + I2C_CR); 526 526 527 527 /* enable the controller */ 528 - i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 528 + i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 529 529 530 530 init_completion(&dev->xfer_complete); 531 531

+5 -1

drivers/i2c/busses/i2c-nvidia-gpu.c

··· 262 262 { } 263 263 }; 264 264 265 + static const struct software_node ccgx_node = { 266 + .properties = ccgx_props, 267 + }; 268 + 265 269 static int gpu_populate_client(struct gpu_i2c_dev *i2cd, int irq) 266 270 { 267 271 i2cd->gpu_ccgx_ucsi = devm_kzalloc(i2cd->dev, ··· 278 274 sizeof(i2cd->gpu_ccgx_ucsi->type)); 279 275 i2cd->gpu_ccgx_ucsi->addr = 0x8; 280 276 i2cd->gpu_ccgx_ucsi->irq = irq; 281 - i2cd->gpu_ccgx_ucsi->properties = ccgx_props; 277 + i2cd->gpu_ccgx_ucsi->swnode = &ccgx_node; 282 278 i2cd->ccgx_client = i2c_new_client_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi); 283 279 return PTR_ERR_OR_ZERO(i2cd->ccgx_client); 284 280 }

+4 -4

drivers/i2c/busses/i2c-omap.c

··· 1404 1404 pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT); 1405 1405 pm_runtime_use_autosuspend(omap->dev); 1406 1406 1407 - r = pm_runtime_get_sync(omap->dev); 1407 + r = pm_runtime_resume_and_get(omap->dev); 1408 1408 if (r < 0) 1409 - goto err_free_mem; 1409 + goto err_disable_pm; 1410 1410 1411 1411 /* 1412 1412 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. ··· 1513 1513 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0); 1514 1514 pm_runtime_dont_use_autosuspend(omap->dev); 1515 1515 pm_runtime_put_sync(omap->dev); 1516 + err_disable_pm: 1516 1517 pm_runtime_disable(&pdev->dev); 1517 - err_free_mem: 1518 1518 1519 1519 return r; 1520 1520 } ··· 1525 1525 int ret; 1526 1526 1527 1527 i2c_del_adapter(&omap->adapter); 1528 - ret = pm_runtime_get_sync(&pdev->dev); 1528 + ret = pm_runtime_resume_and_get(&pdev->dev); 1529 1529 if (ret < 0) 1530 1530 return ret; 1531 1531

-5

drivers/i2c/busses/i2c-powermac.c

··· 76 76 * but I think the current API makes no sense and I don't want 77 77 * any driver that I haven't verified for correctness to go 78 78 * anywhere near a pmac i2c bus anyway ... 79 - * 80 - * I'm also not completely sure what kind of phases to do between 81 - * the actual command and the data (what I am _supposed_ to do that 82 - * is). For now, I assume writes are a single stream and reads have 83 - * a repeat start/addr phase (but not stop in between) 84 79 */ 85 80 case I2C_SMBUS_BLOCK_DATA: 86 81 buf = data->block;

+2 -2

drivers/i2c/busses/i2c-qcom-cci.c

··· 569 569 cci->master[idx].mode = I2C_MODE_STANDARD; 570 570 ret = of_property_read_u32(child, "clock-frequency", &val); 571 571 if (!ret) { 572 - if (val == 400000) 572 + if (val == I2C_MAX_FAST_MODE_FREQ) 573 573 cci->master[idx].mode = I2C_MODE_FAST; 574 - else if (val == 1000000) 574 + else if (val == I2C_MAX_FAST_MODE_PLUS_FREQ) 575 575 cci->master[idx].mode = I2C_MODE_FAST_PLUS; 576 576 } 577 577

+82 -7

drivers/i2c/busses/i2c-rcar.c

··· 141 141 enum dma_data_direction dma_direction; 142 142 143 143 struct reset_control *rstc; 144 + bool atomic_xfer; 144 145 int irq; 145 146 146 147 struct i2c_client *host_notify_client; ··· 354 353 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 355 354 rcar_i2c_write(priv, ICMSR, 0); 356 355 } 357 - rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 356 + 357 + if (!priv->atomic_xfer) 358 + rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 358 359 } 359 360 360 361 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) ··· 421 418 int len; 422 419 423 420 /* Do various checks to see if DMA is feasible at all */ 424 - if (IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 421 + if (priv->atomic_xfer || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 425 422 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA)) 426 423 return false; 427 424 ··· 649 646 /* Nack */ 650 647 if (msr & MNR) { 651 648 /* HW automatically sends STOP after received NACK */ 652 - rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 649 + if (!priv->atomic_xfer) 650 + rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 653 651 priv->flags |= ID_NACK; 654 652 goto out; 655 653 } ··· 671 667 if (priv->flags & ID_DONE) { 672 668 rcar_i2c_write(priv, ICMIER, 0); 673 669 rcar_i2c_write(priv, ICMSR, 0); 674 - wake_up(&priv->wait); 670 + if (!priv->atomic_xfer) 671 + wake_up(&priv->wait); 675 672 } 676 673 677 674 return IRQ_HANDLED; ··· 689 684 690 685 /* Only handle interrupts that are currently enabled */ 691 686 msr = rcar_i2c_read(priv, ICMSR); 692 - msr &= rcar_i2c_read(priv, ICMIER); 687 + if (!priv->atomic_xfer) 688 + msr &= rcar_i2c_read(priv, ICMIER); 693 689 694 690 return rcar_i2c_irq(irq, priv, msr); 695 691 } ··· 702 696 703 697 /* Only handle interrupts that are currently enabled */ 704 698 msr = rcar_i2c_read(priv, ICMSR); 705 - msr &= rcar_i2c_read(priv, ICMIER); 699 + if (!priv->atomic_xfer) 700 + msr &= rcar_i2c_read(priv, ICMIER); 706 701 707 702 /* 708 703 * Clear START or STOP immediately, except for REPSTART after read or ··· 811 804 int i, ret; 812 805 long time_left; 813 806 807 + priv->atomic_xfer = false; 808 + 814 809 pm_runtime_get_sync(dev); 815 810 816 811 /* Check bus state before init otherwise bus busy info will be lost */ ··· 847 838 /* cleanup DMA if it couldn't complete properly due to an error */ 848 839 if (priv->dma_direction != DMA_NONE) 849 840 rcar_i2c_cleanup_dma(priv); 841 + 842 + if (!time_left) { 843 + rcar_i2c_init(priv); 844 + ret = -ETIMEDOUT; 845 + } else if (priv->flags & ID_NACK) { 846 + ret = -ENXIO; 847 + } else if (priv->flags & ID_ARBLOST) { 848 + ret = -EAGAIN; 849 + } else { 850 + ret = num - priv->msgs_left; /* The number of transfer */ 851 + } 852 + out: 853 + pm_runtime_put(dev); 854 + 855 + if (ret < 0 && ret != -ENXIO) 856 + dev_err(dev, "error %d : %x\n", ret, priv->flags); 857 + 858 + return ret; 859 + } 860 + 861 + static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap, 862 + struct i2c_msg *msgs, 863 + int num) 864 + { 865 + struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 866 + struct device *dev = rcar_i2c_priv_to_dev(priv); 867 + unsigned long j; 868 + bool time_left; 869 + int ret; 870 + 871 + priv->atomic_xfer = true; 872 + 873 + pm_runtime_get_sync(dev); 874 + 875 + /* Check bus state before init otherwise bus busy info will be lost */ 876 + ret = rcar_i2c_bus_barrier(priv); 877 + if (ret < 0) 878 + goto out; 879 + 880 + rcar_i2c_init(priv); 881 + 882 + /* init first message */ 883 + priv->msg = msgs; 884 + priv->msgs_left = num; 885 + priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 886 + rcar_i2c_prepare_msg(priv); 887 + 888 + j = jiffies + num * adap->timeout; 889 + do { 890 + u32 msr = rcar_i2c_read(priv, ICMSR); 891 + 892 + msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP; 893 + 894 + if (msr) { 895 + if (priv->devtype < I2C_RCAR_GEN3) 896 + rcar_i2c_gen2_irq(0, priv); 897 + else 898 + rcar_i2c_gen3_irq(0, priv); 899 + } 900 + 901 + time_left = time_before_eq(jiffies, j); 902 + } while (!(priv->flags & ID_DONE) && time_left); 850 903 851 904 if (!time_left) { 852 905 rcar_i2c_init(priv); ··· 993 922 994 923 static const struct i2c_algorithm rcar_i2c_algo = { 995 924 .master_xfer = rcar_i2c_master_xfer, 925 + .master_xfer_atomic = rcar_i2c_master_xfer_atomic, 996 926 .functionality = rcar_i2c_func, 997 927 .reg_slave = rcar_reg_slave, 998 928 .unreg_slave = rcar_unreg_slave, ··· 1099 1027 if (of_property_read_bool(dev->of_node, "smbus")) 1100 1028 priv->flags |= ID_P_HOST_NOTIFY; 1101 1029 1102 - priv->irq = platform_get_irq(pdev, 0); 1030 + ret = platform_get_irq(pdev, 0); 1031 + if (ret < 0) 1032 + goto out_pm_disable; 1033 + priv->irq = ret; 1103 1034 ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv); 1104 1035 if (ret < 0) { 1105 1036 dev_err(dev, "cannot get irq %d\n", priv->irq);

+3 -6

drivers/i2c/busses/i2c-s3c2410.c

··· 24 24 #include <linux/slab.h> 25 25 #include <linux/io.h> 26 26 #include <linux/of.h> 27 + #include <linux/of_device.h> 27 28 #include <linux/gpio/consumer.h> 28 29 #include <linux/pinctrl/consumer.h> 29 30 #include <linux/mfd/syscon.h> ··· 157 156 */ 158 157 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev) 159 158 { 160 - if (pdev->dev.of_node) { 161 - const struct of_device_id *match; 162 - 163 - match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node); 164 - return (kernel_ulong_t)match->data; 165 - } 159 + if (pdev->dev.of_node) 160 + return (kernel_ulong_t)of_device_get_match_data(&pdev->dev); 166 161 167 162 return platform_get_device_id(pdev)->driver_data; 168 163 }

-2

drivers/i2c/busses/i2c-scmi.c

··· 18 18 /* SMBUS HID definition as supported by Microsoft Windows */ 19 19 #define ACPI_SMBUS_MS_HID "SMB0001" 20 20 21 - ACPI_MODULE_NAME("smbus_cmi"); 22 - 23 21 struct smbus_methods_t { 24 22 char *mt_info; 25 23 char *mt_sbr;

+4 -1

drivers/i2c/busses/i2c-sh7760.c

··· 471 471 goto out2; 472 472 } 473 473 474 - id->irq = platform_get_irq(pdev, 0); 474 + ret = platform_get_irq(pdev, 0); 475 + if (ret < 0) 476 + goto out3; 477 + id->irq = ret; 475 478 476 479 id->adap.nr = pdev->id; 477 480 id->adap.algo = &sh7760_i2c_algo;

+3 -2

drivers/i2c/busses/i2c-sprd.c

··· 290 290 struct sprd_i2c *i2c_dev = i2c_adap->algo_data; 291 291 int im, ret; 292 292 293 - ret = pm_runtime_get_sync(i2c_dev->dev); 293 + ret = pm_runtime_resume_and_get(i2c_dev->dev); 294 294 if (ret < 0) 295 295 return ret; 296 296 ··· 576 576 struct sprd_i2c *i2c_dev = platform_get_drvdata(pdev); 577 577 int ret; 578 578 579 - ret = pm_runtime_get_sync(i2c_dev->dev); 579 + ret = pm_runtime_resume_and_get(i2c_dev->dev); 580 580 if (ret < 0) 581 581 return ret; 582 582 ··· 640 640 { .compatible = "sprd,sc9860-i2c", }, 641 641 {}, 642 642 }; 643 + MODULE_DEVICE_TABLE(of, sprd_i2c_of_match); 643 644 644 645 static struct platform_driver sprd_i2c_driver = { 645 646 .probe = sprd_i2c_probe,

+42 -40

drivers/i2c/busses/i2c-stm32f7.c

··· 164 164 #define STM32F7_I2C_DNF_DEFAULT 0 165 165 #define STM32F7_I2C_DNF_MAX 15 166 166 167 - #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1 168 167 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 169 168 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 170 169 ··· 222 223 * @clock_src: I2C clock source frequency (Hz) 223 224 * @rise_time: Rise time (ns) 224 225 * @fall_time: Fall time (ns) 225 - * @dnf: Digital filter coefficient (0-16) 226 - * @analog_filter: Analog filter delay (On/Off) 227 226 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register 228 227 */ 229 228 struct stm32f7_i2c_setup { ··· 229 232 u32 clock_src; 230 233 u32 rise_time; 231 234 u32 fall_time; 232 - u8 dnf; 233 - bool analog_filter; 234 235 u32 fmp_clr_offset; 235 236 }; 236 237 ··· 307 312 * @wakeup_src: boolean to know if the device is a wakeup source 308 313 * @smbus_mode: states that the controller is configured in SMBus mode 309 314 * @host_notify_client: SMBus host-notify client 315 + * @analog_filter: boolean to indicate enabling of the analog filter 316 + * @dnf_dt: value of digital filter requested via dt 317 + * @dnf: value of digital filter to apply 310 318 */ 311 319 struct stm32f7_i2c_dev { 312 320 struct i2c_adapter adap; ··· 338 340 bool wakeup_src; 339 341 bool smbus_mode; 340 342 struct i2c_client *host_notify_client; 343 + bool analog_filter; 344 + u32 dnf_dt; 345 + u32 dnf; 341 346 }; 342 347 343 348 /* ··· 386 385 static const struct stm32f7_i2c_setup stm32f7_setup = { 387 386 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 388 387 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 389 - .dnf = STM32F7_I2C_DNF_DEFAULT, 390 - .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE, 391 388 }; 392 389 393 390 static const struct stm32f7_i2c_setup stm32mp15_setup = { 394 391 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 395 392 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 396 - .dnf = STM32F7_I2C_DNF_DEFAULT, 397 - .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE, 398 393 .fmp_clr_offset = 0x40, 399 394 }; 400 395 ··· 459 462 return -EINVAL; 460 463 } 461 464 462 - if (setup->dnf > STM32F7_I2C_DNF_MAX) { 465 + i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk); 466 + if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) { 463 467 dev_err(i2c_dev->dev, 464 468 "DNF out of bound %d/%d\n", 465 - setup->dnf, STM32F7_I2C_DNF_MAX); 469 + i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk); 466 470 return -EINVAL; 467 471 } 468 472 469 473 /* Analog and Digital Filters */ 470 474 af_delay_min = 471 - (setup->analog_filter ? 475 + (i2c_dev->analog_filter ? 472 476 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0); 473 477 af_delay_max = 474 - (setup->analog_filter ? 478 + (i2c_dev->analog_filter ? 475 479 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0); 476 - dnf_delay = setup->dnf * i2cclk; 480 + dnf_delay = i2c_dev->dnf * i2cclk; 477 481 478 482 sdadel_min = specs->hddat_min + setup->fall_time - 479 - af_delay_min - (setup->dnf + 3) * i2cclk; 483 + af_delay_min - (i2c_dev->dnf + 3) * i2cclk; 480 484 481 485 sdadel_max = specs->vddat_max - setup->rise_time - 482 - af_delay_max - (setup->dnf + 4) * i2cclk; 486 + af_delay_max - (i2c_dev->dnf + 4) * i2cclk; 483 487 484 488 scldel_min = setup->rise_time + specs->sudat_min; 485 489 ··· 646 648 setup->speed_freq = t->bus_freq_hz; 647 649 i2c_dev->setup.rise_time = t->scl_rise_ns; 648 650 i2c_dev->setup.fall_time = t->scl_fall_ns; 651 + i2c_dev->dnf_dt = t->digital_filter_width_ns; 649 652 setup->clock_src = clk_get_rate(i2c_dev->clk); 650 653 651 654 if (!setup->clock_src) { 652 655 dev_err(i2c_dev->dev, "clock rate is 0\n"); 653 656 return -EINVAL; 654 657 } 658 + 659 + if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter")) 660 + i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT; 655 661 656 662 do { 657 663 ret = stm32f7_i2c_compute_timing(i2c_dev, setup, ··· 678 676 return ret; 679 677 } 680 678 679 + i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node, 680 + "i2c-analog-filter"); 681 + 681 682 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n", 682 683 setup->speed_freq, setup->clock_src); 683 684 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", 684 685 setup->rise_time, setup->fall_time); 685 686 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", 686 - (setup->analog_filter ? "On" : "Off"), setup->dnf); 687 + (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf); 687 688 688 689 i2c_dev->bus_rate = setup->speed_freq; 689 690 ··· 725 720 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); 726 721 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 727 722 728 - /* Enable I2C */ 729 - if (i2c_dev->setup.analog_filter) 723 + /* Configure the Analog Filter */ 724 + if (i2c_dev->analog_filter) 730 725 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 731 726 STM32F7_I2C_CR1_ANFOFF); 732 727 else ··· 737 732 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 738 733 STM32F7_I2C_CR1_DNF_MASK); 739 734 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 740 - STM32F7_I2C_CR1_DNF(i2c_dev->setup.dnf)); 735 + STM32F7_I2C_CR1_DNF(i2c_dev->dnf)); 741 736 742 737 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 743 738 STM32F7_I2C_CR1_PE); ··· 1602 1597 1603 1598 /* Bus error */ 1604 1599 if (status & STM32F7_I2C_ISR_BERR) { 1605 - dev_err(dev, "<%s>: Bus error\n", __func__); 1600 + dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n", 1601 + __func__, f7_msg->addr); 1606 1602 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 1607 1603 stm32f7_i2c_release_bus(&i2c_dev->adap); 1608 1604 f7_msg->result = -EIO; ··· 1611 1605 1612 1606 /* Arbitration loss */ 1613 1607 if (status & STM32F7_I2C_ISR_ARLO) { 1614 - dev_dbg(dev, "<%s>: Arbitration loss\n", __func__); 1608 + dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n", 1609 + __func__, f7_msg->addr); 1615 1610 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); 1616 1611 f7_msg->result = -EAGAIN; 1617 1612 } 1618 1613 1619 1614 if (status & STM32F7_I2C_ISR_PECERR) { 1620 - dev_err(dev, "<%s>: PEC error in reception\n", __func__); 1615 + dev_err(dev, "<%s>: PEC error in reception accessing addr 0x%x\n", 1616 + __func__, f7_msg->addr); 1621 1617 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR); 1622 1618 f7_msg->result = -EINVAL; 1623 1619 } ··· 1660 1652 i2c_dev->msg_id = 0; 1661 1653 f7_msg->smbus = false; 1662 1654 1663 - ret = pm_runtime_get_sync(i2c_dev->dev); 1655 + ret = pm_runtime_resume_and_get(i2c_dev->dev); 1664 1656 if (ret < 0) 1665 1657 return ret; 1666 1658 ··· 1706 1698 f7_msg->read_write = read_write; 1707 1699 f7_msg->smbus = true; 1708 1700 1709 - ret = pm_runtime_get_sync(dev); 1701 + ret = pm_runtime_resume_and_get(dev); 1710 1702 if (ret < 0) 1711 1703 return ret; 1712 1704 ··· 1807 1799 if (ret) 1808 1800 return ret; 1809 1801 1810 - ret = pm_runtime_get_sync(dev); 1802 + ret = pm_runtime_resume_and_get(dev); 1811 1803 if (ret < 0) 1812 1804 return ret; 1813 1805 ··· 1888 1880 1889 1881 WARN_ON(!i2c_dev->slave[id]); 1890 1882 1891 - ret = pm_runtime_get_sync(i2c_dev->dev); 1883 + ret = pm_runtime_resume_and_get(i2c_dev->dev); 1892 1884 if (ret < 0) 1893 1885 return ret; 1894 1886 ··· 2035 2027 phy_addr = (dma_addr_t)res->start; 2036 2028 2037 2029 irq_event = platform_get_irq(pdev, 0); 2038 - if (irq_event <= 0) { 2039 - if (irq_event != -EPROBE_DEFER) 2040 - dev_err(&pdev->dev, "Failed to get IRQ event: %d\n", 2041 - irq_event); 2030 + if (irq_event <= 0) 2042 2031 return irq_event ? : -ENOENT; 2043 - } 2044 2032 2045 2033 irq_error = platform_get_irq(pdev, 1); 2046 2034 if (irq_error <= 0) ··· 2271 2267 return 0; 2272 2268 } 2273 2269 2274 - #ifdef CONFIG_PM_SLEEP 2275 - static int stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev) 2270 + static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev) 2276 2271 { 2277 2272 int ret; 2278 2273 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2279 2274 2280 - ret = pm_runtime_get_sync(i2c_dev->dev); 2275 + ret = pm_runtime_resume_and_get(i2c_dev->dev); 2281 2276 if (ret < 0) 2282 2277 return ret; 2283 2278 ··· 2292 2289 return ret; 2293 2290 } 2294 2291 2295 - static int stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev) 2292 + static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev) 2296 2293 { 2297 2294 u32 cr1; 2298 2295 int ret; 2299 2296 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2300 2297 2301 - ret = pm_runtime_get_sync(i2c_dev->dev); 2298 + ret = pm_runtime_resume_and_get(i2c_dev->dev); 2302 2299 if (ret < 0) 2303 2300 return ret; 2304 2301 ··· 2323 2320 return ret; 2324 2321 } 2325 2322 2326 - static int stm32f7_i2c_suspend(struct device *dev) 2323 + static int __maybe_unused stm32f7_i2c_suspend(struct device *dev) 2327 2324 { 2328 2325 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2329 2326 int ret; ··· 2344 2341 return 0; 2345 2342 } 2346 2343 2347 - static int stm32f7_i2c_resume(struct device *dev) 2344 + static int __maybe_unused stm32f7_i2c_resume(struct device *dev) 2348 2345 { 2349 2346 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2350 2347 int ret; ··· 2364 2361 2365 2362 return 0; 2366 2363 } 2367 - #endif 2368 2364 2369 2365 static const struct dev_pm_ops stm32f7_i2c_pm_ops = { 2370 2366 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,

+38 -41

drivers/i2c/busses/i2c-tegra-bpmp.c

··· 38 38 * firmware I2C driver to avoid any issues in future if Linux I2C flags are 39 39 * changed. 40 40 */ 41 - static int tegra_bpmp_xlate_flags(u16 flags, u16 *out) 41 + static void tegra_bpmp_xlate_flags(u16 flags, u16 *out) 42 42 { 43 - if (flags & I2C_M_TEN) { 43 + if (flags & I2C_M_TEN) 44 44 *out |= SERIALI2C_TEN; 45 - flags &= ~I2C_M_TEN; 46 - } 47 45 48 - if (flags & I2C_M_RD) { 46 + if (flags & I2C_M_RD) 49 47 *out |= SERIALI2C_RD; 50 - flags &= ~I2C_M_RD; 51 - } 52 48 53 - if (flags & I2C_M_STOP) { 49 + if (flags & I2C_M_STOP) 54 50 *out |= SERIALI2C_STOP; 55 - flags &= ~I2C_M_STOP; 56 - } 57 51 58 - if (flags & I2C_M_NOSTART) { 52 + if (flags & I2C_M_NOSTART) 59 53 *out |= SERIALI2C_NOSTART; 60 - flags &= ~I2C_M_NOSTART; 61 - } 62 54 63 - if (flags & I2C_M_REV_DIR_ADDR) { 55 + if (flags & I2C_M_REV_DIR_ADDR) 64 56 *out |= SERIALI2C_REV_DIR_ADDR; 65 - flags &= ~I2C_M_REV_DIR_ADDR; 66 - } 67 57 68 - if (flags & I2C_M_IGNORE_NAK) { 58 + if (flags & I2C_M_IGNORE_NAK) 69 59 *out |= SERIALI2C_IGNORE_NAK; 70 - flags &= ~I2C_M_IGNORE_NAK; 71 - } 72 60 73 - if (flags & I2C_M_NO_RD_ACK) { 61 + if (flags & I2C_M_NO_RD_ACK) 74 62 *out |= SERIALI2C_NO_RD_ACK; 75 - flags &= ~I2C_M_NO_RD_ACK; 76 - } 77 63 78 - if (flags & I2C_M_RECV_LEN) { 64 + if (flags & I2C_M_RECV_LEN) 79 65 *out |= SERIALI2C_RECV_LEN; 80 - flags &= ~I2C_M_RECV_LEN; 81 - } 82 - 83 - return 0; 84 66 } 85 67 86 68 /** ··· 79 97 * 80 98 * See deserialize_i2c documentation for the data format in the other direction. 81 99 */ 82 - static int tegra_bpmp_serialize_i2c_msg(struct tegra_bpmp_i2c *i2c, 100 + static void tegra_bpmp_serialize_i2c_msg(struct tegra_bpmp_i2c *i2c, 83 101 struct mrq_i2c_request *request, 84 102 struct i2c_msg *msgs, 85 103 unsigned int num) 86 104 { 87 105 char *buf = request->xfer.data_buf; 88 106 unsigned int i, j, pos = 0; 89 - int err; 90 107 91 108 for (i = 0; i < num; i++) { 92 109 struct i2c_msg *msg = &msgs[i]; 93 110 u16 flags = 0; 94 111 95 - err = tegra_bpmp_xlate_flags(msg->flags, &flags); 96 - if (err < 0) 97 - return err; 112 + tegra_bpmp_xlate_flags(msg->flags, &flags); 98 113 99 114 buf[pos++] = msg->addr & 0xff; 100 115 buf[pos++] = (msg->addr & 0xff00) >> 8; ··· 107 128 } 108 129 109 130 request->xfer.data_size = pos; 110 - 111 - return 0; 112 131 } 113 132 114 133 /** ··· 194 217 else 195 218 err = tegra_bpmp_transfer(i2c->bpmp, &msg); 196 219 197 - return err; 220 + if (err < 0) { 221 + dev_err(i2c->dev, "failed to transfer message: %d\n", err); 222 + return err; 223 + } 224 + 225 + if (msg.rx.ret != 0) { 226 + if (msg.rx.ret == -BPMP_EAGAIN) { 227 + dev_dbg(i2c->dev, "arbitration lost\n"); 228 + return -EAGAIN; 229 + } 230 + 231 + if (msg.rx.ret == -BPMP_ETIMEDOUT) { 232 + dev_dbg(i2c->dev, "timeout\n"); 233 + return -ETIMEDOUT; 234 + } 235 + 236 + if (msg.rx.ret == -BPMP_ENXIO) { 237 + dev_dbg(i2c->dev, "NAK\n"); 238 + return -ENXIO; 239 + } 240 + 241 + dev_err(i2c->dev, "transaction failed: %d\n", msg.rx.ret); 242 + return -EIO; 243 + } 244 + 245 + return 0; 198 246 } 199 247 200 248 static int tegra_bpmp_i2c_xfer_common(struct i2c_adapter *adapter, ··· 240 238 memset(&request, 0, sizeof(request)); 241 239 memset(&response, 0, sizeof(response)); 242 240 243 - err = tegra_bpmp_serialize_i2c_msg(i2c, &request, msgs, num); 244 - if (err < 0) { 245 - dev_err(i2c->dev, "failed to serialize message: %d\n", err); 246 - return err; 247 - } 248 - 241 + tegra_bpmp_serialize_i2c_msg(i2c, &request, msgs, num); 249 242 err = tegra_bpmp_i2c_msg_xfer(i2c, &request, &response, atomic); 250 243 if (err < 0) { 251 244 dev_err(i2c->dev, "failed to transfer message: %d\n", err);

-1

drivers/i2c/busses/i2c-xgene-slimpro.c

··· 19 19 #include <linux/module.h> 20 20 #include <linux/of.h> 21 21 #include <linux/platform_device.h> 22 - #include <linux/version.h> 23 22 24 23 #define MAILBOX_OP_TIMEOUT 1000 /* Operation time out in ms */ 25 24 #define MAILBOX_I2C_INDEX 0

+2 -2

drivers/i2c/busses/i2c-xiic.c

··· 706 706 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 707 707 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 708 708 709 - err = pm_runtime_get_sync(i2c->dev); 709 + err = pm_runtime_resume_and_get(i2c->dev); 710 710 if (err < 0) 711 711 return err; 712 712 ··· 873 873 /* remove adapter & data */ 874 874 i2c_del_adapter(&i2c->adap); 875 875 876 - ret = pm_runtime_get_sync(i2c->dev); 876 + ret = pm_runtime_resume_and_get(i2c->dev); 877 877 if (ret < 0) 878 878 return ret; 879 879

-11

drivers/i2c/i2c-boardinfo.c

··· 47 47 * 48 48 * The board info passed can safely be __initdata, but be careful of embedded 49 49 * pointers (for platform_data, functions, etc) since that won't be copied. 50 - * Device properties are deep-copied though. 51 50 */ 52 51 int i2c_register_board_info(int busnum, struct i2c_board_info const *info, unsigned len) 53 52 { ··· 70 71 71 72 devinfo->busnum = busnum; 72 73 devinfo->board_info = *info; 73 - 74 - if (info->properties) { 75 - devinfo->board_info.properties = 76 - property_entries_dup(info->properties); 77 - if (IS_ERR(devinfo->board_info.properties)) { 78 - status = PTR_ERR(devinfo->board_info.properties); 79 - kfree(devinfo); 80 - break; 81 - } 82 - } 83 74 84 75 if (info->resources) { 85 76 devinfo->board_info.resources =

+85 -29

drivers/i2c/i2c-core-base.c

··· 76 76 static_branch_dec(&i2c_trace_msg_key); 77 77 } 78 78 79 + const char *i2c_freq_mode_string(u32 bus_freq_hz) 80 + { 81 + switch (bus_freq_hz) { 82 + case I2C_MAX_STANDARD_MODE_FREQ: 83 + return "Standard Mode (100 kHz)"; 84 + case I2C_MAX_FAST_MODE_FREQ: 85 + return "Fast Mode (400 kHz)"; 86 + case I2C_MAX_FAST_MODE_PLUS_FREQ: 87 + return "Fast Mode Plus (1.0 MHz)"; 88 + case I2C_MAX_TURBO_MODE_FREQ: 89 + return "Turbo Mode (1.4 MHz)"; 90 + case I2C_MAX_HIGH_SPEED_MODE_FREQ: 91 + return "High Speed Mode (3.4 MHz)"; 92 + case I2C_MAX_ULTRA_FAST_MODE_FREQ: 93 + return "Ultra Fast Mode (5.0 MHz)"; 94 + default: 95 + return "Unknown Mode"; 96 + } 97 + } 98 + EXPORT_SYMBOL_GPL(i2c_freq_mode_string); 99 + 79 100 const struct i2c_device_id *i2c_match_id(const struct i2c_device_id *id, 80 101 const struct i2c_client *client) 81 102 { ··· 270 249 int i2c_recover_bus(struct i2c_adapter *adap) 271 250 { 272 251 if (!adap->bus_recovery_info) 273 - return -EOPNOTSUPP; 252 + return -EBUSY; 274 253 275 254 dev_dbg(&adap->dev, "Trying i2c bus recovery\n"); 276 255 return adap->bus_recovery_info->recover_bus(adap); ··· 540 519 if (status) 541 520 goto err_clear_wakeup_irq; 542 521 522 + client->devres_group_id = devres_open_group(&client->dev, NULL, 523 + GFP_KERNEL); 524 + if (!client->devres_group_id) { 525 + status = -ENOMEM; 526 + goto err_detach_pm_domain; 527 + } 528 + 543 529 /* 544 530 * When there are no more users of probe(), 545 531 * rename probe_new to probe. ··· 559 531 else 560 532 status = -EINVAL; 561 533 534 + /* 535 + * Note that we are not closing the devres group opened above so 536 + * even resources that were attached to the device after probe is 537 + * run are released when i2c_device_remove() is executed. This is 538 + * needed as some drivers would allocate additional resources, 539 + * for example when updating firmware. 540 + */ 541 + 562 542 if (status) 563 - goto err_detach_pm_domain; 543 + goto err_release_driver_resources; 564 544 565 545 return 0; 566 546 547 + err_release_driver_resources: 548 + devres_release_group(&client->dev, client->devres_group_id); 567 549 err_detach_pm_domain: 568 550 dev_pm_domain_detach(&client->dev, true); 569 551 err_clear_wakeup_irq: ··· 601 563 if (status) 602 564 dev_warn(dev, "remove failed (%pe), will be ignored\n", ERR_PTR(status)); 603 565 } 566 + 567 + devres_release_group(&client->dev, client->devres_group_id); 604 568 605 569 dev_pm_domain_detach(&client->dev, true); 606 570 ··· 652 612 if (len != -ENODEV) 653 613 return len; 654 614 655 - len = acpi_device_modalias(dev, buf, PAGE_SIZE -1); 615 + len = acpi_device_modalias(dev, buf, PAGE_SIZE - 1); 656 616 if (len != -ENODEV) 657 617 return len; 658 618 ··· 950 910 951 911 i2c_dev_set_name(adap, client, info); 952 912 953 - if (info->properties) { 954 - status = device_add_properties(&client->dev, info->properties); 913 + if (info->swnode) { 914 + status = device_add_software_node(&client->dev, info->swnode); 955 915 if (status) { 956 916 dev_err(&adap->dev, 957 - "Failed to add properties to client %s: %d\n", 917 + "Failed to add software node to client %s: %d\n", 958 918 client->name, status); 959 919 goto out_err_put_of_node; 960 920 } ··· 962 922 963 923 status = device_register(&client->dev); 964 924 if (status) 965 - goto out_free_props; 925 + goto out_remove_swnode; 966 926 967 927 dev_dbg(&adap->dev, "client [%s] registered with bus id %s\n", 968 928 client->name, dev_name(&client->dev)); 969 929 970 930 return client; 971 931 972 - out_free_props: 973 - if (info->properties) 974 - device_remove_properties(&client->dev); 932 + out_remove_swnode: 933 + device_remove_software_node(&client->dev); 975 934 out_err_put_of_node: 976 935 of_node_put(info->of_node); 977 936 out_err: ··· 1000 961 1001 962 if (ACPI_COMPANION(&client->dev)) 1002 963 acpi_device_clear_enumerated(ACPI_COMPANION(&client->dev)); 964 + device_remove_software_node(&client->dev); 1003 965 device_unregister(&client->dev); 1004 966 } 1005 967 EXPORT_SYMBOL_GPL(i2c_unregister_device); ··· 1057 1017 } 1058 1018 EXPORT_SYMBOL_GPL(i2c_new_dummy_device); 1059 1019 1060 - struct i2c_dummy_devres { 1061 - struct i2c_client *client; 1062 - }; 1063 - 1064 - static void devm_i2c_release_dummy(struct device *dev, void *res) 1020 + static void devm_i2c_release_dummy(void *client) 1065 1021 { 1066 - struct i2c_dummy_devres *this = res; 1067 - 1068 - i2c_unregister_device(this->client); 1022 + i2c_unregister_device(client); 1069 1023 } 1070 1024 1071 1025 /** ··· 1076 1042 struct i2c_adapter *adapter, 1077 1043 u16 address) 1078 1044 { 1079 - struct i2c_dummy_devres *dr; 1080 1045 struct i2c_client *client; 1081 - 1082 - dr = devres_alloc(devm_i2c_release_dummy, sizeof(*dr), GFP_KERNEL); 1083 - if (!dr) 1084 - return ERR_PTR(-ENOMEM); 1046 + int ret; 1085 1047 1086 1048 client = i2c_new_dummy_device(adapter, address); 1087 - if (IS_ERR(client)) { 1088 - devres_free(dr); 1089 - } else { 1090 - dr->client = client; 1091 - devres_add(dev, dr); 1092 - } 1049 + if (IS_ERR(client)) 1050 + return client; 1051 + 1052 + ret = devm_add_action_or_reset(dev, devm_i2c_release_dummy, client); 1053 + if (ret) 1054 + return ERR_PTR(ret); 1093 1055 1094 1056 return client; 1095 1057 } ··· 1733 1703 memset(&adap->dev, 0, sizeof(adap->dev)); 1734 1704 } 1735 1705 EXPORT_SYMBOL(i2c_del_adapter); 1706 + 1707 + static void devm_i2c_del_adapter(void *adapter) 1708 + { 1709 + i2c_del_adapter(adapter); 1710 + } 1711 + 1712 + /** 1713 + * devm_i2c_add_adapter - device-managed variant of i2c_add_adapter() 1714 + * @dev: managing device for adding this I2C adapter 1715 + * @adapter: the adapter to add 1716 + * Context: can sleep 1717 + * 1718 + * Add adapter with dynamic bus number, same with i2c_add_adapter() 1719 + * but the adapter will be auto deleted on driver detach. 1720 + */ 1721 + int devm_i2c_add_adapter(struct device *dev, struct i2c_adapter *adapter) 1722 + { 1723 + int ret; 1724 + 1725 + ret = i2c_add_adapter(adapter); 1726 + if (ret) 1727 + return ret; 1728 + 1729 + return devm_add_action_or_reset(dev, devm_i2c_del_adapter, adapter); 1730 + } 1731 + EXPORT_SYMBOL_GPL(devm_i2c_add_adapter); 1736 1732 1737 1733 static void i2c_parse_timing(struct device *dev, char *prop_name, u32 *cur_val_p, 1738 1734 u32 def_val, bool use_def)

+7 -2

drivers/i2c/i2c-dev.c

··· 440 440 sizeof(rdwr_arg))) 441 441 return -EFAULT; 442 442 443 - /* Put an arbitrary limit on the number of messages that can 444 - * be sent at once */ 443 + if (!rdwr_arg.msgs || rdwr_arg.nmsgs == 0) 444 + return -EINVAL; 445 + 446 + /* 447 + * Put an arbitrary limit on the number of messages that can 448 + * be sent at once 449 + */ 445 450 if (rdwr_arg.nmsgs > I2C_RDWR_IOCTL_MAX_MSGS) 446 451 return -EINVAL; 447 452

+4 -2

drivers/input/mouse/elantech.c

··· 1885 1885 }; 1886 1886 unsigned int idx = 0; 1887 1887 1888 - smbus_board.properties = i2c_props; 1889 - 1890 1888 i2c_props[idx++] = PROPERTY_ENTRY_U32("touchscreen-size-x", 1891 1889 info->x_max + 1); 1892 1890 i2c_props[idx++] = PROPERTY_ENTRY_U32("touchscreen-size-y", ··· 1915 1917 1916 1918 if (elantech_is_buttonpad(info)) 1917 1919 i2c_props[idx++] = PROPERTY_ENTRY_BOOL("elan,clickpad"); 1920 + 1921 + smbus_board.fwnode = fwnode_create_software_node(i2c_props, NULL); 1922 + if (IS_ERR(smbus_board.fwnode)) 1923 + return PTR_ERR(smbus_board.fwnode); 1918 1924 1919 1925 return psmouse_smbus_init(psmouse, &smbus_board, NULL, 0, false, 1920 1926 leave_breadcrumbs);

+60 -40

drivers/platform/chrome/chromeos_laptop.c

··· 52 52 enum i2c_adapter_type type; 53 53 u32 pci_devid; 54 54 55 + const struct property_entry *properties; 56 + 55 57 struct i2c_client *client; 56 58 }; 57 59 58 60 struct acpi_peripheral { 59 61 char hid[ACPI_ID_LEN]; 60 - const struct property_entry *properties; 62 + struct software_node swnode; 63 + struct i2c_client *client; 61 64 }; 62 65 63 66 struct chromeos_laptop { ··· 71 68 struct i2c_peripheral *i2c_peripherals; 72 69 unsigned int num_i2c_peripherals; 73 70 74 - const struct acpi_peripheral *acpi_peripherals; 71 + struct acpi_peripheral *acpi_peripherals; 75 72 unsigned int num_acpi_peripherals; 76 73 }; 77 74 ··· 164 161 165 162 static bool chromeos_laptop_adjust_client(struct i2c_client *client) 166 163 { 167 - const struct acpi_peripheral *acpi_dev; 164 + struct acpi_peripheral *acpi_dev; 168 165 struct acpi_device_id acpi_ids[2] = { }; 169 166 int i; 170 167 int error; ··· 178 175 memcpy(acpi_ids[0].id, acpi_dev->hid, ACPI_ID_LEN); 179 176 180 177 if (acpi_match_device(acpi_ids, &client->dev)) { 181 - error = device_add_properties(&client->dev, 182 - acpi_dev->properties); 178 + error = device_add_software_node(&client->dev, &acpi_dev->swnode); 183 179 if (error) { 184 180 dev_err(&client->dev, 185 181 "failed to add properties: %d\n", 186 182 error); 187 183 break; 188 184 } 185 + 186 + acpi_dev->client = client; 189 187 190 188 return true; 191 189 } ··· 197 193 198 194 static void chromeos_laptop_detach_i2c_client(struct i2c_client *client) 199 195 { 196 + struct acpi_peripheral *acpi_dev; 200 197 struct i2c_peripheral *i2c_dev; 201 198 int i; 202 199 203 - for (i = 0; i < cros_laptop->num_i2c_peripherals; i++) { 204 - i2c_dev = &cros_laptop->i2c_peripherals[i]; 200 + if (has_acpi_companion(&client->dev)) 201 + for (i = 0; i < cros_laptop->num_acpi_peripherals; i++) { 202 + acpi_dev = &cros_laptop->acpi_peripherals[i]; 205 203 206 - if (i2c_dev->client == client) 207 - i2c_dev->client = NULL; 208 - } 204 + if (acpi_dev->client == client) { 205 + acpi_dev->client = NULL; 206 + return; 207 + } 208 + } 209 + else 210 + for (i = 0; i < cros_laptop->num_i2c_peripherals; i++) { 211 + i2c_dev = &cros_laptop->i2c_peripherals[i]; 212 + 213 + if (i2c_dev->client == client) { 214 + i2c_dev->client = NULL; 215 + return; 216 + } 217 + } 209 218 } 210 219 211 220 static int chromeos_laptop_i2c_notifier_call(struct notifier_block *nb, ··· 319 302 .board_info = { 320 303 I2C_BOARD_INFO("atmel_mxt_ts", 321 304 ATMEL_TS_I2C_ADDR), 322 - .properties = 323 - chromebook_atmel_touchscreen_props, 324 305 .flags = I2C_CLIENT_WAKE, 325 306 }, 326 307 .dmi_name = "touchscreen", 327 308 .irqflags = IRQF_TRIGGER_FALLING, 328 309 .type = I2C_ADAPTER_PANEL, 329 310 .alt_addr = ATMEL_TS_I2C_BL_ADDR, 311 + .properties = chromebook_atmel_touchscreen_props, 330 312 }, 331 313 /* Touchpad. */ 332 314 { 333 315 .board_info = { 334 316 I2C_BOARD_INFO("atmel_mxt_tp", 335 317 ATMEL_TP_I2C_ADDR), 336 - .properties = 337 - chromebook_pixel_trackpad_props, 338 318 .flags = I2C_CLIENT_WAKE, 339 319 }, 340 320 .dmi_name = "trackpad", 341 321 .irqflags = IRQF_TRIGGER_FALLING, 342 322 .type = I2C_ADAPTER_VGADDC, 343 323 .alt_addr = ATMEL_TP_I2C_BL_ADDR, 324 + .properties = chromebook_pixel_trackpad_props, 344 325 }, 345 326 /* Light Sensor. */ 346 327 { ··· 429 414 .board_info = { 430 415 I2C_BOARD_INFO("atmel_mxt_ts", 431 416 ATMEL_TS_I2C_ADDR), 432 - .properties = 433 - chromebook_atmel_touchscreen_props, 434 417 .flags = I2C_CLIENT_WAKE, 435 418 }, 436 419 .dmi_name = "touchscreen", ··· 436 423 .type = I2C_ADAPTER_DESIGNWARE, 437 424 .pci_devid = PCI_DEVID(0, PCI_DEVFN(0x15, 0x2)), 438 425 .alt_addr = ATMEL_TS_I2C_BL_ADDR, 426 + .properties = chromebook_atmel_touchscreen_props, 439 427 }, 440 428 /* Touchpad. */ 441 429 { ··· 512 498 /* Touchpad */ 513 499 { 514 500 .hid = "ATML0000", 515 - .properties = samus_trackpad_props, 501 + .swnode = { 502 + .properties = samus_trackpad_props, 503 + }, 516 504 }, 517 505 /* Touchsceen */ 518 506 { 519 507 .hid = "ATML0001", 520 - .properties = chromebook_atmel_touchscreen_props, 508 + .swnode = { 509 + .properties = chromebook_atmel_touchscreen_props, 510 + }, 521 511 }, 522 512 }; 523 513 DECLARE_ACPI_CROS_LAPTOP(samus); ··· 530 512 /* Touchpad */ 531 513 { 532 514 .hid = "ATML0000", 533 - .properties = chromebook_pixel_trackpad_props, 515 + .swnode = { 516 + .properties = chromebook_pixel_trackpad_props, 517 + }, 534 518 }, 535 519 /* Touchsceen */ 536 520 { 537 521 .hid = "ATML0001", 538 - .properties = chromebook_atmel_touchscreen_props, 522 + .swnode = { 523 + .properties = chromebook_atmel_touchscreen_props, 524 + }, 539 525 }, 540 526 }; 541 527 DECLARE_ACPI_CROS_LAPTOP(generic_atmel); ··· 765 743 if (error) 766 744 goto err_out; 767 745 768 - /* We need to deep-copy properties */ 769 - if (info->properties) { 770 - info->properties = 771 - property_entries_dup(info->properties); 772 - if (IS_ERR(info->properties)) { 773 - error = PTR_ERR(info->properties); 746 + /* Create primary fwnode for the device - copies everything */ 747 + if (i2c_dev->properties) { 748 + info->fwnode = fwnode_create_software_node(i2c_dev->properties, NULL); 749 + if (IS_ERR(info->fwnode)) { 750 + error = PTR_ERR(info->fwnode); 774 751 goto err_out; 775 752 } 776 753 } ··· 781 760 while (--i >= 0) { 782 761 i2c_dev = &cros_laptop->i2c_peripherals[i]; 783 762 info = &i2c_dev->board_info; 784 - if (info->properties) 785 - property_entries_free(info->properties); 763 + if (!IS_ERR_OR_NULL(info->fwnode)) 764 + fwnode_remove_software_node(info->fwnode); 786 765 } 787 766 kfree(cros_laptop->i2c_peripherals); 788 767 return error; ··· 822 801 *acpi_dev = *src_dev; 823 802 824 803 /* We need to deep-copy properties */ 825 - if (src_dev->properties) { 826 - acpi_dev->properties = 827 - property_entries_dup(src_dev->properties); 828 - if (IS_ERR(acpi_dev->properties)) { 829 - error = PTR_ERR(acpi_dev->properties); 804 + if (src_dev->swnode.properties) { 805 + acpi_dev->swnode.properties = 806 + property_entries_dup(src_dev->swnode.properties); 807 + if (IS_ERR(acpi_dev->swnode.properties)) { 808 + error = PTR_ERR(acpi_dev->swnode.properties); 830 809 goto err_out; 831 810 } 832 811 } ··· 842 821 err_out: 843 822 while (--i >= 0) { 844 823 acpi_dev = &acpi_peripherals[i]; 845 - if (acpi_dev->properties) 846 - property_entries_free(acpi_dev->properties); 824 + if (!IS_ERR_OR_NULL(acpi_dev->swnode.properties)) 825 + property_entries_free(acpi_dev->swnode.properties); 847 826 } 848 827 849 828 kfree(acpi_peripherals); ··· 854 833 { 855 834 const struct acpi_peripheral *acpi_dev; 856 835 struct i2c_peripheral *i2c_dev; 857 - struct i2c_board_info *info; 858 836 int i; 859 837 860 838 for (i = 0; i < cros_laptop->num_i2c_peripherals; i++) { 861 839 i2c_dev = &cros_laptop->i2c_peripherals[i]; 862 - info = &i2c_dev->board_info; 863 - 864 840 i2c_unregister_device(i2c_dev->client); 865 - property_entries_free(info->properties); 866 841 } 867 842 868 843 for (i = 0; i < cros_laptop->num_acpi_peripherals; i++) { 869 844 acpi_dev = &cros_laptop->acpi_peripherals[i]; 870 845 871 - property_entries_free(acpi_dev->properties); 846 + if (acpi_dev->client) 847 + device_remove_software_node(&acpi_dev->client->dev); 848 + 849 + property_entries_free(acpi_dev->swnode.properties); 872 850 } 873 851 874 852 kfree(cros_laptop->i2c_peripherals);

+5 -1

drivers/platform/x86/intel_cht_int33fe_microb.c

··· 35 35 { } 36 36 }; 37 37 38 + static const struct software_node bq27xxx_node = { 39 + .properties = bq27xxx_props, 40 + }; 41 + 38 42 int cht_int33fe_microb_probe(struct cht_int33fe_data *data) 39 43 { 40 44 struct device *dev = data->dev; ··· 47 43 memset(&board_info, 0, sizeof(board_info)); 48 44 strscpy(board_info.type, "bq27542", ARRAY_SIZE(board_info.type)); 49 45 board_info.dev_name = "bq27542"; 50 - board_info.properties = bq27xxx_props; 46 + board_info.swnode = &bq27xxx_node; 51 47 data->battery_fg = i2c_acpi_new_device(dev, 1, &board_info); 52 48 53 49 return PTR_ERR_OR_ZERO(data->battery_fg);

+11 -2

include/linux/i2c.h

··· 51 51 struct property_entry; 52 52 53 53 #if IS_ENABLED(CONFIG_I2C) 54 + /* Return the Frequency mode string based on the bus frequency */ 55 + const char *i2c_freq_mode_string(u32 bus_freq_hz); 56 + 54 57 /* 55 58 * The master routines are the ones normally used to transmit data to devices 56 59 * on a bus (or read from them). Apart from two basic transfer functions to ··· 309 306 * userspace_devices list 310 307 * @slave_cb: Callback when I2C slave mode of an adapter is used. The adapter 311 308 * calls it to pass on slave events to the slave driver. 309 + * @devres_group_id: id of the devres group that will be created for resources 310 + * acquired when probing this device. 312 311 * 313 312 * An i2c_client identifies a single device (i.e. chip) connected to an 314 313 * i2c bus. The behaviour exposed to Linux is defined by the driver ··· 339 334 #if IS_ENABLED(CONFIG_I2C_SLAVE) 340 335 i2c_slave_cb_t slave_cb; /* callback for slave mode */ 341 336 #endif 337 + void *devres_group_id; /* ID of probe devres group */ 342 338 }; 343 339 #define to_i2c_client(d) container_of(d, struct i2c_client, dev) 344 340 ··· 397 391 * @platform_data: stored in i2c_client.dev.platform_data 398 392 * @of_node: pointer to OpenFirmware device node 399 393 * @fwnode: device node supplied by the platform firmware 400 - * @properties: additional device properties for the device 394 + * @swnode: software node for the device 401 395 * @resources: resources associated with the device 402 396 * @num_resources: number of resources in the @resources array 403 397 * @irq: stored in i2c_client.irq ··· 421 415 void *platform_data; 422 416 struct device_node *of_node; 423 417 struct fwnode_handle *fwnode; 424 - const struct property_entry *properties; 418 + const struct software_node *swnode; 425 419 const struct resource *resources; 426 420 unsigned int num_resources; 427 421 int irq; ··· 693 687 #define I2C_AQ_NO_ZERO_LEN_READ BIT(5) 694 688 #define I2C_AQ_NO_ZERO_LEN_WRITE BIT(6) 695 689 #define I2C_AQ_NO_ZERO_LEN (I2C_AQ_NO_ZERO_LEN_READ | I2C_AQ_NO_ZERO_LEN_WRITE) 690 + /* adapter cannot do repeated START */ 691 + #define I2C_AQ_NO_REP_START BIT(7) 696 692 697 693 /* 698 694 * i2c_adapter is the structure used to identify a physical i2c bus along ··· 852 844 */ 853 845 #if IS_ENABLED(CONFIG_I2C) 854 846 int i2c_add_adapter(struct i2c_adapter *adap); 847 + int devm_i2c_add_adapter(struct device *dev, struct i2c_adapter *adapter); 855 848 void i2c_del_adapter(struct i2c_adapter *adap); 856 849 int i2c_add_numbered_adapter(struct i2c_adapter *adap); 857 850

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