Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2024-01-04' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"These were from over the holiday period, mainly i915, a couple of
qaic, bridge and an mgag200.
qaic:
- fix GEM import
- add quirk for soc version
bridge:
- parade-ps8640, ti-sn65dsi86: fix aux reads bounds
mgag200:
- fix gamma LUT init
i915:
- Fix bogus DPCD rev usage for DP phy test pattern setup
- Fix handling of MMIO triggered reports in the OA buffer"
* tag 'drm-fixes-2024-01-04' of git://anongit.freedesktop.org/drm/drm:
drm/i915/perf: Update handling of MMIO triggered reports
drm/i915/dp: Fix passing the correct DPCD_REV for drm_dp_set_phy_test_pattern
drm/mgag200: Fix gamma lut not initialized for G200ER, G200EV, G200SE
drm/bridge: ps8640: Fix size mismatch warning w/ len
drm/bridge: ti-sn65dsi86: Never store more than msg->size bytes in AUX xfer
drm/bridge: parade-ps8640: Never store more than msg->size bytes in AUX xfer
accel/qaic: Implement quirk for SOC_HW_VERSION
accel/qaic: Fix GEM import path code
+83
-20
+14
-1
drivers/accel/qaic/mhi_controller.c
+14
-1
drivers/accel/qaic/mhi_controller.c
···
404
404
405
405
static int mhi_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 *out)
406
406
{
407
-
u32 tmp = readl_relaxed(addr);
407
+
u32 tmp;
408
408
409
+
/*
410
+
* SOC_HW_VERSION quirk
411
+
* The SOC_HW_VERSION register (offset 0x224) is not reliable and
412
+
* may contain uninitialized values, including 0xFFFFFFFF. This could
413
+
* cause a false positive link down error. Instead, intercept any
414
+
* reads and provide the correct value of the register.
415
+
*/
416
+
if (addr - mhi_cntrl->regs == 0x224) {
417
+
*out = 0x60110200;
418
+
return 0;
419
+
}
420
+
421
+
tmp = readl_relaxed(addr);
409
422
if (tmp == U32_MAX)
410
423
return -EIO;
411
424
+2
-4
drivers/accel/qaic/qaic_data.c
+2
-4
drivers/accel/qaic/qaic_data.c
···
777
777
struct dma_buf_attachment *attach;
778
778
struct drm_gem_object *obj;
779
779
struct qaic_bo *bo;
780
-
size_t size;
781
780
int ret;
782
781
783
782
bo = qaic_alloc_init_bo();
···
794
795
goto attach_fail;
795
796
}
796
797
797
-
size = PAGE_ALIGN(attach->dmabuf->size);
798
-
if (size == 0) {
798
+
if (!attach->dmabuf->size) {
799
799
ret = -EINVAL;
800
800
goto size_align_fail;
801
801
}
802
802
803
-
drm_gem_private_object_init(dev, obj, size);
803
+
drm_gem_private_object_init(dev, obj, attach->dmabuf->size);
804
804
/*
805
805
* skipping dma_buf_map_attachment() as we do not know the direction
806
806
* just yet. Once the direction is known in the subsequent IOCTL to
+4
-3
drivers/gpu/drm/bridge/parade-ps8640.c
+4
-3
drivers/gpu/drm/bridge/parade-ps8640.c
···
210
210
struct ps8640 *ps_bridge = aux_to_ps8640(aux);
211
211
struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL];
212
212
struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
213
-
unsigned int len = msg->size;
213
+
size_t len = msg->size;
214
214
unsigned int data;
215
215
unsigned int base;
216
216
int ret;
···
330
330
return ret;
331
331
}
332
332
333
-
buf[i] = data;
333
+
if (i < msg->size)
334
+
buf[i] = data;
334
335
}
335
336
}
336
337
337
-
return len;
338
+
return min(len, msg->size);
338
339
}
339
340
340
341
static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
+3
-1
drivers/gpu/drm/bridge/ti-sn65dsi86.c
+3
-1
drivers/gpu/drm/bridge/ti-sn65dsi86.c
···
527
527
u32 request_val = AUX_CMD_REQ(msg->request);
528
528
u8 *buf = msg->buffer;
529
529
unsigned int len = msg->size;
530
+
unsigned int short_len;
530
531
unsigned int val;
531
532
int ret;
532
533
u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
···
601
600
}
602
601
603
602
if (val & AUX_IRQ_STATUS_AUX_SHORT) {
604
-
ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &len);
603
+
ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len);
604
+
len = min(len, short_len);
605
605
if (ret)
606
606
goto exit;
607
607
} else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
+1
-1
drivers/gpu/drm/i915/display/intel_dp.c
+1
-1
drivers/gpu/drm/i915/display/intel_dp.c
+34
-5
drivers/gpu/drm/i915/i915_perf.c
+34
-5
drivers/gpu/drm/i915/i915_perf.c
···
772
772
* The reason field includes flags identifying what
773
773
* triggered this specific report (mostly timer
774
774
* triggered or e.g. due to a context switch).
775
-
*
776
-
* In MMIO triggered reports, some platforms do not set the
777
-
* reason bit in this field and it is valid to have a reason
778
-
* field of zero.
779
775
*/
780
776
reason = oa_report_reason(stream, report);
781
777
ctx_id = oa_context_id(stream, report32);
···
783
787
*
784
788
* Note: that we don't clear the valid_ctx_bit so userspace can
785
789
* understand that the ID has been squashed by the kernel.
790
+
*
791
+
* Update:
792
+
*
793
+
* On XEHP platforms the behavior of context id valid bit has
794
+
* changed compared to prior platforms. To describe this, we
795
+
* define a few terms:
796
+
*
797
+
* context-switch-report: This is a report with the reason type
798
+
* being context-switch. It is generated when a context switches
799
+
* out.
800
+
*
801
+
* context-valid-bit: A bit that is set in the report ID field
802
+
* to indicate that a valid context has been loaded.
803
+
*
804
+
* gpu-idle: A condition characterized by a
805
+
* context-switch-report with context-valid-bit set to 0.
806
+
*
807
+
* On prior platforms, context-id-valid bit is set to 0 only
808
+
* when GPU goes idle. In all other reports, it is set to 1.
809
+
*
810
+
* On XEHP platforms, context-valid-bit is set to 1 in a context
811
+
* switch report if a new context switched in. For all other
812
+
* reports it is set to 0.
813
+
*
814
+
* This change in behavior causes an issue with MMIO triggered
815
+
* reports. MMIO triggered reports have the markers in the
816
+
* context ID field and the context-valid-bit is 0. The logic
817
+
* below to squash the context ID would render the report
818
+
* useless since the user will not be able to find it in the OA
819
+
* buffer. Since MMIO triggered reports exist only on XEHP,
820
+
* we should avoid squashing these for XEHP platforms.
786
821
*/
787
-
if (oa_report_ctx_invalid(stream, report)) {
822
+
823
+
if (oa_report_ctx_invalid(stream, report) &&
824
+
GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 50)) {
788
825
ctx_id = INVALID_CTX_ID;
789
826
oa_context_id_squash(stream, report32);
790
827
}
+5
drivers/gpu/drm/mgag200/mgag200_drv.h
+5
drivers/gpu/drm/mgag200/mgag200_drv.h
···
392
392
.destroy = drm_plane_cleanup, \
393
393
DRM_GEM_SHADOW_PLANE_FUNCS
394
394
395
+
void mgag200_crtc_set_gamma_linear(struct mga_device *mdev, const struct drm_format_info *format);
396
+
void mgag200_crtc_set_gamma(struct mga_device *mdev,
397
+
const struct drm_format_info *format,
398
+
struct drm_color_lut *lut);
399
+
395
400
enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc,
396
401
const struct drm_display_mode *mode);
397
402
int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state);
+5
drivers/gpu/drm/mgag200/mgag200_g200er.c
+5
drivers/gpu/drm/mgag200/mgag200_g200er.c
···
202
202
203
203
mgag200_g200er_reset_tagfifo(mdev);
204
204
205
+
if (crtc_state->gamma_lut)
206
+
mgag200_crtc_set_gamma(mdev, format, crtc_state->gamma_lut->data);
207
+
else
208
+
mgag200_crtc_set_gamma_linear(mdev, format);
209
+
205
210
mgag200_enable_display(mdev);
206
211
207
212
if (funcs->enable_vidrst)
+5
drivers/gpu/drm/mgag200/mgag200_g200ev.c
+5
drivers/gpu/drm/mgag200/mgag200_g200ev.c
···
203
203
204
204
mgag200_g200ev_set_hiprilvl(mdev);
205
205
206
+
if (crtc_state->gamma_lut)
207
+
mgag200_crtc_set_gamma(mdev, format, crtc_state->gamma_lut->data);
208
+
else
209
+
mgag200_crtc_set_gamma_linear(mdev, format);
210
+
206
211
mgag200_enable_display(mdev);
207
212
208
213
if (funcs->enable_vidrst)
+5
drivers/gpu/drm/mgag200/mgag200_g200se.c
+5
drivers/gpu/drm/mgag200/mgag200_g200se.c
···
334
334
335
335
mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, format);
336
336
337
+
if (crtc_state->gamma_lut)
338
+
mgag200_crtc_set_gamma(mdev, format, crtc_state->gamma_lut->data);
339
+
else
340
+
mgag200_crtc_set_gamma_linear(mdev, format);
341
+
337
342
mgag200_enable_display(mdev);
338
343
339
344
if (funcs->enable_vidrst)
+5
-5
drivers/gpu/drm/mgag200/mgag200_mode.c
+5
-5
drivers/gpu/drm/mgag200/mgag200_mode.c
···
28
28
* This file contains setup code for the CRTC.
29
29
*/
30
30
31
-
static void mgag200_crtc_set_gamma_linear(struct mga_device *mdev,
32
-
const struct drm_format_info *format)
31
+
void mgag200_crtc_set_gamma_linear(struct mga_device *mdev,
32
+
const struct drm_format_info *format)
33
33
{
34
34
int i;
35
35
···
65
65
}
66
66
}
67
67
68
-
static void mgag200_crtc_set_gamma(struct mga_device *mdev,
69
-
const struct drm_format_info *format,
70
-
struct drm_color_lut *lut)
68
+
void mgag200_crtc_set_gamma(struct mga_device *mdev,
69
+
const struct drm_format_info *format,
70
+
struct drm_color_lut *lut)
71
71
{
72
72
int i;
73
73