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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge tag 'pci-v4.19-fixes-3' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Bjorn writes:
"PCI fixes for v4.19:
- Reprogram bridge prefetch registers to fix NVIDIA and Radeon issues
after suspend/resume (Daniel Drake)
- Fix mvebu I/O mapping creation sequence (Thomas Petazzoni)
- Fix minor MAINTAINERS file match issue (Bjorn Helgaas)"
* tag 'pci-v4.19-fixes-3' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
PCI: mvebu: Fix PCI I/O mapping creation sequence
MAINTAINERS: Remove obsolete drivers/pci pattern from ACPI section
PCI: Reprogram bridge prefetch registers on resume
+68
-14
-1
MAINTAINERS
-1
MAINTAINERS
+49
-5
drivers/pci/controller/pci-mvebu.c
+49
-5
drivers/pci/controller/pci-mvebu.c
···
1145
1145
{
1146
1146
struct device *dev = &pcie->pdev->dev;
1147
1147
struct device_node *np = dev->of_node;
1148
-
unsigned int i;
1149
1148
int ret;
1150
1149
1151
1150
INIT_LIST_HEAD(&pcie->resources);
···
1178
1179
resource_size(&pcie->io) - 1);
1179
1180
pcie->realio.name = "PCI I/O";
1180
1181
1181
-
for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K)
1182
-
pci_ioremap_io(i, pcie->io.start + i);
1183
-
1184
1182
pci_add_resource(&pcie->resources, &pcie->realio);
1185
1183
}
1186
1184
1187
1185
return devm_request_pci_bus_resources(dev, &pcie->resources);
1186
+
}
1187
+
1188
+
/*
1189
+
* This is a copy of pci_host_probe(), except that it does the I/O
1190
+
* remap as the last step, once we are sure we won't fail.
1191
+
*
1192
+
* It should be removed once the I/O remap error handling issue has
1193
+
* been sorted out.
1194
+
*/
1195
+
static int mvebu_pci_host_probe(struct pci_host_bridge *bridge)
1196
+
{
1197
+
struct mvebu_pcie *pcie;
1198
+
struct pci_bus *bus, *child;
1199
+
int ret;
1200
+
1201
+
ret = pci_scan_root_bus_bridge(bridge);
1202
+
if (ret < 0) {
1203
+
dev_err(bridge->dev.parent, "Scanning root bridge failed");
1204
+
return ret;
1205
+
}
1206
+
1207
+
pcie = pci_host_bridge_priv(bridge);
1208
+
if (resource_size(&pcie->io) != 0) {
1209
+
unsigned int i;
1210
+
1211
+
for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K)
1212
+
pci_ioremap_io(i, pcie->io.start + i);
1213
+
}
1214
+
1215
+
bus = bridge->bus;
1216
+
1217
+
/*
1218
+
* We insert PCI resources into the iomem_resource and
1219
+
* ioport_resource trees in either pci_bus_claim_resources()
1220
+
* or pci_bus_assign_resources().
1221
+
*/
1222
+
if (pci_has_flag(PCI_PROBE_ONLY)) {
1223
+
pci_bus_claim_resources(bus);
1224
+
} else {
1225
+
pci_bus_size_bridges(bus);
1226
+
pci_bus_assign_resources(bus);
1227
+
1228
+
list_for_each_entry(child, &bus->children, node)
1229
+
pcie_bus_configure_settings(child);
1230
+
}
1231
+
1232
+
pci_bus_add_devices(bus);
1233
+
return 0;
1188
1234
}
1189
1235
1190
1236
static int mvebu_pcie_probe(struct platform_device *pdev)
···
1312
1268
bridge->align_resource = mvebu_pcie_align_resource;
1313
1269
bridge->msi = pcie->msi;
1314
1270
1315
-
return pci_host_probe(bridge);
1271
+
return mvebu_pci_host_probe(bridge);
1316
1272
}
1317
1273
1318
1274
static const struct of_device_id mvebu_pcie_of_match_table[] = {
+19
-8
drivers/pci/pci.c
+19
-8
drivers/pci/pci.c
···
1289
1289
EXPORT_SYMBOL(pci_save_state);
1290
1290
1291
1291
static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1292
-
u32 saved_val, int retry)
1292
+
u32 saved_val, int retry, bool force)
1293
1293
{
1294
1294
u32 val;
1295
1295
1296
1296
pci_read_config_dword(pdev, offset, &val);
1297
-
if (val == saved_val)
1297
+
if (!force && val == saved_val)
1298
1298
return;
1299
1299
1300
1300
for (;;) {
···
1313
1313
}
1314
1314
1315
1315
static void pci_restore_config_space_range(struct pci_dev *pdev,
1316
-
int start, int end, int retry)
1316
+
int start, int end, int retry,
1317
+
bool force)
1317
1318
{
1318
1319
int index;
1319
1320
1320
1321
for (index = end; index >= start; index--)
1321
1322
pci_restore_config_dword(pdev, 4 * index,
1322
1323
pdev->saved_config_space[index],
1323
-
retry);
1324
+
retry, force);
1324
1325
}
1325
1326
1326
1327
static void pci_restore_config_space(struct pci_dev *pdev)
1327
1328
{
1328
1329
if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1329
-
pci_restore_config_space_range(pdev, 10, 15, 0);
1330
+
pci_restore_config_space_range(pdev, 10, 15, 0, false);
1330
1331
/* Restore BARs before the command register. */
1331
-
pci_restore_config_space_range(pdev, 4, 9, 10);
1332
-
pci_restore_config_space_range(pdev, 0, 3, 0);
1332
+
pci_restore_config_space_range(pdev, 4, 9, 10, false);
1333
+
pci_restore_config_space_range(pdev, 0, 3, 0, false);
1334
+
} else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1335
+
pci_restore_config_space_range(pdev, 12, 15, 0, false);
1336
+
1337
+
/*
1338
+
* Force rewriting of prefetch registers to avoid S3 resume
1339
+
* issues on Intel PCI bridges that occur when these
1340
+
* registers are not explicitly written.
1341
+
*/
1342
+
pci_restore_config_space_range(pdev, 9, 11, 0, true);
1343
+
pci_restore_config_space_range(pdev, 0, 8, 0, false);
1333
1344
} else {
1334
-
pci_restore_config_space_range(pdev, 0, 15, 0);
1345
+
pci_restore_config_space_range(pdev, 0, 15, 0, false);
1335
1346
}
1336
1347
}
1337
1348