Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mips_6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer:
- DT cleanups
- fix for early use of kzalloc on mt7621 platform
- cleanups and fixes
* tag 'mips_6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (21 commits)
MIPS: OCTEON: warn only once if deprecated link status is being used
MIPS: BCM63xx: Add check for NULL for clk in clk_enable
platform/mips: Adjust Kconfig to keep consistency
MIPS: OCTEON: cvmx-bootmem: use strscpy() to instead of strncpy()
MIPS: mscc: jaguar2: Fix pca9545 i2c-mux node names
mips/pci: use devm_platform_ioremap_resource()
mips: ralink: mt7621: do not use kzalloc too early
mips: ralink: mt7621: soc queries and tests as functions
mips: ralink: mt7621: define MT7621_SYSC_BASE with __iomem
MIPS: Restore symbol versions for copy_page_cpu and clear_page_cpu
mips: dts: remove label = "cpu" from DSA dt-binding
mips: ralink: mt7621: change DSA port labels to generic naming
mips: ralink: mt7621: fix phy-mode of external phy on GB-PC2
MIPS: vpe-cmp: fix possible memory leak while module exiting
MIPS: vpe-mt: fix possible memory leak while module exiting
dt-bindings: mips: brcm: add Broadcom SoCs bindings
dt-bindings: mips: add CPU bindings for MIPS architecture
mips: dts: brcm: bcm7435: add "interrupt-names" for NAND controller
mips: dts: bcm63268: add TWD block timer
MIPS: Use "grep -E" instead of "egrep"
...
+313
-133
-8
Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt
-8
Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt
+96
Documentation/devicetree/bindings/mips/brcm/soc.yaml
+96
Documentation/devicetree/bindings/mips/brcm/soc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mips/brcm/soc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Broadcom cable/DSL/settop platforms
8
+
9
+
maintainers:
10
+
- Florian Fainelli <f.fainelli@gmail.com>
11
+
12
+
description: |
13
+
Boards Broadcom cable/DSL/settop SoC shall have the following properties.
14
+
The experimental -viper variants are for running Linux on the 3384's
15
+
BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
16
+
17
+
properties:
18
+
$nodename:
19
+
const: '/'
20
+
21
+
compatible:
22
+
enum:
23
+
- brcm,bcm3368
24
+
- brcm,bcm3384
25
+
- brcm,bcm33843
26
+
- brcm,bcm3384-viper
27
+
- brcm,bcm33843-viper
28
+
- brcm,bcm6328
29
+
- brcm,bcm6358
30
+
- brcm,bcm6362
31
+
- brcm,bcm6368
32
+
- brcm,bcm63168
33
+
- brcm,bcm63268
34
+
- brcm,bcm7125
35
+
- brcm,bcm7346
36
+
- brcm,bcm7358
37
+
- brcm,bcm7360
38
+
- brcm,bcm7362
39
+
- brcm,bcm7420
40
+
- brcm,bcm7425
41
+
42
+
cpus:
43
+
type: object
44
+
additionalProperties: false
45
+
properties:
46
+
'#address-cells':
47
+
const: 1
48
+
49
+
'#size-cells':
50
+
const: 0
51
+
52
+
mips-hpt-frequency:
53
+
description: MIPS counter high precision timer frequency.
54
+
This is common to all CPUs in the system so it lives
55
+
under the "cpus" node.
56
+
$ref: /schemas/types.yaml#/definitions/uint32
57
+
58
+
patternProperties:
59
+
"^cpu@[0-9]$":
60
+
type: object
61
+
$ref: /schemas/mips/cpus.yaml#
62
+
unevaluatedProperties: false
63
+
64
+
required:
65
+
- mips-hpt-frequency
66
+
67
+
additionalProperties: true
68
+
69
+
examples:
70
+
- |
71
+
/ {
72
+
compatible = "brcm,bcm3368";
73
+
#address-cells = <1>;
74
+
#size-cells = <1>;
75
+
model = "Broadcom 3368";
76
+
77
+
cpus {
78
+
#address-cells = <1>;
79
+
#size-cells = <0>;
80
+
81
+
mips-hpt-frequency = <150000000>;
82
+
83
+
cpu@0 {
84
+
compatible = "brcm,bmips4350";
85
+
device_type = "cpu";
86
+
reg = <0>;
87
+
};
88
+
89
+
cpu@1 {
90
+
compatible = "brcm,bmips4350";
91
+
device_type = "cpu";
92
+
reg = <1>;
93
+
};
94
+
};
95
+
};
96
+
...
+115
Documentation/devicetree/bindings/mips/cpus.yaml
+115
Documentation/devicetree/bindings/mips/cpus.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mips/cpus.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MIPS CPUs bindings
8
+
9
+
maintainers:
10
+
- Thomas Bogendoerfer <tsbogend@alpha.franken.de>
11
+
- 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
12
+
13
+
description: |
14
+
The device tree allows to describe the layout of CPUs in a system through
15
+
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
16
+
defining properties for every CPU.
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- brcm,bmips3300
22
+
- brcm,bmips4350
23
+
- brcm,bmips4380
24
+
- brcm,bmips5000
25
+
- brcm,bmips5200
26
+
- ingenic,xburst-mxu1.0
27
+
- ingenic,xburst-fpu1.0-mxu1.1
28
+
- ingenic,xburst-fpu2.0-mxu2.0
29
+
- ingenic,xburst2-fpu2.1-mxu2.1-smt
30
+
- loongson,gs264
31
+
- mips,m14Kc
32
+
- mips,mips4Kc
33
+
- mips,mips4KEc
34
+
- mips,mips24Kc
35
+
- mips,mips24KEc
36
+
- mips,mips74Kc
37
+
- mips,mips1004Kc
38
+
- mti,interaptiv
39
+
- mti,mips24KEc
40
+
- mti,mips14KEc
41
+
- mti,mips14Kc
42
+
43
+
reg:
44
+
maxItems: 1
45
+
46
+
clocks:
47
+
maxItems: 1
48
+
49
+
device_type: true
50
+
51
+
allOf:
52
+
- if:
53
+
properties:
54
+
compatible:
55
+
contains:
56
+
enum:
57
+
- ingenic,xburst-mxu1.0
58
+
- ingenic,xburst-fpu1.0-mxu1.1
59
+
- ingenic,xburst-fpu2.0-mxu2.0
60
+
- ingenic,xburst2-fpu2.1-mxu2.1-smt
61
+
then:
62
+
required:
63
+
- device_type
64
+
- clocks
65
+
66
+
required:
67
+
- compatible
68
+
- reg
69
+
70
+
additionalProperties: false
71
+
72
+
examples:
73
+
- |
74
+
cpus {
75
+
#size-cells = <0>;
76
+
#address-cells = <1>;
77
+
78
+
cpu@0 {
79
+
compatible = "mips,mips1004Kc";
80
+
device_type = "cpu";
81
+
reg = <0>;
82
+
};
83
+
84
+
cpu@1 {
85
+
compatible = "mips,mips1004Kc";
86
+
device_type = "cpu";
87
+
reg = <1>;
88
+
};
89
+
};
90
+
91
+
- |
92
+
// Example 2 (Ingenic CPU)
93
+
#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
94
+
95
+
cpus {
96
+
#address-cells = <1>;
97
+
#size-cells = <0>;
98
+
99
+
cpu@0 {
100
+
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
101
+
device_type = "cpu";
102
+
reg = <0>;
103
+
104
+
clocks = <&cgu JZ4780_CLK_CPU>;
105
+
};
106
+
107
+
cpu@1 {
108
+
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
109
+
device_type = "cpu";
110
+
reg = <1>;
111
+
112
+
clocks = <&cgu JZ4780_CLK_CORE1>;
113
+
};
114
+
};
115
+
...
-69
Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
-69
Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: Bindings for Ingenic XBurst family CPUs
8
-
9
-
maintainers:
10
-
- 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
11
-
12
-
description:
13
-
Ingenic XBurst family CPUs shall have the following properties.
14
-
15
-
properties:
16
-
compatible:
17
-
oneOf:
18
-
19
-
- description: Ingenic XBurst®1 CPU Cores
20
-
enum:
21
-
- ingenic,xburst-mxu1.0
22
-
- ingenic,xburst-fpu1.0-mxu1.1
23
-
- ingenic,xburst-fpu2.0-mxu2.0
24
-
25
-
- description: Ingenic XBurst®2 CPU Cores
26
-
enum:
27
-
- ingenic,xburst2-fpu2.1-mxu2.1-smt
28
-
29
-
reg:
30
-
maxItems: 1
31
-
32
-
clocks:
33
-
maxItems: 1
34
-
35
-
device_type: true
36
-
37
-
required:
38
-
- device_type
39
-
- compatible
40
-
- reg
41
-
- clocks
42
-
43
-
additionalProperties: false
44
-
45
-
examples:
46
-
- |
47
-
#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
48
-
49
-
cpus {
50
-
#address-cells = <1>;
51
-
#size-cells = <0>;
52
-
53
-
cpu0: cpu@0 {
54
-
device_type = "cpu";
55
-
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
56
-
reg = <0>;
57
-
58
-
clocks = <&cgu JZ4780_CLK_CPU>;
59
-
};
60
-
61
-
cpu1: cpu@1 {
62
-
device_type = "cpu";
63
-
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
64
-
reg = <1>;
65
-
66
-
clocks = <&cgu JZ4780_CLK_CORE1>;
67
-
};
68
-
};
69
-
...
+1
-1
arch/mips/Makefile
+1
-1
arch/mips/Makefile
···
318
318
319
319
ifdef CONFIG_MIPS
320
320
CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -x c /dev/null | \
321
-
egrep -vw '__GNUC_(MINOR_|PATCHLEVEL_)?_' | \
321
+
grep -E -vw '__GNUC_(MINOR_|PATCHLEVEL_)?_' | \
322
322
sed -e "s/^\#define /-D'/" -e "s/ /'='/" -e "s/$$/'/" -e 's/\$$/&&/g')
323
323
endif
324
324
+2
arch/mips/bcm63xx/clk.c
+2
arch/mips/bcm63xx/clk.c
+5
arch/mips/boot/dts/brcm/bcm63268.dtsi
+5
arch/mips/boot/dts/brcm/bcm63268.dtsi
+1
arch/mips/boot/dts/brcm/bcm7435.dtsi
+1
arch/mips/boot/dts/brcm/bcm7435.dtsi
+1
-1
arch/mips/boot/dts/ingenic/ci20.dts
+1
-1
arch/mips/boot/dts/ingenic/ci20.dts
+2
-2
arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
+2
-2
arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
···
208
208
};
209
209
210
210
&i2c0 {
211
-
pca9545@70 {
211
+
i2c-mux@70 {
212
212
compatible = "nxp,pca9545";
213
213
reg = <0x70>;
214
214
#address-cells = <1>;
···
236
236
reg = <3>;
237
237
};
238
238
};
239
-
pca9545@71 {
239
+
i2c-mux@71 {
240
240
compatible = "nxp,pca9545";
241
241
reg = <0x71>;
242
242
#address-cells = <1>;
-1
arch/mips/boot/dts/qca/ar9331.dtsi
-1
arch/mips/boot/dts/qca/ar9331.dtsi
+1
-1
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
+1
-1
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
+5
-6
arch/mips/boot/dts/ralink/mt7621.dtsi
+5
-6
arch/mips/boot/dts/ralink/mt7621.dtsi
···
357
357
port@0 {
358
358
status = "disabled";
359
359
reg = <0>;
360
-
label = "lan0";
360
+
label = "swp0";
361
361
};
362
362
363
363
port@1 {
364
364
status = "disabled";
365
365
reg = <1>;
366
-
label = "lan1";
366
+
label = "swp1";
367
367
};
368
368
369
369
port@2 {
370
370
status = "disabled";
371
371
reg = <2>;
372
-
label = "lan2";
372
+
label = "swp2";
373
373
};
374
374
375
375
port@3 {
376
376
status = "disabled";
377
377
reg = <3>;
378
-
label = "lan3";
378
+
label = "swp3";
379
379
};
380
380
381
381
port@4 {
382
382
status = "disabled";
383
383
reg = <4>;
384
-
label = "lan4";
384
+
label = "swp4";
385
385
};
386
386
387
387
port@6 {
388
388
reg = <6>;
389
-
label = "cpu";
390
389
ethernet = <&gmac0>;
391
390
phy-mode = "trgmii";
392
391
+1
-2
arch/mips/cavium-octeon/executive/cvmx-bootmem.c
+1
-2
arch/mips/cavium-octeon/executive/cvmx-bootmem.c
···
780
780
if (addr_allocated >= 0) {
781
781
named_block_desc_ptr->base_addr = addr_allocated;
782
782
named_block_desc_ptr->size = size;
783
-
strncpy(named_block_desc_ptr->name, name,
783
+
strscpy(named_block_desc_ptr->name, name,
784
784
cvmx_bootmem_desc->named_block_name_len);
785
-
named_block_desc_ptr->name[cvmx_bootmem_desc->named_block_name_len - 1] = 0;
786
785
}
787
786
788
787
if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+1
-1
arch/mips/cavium-octeon/executive/cvmx-helper-board.c
+1
-1
arch/mips/cavium-octeon/executive/cvmx-helper-board.c
+1
-1
arch/mips/cavium-octeon/executive/cvmx-helper.c
+1
-1
arch/mips/cavium-octeon/executive/cvmx-helper.c
···
1096
1096
if (index == 0)
1097
1097
result = __cvmx_helper_rgmii_link_get(ipd_port);
1098
1098
else {
1099
-
WARN(1, "Using deprecated link status - please update your DT");
1099
+
WARN_ONCE(1, "Using deprecated link status - please update your DT");
1100
1100
result.s.full_duplex = 1;
1101
1101
result.s.link_up = 1;
1102
1102
result.s.speed = 1000;
+3
arch/mips/include/asm/asm-prototypes.h
+3
arch/mips/include/asm/asm-prototypes.h
+3
-1
arch/mips/include/asm/mach-ralink/mt7621.h
+3
-1
arch/mips/include/asm/mach-ralink/mt7621.h
···
7
7
#ifndef _MT7621_REGS_H_
8
8
#define _MT7621_REGS_H_
9
9
10
+
#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x)))
11
+
10
12
#define MT7621_PALMBUS_BASE 0x1C000000
11
13
#define MT7621_PALMBUS_SIZE 0x03FFFFFF
12
14
13
-
#define MT7621_SYSC_BASE 0x1E000000
15
+
#define MT7621_SYSC_BASE IOMEM(0x1E000000)
14
16
15
17
#define SYSC_REG_CHIP_NAME0 0x00
16
18
#define SYSC_REG_CHIP_NAME1 0x04
+2
-2
arch/mips/kernel/vpe-cmp.c
+2
-2
arch/mips/kernel/vpe-cmp.c
···
75
75
76
76
static void vpe_device_release(struct device *cd)
77
77
{
78
-
kfree(cd);
79
78
}
80
79
81
80
static struct class vpe_class = {
···
156
157
device_del(&vpe_device);
157
158
158
159
out_class:
160
+
put_device(&vpe_device);
159
161
class_unregister(&vpe_class);
160
162
161
163
out_chrdev:
···
169
169
{
170
170
struct vpe *v, *n;
171
171
172
-
device_del(&vpe_device);
172
+
device_unregister(&vpe_device);
173
173
class_unregister(&vpe_class);
174
174
unregister_chrdev(major, VPE_MODULE_NAME);
175
175
+2
-2
arch/mips/kernel/vpe-mt.c
+2
-2
arch/mips/kernel/vpe-mt.c
···
313
313
314
314
static void vpe_device_release(struct device *cd)
315
315
{
316
-
kfree(cd);
317
316
}
318
317
319
318
static struct class vpe_class = {
···
496
497
device_del(&vpe_device);
497
498
498
499
out_class:
500
+
put_device(&vpe_device);
499
501
class_unregister(&vpe_class);
500
502
501
503
out_chrdev:
···
509
509
{
510
510
struct vpe *v, *n;
511
511
512
-
device_del(&vpe_device);
512
+
device_unregister(&vpe_device);
513
513
class_unregister(&vpe_class);
514
514
unregister_chrdev(major, VPE_MODULE_NAME);
515
515
+1
-3
arch/mips/pci/pci-rt3883.c
+1
-3
arch/mips/pci/pci-rt3883.c
···
404
404
struct rt3883_pci_controller *rpc;
405
405
struct device *dev = &pdev->dev;
406
406
struct device_node *np = dev->of_node;
407
-
struct resource *res;
408
407
struct device_node *child;
409
408
u32 val;
410
409
int err;
···
413
414
if (!rpc)
414
415
return -ENOMEM;
415
416
416
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
417
-
rpc->base = devm_ioremap_resource(dev, res);
417
+
rpc->base = devm_platform_ioremap_resource(pdev, 0);
418
418
if (IS_ERR(rpc->base))
419
419
return PTR_ERR(rpc->base);
420
420
+68
-29
arch/mips/ralink/mt7621.c
+68
-29
arch/mips/ralink/mt7621.c
···
25
25
#define MT7621_MEM_TEST_PATTERN 0xaa5555aa
26
26
27
27
static u32 detect_magic __initdata;
28
+
static struct ralink_soc_info *soc_info_ptr;
28
29
29
30
int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
30
31
{
···
98
97
panic("Failed to remap core resources");
99
98
}
100
99
101
-
static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev)
100
+
static unsigned int __init mt7621_get_soc_name0(void)
101
+
{
102
+
return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);
103
+
}
104
+
105
+
static unsigned int __init mt7621_get_soc_name1(void)
106
+
{
107
+
return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME1);
108
+
}
109
+
110
+
static bool __init mt7621_soc_valid(void)
111
+
{
112
+
if (mt7621_get_soc_name0() == MT7621_CHIP_NAME0 &&
113
+
mt7621_get_soc_name1() == MT7621_CHIP_NAME1)
114
+
return true;
115
+
else
116
+
return false;
117
+
}
118
+
119
+
static const char __init *mt7621_get_soc_id(void)
120
+
{
121
+
if (mt7621_soc_valid())
122
+
return "MT7621";
123
+
else
124
+
return "invalid";
125
+
}
126
+
127
+
static unsigned int __init mt7621_get_soc_rev(void)
128
+
{
129
+
return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV);
130
+
}
131
+
132
+
static unsigned int __init mt7621_get_soc_ver(void)
133
+
{
134
+
return (mt7621_get_soc_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK;
135
+
}
136
+
137
+
static unsigned int __init mt7621_get_soc_eco(void)
138
+
{
139
+
return (mt7621_get_soc_rev() & CHIP_REV_ECO_MASK);
140
+
}
141
+
142
+
static const char __init *mt7621_get_soc_revision(void)
143
+
{
144
+
if (mt7621_get_soc_rev() == 1 && mt7621_get_soc_eco() == 1)
145
+
return "E2";
146
+
else
147
+
return "E1";
148
+
}
149
+
150
+
static int __init mt7621_soc_dev_init(void)
102
151
{
103
152
struct soc_device *soc_dev;
104
153
struct soc_device_attribute *soc_dev_attr;
105
154
106
155
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
107
156
if (!soc_dev_attr)
108
-
return;
157
+
return -ENOMEM;
109
158
110
159
soc_dev_attr->soc_id = "mt7621";
111
160
soc_dev_attr->family = "Ralink";
161
+
soc_dev_attr->revision = mt7621_get_soc_revision();
112
162
113
-
if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 &&
114
-
(rev & CHIP_REV_ECO_MASK) == 1)
115
-
soc_dev_attr->revision = "E2";
116
-
else
117
-
soc_dev_attr->revision = "E1";
118
-
119
-
soc_dev_attr->data = soc_info;
163
+
soc_dev_attr->data = soc_info_ptr;
120
164
121
165
soc_dev = soc_device_register(soc_dev_attr);
122
166
if (IS_ERR(soc_dev)) {
123
167
kfree(soc_dev_attr);
124
-
return;
168
+
return PTR_ERR(soc_dev);
125
169
}
170
+
171
+
return 0;
126
172
}
173
+
device_initcall(mt7621_soc_dev_init);
127
174
128
175
void __init prom_soc_init(struct ralink_soc_info *soc_info)
129
176
{
130
-
void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
131
-
unsigned char *name = NULL;
132
-
u32 n0;
133
-
u32 n1;
134
-
u32 rev;
135
-
136
177
/* Early detection of CMP support */
137
178
mips_cm_probe();
138
179
mips_cpc_probe();
···
197
154
__sync();
198
155
}
199
156
200
-
n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
201
-
n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
202
-
203
-
if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
204
-
name = "MT7621";
157
+
if (mt7621_soc_valid())
205
158
soc_info->compatible = "mediatek,mt7621-soc";
206
-
} else {
207
-
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
208
-
}
159
+
else
160
+
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n",
161
+
mt7621_get_soc_name0(),
162
+
mt7621_get_soc_name1());
209
163
ralink_soc = MT762X_SOC_MT7621AT;
210
-
rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
211
164
212
165
snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
213
166
"MediaTek %s ver:%u eco:%u",
214
-
name,
215
-
(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
216
-
(rev & CHIP_REV_ECO_MASK));
167
+
mt7621_get_soc_id(),
168
+
mt7621_get_soc_ver(),
169
+
mt7621_get_soc_eco());
217
170
218
171
soc_info->mem_detect = mt7621_memory_detect;
219
172
220
-
soc_dev_init(soc_info, rev);
173
+
soc_info_ptr = soc_info;
221
174
222
175
if (!register_cps_smp_ops())
223
176
return;
+1
-1
arch/mips/vdso/Makefile
+1
-1
arch/mips/vdso/Makefile
···
71
71
72
72
# Check that we don't have PIC 'jalr t9' calls left
73
73
quiet_cmd_vdso_mips_check = VDSOCHK $@
74
-
cmd_vdso_mips_check = if $(OBJDUMP) --disassemble $@ | egrep -h "jalr.*t9" > /dev/null; \
74
+
cmd_vdso_mips_check = if $(OBJDUMP) --disassemble $@ | grep -E -h "jalr.*t9" > /dev/null; \
75
75
then (echo >&2 "$@: PIC 'jalr t9' calls are not supported"; \
76
76
rm -f $@; /bin/false); fi
77
77
-2
drivers/platform/Kconfig
-2
drivers/platform/Kconfig
+1
drivers/platform/mips/Kconfig
+1
drivers/platform/mips/Kconfig