tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'x86_urgent_for_v5.19_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 fixes from Borislav Petkov:

- Improve the check whether the kernel supports WP mappings so that it
can accomodate a XenPV guest due to how the latter is setting up the
PAT machinery

- Now that the retbleed nightmare is public, here's the first round of
fallout fixes:

* Fix a build failure on 32-bit due to missing include

* Remove an untraining point in espfix64 return path

* other small cleanups

* tag 'x86_urgent_for_v5.19_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/bugs: Remove apostrophe typo
um: Add missing apply_returns()
x86/entry: Remove UNTRAIN_RET from native_irq_return_ldt
x86/bugs: Mark retbleed_strings static
x86/pat: Fix x86_has_pat_wp()
x86/asm/32: Fix ANNOTATE_UNRET_SAFE use on 32-bit

Linus Torvalds 59c80f05 2eccaca7

+19 -5
+4
arch/um/kernel/um_arch.c
··· 432 432 { 433 433 } 434 434 435 + void apply_returns(s32 *start, s32 *end) 436 + { 437 + } 438 + 435 439 void apply_alternatives(struct alt_instr *start, struct alt_instr *end) 436 440 { 437 441 }
-1
arch/x86/entry/entry_64.S
··· 727 727 pushq %rdi /* Stash user RDI */ 728 728 swapgs /* to kernel GS */ 729 729 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 730 - UNTRAIN_RET 731 730 732 731 movq PER_CPU_VAR(espfix_waddr), %rdi 733 732 movq %rax, (0*8)(%rdi) /* user RAX */
+2 -2
arch/x86/kernel/cpu/bugs.c
··· 793 793 RETBLEED_CMD_IBPB, 794 794 }; 795 795 796 - const char * const retbleed_strings[] = { 796 + static const char * const retbleed_strings[] = { 797 797 [RETBLEED_MITIGATION_NONE] = "Vulnerable", 798 798 [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk", 799 799 [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB", ··· 1181 1181 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) { 1182 1182 if (mode != SPECTRE_V2_USER_STRICT && 1183 1183 mode != SPECTRE_V2_USER_STRICT_PREFERRED) 1184 - pr_info("Selecting STIBP always-on mode to complement retbleed mitigation'\n"); 1184 + pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n"); 1185 1185 mode = SPECTRE_V2_USER_STRICT_PREFERRED; 1186 1186 } 1187 1187
+1
arch/x86/kernel/head_32.S
··· 23 23 #include <asm/cpufeatures.h> 24 24 #include <asm/percpu.h> 25 25 #include <asm/nops.h> 26 + #include <asm/nospec-branch.h> 26 27 #include <asm/bootparam.h> 27 28 #include <asm/export.h> 28 29 #include <asm/pgtable_32.h>
+12 -2
arch/x86/mm/init.c
··· 77 77 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC, 78 78 }; 79 79 80 - /* Check that the write-protect PAT entry is set for write-protect */ 80 + /* 81 + * Check that the write-protect PAT entry is set for write-protect. 82 + * To do this without making assumptions how PAT has been set up (Xen has 83 + * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache 84 + * mode via the __cachemode2pte_tbl[] into protection bits (those protection 85 + * bits will select a cache mode of WP or better), and then translate the 86 + * protection bits back into the cache mode using __pte2cm_idx() and the 87 + * __pte2cachemode_tbl[] array. This will return the really used cache mode. 88 + */ 81 89 bool x86_has_pat_wp(void) 82 90 { 83 - return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] == _PAGE_CACHE_MODE_WP; 91 + uint16_t prot = __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP]; 92 + 93 + return __pte2cachemode_tbl[__pte2cm_idx(prot)] == _PAGE_CACHE_MODE_WP; 84 94 } 85 95 86 96 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)