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riscv: add RISC-V Svrsw60t59b extension support

The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software to use.

Link: https://lkml.kernel.org/r/20251113072806.795029-4-zhangchunyan@iscas.ac.cn
Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Alexandre Ghiti <alex@ghiti.fr>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Axel Rasmussen <axelrasmussen@google.com>
Cc: Christian Brauner <brauner@kernel.org>
Cc: Conor Dooley <conor.dooley@microchip.com>
Cc: Conor Dooley <conor@kernel.org>
Cc: David Hildenbrand <david@redhat.com>
Cc: Jan Kara <jack@suse.cz>
Cc: Liam Howlett <liam.howlett@oracle.com>
Cc: Lorenzo Stoakes <lorenzo.stoakes@oracle.com>
Cc: Michal Hocko <mhocko@suse.com>
Cc: Mike Rapoport <rppt@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Suren Baghdasaryan <surenb@google.com>
Cc: Vlastimil Babka <vbabka@suse.cz>
Cc: Yuanchu Xie <yuanchu@google.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>

authored by

Chunyan Zhang and committed by
Andrew Morton
59f6acb4 f59c0924

+16
+14
arch/riscv/Kconfig
··· 849 849 850 850 If you don't know what to do here, say Y. 851 851 852 + config RISCV_ISA_SVRSW60T59B 853 + bool "Svrsw60t59b extension support for using PTE bits 60 and 59" 854 + depends on MMU && 64BIT 855 + depends on RISCV_ALTERNATIVE 856 + default y 857 + help 858 + Adds support to dynamically detect the presence of the Svrsw60t59b 859 + extension and enable its usage. 860 + 861 + The Svrsw60t59b extension allows to free the PTE reserved bits 60 862 + and 59 for software to use. 863 + 864 + If you don't know what to do here, say Y. 865 + 852 866 config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI 853 867 def_bool y 854 868 # https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
+1
arch/riscv/include/asm/hwcap.h
··· 106 106 #define RISCV_ISA_EXT_ZAAMO 97 107 107 #define RISCV_ISA_EXT_ZALRSC 98 108 108 #define RISCV_ISA_EXT_ZICBOP 99 109 + #define RISCV_ISA_EXT_SVRSW60T59B 100 109 110 110 111 #define RISCV_ISA_EXT_XLINUXENVCFG 127 111 112
+1
arch/riscv/kernel/cpufeature.c
··· 539 539 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), 540 540 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), 541 541 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), 542 + __RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B), 542 543 __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), 543 544 }; 544 545