tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: Add sysfs interface for sdma reset mask

Add the sysfs interface for sdma:
sdma_reset_mask

The interface is read-only and show the resets supported by the IP.
For example, full adapter reset (mode1/mode2/BACO/etc),
soft reset, queue reset, and pipe reset.

V2: the sysfs node returns a text string instead of some flags (Christian)
v3: add a generic helper which takes the ring as parameter
and print the strings in the order they are applied (Christian)

check amdgpu_gpu_recovery before creating sysfs file itself,
and initialize supported_reset_types in IP version files (Lijo)

Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Jesse.zhang@amd.com and committed by
Alex Deucher 59fd50b8 edd345f7

+112
+41
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
··· 413 413 &amdgpu_debugfs_sdma_sched_mask_fops); 414 414 #endif 415 415 } 416 + 417 + static ssize_t amdgpu_get_sdma_reset_mask(struct device *dev, 418 + struct device_attribute *attr, 419 + char *buf) 420 + { 421 + struct drm_device *ddev = dev_get_drvdata(dev); 422 + struct amdgpu_device *adev = drm_to_adev(ddev); 423 + 424 + if (!adev) 425 + return -ENODEV; 426 + 427 + return amdgpu_show_reset_mask(buf, adev->sdma.supported_reset); 428 + } 429 + 430 + static DEVICE_ATTR(sdma_reset_mask, 0444, 431 + amdgpu_get_sdma_reset_mask, NULL); 432 + 433 + int amdgpu_sdma_sysfs_reset_mask_init(struct amdgpu_device *adev) 434 + { 435 + int r = 0; 436 + 437 + if (!amdgpu_gpu_recovery) 438 + return r; 439 + 440 + if (adev->sdma.num_instances) { 441 + r = device_create_file(adev->dev, &dev_attr_sdma_reset_mask); 442 + if (r) 443 + return r; 444 + } 445 + 446 + return r; 447 + } 448 + 449 + void amdgpu_sdma_sysfs_reset_mask_fini(struct amdgpu_device *adev) 450 + { 451 + if (!amdgpu_gpu_recovery) 452 + return; 453 + 454 + if (adev->sdma.num_instances) 455 + device_remove_file(adev->dev, &dev_attr_sdma_reset_mask); 456 + }
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
··· 116 116 struct ras_common_if *ras_if; 117 117 struct amdgpu_sdma_ras *ras; 118 118 uint32_t *ip_dump; 119 + uint32_t supported_reset; 119 120 }; 120 121 121 122 /* ··· 177 176 bool duplicate); 178 177 int amdgpu_sdma_ras_sw_init(struct amdgpu_device *adev); 179 178 void amdgpu_debugfs_sdma_sched_mask_init(struct amdgpu_device *adev); 179 + int amdgpu_sdma_sysfs_reset_mask_init(struct amdgpu_device *adev); 180 + void amdgpu_sdma_sysfs_reset_mask_fini(struct amdgpu_device *adev); 180 181 #endif
+9
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
··· 1430 1430 } 1431 1431 } 1432 1432 1433 + /* TODO: Add queue reset mask when FW fully supports it */ 1434 + adev->sdma.supported_reset = 1435 + amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1436 + 1433 1437 if (amdgpu_sdma_ras_sw_init(adev)) { 1434 1438 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1435 1439 return -EINVAL; ··· 1445 1441 adev->sdma.ip_dump = ptr; 1446 1442 else 1447 1443 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1444 + 1445 + r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1446 + if (r) 1447 + return r; 1448 1448 1449 1449 return r; 1450 1450 } ··· 1464 1456 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1465 1457 } 1466 1458 1459 + amdgpu_sdma_sysfs_reset_mask_fini(adev); 1467 1460 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 1468 1461 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) 1469 1462 amdgpu_sdma_destroy_inst_ctx(adev, true);
+18
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
··· 1452 1452 return r; 1453 1453 } 1454 1454 1455 + adev->sdma.supported_reset = 1456 + amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1457 + switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1458 + case IP_VERSION(5, 0, 0): 1459 + case IP_VERSION(5, 0, 2): 1460 + case IP_VERSION(5, 0, 5): 1461 + if (adev->sdma.instance[0].fw_version >= 35) 1462 + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1463 + break; 1464 + default: 1465 + break; 1466 + } 1467 + 1455 1468 /* Allocate memory for SDMA IP Dump buffer */ 1456 1469 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1457 1470 if (ptr) 1458 1471 adev->sdma.ip_dump = ptr; 1459 1472 else 1460 1473 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1474 + 1475 + r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1476 + if (r) 1477 + return r; 1461 1478 1462 1479 return r; 1463 1480 } ··· 1487 1470 for (i = 0; i < adev->sdma.num_instances; i++) 1488 1471 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1489 1472 1473 + amdgpu_sdma_sysfs_reset_mask_fini(adev); 1490 1474 amdgpu_sdma_destroy_inst_ctx(adev, false); 1491 1475 1492 1476 kfree(adev->sdma.ip_dump);
+23
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
··· 1357 1357 return r; 1358 1358 } 1359 1359 1360 + adev->sdma.supported_reset = 1361 + amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1362 + switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1363 + case IP_VERSION(5, 2, 0): 1364 + case IP_VERSION(5, 2, 2): 1365 + case IP_VERSION(5, 2, 3): 1366 + case IP_VERSION(5, 2, 4): 1367 + if (adev->sdma.instance[0].fw_version >= 76) 1368 + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1369 + break; 1370 + case IP_VERSION(5, 2, 5): 1371 + if (adev->sdma.instance[0].fw_version >= 34) 1372 + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1373 + break; 1374 + default: 1375 + break; 1376 + } 1377 + 1360 1378 /* Allocate memory for SDMA IP Dump buffer */ 1361 1379 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1362 1380 if (ptr) 1363 1381 adev->sdma.ip_dump = ptr; 1364 1382 else 1365 1383 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1384 + 1385 + r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1386 + if (r) 1387 + return r; 1366 1388 1367 1389 return r; 1368 1390 } ··· 1397 1375 for (i = 0; i < adev->sdma.num_instances; i++) 1398 1376 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1399 1377 1378 + amdgpu_sdma_sysfs_reset_mask_fini(adev); 1400 1379 amdgpu_sdma_destroy_inst_ctx(adev, true); 1401 1380 1402 1381 kfree(adev->sdma.ip_dump);
+18
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
··· 1350 1350 return r; 1351 1351 } 1352 1352 1353 + adev->sdma.supported_reset = 1354 + amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1355 + switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1356 + case IP_VERSION(6, 0, 0): 1357 + case IP_VERSION(6, 0, 2): 1358 + case IP_VERSION(6, 0, 3): 1359 + if (adev->sdma.instance[0].fw_version >= 21) 1360 + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1361 + break; 1362 + default: 1363 + break; 1364 + } 1365 + 1353 1366 if (amdgpu_sdma_ras_sw_init(adev)) { 1354 1367 dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); 1355 1368 return -EINVAL; ··· 1375 1362 else 1376 1363 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1377 1364 1365 + r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1366 + if (r) 1367 + return r; 1368 + 1378 1369 return r; 1379 1370 } 1380 1371 ··· 1390 1373 for (i = 0; i < adev->sdma.num_instances; i++) 1391 1374 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1392 1375 1376 + amdgpu_sdma_sysfs_reset_mask_fini(adev); 1393 1377 amdgpu_sdma_destroy_inst_ctx(adev, true); 1394 1378 1395 1379 kfree(adev->sdma.ip_dump);