Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Revert "drm/amdgpu: switch to golden tsc registers for raven/raven2"
This reverts commit f03eb1d26c2739b75580f58bbab4ab2d5d3eba46.
This results in inconsistent timing reported via asynchronous
GPU queries.
Link: https://lists.freedesktop.org/archives/amd-gfx/2023-May/093731.html
Cc: Jesse.Zhang@amd.com
Cc: michel@daenzer.net
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-40
-40
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
-40
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
···
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#define mmGOLDEN_TSC_COUNT_LOWER_Renoir 0x0026
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#define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX 1
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-
#define mmGOLDEN_TSC_COUNT_UPPER_Raven 0x007a
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-
#define mmGOLDEN_TSC_COUNT_UPPER_Raven_BASE_IDX 0
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#define mmGOLDEN_TSC_COUNT_LOWER_Raven 0x007b
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#define mmGOLDEN_TSC_COUNT_LOWER_Raven_BASE_IDX 0
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-
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#define mmGOLDEN_TSC_COUNT_UPPER_Raven2 0x0068
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#define mmGOLDEN_TSC_COUNT_UPPER_Raven2_BASE_IDX 0
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#define mmGOLDEN_TSC_COUNT_LOWER_Raven2 0x0069
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#define mmGOLDEN_TSC_COUNT_LOWER_Raven2_BASE_IDX 0
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-
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enum ta_ras_gfx_subblock {
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/*CPC*/
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TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
···
4007
4017
*/
4008
4018
if (hi_check != clock_hi) {
4009
4019
clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir);
4010
-
clock_hi = hi_check;
4011
-
}
4012
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preempt_enable();
4013
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clock = clock_lo | (clock_hi << 32ULL);
4014
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break;
4015
-
case IP_VERSION(9, 1, 0):
4016
-
preempt_disable();
4017
-
clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
4018
-
clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);
4019
-
hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
4020
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/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over
4021
-
* roughly every 42 seconds.
4022
-
*/
4023
-
if (hi_check != clock_hi) {
4024
-
clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);
4025
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clock_hi = hi_check;
4026
-
}
4027
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preempt_enable();
4028
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clock = clock_lo | (clock_hi << 32ULL);
4029
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break;
4030
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case IP_VERSION(9, 2, 2):
4031
-
preempt_disable();
4032
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clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
4033
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clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
4034
-
hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
4035
-
/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over
4036
-
* roughly every 42 seconds.
4037
-
*/
4038
-
if (hi_check != clock_hi) {
4039
-
clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
4040
4020
clock_hi = hi_check;
4041
4021
}
4042
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preempt_enable();