Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A set of clk fixes for the Qualcomm, Mediatek, and Allwinner drivers:
- Fix the Qualcomm Stromer Plus PLL set_rate() clk_op to explicitly
set the alpha enable bit and not set bits that don't exist
- Mark Qualcomm IPQ9574 crypto clks as voted to avoid stuck clk
warnings
- Fix the parent of some PLLs on Qualcomm sm6530 so their rate is
correct
- Fix the min/max rate clamping logic in the Allwinner driver that
got broken in v6.9
- Limit runtime PM enabling in the Mediatek driver to only
mt8183-mfgcfg so that system wide resume doesn't break on other
Mediatek SoCs"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: mediatek: mt8183: Only enable runtime PM on mt8183-mfgcfg
clk: sunxi-ng: common: Don't call hw_to_ccu_common on hw without common
clk: qcom: gcc-ipq9574: Add BRANCH_HALT_VOTED flag
clk: qcom: apss-ipq-pll: remove 'config_ctl_hi_val' from Stromer pll configs
clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs
clk: qcom: gcc-sm6350: Fix gpll6* & gpll7 parents
+43
-27
+1
drivers/clk/mediatek/clk-mt8183-mfgcfg.c
+1
drivers/clk/mediatek/clk-mt8183-mfgcfg.c
+14
-10
drivers/clk/mediatek/clk-mtk.c
+14
-10
drivers/clk/mediatek/clk-mtk.c
···
496
496
}
497
497
498
498
499
-
devm_pm_runtime_enable(&pdev->dev);
500
-
/*
501
-
* Do a pm_runtime_resume_and_get() to workaround a possible
502
-
* deadlock between clk_register() and the genpd framework.
503
-
*/
504
-
r = pm_runtime_resume_and_get(&pdev->dev);
505
-
if (r)
506
-
return r;
499
+
if (mcd->need_runtime_pm) {
500
+
devm_pm_runtime_enable(&pdev->dev);
501
+
/*
502
+
* Do a pm_runtime_resume_and_get() to workaround a possible
503
+
* deadlock between clk_register() and the genpd framework.
504
+
*/
505
+
r = pm_runtime_resume_and_get(&pdev->dev);
506
+
if (r)
507
+
return r;
508
+
}
507
509
508
510
/* Calculate how many clk_hw_onecell_data entries to allocate */
509
511
num_clks = mcd->num_clks + mcd->num_composite_clks;
···
587
585
goto unregister_clks;
588
586
}
589
587
590
-
pm_runtime_put(&pdev->dev);
588
+
if (mcd->need_runtime_pm)
589
+
pm_runtime_put(&pdev->dev);
591
590
592
591
return r;
593
592
···
621
618
if (mcd->shared_io && base)
622
619
iounmap(base);
623
620
624
-
pm_runtime_put(&pdev->dev);
621
+
if (mcd->need_runtime_pm)
622
+
pm_runtime_put(&pdev->dev);
625
623
return r;
626
624
}
627
625
+2
drivers/clk/mediatek/clk-mtk.h
+2
drivers/clk/mediatek/clk-mtk.h
-2
drivers/clk/qcom/apss-ipq-pll.c
-2
drivers/clk/qcom/apss-ipq-pll.c
···
70
70
static const struct alpha_pll_config ipq5018_pll_config = {
71
71
.l = 0x2a,
72
72
.config_ctl_val = 0x4001075b,
73
-
.config_ctl_hi_val = 0x304,
74
73
.main_output_mask = BIT(0),
75
74
.aux_output_mask = BIT(1),
76
75
.early_output_mask = BIT(3),
···
83
84
static const struct alpha_pll_config ipq5332_pll_config = {
84
85
.l = 0x2d,
85
86
.config_ctl_val = 0x4001075b,
86
-
.config_ctl_hi_val = 0x304,
87
87
.main_output_mask = BIT(0),
88
88
.aux_output_mask = BIT(1),
89
89
.early_output_mask = BIT(3),
+3
drivers/clk/qcom/clk-alpha-pll.c
+3
drivers/clk/qcom/clk-alpha-pll.c
···
2574
2574
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2575
2575
a >> ALPHA_BITWIDTH);
2576
2576
2577
+
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2578
+
PLL_ALPHA_EN, PLL_ALPHA_EN);
2579
+
2577
2580
regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
2578
2581
2579
2582
/* Wait five micro seconds or more */
+6
-4
drivers/clk/qcom/gcc-ipq9574.c
+6
-4
drivers/clk/qcom/gcc-ipq9574.c
···
2140
2140
2141
2141
static struct clk_branch gcc_crypto_axi_clk = {
2142
2142
.halt_reg = 0x16010,
2143
+
.halt_check = BRANCH_HALT_VOTED,
2143
2144
.clkr = {
2144
-
.enable_reg = 0x16010,
2145
-
.enable_mask = BIT(0),
2145
+
.enable_reg = 0xb004,
2146
+
.enable_mask = BIT(15),
2146
2147
.hw.init = &(const struct clk_init_data) {
2147
2148
.name = "gcc_crypto_axi_clk",
2148
2149
.parent_hws = (const struct clk_hw *[]) {
···
2157
2156
2158
2157
static struct clk_branch gcc_crypto_ahb_clk = {
2159
2158
.halt_reg = 0x16014,
2159
+
.halt_check = BRANCH_HALT_VOTED,
2160
2160
.clkr = {
2161
-
.enable_reg = 0x16014,
2162
-
.enable_mask = BIT(0),
2161
+
.enable_reg = 0xb004,
2162
+
.enable_mask = BIT(16),
2163
2163
.hw.init = &(const struct clk_init_data) {
2164
2164
.name = "gcc_crypto_ahb_clk",
2165
2165
.parent_hws = (const struct clk_hw *[]) {
+5
-5
drivers/clk/qcom/gcc-sm6350.c
+5
-5
drivers/clk/qcom/gcc-sm6350.c
···
100
100
.enable_mask = BIT(6),
101
101
.hw.init = &(struct clk_init_data){
102
102
.name = "gpll6",
103
-
.parent_hws = (const struct clk_hw*[]){
104
-
&gpll0.clkr.hw,
103
+
.parent_data = &(const struct clk_parent_data){
104
+
.fw_name = "bi_tcxo",
105
105
},
106
106
.num_parents = 1,
107
107
.ops = &clk_alpha_pll_fixed_fabia_ops,
···
124
124
.clkr.hw.init = &(struct clk_init_data){
125
125
.name = "gpll6_out_even",
126
126
.parent_hws = (const struct clk_hw*[]){
127
-
&gpll0.clkr.hw,
127
+
&gpll6.clkr.hw,
128
128
},
129
129
.num_parents = 1,
130
130
.ops = &clk_alpha_pll_postdiv_fabia_ops,
···
139
139
.enable_mask = BIT(7),
140
140
.hw.init = &(struct clk_init_data){
141
141
.name = "gpll7",
142
-
.parent_hws = (const struct clk_hw*[]){
143
-
&gpll0.clkr.hw,
142
+
.parent_data = &(const struct clk_parent_data){
143
+
.fw_name = "bi_tcxo",
144
144
},
145
145
.num_parents = 1,
146
146
.ops = &clk_alpha_pll_fixed_fabia_ops,
+12
-6
drivers/clk/sunxi-ng/ccu_common.c
+12
-6
drivers/clk/sunxi-ng/ccu_common.c
···
132
132
133
133
for (i = 0; i < desc->hw_clks->num ; i++) {
134
134
struct clk_hw *hw = desc->hw_clks->hws[i];
135
-
struct ccu_common *common = hw_to_ccu_common(hw);
136
135
const char *name;
137
136
138
137
if (!hw)
···
146
147
pr_err("Couldn't register clock %d - %s\n", i, name);
147
148
goto err_clk_unreg;
148
149
}
150
+
}
149
151
150
-
if (common->max_rate)
151
-
clk_hw_set_rate_range(hw, common->min_rate,
152
-
common->max_rate);
152
+
for (i = 0; i < desc->num_ccu_clks; i++) {
153
+
struct ccu_common *cclk = desc->ccu_clks[i];
154
+
155
+
if (!cclk)
156
+
continue;
157
+
158
+
if (cclk->max_rate)
159
+
clk_hw_set_rate_range(&cclk->hw, cclk->min_rate,
160
+
cclk->max_rate);
153
161
else
154
-
WARN(common->min_rate,
162
+
WARN(cclk->min_rate,
155
163
"No max_rate, ignoring min_rate of clock %d - %s\n",
156
-
i, name);
164
+
i, clk_hw_get_name(&cclk->hw));
157
165
}
158
166
159
167
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,