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media: rkisp1: Fix filter mode register configuration

The rkisp1_flt_config() function performs an initial direct write to
RKISP1_CIF_ISP_FILT_MODE without including the RKISP1_CIF_ISP_FLT_ENA
bit, which clears the filter enable bit in the hardware.

The subsequent read/modify/write sequence then reads back the register
with the enable bit already cleared and cannot restore it, resulting in
the filter being inadvertently disabled.

Remove the redundant direct write. The read/modify/write sequence alone
correctly preserves the existing enable bit state while updating the
DNR mode and filter configuration bits.

Signed-off-by: Rui Wang <rui.wang@ideasonboard.com>
Reviewed-by: Stefan Klug <stefan.klug@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://patch.msgid.link/20260105171142.147792-2-rui.wang@ideasonboard.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>

authored by

Rui Wang and committed by
Hans Verkuil 5a50f2b6 bb0365f4

-6
-6
drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
··· 411 411 rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_FILT_LUM_WEIGHT, 412 412 arg->lum_weight); 413 413 414 - rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_FILT_MODE, 415 - (arg->mode ? RKISP1_CIF_ISP_FLT_MODE_DNR : 0) | 416 - RKISP1_CIF_ISP_FLT_CHROMA_V_MODE(arg->chr_v_mode) | 417 - RKISP1_CIF_ISP_FLT_CHROMA_H_MODE(arg->chr_h_mode) | 418 - RKISP1_CIF_ISP_FLT_GREEN_STAGE1(arg->grn_stage1)); 419 - 420 414 /* avoid to override the old enable value */ 421 415 filt_mode = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_FILT_MODE); 422 416 filt_mode &= RKISP1_CIF_ISP_FLT_ENA;