Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'icc-6.13-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
Georgi writes:
interconnect changes for 6.13
This pull request contains the interconnect changes for the 6.13-rc1 merge
window. It contains new drivers and clean-ups with the following highlights:
Core changes:
- Remove a useless kfree_const() usage
- Switch back to struct platform_driver::remove()
- Use of_property_present() for non-boolean properties
Driver changes:
- New driver for QCS615 platforms
- New driver for SAR2130P platforms
- New driver for QCS8300 platforms
- Probe defer incase of missing QoS clock dependency in rpmh driver
- Rename qos_clks_required flag to qos_requires_clocks in rpmh driver
- Constify pointers to qcom_icc_node in msm8937 driver
Signed-off-by: Georgi Djakov <djakov@kernel.org>
* tag 'icc-6.13-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
interconnect: Use of_property_present() for non-boolean properties
dt-bindings: interconnect: qcom-bwmon: Document QCS8300 bwmon compatibles
interconnect: qcom: add QCS8300 interconnect provider driver
interconnect: Switch back to struct platform_driver::remove()
interconnect: qcom: add support for SAR2130P
dt-bindings: interconnect: qcom: document SAR2130P NoC
interconnect: qcom: add QCS615 interconnect provider driver
dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in QCS615 SoC
dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in QCS8300 SoC
interconnect: Remove a useless kfree_const() usage
interconnect: qcom: msm8937: constify pointer to qcom_icc_node
interconnect: qcom: icc-rpmh: rename qos_clks_required flag
interconnect: qcom: icc-rpmh: probe defer incase of missing QoS clock dependency
+6701
-51
+2
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
+2
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
···
26
26
- items:
27
27
- enum:
28
28
- qcom,qcm2290-cpu-bwmon
29
+
- qcom,qcs8300-cpu-bwmon
29
30
- qcom,sa8775p-cpu-bwmon
30
31
- qcom,sc7180-cpu-bwmon
31
32
- qcom,sc7280-cpu-bwmon
···
41
40
- const: qcom,sdm845-bwmon # BWMON v4, unified register space
42
41
- items:
43
42
- enum:
43
+
- qcom,qcs8300-llcc-bwmon
44
44
- qcom,sa8775p-llcc-bwmon
45
45
- qcom,sc7180-llcc-bwmon
46
46
- qcom,sc8280xp-llcc-bwmon
+73
Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
+73
Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,qcs615-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on QCS615
8
+
9
+
maintainers:
10
+
- Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
11
+
12
+
description: |
13
+
RPMh interconnect providers support system bandwidth requirements through
14
+
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
15
+
able to communicate with the BCM through the Resource State Coordinator (RSC)
16
+
associated with each execution environment. Provider nodes must point to at
17
+
least one RPMh device child node pertaining to their RSC and each provider
18
+
can map to multiple RPMh resources.
19
+
20
+
See also: include/dt-bindings/interconnect/qcom,qcs615-rpmh.h
21
+
22
+
properties:
23
+
compatible:
24
+
enum:
25
+
- qcom,qcs615-aggre1-noc
26
+
- qcom,qcs615-camnoc-virt
27
+
- qcom,qcs615-config-noc
28
+
- qcom,qcs615-dc-noc
29
+
- qcom,qcs615-gem-noc
30
+
- qcom,qcs615-ipa-virt
31
+
- qcom,qcs615-mc-virt
32
+
- qcom,qcs615-mmss-noc
33
+
- qcom,qcs615-system-noc
34
+
35
+
reg:
36
+
maxItems: 1
37
+
38
+
required:
39
+
- compatible
40
+
41
+
allOf:
42
+
- $ref: qcom,rpmh-common.yaml#
43
+
- if:
44
+
properties:
45
+
compatible:
46
+
contains:
47
+
enum:
48
+
- qcom,qcs615-camnoc-virt
49
+
- qcom,qcs615-ipa-virt
50
+
- qcom,qcs615-mc-virt
51
+
then:
52
+
properties:
53
+
reg: false
54
+
else:
55
+
required:
56
+
- reg
57
+
58
+
unevaluatedProperties: false
59
+
60
+
examples:
61
+
- |
62
+
gem_noc: interconnect@9680000 {
63
+
compatible = "qcom,qcs615-gem-noc";
64
+
reg = <0x9680000 0x3e200>;
65
+
#interconnect-cells = <2>;
66
+
qcom,bcm-voters = <&apps_bcm_voter>;
67
+
};
68
+
69
+
mc_virt: interconnect-2 {
70
+
compatible = "qcom,qcs615-mc-virt";
71
+
#interconnect-cells = <2>;
72
+
qcom,bcm-voters = <&apps_bcm_voter>;
73
+
};
+72
Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml
+72
Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,qcs8300-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on QCS8300
8
+
9
+
maintainers:
10
+
- Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
11
+
12
+
description: |
13
+
RPMh interconnect providers support system bandwidth requirements through
14
+
RPMh hardware accelerators known as Bus Clock Manager (BCM).
15
+
16
+
See also: include/dt-bindings/interconnect/qcom,qcs8300-rpmh.h
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- qcom,qcs8300-aggre1-noc
22
+
- qcom,qcs8300-aggre2-noc
23
+
- qcom,qcs8300-clk-virt
24
+
- qcom,qcs8300-config-noc
25
+
- qcom,qcs8300-dc-noc
26
+
- qcom,qcs8300-gem-noc
27
+
- qcom,qcs8300-gpdsp-anoc
28
+
- qcom,qcs8300-lpass-ag-noc
29
+
- qcom,qcs8300-mc-virt
30
+
- qcom,qcs8300-mmss-noc
31
+
- qcom,qcs8300-nspa-noc
32
+
- qcom,qcs8300-pcie-anoc
33
+
- qcom,qcs8300-system-noc
34
+
35
+
reg:
36
+
maxItems: 1
37
+
38
+
required:
39
+
- compatible
40
+
41
+
allOf:
42
+
- $ref: qcom,rpmh-common.yaml#
43
+
- if:
44
+
properties:
45
+
compatible:
46
+
contains:
47
+
enum:
48
+
- qcom,qcs8300-clk-virt
49
+
- qcom,qcs8300-mc-virt
50
+
then:
51
+
properties:
52
+
reg: false
53
+
else:
54
+
required:
55
+
- reg
56
+
57
+
unevaluatedProperties: false
58
+
59
+
examples:
60
+
- |
61
+
gem_noc: interconnect@9100000 {
62
+
compatible = "qcom,qcs8300-gem-noc";
63
+
reg = <0x9100000 0xf7080>;
64
+
#interconnect-cells = <2>;
65
+
qcom,bcm-voters = <&apps_bcm_voter>;
66
+
};
67
+
68
+
clk_virt: interconnect-0 {
69
+
compatible = "qcom,qcs8300-clk-virt";
70
+
#interconnect-cells = <2>;
71
+
qcom,bcm-voters = <&apps_bcm_voter>;
72
+
};
+117
Documentation/devicetree/bindings/interconnect/qcom,sar2130p-rpmh.yaml
+117
Documentation/devicetree/bindings/interconnect/qcom,sar2130p-rpmh.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,sar2130p-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on SAR2130P
8
+
9
+
maintainers:
10
+
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
+
- Georgi Djakov <djakov@kernel.org>
12
+
13
+
description: |
14
+
RPMh interconnect providers support system bandwidth requirements through
15
+
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
16
+
able to communicate with the BCM through the Resource State Coordinator (RSC)
17
+
associated with each execution environment. Provider nodes must point to at
18
+
least one RPMh device child node pertaining to their RSC and each provider
19
+
can map to multiple RPMh resources.
20
+
21
+
See also:: include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h
22
+
23
+
properties:
24
+
compatible:
25
+
enum:
26
+
- qcom,sar2130p-clk-virt
27
+
- qcom,sar2130p-config-noc
28
+
- qcom,sar2130p-gem-noc
29
+
- qcom,sar2130p-lpass-ag-noc
30
+
- qcom,sar2130p-mc-virt
31
+
- qcom,sar2130p-mmss-noc
32
+
- qcom,sar2130p-nsp-noc
33
+
- qcom,sar2130p-pcie-anoc
34
+
- qcom,sar2130p-system-noc
35
+
36
+
reg:
37
+
maxItems: 1
38
+
39
+
clocks:
40
+
minItems: 1
41
+
maxItems: 2
42
+
43
+
required:
44
+
- compatible
45
+
46
+
allOf:
47
+
- $ref: qcom,rpmh-common.yaml#
48
+
- if:
49
+
properties:
50
+
compatible:
51
+
contains:
52
+
enum:
53
+
- qcom,sar2130p-clk-virt
54
+
- qcom,sar2130p-mc-virt
55
+
then:
56
+
properties:
57
+
reg: false
58
+
else:
59
+
required:
60
+
- reg
61
+
62
+
- if:
63
+
properties:
64
+
compatible:
65
+
contains:
66
+
enum:
67
+
- qcom,sar2130p-pcie-anoc
68
+
then:
69
+
properties:
70
+
clocks:
71
+
items:
72
+
- description: aggre-NOC PCIe AXI clock
73
+
- description: cfg-NOC PCIe a-NOC AHB clock
74
+
75
+
- if:
76
+
properties:
77
+
compatible:
78
+
contains:
79
+
enum:
80
+
- qcom,sar2130p-system-noc
81
+
then:
82
+
properties:
83
+
clocks:
84
+
items:
85
+
- description: aggre USB3 PRIM AXI clock
86
+
87
+
- if:
88
+
properties:
89
+
compatible:
90
+
contains:
91
+
enum:
92
+
- qcom,sar2130p-system-noc
93
+
- qcom,sar2130p-pcie-anoc
94
+
then:
95
+
required:
96
+
- clocks
97
+
else:
98
+
properties:
99
+
clocks: false
100
+
101
+
unevaluatedProperties: false
102
+
103
+
examples:
104
+
- |
105
+
clk_virt: interconnect-0 {
106
+
compatible = "qcom,sar2130p-clk-virt";
107
+
#interconnect-cells = <2>;
108
+
qcom,bcm-voters = <&apps_bcm_voter>;
109
+
};
110
+
111
+
aggre1_noc: interconnect@1680000 {
112
+
compatible = "qcom,sar2130p-system-noc";
113
+
reg = <0x01680000 0x29080>;
114
+
#interconnect-cells = <2>;
115
+
clocks = <&gcc_prim_axi_clk>;
116
+
qcom,bcm-voters = <&apps_bcm_voter>;
117
+
};
+2
-2
drivers/interconnect/core.c
+2
-2
drivers/interconnect/core.c
···
808
808
mutex_unlock(&icc_bw_lock);
809
809
mutex_unlock(&icc_lock);
810
810
811
-
kfree_const(path->name);
811
+
kfree(path->name);
812
812
kfree(path);
813
813
}
814
814
EXPORT_SYMBOL_GPL(icc_put);
···
1081
1081
int count = 0;
1082
1082
1083
1083
for_each_available_child_of_node(np, child) {
1084
-
if (of_property_read_bool(child, "#interconnect-cells") &&
1084
+
if (of_property_present(child, "#interconnect-cells") &&
1085
1085
likely(!of_match_node(ignore_list, child)))
1086
1086
count++;
1087
1087
count += of_count_icc_providers(child);
+1
-1
drivers/interconnect/imx/imx8mm.c
+1
-1
drivers/interconnect/imx/imx8mm.c
+1
-1
drivers/interconnect/imx/imx8mn.c
+1
-1
drivers/interconnect/imx/imx8mn.c
+1
-1
drivers/interconnect/imx/imx8mp.c
+1
-1
drivers/interconnect/imx/imx8mp.c
+1
-1
drivers/interconnect/imx/imx8mq.c
+1
-1
drivers/interconnect/imx/imx8mq.c
+1
-1
drivers/interconnect/mediatek/mt8183.c
+1
-1
drivers/interconnect/mediatek/mt8183.c
+1
-1
drivers/interconnect/mediatek/mt8195.c
+1
-1
drivers/interconnect/mediatek/mt8195.c
+29
drivers/interconnect/qcom/Kconfig
+29
drivers/interconnect/qcom/Kconfig
···
105
105
This is a driver for the Qualcomm Network-on-Chip on qcs404-based
106
106
platforms.
107
107
108
+
config INTERCONNECT_QCOM_QCS615
109
+
tristate "Qualcomm QCS615 interconnect driver"
110
+
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
111
+
select INTERCONNECT_QCOM_RPMH
112
+
select INTERCONNECT_QCOM_BCM_VOTER
113
+
help
114
+
This is a driver for the Qualcomm Network-on-Chip on qcs615-based
115
+
platforms.
116
+
117
+
config INTERCONNECT_QCOM_QCS8300
118
+
tristate "Qualcomm QCS8300 interconnect driver"
119
+
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
120
+
select INTERCONNECT_QCOM_RPMH
121
+
select INTERCONNECT_QCOM_BCM_VOTER
122
+
help
123
+
This is a driver for the Qualcomm Technologies, Inc. Network-on-Chip
124
+
on QCS8300-based platforms. The interconnect provider collects and
125
+
aggreagates the cosumer bandwidth requests to satisfy constraints
126
+
placed on Network-on-Chip performance states.
127
+
108
128
config INTERCONNECT_QCOM_QDU1000
109
129
tristate "Qualcomm QDU1000/QRU1000 interconnect driver"
110
130
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
···
155
135
select INTERCONNECT_QCOM_BCM_VOTER
156
136
help
157
137
This is a driver for the Qualcomm Network-on-Chip on sa8775p-based
138
+
platforms.
139
+
140
+
config INTERCONNECT_QCOM_SAR2130P
141
+
tristate "Qualcomm SAR2130P interconnect driver"
142
+
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
143
+
select INTERCONNECT_QCOM_RPMH
144
+
select INTERCONNECT_QCOM_BCM_VOTER
145
+
help
146
+
This is a driver for the Qualcomm Network-on-Chip on SAR2130P-based
158
147
platforms.
159
148
160
149
config INTERCONNECT_QCOM_SC7180
+6
drivers/interconnect/qcom/Makefile
+6
drivers/interconnect/qcom/Makefile
···
15
15
icc-osm-l3-objs := osm-l3.o
16
16
qnoc-qcm2290-objs := qcm2290.o
17
17
qnoc-qcs404-objs := qcs404.o
18
+
qnoc-qcs615-objs := qcs615.o
19
+
qnoc-qcs8300-objs := qcs8300.o
18
20
qnoc-qdu1000-objs := qdu1000.o
19
21
icc-rpmh-obj := icc-rpmh.o
20
22
qnoc-sa8775p-objs := sa8775p.o
23
+
qnoc-sar2130p-objs := sar2130p.o
21
24
qnoc-sc7180-objs := sc7180.o
22
25
qnoc-sc7280-objs := sc7280.o
23
26
qnoc-sc8180x-objs := sc8180x.o
···
55
52
obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
56
53
obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o
57
54
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
55
+
obj-$(CONFIG_INTERCONNECT_QCOM_QCS615) += qnoc-qcs615.o
56
+
obj-$(CONFIG_INTERCONNECT_QCOM_QCS8300) += qnoc-qcs8300.o
58
57
obj-$(CONFIG_INTERCONNECT_QCOM_QDU1000) += qnoc-qdu1000.o
59
58
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
60
59
obj-$(CONFIG_INTERCONNECT_QCOM_SA8775P) += qnoc-sa8775p.o
60
+
obj-$(CONFIG_INTERCONNECT_QCOM_SAR2130P) += qnoc-sar2130p.o
61
61
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
62
62
obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o
63
63
obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) += qnoc-sc8180x.o
+4
-1
drivers/interconnect/qcom/icc-rpmh.c
+4
-1
drivers/interconnect/qcom/icc-rpmh.c
···
311
311
}
312
312
313
313
qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks);
314
-
if (qp->num_clks < 0 || (!qp->num_clks && desc->qos_clks_required)) {
314
+
if (qp->num_clks == -EPROBE_DEFER)
315
+
return dev_err_probe(dev, qp->num_clks, "Failed to get QoS clocks\n");
316
+
317
+
if (qp->num_clks < 0 || (!qp->num_clks && desc->qos_requires_clocks)) {
315
318
dev_info(dev, "Skipping QoS, failed to get clk: %d\n", qp->num_clks);
316
319
goto skip_qos_config;
317
320
}
+1
-1
drivers/interconnect/qcom/icc-rpmh.h
+1
-1
drivers/interconnect/qcom/icc-rpmh.h
+1
-1
drivers/interconnect/qcom/msm8909.c
+1
-1
drivers/interconnect/qcom/msm8909.c
+1
-1
drivers/interconnect/qcom/msm8916.c
+1
-1
drivers/interconnect/qcom/msm8916.c
+5
-5
drivers/interconnect/qcom/msm8937.c
+5
-5
drivers/interconnect/qcom/msm8937.c
···
1175
1175
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1176
1176
};
1177
1177
1178
-
static struct qcom_icc_node *msm8937_bimc_nodes[] = {
1178
+
static struct qcom_icc_node * const msm8937_bimc_nodes[] = {
1179
1179
[MAS_APPS_PROC] = &mas_apps_proc,
1180
1180
[MAS_OXILI] = &mas_oxili,
1181
1181
[MAS_SNOC_BIMC_0] = &mas_snoc_bimc_0,
···
1204
1204
.ab_coeff = 154,
1205
1205
};
1206
1206
1207
-
static struct qcom_icc_node *msm8937_pcnoc_nodes[] = {
1207
+
static struct qcom_icc_node * const msm8937_pcnoc_nodes[] = {
1208
1208
[MAS_SPDM] = &mas_spdm,
1209
1209
[MAS_BLSP_1] = &mas_blsp_1,
1210
1210
[MAS_BLSP_2] = &mas_blsp_2,
···
1268
1268
.regmap_cfg = &msm8937_pcnoc_regmap_config,
1269
1269
};
1270
1270
1271
-
static struct qcom_icc_node *msm8937_snoc_nodes[] = {
1271
+
static struct qcom_icc_node * const msm8937_snoc_nodes[] = {
1272
1272
[MAS_QDSS_BAM] = &mas_qdss_bam,
1273
1273
[MAS_BIMC_SNOC] = &mas_bimc_snoc,
1274
1274
[MAS_PCNOC_SNOC] = &mas_pcnoc_snoc,
···
1304
1304
.qos_offset = 0x7000,
1305
1305
};
1306
1306
1307
-
static struct qcom_icc_node *msm8937_snoc_mm_nodes[] = {
1307
+
static struct qcom_icc_node * const msm8937_snoc_mm_nodes[] = {
1308
1308
[MAS_JPEG] = &mas_jpeg,
1309
1309
[MAS_MDP] = &mas_mdp,
1310
1310
[MAS_VENUS] = &mas_venus,
···
1337
1337
1338
1338
static struct platform_driver msm8937_noc_driver = {
1339
1339
.probe = qnoc_probe,
1340
-
.remove_new = qnoc_remove,
1340
+
.remove = qnoc_remove,
1341
1341
.driver = {
1342
1342
.name = "qnoc-msm8937",
1343
1343
.of_match_table = msm8937_noc_of_match,
+1
-1
drivers/interconnect/qcom/msm8939.c
+1
-1
drivers/interconnect/qcom/msm8939.c
+1
-1
drivers/interconnect/qcom/msm8953.c
+1
-1
drivers/interconnect/qcom/msm8953.c
+1
-1
drivers/interconnect/qcom/msm8974.c
+1
-1
drivers/interconnect/qcom/msm8974.c
+1
-1
drivers/interconnect/qcom/msm8976.c
+1
-1
drivers/interconnect/qcom/msm8976.c
+1
-1
drivers/interconnect/qcom/msm8996.c
+1
-1
drivers/interconnect/qcom/msm8996.c
+1
-1
drivers/interconnect/qcom/osm-l3.c
+1
-1
drivers/interconnect/qcom/osm-l3.c
+1
-1
drivers/interconnect/qcom/qcm2290.c
+1
-1
drivers/interconnect/qcom/qcm2290.c
+1
-1
drivers/interconnect/qcom/qcs404.c
+1
-1
drivers/interconnect/qcom/qcs404.c
+1563
drivers/interconnect/qcom/qcs615.c
+1563
drivers/interconnect/qcom/qcs615.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*
5
+
*/
6
+
7
+
#include <linux/device.h>
8
+
#include <linux/interconnect.h>
9
+
#include <linux/interconnect-provider.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of_platform.h>
12
+
#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
13
+
14
+
#include "bcm-voter.h"
15
+
#include "icc-rpmh.h"
16
+
#include "qcs615.h"
17
+
18
+
static struct qcom_icc_node qhm_a1noc_cfg = {
19
+
.name = "qhm_a1noc_cfg",
20
+
.id = QCS615_MASTER_A1NOC_CFG,
21
+
.channels = 1,
22
+
.buswidth = 4,
23
+
.num_links = 1,
24
+
.links = { QCS615_SLAVE_SERVICE_A2NOC },
25
+
};
26
+
27
+
static struct qcom_icc_node qhm_qdss_bam = {
28
+
.name = "qhm_qdss_bam",
29
+
.id = QCS615_MASTER_QDSS_BAM,
30
+
.channels = 1,
31
+
.buswidth = 4,
32
+
.num_links = 1,
33
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
34
+
};
35
+
36
+
static struct qcom_icc_node qhm_qspi = {
37
+
.name = "qhm_qspi",
38
+
.id = QCS615_MASTER_QSPI,
39
+
.channels = 1,
40
+
.buswidth = 4,
41
+
.num_links = 1,
42
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
43
+
};
44
+
45
+
static struct qcom_icc_node qhm_qup0 = {
46
+
.name = "qhm_qup0",
47
+
.id = QCS615_MASTER_QUP_0,
48
+
.channels = 1,
49
+
.buswidth = 4,
50
+
.num_links = 1,
51
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
52
+
};
53
+
54
+
static struct qcom_icc_node qhm_qup1 = {
55
+
.name = "qhm_qup1",
56
+
.id = QCS615_MASTER_BLSP_1,
57
+
.channels = 1,
58
+
.buswidth = 4,
59
+
.num_links = 1,
60
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
61
+
};
62
+
63
+
static struct qcom_icc_node qnm_cnoc = {
64
+
.name = "qnm_cnoc",
65
+
.id = QCS615_MASTER_CNOC_A2NOC,
66
+
.channels = 1,
67
+
.buswidth = 8,
68
+
.num_links = 1,
69
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
70
+
};
71
+
72
+
static struct qcom_icc_node qxm_crypto = {
73
+
.name = "qxm_crypto",
74
+
.id = QCS615_MASTER_CRYPTO,
75
+
.channels = 1,
76
+
.buswidth = 8,
77
+
.num_links = 1,
78
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
79
+
};
80
+
81
+
static struct qcom_icc_node qxm_ipa = {
82
+
.name = "qxm_ipa",
83
+
.id = QCS615_MASTER_IPA,
84
+
.channels = 1,
85
+
.buswidth = 8,
86
+
.num_links = 1,
87
+
.links = { QCS615_SLAVE_LPASS_SNOC },
88
+
};
89
+
90
+
static struct qcom_icc_node xm_emac_avb = {
91
+
.name = "xm_emac_avb",
92
+
.id = QCS615_MASTER_EMAC_EVB,
93
+
.channels = 1,
94
+
.buswidth = 8,
95
+
.num_links = 1,
96
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
97
+
};
98
+
99
+
static struct qcom_icc_node xm_pcie = {
100
+
.name = "xm_pcie",
101
+
.id = QCS615_MASTER_PCIE,
102
+
.channels = 1,
103
+
.buswidth = 8,
104
+
.num_links = 1,
105
+
.links = { QCS615_SLAVE_ANOC_PCIE_SNOC },
106
+
};
107
+
108
+
static struct qcom_icc_node xm_qdss_etr = {
109
+
.name = "xm_qdss_etr",
110
+
.id = QCS615_MASTER_QDSS_ETR,
111
+
.channels = 1,
112
+
.buswidth = 8,
113
+
.num_links = 1,
114
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
115
+
};
116
+
117
+
static struct qcom_icc_node xm_sdc1 = {
118
+
.name = "xm_sdc1",
119
+
.id = QCS615_MASTER_SDCC_1,
120
+
.channels = 1,
121
+
.buswidth = 8,
122
+
.num_links = 1,
123
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
124
+
};
125
+
126
+
static struct qcom_icc_node xm_sdc2 = {
127
+
.name = "xm_sdc2",
128
+
.id = QCS615_MASTER_SDCC_2,
129
+
.channels = 1,
130
+
.buswidth = 8,
131
+
.num_links = 1,
132
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
133
+
};
134
+
135
+
static struct qcom_icc_node xm_ufs_mem = {
136
+
.name = "xm_ufs_mem",
137
+
.id = QCS615_MASTER_UFS_MEM,
138
+
.channels = 1,
139
+
.buswidth = 8,
140
+
.num_links = 1,
141
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
142
+
};
143
+
144
+
static struct qcom_icc_node xm_usb2 = {
145
+
.name = "xm_usb2",
146
+
.id = QCS615_MASTER_USB2,
147
+
.channels = 1,
148
+
.buswidth = 8,
149
+
.num_links = 1,
150
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
151
+
};
152
+
153
+
static struct qcom_icc_node xm_usb3_0 = {
154
+
.name = "xm_usb3_0",
155
+
.id = QCS615_MASTER_USB3_0,
156
+
.channels = 1,
157
+
.buswidth = 8,
158
+
.num_links = 1,
159
+
.links = { QCS615_SLAVE_A1NOC_SNOC },
160
+
};
161
+
162
+
static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
163
+
.name = "qxm_camnoc_hf0_uncomp",
164
+
.id = QCS615_MASTER_CAMNOC_HF0_UNCOMP,
165
+
.channels = 1,
166
+
.buswidth = 32,
167
+
.num_links = 1,
168
+
.links = { QCS615_SLAVE_CAMNOC_UNCOMP },
169
+
};
170
+
171
+
static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
172
+
.name = "qxm_camnoc_hf1_uncomp",
173
+
.id = QCS615_MASTER_CAMNOC_HF1_UNCOMP,
174
+
.channels = 1,
175
+
.buswidth = 32,
176
+
.num_links = 1,
177
+
.links = { QCS615_SLAVE_CAMNOC_UNCOMP },
178
+
};
179
+
180
+
static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
181
+
.name = "qxm_camnoc_sf_uncomp",
182
+
.id = QCS615_MASTER_CAMNOC_SF_UNCOMP,
183
+
.channels = 1,
184
+
.buswidth = 32,
185
+
.num_links = 1,
186
+
.links = { QCS615_SLAVE_CAMNOC_UNCOMP },
187
+
};
188
+
189
+
static struct qcom_icc_node qhm_spdm = {
190
+
.name = "qhm_spdm",
191
+
.id = QCS615_MASTER_SPDM,
192
+
.channels = 1,
193
+
.buswidth = 4,
194
+
.num_links = 1,
195
+
.links = { QCS615_SLAVE_CNOC_A2NOC },
196
+
};
197
+
198
+
static struct qcom_icc_node qnm_snoc = {
199
+
.name = "qnm_snoc",
200
+
.id = QCS615_MASTER_SNOC_CNOC,
201
+
.channels = 1,
202
+
.buswidth = 8,
203
+
.num_links = 39,
204
+
.links = { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST,
205
+
QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP,
206
+
QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG,
207
+
QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG,
208
+
QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG,
209
+
QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG,
210
+
QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM,
211
+
QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG,
212
+
QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG,
213
+
QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG,
214
+
QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG,
215
+
QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0,
216
+
QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1,
217
+
QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG,
218
+
QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR,
219
+
QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH,
220
+
QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG,
221
+
QCS615_SLAVE_USB2, QCS615_SLAVE_USB3,
222
+
QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG,
223
+
QCS615_SLAVE_SERVICE_CNOC },
224
+
};
225
+
226
+
static struct qcom_icc_node xm_qdss_dap = {
227
+
.name = "xm_qdss_dap",
228
+
.id = QCS615_MASTER_QDSS_DAP,
229
+
.channels = 1,
230
+
.buswidth = 8,
231
+
.num_links = 40,
232
+
.links = { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST,
233
+
QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP,
234
+
QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG,
235
+
QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG,
236
+
QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG,
237
+
QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG,
238
+
QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM,
239
+
QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG,
240
+
QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG,
241
+
QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG,
242
+
QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG,
243
+
QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0,
244
+
QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1,
245
+
QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG,
246
+
QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR,
247
+
QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH,
248
+
QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG,
249
+
QCS615_SLAVE_USB2, QCS615_SLAVE_USB3,
250
+
QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG,
251
+
QCS615_SLAVE_CNOC_A2NOC, QCS615_SLAVE_SERVICE_CNOC },
252
+
};
253
+
254
+
static struct qcom_icc_node qhm_cnoc = {
255
+
.name = "qhm_cnoc",
256
+
.id = QCS615_MASTER_CNOC_DC_NOC,
257
+
.channels = 1,
258
+
.buswidth = 4,
259
+
.num_links = 2,
260
+
.links = { QCS615_SLAVE_DC_NOC_GEMNOC, QCS615_SLAVE_LLCC_CFG },
261
+
};
262
+
263
+
static struct qcom_icc_node acm_apps = {
264
+
.name = "acm_apps",
265
+
.id = QCS615_MASTER_APPSS_PROC,
266
+
.channels = 1,
267
+
.buswidth = 16,
268
+
.num_links = 3,
269
+
.links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC,
270
+
QCS615_SLAVE_MEM_NOC_PCIE_SNOC },
271
+
};
272
+
273
+
static struct qcom_icc_node acm_gpu_tcu = {
274
+
.name = "acm_gpu_tcu",
275
+
.id = QCS615_MASTER_GPU_TCU,
276
+
.channels = 1,
277
+
.buswidth = 8,
278
+
.num_links = 2,
279
+
.links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC },
280
+
};
281
+
282
+
static struct qcom_icc_node acm_sys_tcu = {
283
+
.name = "acm_sys_tcu",
284
+
.id = QCS615_MASTER_SYS_TCU,
285
+
.channels = 1,
286
+
.buswidth = 8,
287
+
.num_links = 2,
288
+
.links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC },
289
+
};
290
+
291
+
static struct qcom_icc_node qhm_gemnoc_cfg = {
292
+
.name = "qhm_gemnoc_cfg",
293
+
.id = QCS615_MASTER_GEM_NOC_CFG,
294
+
.channels = 1,
295
+
.buswidth = 4,
296
+
.num_links = 2,
297
+
.links = { QCS615_SLAVE_MSS_PROC_MS_MPU_CFG, QCS615_SLAVE_SERVICE_GEM_NOC },
298
+
};
299
+
300
+
static struct qcom_icc_node qnm_gpu = {
301
+
.name = "qnm_gpu",
302
+
.id = QCS615_MASTER_GFX3D,
303
+
.channels = 2,
304
+
.buswidth = 32,
305
+
.num_links = 2,
306
+
.links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC },
307
+
};
308
+
309
+
static struct qcom_icc_node qnm_mnoc_hf = {
310
+
.name = "qnm_mnoc_hf",
311
+
.id = QCS615_MASTER_MNOC_HF_MEM_NOC,
312
+
.channels = 1,
313
+
.buswidth = 32,
314
+
.num_links = 1,
315
+
.links = { QCS615_SLAVE_LLCC },
316
+
};
317
+
318
+
static struct qcom_icc_node qnm_mnoc_sf = {
319
+
.name = "qnm_mnoc_sf",
320
+
.id = QCS615_MASTER_MNOC_SF_MEM_NOC,
321
+
.channels = 1,
322
+
.buswidth = 32,
323
+
.num_links = 2,
324
+
.links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC },
325
+
};
326
+
327
+
static struct qcom_icc_node qnm_snoc_gc = {
328
+
.name = "qnm_snoc_gc",
329
+
.id = QCS615_MASTER_SNOC_GC_MEM_NOC,
330
+
.channels = 1,
331
+
.buswidth = 8,
332
+
.num_links = 1,
333
+
.links = { QCS615_SLAVE_LLCC },
334
+
};
335
+
336
+
static struct qcom_icc_node qnm_snoc_sf = {
337
+
.name = "qnm_snoc_sf",
338
+
.id = QCS615_MASTER_SNOC_SF_MEM_NOC,
339
+
.channels = 1,
340
+
.buswidth = 16,
341
+
.num_links = 1,
342
+
.links = { QCS615_SLAVE_LLCC },
343
+
};
344
+
345
+
static struct qcom_icc_node ipa_core_master = {
346
+
.name = "ipa_core_master",
347
+
.id = QCS615_MASTER_IPA_CORE,
348
+
.channels = 1,
349
+
.buswidth = 8,
350
+
.num_links = 1,
351
+
.links = { QCS615_SLAVE_IPA_CORE },
352
+
};
353
+
354
+
static struct qcom_icc_node llcc_mc = {
355
+
.name = "llcc_mc",
356
+
.id = QCS615_MASTER_LLCC,
357
+
.channels = 2,
358
+
.buswidth = 4,
359
+
.num_links = 1,
360
+
.links = { QCS615_SLAVE_EBI1 },
361
+
};
362
+
363
+
static struct qcom_icc_node qhm_mnoc_cfg = {
364
+
.name = "qhm_mnoc_cfg",
365
+
.id = QCS615_MASTER_CNOC_MNOC_CFG,
366
+
.channels = 1,
367
+
.buswidth = 4,
368
+
.num_links = 1,
369
+
.links = { QCS615_SLAVE_SERVICE_MNOC },
370
+
};
371
+
372
+
static struct qcom_icc_node qxm_camnoc_hf0 = {
373
+
.name = "qxm_camnoc_hf0",
374
+
.id = QCS615_MASTER_CAMNOC_HF0,
375
+
.channels = 1,
376
+
.buswidth = 32,
377
+
.num_links = 1,
378
+
.links = { QCS615_SLAVE_MNOC_HF_MEM_NOC },
379
+
};
380
+
381
+
static struct qcom_icc_node qxm_camnoc_hf1 = {
382
+
.name = "qxm_camnoc_hf1",
383
+
.id = QCS615_MASTER_CAMNOC_HF1,
384
+
.channels = 1,
385
+
.buswidth = 32,
386
+
.num_links = 1,
387
+
.links = { QCS615_SLAVE_MNOC_HF_MEM_NOC },
388
+
};
389
+
390
+
static struct qcom_icc_node qxm_camnoc_sf = {
391
+
.name = "qxm_camnoc_sf",
392
+
.id = QCS615_MASTER_CAMNOC_SF,
393
+
.channels = 1,
394
+
.buswidth = 32,
395
+
.num_links = 1,
396
+
.links = { QCS615_SLAVE_MNOC_SF_MEM_NOC },
397
+
};
398
+
399
+
static struct qcom_icc_node qxm_mdp0 = {
400
+
.name = "qxm_mdp0",
401
+
.id = QCS615_MASTER_MDP0,
402
+
.channels = 1,
403
+
.buswidth = 32,
404
+
.num_links = 1,
405
+
.links = { QCS615_SLAVE_MNOC_HF_MEM_NOC },
406
+
};
407
+
408
+
static struct qcom_icc_node qxm_rot = {
409
+
.name = "qxm_rot",
410
+
.id = QCS615_MASTER_ROTATOR,
411
+
.channels = 1,
412
+
.buswidth = 32,
413
+
.num_links = 1,
414
+
.links = { QCS615_SLAVE_MNOC_SF_MEM_NOC },
415
+
};
416
+
417
+
static struct qcom_icc_node qxm_venus0 = {
418
+
.name = "qxm_venus0",
419
+
.id = QCS615_MASTER_VIDEO_P0,
420
+
.channels = 1,
421
+
.buswidth = 32,
422
+
.num_links = 1,
423
+
.links = { QCS615_SLAVE_MNOC_SF_MEM_NOC },
424
+
};
425
+
426
+
static struct qcom_icc_node qxm_venus_arm9 = {
427
+
.name = "qxm_venus_arm9",
428
+
.id = QCS615_MASTER_VIDEO_PROC,
429
+
.channels = 1,
430
+
.buswidth = 8,
431
+
.num_links = 1,
432
+
.links = { QCS615_SLAVE_MNOC_SF_MEM_NOC },
433
+
};
434
+
435
+
static struct qcom_icc_node qhm_snoc_cfg = {
436
+
.name = "qhm_snoc_cfg",
437
+
.id = QCS615_MASTER_SNOC_CFG,
438
+
.channels = 1,
439
+
.buswidth = 4,
440
+
.num_links = 1,
441
+
.links = { QCS615_SLAVE_SERVICE_SNOC },
442
+
};
443
+
444
+
static struct qcom_icc_node qnm_aggre1_noc = {
445
+
.name = "qnm_aggre1_noc",
446
+
.id = QCS615_MASTER_A1NOC_SNOC,
447
+
.channels = 1,
448
+
.buswidth = 16,
449
+
.num_links = 8,
450
+
.links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC,
451
+
QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM,
452
+
QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0,
453
+
QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU },
454
+
};
455
+
456
+
static struct qcom_icc_node qnm_gemnoc = {
457
+
.name = "qnm_gemnoc",
458
+
.id = QCS615_MASTER_GEM_NOC_SNOC,
459
+
.channels = 1,
460
+
.buswidth = 8,
461
+
.num_links = 6,
462
+
.links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC,
463
+
QCS615_SLAVE_IMEM, QCS615_SLAVE_PIMEM,
464
+
QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU },
465
+
};
466
+
467
+
static struct qcom_icc_node qnm_gemnoc_pcie = {
468
+
.name = "qnm_gemnoc_pcie",
469
+
.id = QCS615_MASTER_GEM_NOC_PCIE_SNOC,
470
+
.channels = 1,
471
+
.buswidth = 8,
472
+
.num_links = 1,
473
+
.links = { QCS615_SLAVE_PCIE_0 },
474
+
};
475
+
476
+
static struct qcom_icc_node qnm_lpass_anoc = {
477
+
.name = "qnm_lpass_anoc",
478
+
.id = QCS615_MASTER_LPASS_ANOC,
479
+
.channels = 1,
480
+
.buswidth = 8,
481
+
.num_links = 7,
482
+
.links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC,
483
+
QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM,
484
+
QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0,
485
+
QCS615_SLAVE_QDSS_STM },
486
+
};
487
+
488
+
static struct qcom_icc_node qnm_pcie_anoc = {
489
+
.name = "qnm_pcie_anoc",
490
+
.id = QCS615_MASTER_ANOC_PCIE_SNOC,
491
+
.channels = 1,
492
+
.buswidth = 8,
493
+
.num_links = 5,
494
+
.links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC,
495
+
QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM,
496
+
QCS615_SLAVE_QDSS_STM },
497
+
};
498
+
499
+
static struct qcom_icc_node qxm_pimem = {
500
+
.name = "qxm_pimem",
501
+
.id = QCS615_MASTER_PIMEM,
502
+
.channels = 1,
503
+
.buswidth = 8,
504
+
.num_links = 2,
505
+
.links = { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM },
506
+
};
507
+
508
+
static struct qcom_icc_node xm_gic = {
509
+
.name = "xm_gic",
510
+
.id = QCS615_MASTER_GIC,
511
+
.channels = 1,
512
+
.buswidth = 8,
513
+
.num_links = 2,
514
+
.links = { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM },
515
+
};
516
+
517
+
static struct qcom_icc_node qns_a1noc_snoc = {
518
+
.name = "qns_a1noc_snoc",
519
+
.id = QCS615_SLAVE_A1NOC_SNOC,
520
+
.channels = 1,
521
+
.buswidth = 16,
522
+
.num_links = 1,
523
+
.links = { QCS615_MASTER_A1NOC_SNOC },
524
+
};
525
+
526
+
static struct qcom_icc_node qns_lpass_snoc = {
527
+
.name = "qns_lpass_snoc",
528
+
.id = QCS615_SLAVE_LPASS_SNOC,
529
+
.channels = 1,
530
+
.buswidth = 8,
531
+
.num_links = 1,
532
+
.links = { QCS615_MASTER_LPASS_ANOC },
533
+
};
534
+
535
+
static struct qcom_icc_node qns_pcie_snoc = {
536
+
.name = "qns_pcie_snoc",
537
+
.id = QCS615_SLAVE_ANOC_PCIE_SNOC,
538
+
.channels = 1,
539
+
.buswidth = 8,
540
+
.num_links = 1,
541
+
.links = { QCS615_MASTER_ANOC_PCIE_SNOC },
542
+
};
543
+
544
+
static struct qcom_icc_node srvc_aggre2_noc = {
545
+
.name = "srvc_aggre2_noc",
546
+
.id = QCS615_SLAVE_SERVICE_A2NOC,
547
+
.channels = 1,
548
+
.buswidth = 4,
549
+
.num_links = 0,
550
+
};
551
+
552
+
static struct qcom_icc_node qns_camnoc_uncomp = {
553
+
.name = "qns_camnoc_uncomp",
554
+
.id = QCS615_SLAVE_CAMNOC_UNCOMP,
555
+
.channels = 1,
556
+
.buswidth = 32,
557
+
.num_links = 0,
558
+
};
559
+
560
+
static struct qcom_icc_node qhs_a1_noc_cfg = {
561
+
.name = "qhs_a1_noc_cfg",
562
+
.id = QCS615_SLAVE_A1NOC_CFG,
563
+
.channels = 1,
564
+
.buswidth = 4,
565
+
.num_links = 1,
566
+
.links = { QCS615_MASTER_A1NOC_CFG },
567
+
};
568
+
569
+
static struct qcom_icc_node qhs_ahb2phy_east = {
570
+
.name = "qhs_ahb2phy_east",
571
+
.id = QCS615_SLAVE_AHB2PHY_EAST,
572
+
.channels = 1,
573
+
.buswidth = 4,
574
+
.num_links = 0,
575
+
};
576
+
577
+
static struct qcom_icc_node qhs_ahb2phy_west = {
578
+
.name = "qhs_ahb2phy_west",
579
+
.id = QCS615_SLAVE_AHB2PHY_WEST,
580
+
.channels = 1,
581
+
.buswidth = 4,
582
+
.num_links = 0,
583
+
};
584
+
585
+
static struct qcom_icc_node qhs_aop = {
586
+
.name = "qhs_aop",
587
+
.id = QCS615_SLAVE_AOP,
588
+
.channels = 1,
589
+
.buswidth = 4,
590
+
.num_links = 0,
591
+
};
592
+
593
+
static struct qcom_icc_node qhs_aoss = {
594
+
.name = "qhs_aoss",
595
+
.id = QCS615_SLAVE_AOSS,
596
+
.channels = 1,
597
+
.buswidth = 4,
598
+
.num_links = 0,
599
+
};
600
+
601
+
static struct qcom_icc_node qhs_camera_cfg = {
602
+
.name = "qhs_camera_cfg",
603
+
.id = QCS615_SLAVE_CAMERA_CFG,
604
+
.channels = 1,
605
+
.buswidth = 4,
606
+
.num_links = 0,
607
+
};
608
+
609
+
static struct qcom_icc_node qhs_clk_ctl = {
610
+
.name = "qhs_clk_ctl",
611
+
.id = QCS615_SLAVE_CLK_CTL,
612
+
.channels = 1,
613
+
.buswidth = 4,
614
+
.num_links = 0,
615
+
};
616
+
617
+
static struct qcom_icc_node qhs_cpr_cx = {
618
+
.name = "qhs_cpr_cx",
619
+
.id = QCS615_SLAVE_RBCPR_CX_CFG,
620
+
.channels = 1,
621
+
.buswidth = 4,
622
+
.num_links = 0,
623
+
};
624
+
625
+
static struct qcom_icc_node qhs_cpr_mx = {
626
+
.name = "qhs_cpr_mx",
627
+
.id = QCS615_SLAVE_RBCPR_MX_CFG,
628
+
.channels = 1,
629
+
.buswidth = 4,
630
+
.num_links = 0,
631
+
};
632
+
633
+
static struct qcom_icc_node qhs_crypto0_cfg = {
634
+
.name = "qhs_crypto0_cfg",
635
+
.id = QCS615_SLAVE_CRYPTO_0_CFG,
636
+
.channels = 1,
637
+
.buswidth = 4,
638
+
.num_links = 0,
639
+
};
640
+
641
+
static struct qcom_icc_node qhs_ddrss_cfg = {
642
+
.name = "qhs_ddrss_cfg",
643
+
.id = QCS615_SLAVE_CNOC_DDRSS,
644
+
.channels = 1,
645
+
.buswidth = 4,
646
+
.num_links = 1,
647
+
.links = { QCS615_MASTER_CNOC_DC_NOC },
648
+
};
649
+
650
+
static struct qcom_icc_node qhs_display_cfg = {
651
+
.name = "qhs_display_cfg",
652
+
.id = QCS615_SLAVE_DISPLAY_CFG,
653
+
.channels = 1,
654
+
.buswidth = 4,
655
+
.num_links = 0,
656
+
};
657
+
658
+
static struct qcom_icc_node qhs_emac_avb_cfg = {
659
+
.name = "qhs_emac_avb_cfg",
660
+
.id = QCS615_SLAVE_EMAC_AVB_CFG,
661
+
.channels = 1,
662
+
.buswidth = 4,
663
+
.num_links = 0,
664
+
};
665
+
666
+
static struct qcom_icc_node qhs_glm = {
667
+
.name = "qhs_glm",
668
+
.id = QCS615_SLAVE_GLM,
669
+
.channels = 1,
670
+
.buswidth = 4,
671
+
.num_links = 0,
672
+
};
673
+
674
+
static struct qcom_icc_node qhs_gpuss_cfg = {
675
+
.name = "qhs_gpuss_cfg",
676
+
.id = QCS615_SLAVE_GFX3D_CFG,
677
+
.channels = 1,
678
+
.buswidth = 8,
679
+
.num_links = 0,
680
+
};
681
+
682
+
static struct qcom_icc_node qhs_imem_cfg = {
683
+
.name = "qhs_imem_cfg",
684
+
.id = QCS615_SLAVE_IMEM_CFG,
685
+
.channels = 1,
686
+
.buswidth = 4,
687
+
.num_links = 0,
688
+
};
689
+
690
+
static struct qcom_icc_node qhs_ipa = {
691
+
.name = "qhs_ipa",
692
+
.id = QCS615_SLAVE_IPA_CFG,
693
+
.channels = 1,
694
+
.buswidth = 4,
695
+
.num_links = 0,
696
+
};
697
+
698
+
static struct qcom_icc_node qhs_mnoc_cfg = {
699
+
.name = "qhs_mnoc_cfg",
700
+
.id = QCS615_SLAVE_CNOC_MNOC_CFG,
701
+
.channels = 1,
702
+
.buswidth = 4,
703
+
.num_links = 1,
704
+
.links = { QCS615_MASTER_CNOC_MNOC_CFG },
705
+
};
706
+
707
+
static struct qcom_icc_node qhs_pcie_config = {
708
+
.name = "qhs_pcie_config",
709
+
.id = QCS615_SLAVE_PCIE_CFG,
710
+
.channels = 1,
711
+
.buswidth = 4,
712
+
.num_links = 0,
713
+
};
714
+
715
+
static struct qcom_icc_node qhs_pimem_cfg = {
716
+
.name = "qhs_pimem_cfg",
717
+
.id = QCS615_SLAVE_PIMEM_CFG,
718
+
.channels = 1,
719
+
.buswidth = 4,
720
+
.num_links = 0,
721
+
};
722
+
723
+
static struct qcom_icc_node qhs_prng = {
724
+
.name = "qhs_prng",
725
+
.id = QCS615_SLAVE_PRNG,
726
+
.channels = 1,
727
+
.buswidth = 4,
728
+
.num_links = 0,
729
+
};
730
+
731
+
static struct qcom_icc_node qhs_qdss_cfg = {
732
+
.name = "qhs_qdss_cfg",
733
+
.id = QCS615_SLAVE_QDSS_CFG,
734
+
.channels = 1,
735
+
.buswidth = 4,
736
+
.num_links = 0,
737
+
};
738
+
739
+
static struct qcom_icc_node qhs_qspi = {
740
+
.name = "qhs_qspi",
741
+
.id = QCS615_SLAVE_QSPI,
742
+
.channels = 1,
743
+
.buswidth = 4,
744
+
.num_links = 0,
745
+
};
746
+
747
+
static struct qcom_icc_node qhs_qup0 = {
748
+
.name = "qhs_qup0",
749
+
.id = QCS615_SLAVE_QUP_0,
750
+
.channels = 1,
751
+
.buswidth = 4,
752
+
.num_links = 0,
753
+
};
754
+
755
+
static struct qcom_icc_node qhs_qup1 = {
756
+
.name = "qhs_qup1",
757
+
.id = QCS615_SLAVE_QUP_1,
758
+
.channels = 1,
759
+
.buswidth = 4,
760
+
.num_links = 0,
761
+
};
762
+
763
+
static struct qcom_icc_node qhs_sdc1 = {
764
+
.name = "qhs_sdc1",
765
+
.id = QCS615_SLAVE_SDCC_1,
766
+
.channels = 1,
767
+
.buswidth = 4,
768
+
.num_links = 0,
769
+
};
770
+
771
+
static struct qcom_icc_node qhs_sdc2 = {
772
+
.name = "qhs_sdc2",
773
+
.id = QCS615_SLAVE_SDCC_2,
774
+
.channels = 1,
775
+
.buswidth = 4,
776
+
.num_links = 0,
777
+
};
778
+
779
+
static struct qcom_icc_node qhs_snoc_cfg = {
780
+
.name = "qhs_snoc_cfg",
781
+
.id = QCS615_SLAVE_SNOC_CFG,
782
+
.channels = 1,
783
+
.buswidth = 4,
784
+
.num_links = 1,
785
+
.links = { QCS615_MASTER_SNOC_CFG },
786
+
};
787
+
788
+
static struct qcom_icc_node qhs_spdm = {
789
+
.name = "qhs_spdm",
790
+
.id = QCS615_SLAVE_SPDM_WRAPPER,
791
+
.channels = 1,
792
+
.buswidth = 4,
793
+
.num_links = 0,
794
+
};
795
+
796
+
static struct qcom_icc_node qhs_tcsr = {
797
+
.name = "qhs_tcsr",
798
+
.id = QCS615_SLAVE_TCSR,
799
+
.channels = 1,
800
+
.buswidth = 4,
801
+
.num_links = 0,
802
+
};
803
+
804
+
static struct qcom_icc_node qhs_tlmm_east = {
805
+
.name = "qhs_tlmm_east",
806
+
.id = QCS615_SLAVE_TLMM_EAST,
807
+
.channels = 1,
808
+
.buswidth = 4,
809
+
.num_links = 0,
810
+
};
811
+
812
+
static struct qcom_icc_node qhs_tlmm_south = {
813
+
.name = "qhs_tlmm_south",
814
+
.id = QCS615_SLAVE_TLMM_SOUTH,
815
+
.channels = 1,
816
+
.buswidth = 4,
817
+
.num_links = 0,
818
+
};
819
+
820
+
static struct qcom_icc_node qhs_tlmm_west = {
821
+
.name = "qhs_tlmm_west",
822
+
.id = QCS615_SLAVE_TLMM_WEST,
823
+
.channels = 1,
824
+
.buswidth = 4,
825
+
.num_links = 0,
826
+
};
827
+
828
+
static struct qcom_icc_node qhs_ufs_mem_cfg = {
829
+
.name = "qhs_ufs_mem_cfg",
830
+
.id = QCS615_SLAVE_UFS_MEM_CFG,
831
+
.channels = 1,
832
+
.buswidth = 4,
833
+
.num_links = 0,
834
+
};
835
+
836
+
static struct qcom_icc_node qhs_usb2 = {
837
+
.name = "qhs_usb2",
838
+
.id = QCS615_SLAVE_USB2,
839
+
.channels = 1,
840
+
.buswidth = 4,
841
+
.num_links = 0,
842
+
};
843
+
844
+
static struct qcom_icc_node qhs_usb3 = {
845
+
.name = "qhs_usb3",
846
+
.id = QCS615_SLAVE_USB3,
847
+
.channels = 1,
848
+
.buswidth = 4,
849
+
.num_links = 0,
850
+
};
851
+
852
+
static struct qcom_icc_node qhs_venus_cfg = {
853
+
.name = "qhs_venus_cfg",
854
+
.id = QCS615_SLAVE_VENUS_CFG,
855
+
.channels = 1,
856
+
.buswidth = 4,
857
+
.num_links = 0,
858
+
};
859
+
860
+
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
861
+
.name = "qhs_vsense_ctrl_cfg",
862
+
.id = QCS615_SLAVE_VSENSE_CTRL_CFG,
863
+
.channels = 1,
864
+
.buswidth = 4,
865
+
.num_links = 0,
866
+
};
867
+
868
+
static struct qcom_icc_node qns_cnoc_a2noc = {
869
+
.name = "qns_cnoc_a2noc",
870
+
.id = QCS615_SLAVE_CNOC_A2NOC,
871
+
.channels = 1,
872
+
.buswidth = 8,
873
+
.num_links = 1,
874
+
.links = { QCS615_MASTER_CNOC_A2NOC },
875
+
};
876
+
877
+
static struct qcom_icc_node srvc_cnoc = {
878
+
.name = "srvc_cnoc",
879
+
.id = QCS615_SLAVE_SERVICE_CNOC,
880
+
.channels = 1,
881
+
.buswidth = 4,
882
+
.num_links = 0,
883
+
};
884
+
885
+
static struct qcom_icc_node qhs_dc_noc_gemnoc = {
886
+
.name = "qhs_dc_noc_gemnoc",
887
+
.id = QCS615_SLAVE_DC_NOC_GEMNOC,
888
+
.channels = 1,
889
+
.buswidth = 4,
890
+
.num_links = 1,
891
+
.links = { QCS615_MASTER_GEM_NOC_CFG },
892
+
};
893
+
894
+
static struct qcom_icc_node qhs_llcc = {
895
+
.name = "qhs_llcc",
896
+
.id = QCS615_SLAVE_LLCC_CFG,
897
+
.channels = 1,
898
+
.buswidth = 4,
899
+
.num_links = 0,
900
+
};
901
+
902
+
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
903
+
.name = "qhs_mdsp_ms_mpu_cfg",
904
+
.id = QCS615_SLAVE_MSS_PROC_MS_MPU_CFG,
905
+
.channels = 1,
906
+
.buswidth = 4,
907
+
.num_links = 0,
908
+
};
909
+
910
+
static struct qcom_icc_node qns_gem_noc_snoc = {
911
+
.name = "qns_gem_noc_snoc",
912
+
.id = QCS615_SLAVE_GEM_NOC_SNOC,
913
+
.channels = 1,
914
+
.buswidth = 8,
915
+
.num_links = 1,
916
+
.links = { QCS615_MASTER_GEM_NOC_SNOC },
917
+
};
918
+
919
+
static struct qcom_icc_node qns_llcc = {
920
+
.name = "qns_llcc",
921
+
.id = QCS615_SLAVE_LLCC,
922
+
.channels = 1,
923
+
.buswidth = 16,
924
+
.num_links = 1,
925
+
.links = { QCS615_MASTER_LLCC },
926
+
};
927
+
928
+
static struct qcom_icc_node qns_sys_pcie = {
929
+
.name = "qns_sys_pcie",
930
+
.id = QCS615_SLAVE_MEM_NOC_PCIE_SNOC,
931
+
.channels = 1,
932
+
.buswidth = 8,
933
+
.num_links = 1,
934
+
.links = { QCS615_MASTER_GEM_NOC_PCIE_SNOC },
935
+
};
936
+
937
+
static struct qcom_icc_node srvc_gemnoc = {
938
+
.name = "srvc_gemnoc",
939
+
.id = QCS615_SLAVE_SERVICE_GEM_NOC,
940
+
.channels = 1,
941
+
.buswidth = 4,
942
+
.num_links = 0,
943
+
};
944
+
945
+
static struct qcom_icc_node ipa_core_slave = {
946
+
.name = "ipa_core_slave",
947
+
.id = QCS615_SLAVE_IPA_CORE,
948
+
.channels = 1,
949
+
.buswidth = 8,
950
+
.num_links = 0,
951
+
};
952
+
953
+
static struct qcom_icc_node ebi = {
954
+
.name = "ebi",
955
+
.id = QCS615_SLAVE_EBI1,
956
+
.channels = 2,
957
+
.buswidth = 4,
958
+
.num_links = 0,
959
+
};
960
+
961
+
static struct qcom_icc_node qns2_mem_noc = {
962
+
.name = "qns2_mem_noc",
963
+
.id = QCS615_SLAVE_MNOC_SF_MEM_NOC,
964
+
.channels = 1,
965
+
.buswidth = 32,
966
+
.num_links = 1,
967
+
.links = { QCS615_MASTER_MNOC_SF_MEM_NOC },
968
+
};
969
+
970
+
static struct qcom_icc_node qns_mem_noc_hf = {
971
+
.name = "qns_mem_noc_hf",
972
+
.id = QCS615_SLAVE_MNOC_HF_MEM_NOC,
973
+
.channels = 1,
974
+
.buswidth = 32,
975
+
.num_links = 1,
976
+
.links = { QCS615_MASTER_MNOC_HF_MEM_NOC },
977
+
};
978
+
979
+
static struct qcom_icc_node srvc_mnoc = {
980
+
.name = "srvc_mnoc",
981
+
.id = QCS615_SLAVE_SERVICE_MNOC,
982
+
.channels = 1,
983
+
.buswidth = 4,
984
+
.num_links = 0,
985
+
};
986
+
987
+
static struct qcom_icc_node qhs_apss = {
988
+
.name = "qhs_apss",
989
+
.id = QCS615_SLAVE_APPSS,
990
+
.channels = 1,
991
+
.buswidth = 8,
992
+
.num_links = 0,
993
+
};
994
+
995
+
static struct qcom_icc_node qns_cnoc = {
996
+
.name = "qns_cnoc",
997
+
.id = QCS615_SLAVE_SNOC_CNOC,
998
+
.channels = 1,
999
+
.buswidth = 8,
1000
+
.num_links = 1,
1001
+
.links = { QCS615_MASTER_SNOC_CNOC },
1002
+
};
1003
+
1004
+
static struct qcom_icc_node qns_gemnoc_sf = {
1005
+
.name = "qns_gemnoc_sf",
1006
+
.id = QCS615_SLAVE_SNOC_GEM_NOC_SF,
1007
+
.channels = 1,
1008
+
.buswidth = 16,
1009
+
.num_links = 1,
1010
+
.links = { QCS615_MASTER_SNOC_SF_MEM_NOC },
1011
+
};
1012
+
1013
+
static struct qcom_icc_node qns_memnoc_gc = {
1014
+
.name = "qns_memnoc_gc",
1015
+
.id = QCS615_SLAVE_SNOC_MEM_NOC_GC,
1016
+
.channels = 1,
1017
+
.buswidth = 8,
1018
+
.num_links = 1,
1019
+
.links = { QCS615_MASTER_SNOC_GC_MEM_NOC },
1020
+
};
1021
+
1022
+
static struct qcom_icc_node qxs_imem = {
1023
+
.name = "qxs_imem",
1024
+
.id = QCS615_SLAVE_IMEM,
1025
+
.channels = 1,
1026
+
.buswidth = 8,
1027
+
.num_links = 0,
1028
+
};
1029
+
1030
+
static struct qcom_icc_node qxs_pimem = {
1031
+
.name = "qxs_pimem",
1032
+
.id = QCS615_SLAVE_PIMEM,
1033
+
.channels = 1,
1034
+
.buswidth = 8,
1035
+
.num_links = 0,
1036
+
};
1037
+
1038
+
static struct qcom_icc_node srvc_snoc = {
1039
+
.name = "srvc_snoc",
1040
+
.id = QCS615_SLAVE_SERVICE_SNOC,
1041
+
.channels = 1,
1042
+
.buswidth = 4,
1043
+
.num_links = 0,
1044
+
};
1045
+
1046
+
static struct qcom_icc_node xs_pcie = {
1047
+
.name = "xs_pcie",
1048
+
.id = QCS615_SLAVE_PCIE_0,
1049
+
.channels = 1,
1050
+
.buswidth = 8,
1051
+
.num_links = 0,
1052
+
};
1053
+
1054
+
static struct qcom_icc_node xs_qdss_stm = {
1055
+
.name = "xs_qdss_stm",
1056
+
.id = QCS615_SLAVE_QDSS_STM,
1057
+
.channels = 1,
1058
+
.buswidth = 4,
1059
+
.num_links = 0,
1060
+
};
1061
+
1062
+
static struct qcom_icc_node xs_sys_tcu_cfg = {
1063
+
.name = "xs_sys_tcu_cfg",
1064
+
.id = QCS615_SLAVE_TCU,
1065
+
.channels = 1,
1066
+
.buswidth = 8,
1067
+
.num_links = 0,
1068
+
};
1069
+
1070
+
static struct qcom_icc_bcm bcm_acv = {
1071
+
.name = "ACV",
1072
+
.num_nodes = 1,
1073
+
.nodes = { &ebi },
1074
+
};
1075
+
1076
+
static struct qcom_icc_bcm bcm_ce0 = {
1077
+
.name = "CE0",
1078
+
.num_nodes = 1,
1079
+
.nodes = { &qxm_crypto },
1080
+
};
1081
+
1082
+
static struct qcom_icc_bcm bcm_cn0 = {
1083
+
.name = "CN0",
1084
+
.keepalive = true,
1085
+
.num_nodes = 37,
1086
+
.nodes = { &qhm_spdm, &qnm_snoc,
1087
+
&qhs_a1_noc_cfg, &qhs_aop,
1088
+
&qhs_aoss, &qhs_camera_cfg,
1089
+
&qhs_clk_ctl, &qhs_cpr_cx,
1090
+
&qhs_cpr_mx, &qhs_crypto0_cfg,
1091
+
&qhs_ddrss_cfg, &qhs_display_cfg,
1092
+
&qhs_emac_avb_cfg, &qhs_glm,
1093
+
&qhs_gpuss_cfg, &qhs_imem_cfg,
1094
+
&qhs_ipa, &qhs_mnoc_cfg,
1095
+
&qhs_pcie_config, &qhs_pimem_cfg,
1096
+
&qhs_prng, &qhs_qdss_cfg,
1097
+
&qhs_qup0, &qhs_qup1,
1098
+
&qhs_snoc_cfg, &qhs_spdm,
1099
+
&qhs_tcsr, &qhs_tlmm_east,
1100
+
&qhs_tlmm_south, &qhs_tlmm_west,
1101
+
&qhs_ufs_mem_cfg, &qhs_usb2,
1102
+
&qhs_usb3, &qhs_venus_cfg,
1103
+
&qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc,
1104
+
&srvc_cnoc },
1105
+
};
1106
+
1107
+
static struct qcom_icc_bcm bcm_cn1 = {
1108
+
.name = "CN1",
1109
+
.num_nodes = 8,
1110
+
.nodes = { &qhm_qspi, &xm_sdc1,
1111
+
&xm_sdc2, &qhs_ahb2phy_east,
1112
+
&qhs_ahb2phy_west, &qhs_qspi,
1113
+
&qhs_sdc1, &qhs_sdc2 },
1114
+
};
1115
+
1116
+
static struct qcom_icc_bcm bcm_ip0 = {
1117
+
.name = "IP0",
1118
+
.num_nodes = 1,
1119
+
.nodes = { &ipa_core_slave },
1120
+
};
1121
+
1122
+
static struct qcom_icc_bcm bcm_mc0 = {
1123
+
.name = "MC0",
1124
+
.keepalive = true,
1125
+
.num_nodes = 1,
1126
+
.nodes = { &ebi },
1127
+
};
1128
+
1129
+
static struct qcom_icc_bcm bcm_mm0 = {
1130
+
.name = "MM0",
1131
+
.keepalive = true,
1132
+
.num_nodes = 1,
1133
+
.nodes = { &qns_mem_noc_hf },
1134
+
};
1135
+
1136
+
static struct qcom_icc_bcm bcm_mm1 = {
1137
+
.name = "MM1",
1138
+
.num_nodes = 7,
1139
+
.nodes = { &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp,
1140
+
&qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0,
1141
+
&qxm_camnoc_hf1, &qxm_mdp0,
1142
+
&qxm_rot },
1143
+
};
1144
+
1145
+
static struct qcom_icc_bcm bcm_mm2 = {
1146
+
.name = "MM2",
1147
+
.num_nodes = 2,
1148
+
.nodes = { &qxm_camnoc_sf, &qns2_mem_noc },
1149
+
};
1150
+
1151
+
static struct qcom_icc_bcm bcm_mm3 = {
1152
+
.name = "MM3",
1153
+
.num_nodes = 2,
1154
+
.nodes = { &qxm_venus0, &qxm_venus_arm9 },
1155
+
};
1156
+
1157
+
static struct qcom_icc_bcm bcm_qup0 = {
1158
+
.name = "QUP0",
1159
+
.keepalive = true,
1160
+
.vote_scale = 1,
1161
+
.num_nodes = 2,
1162
+
.nodes = { &qhm_qup0, &qhm_qup1 },
1163
+
};
1164
+
1165
+
static struct qcom_icc_bcm bcm_sh0 = {
1166
+
.name = "SH0",
1167
+
.keepalive = true,
1168
+
.num_nodes = 1,
1169
+
.nodes = { &qns_llcc },
1170
+
};
1171
+
1172
+
static struct qcom_icc_bcm bcm_sh2 = {
1173
+
.name = "SH2",
1174
+
.num_nodes = 1,
1175
+
.nodes = { &acm_apps },
1176
+
};
1177
+
1178
+
static struct qcom_icc_bcm bcm_sh3 = {
1179
+
.name = "SH3",
1180
+
.num_nodes = 1,
1181
+
.nodes = { &qns_gem_noc_snoc },
1182
+
};
1183
+
1184
+
static struct qcom_icc_bcm bcm_sn0 = {
1185
+
.name = "SN0",
1186
+
.keepalive = true,
1187
+
.num_nodes = 1,
1188
+
.nodes = { &qns_gemnoc_sf },
1189
+
};
1190
+
1191
+
static struct qcom_icc_bcm bcm_sn1 = {
1192
+
.name = "SN1",
1193
+
.num_nodes = 1,
1194
+
.nodes = { &qxs_imem },
1195
+
};
1196
+
1197
+
static struct qcom_icc_bcm bcm_sn2 = {
1198
+
.name = "SN2",
1199
+
.num_nodes = 1,
1200
+
.nodes = { &qns_memnoc_gc },
1201
+
};
1202
+
1203
+
static struct qcom_icc_bcm bcm_sn3 = {
1204
+
.name = "SN3",
1205
+
.num_nodes = 2,
1206
+
.nodes = { &srvc_aggre2_noc, &qns_cnoc },
1207
+
};
1208
+
1209
+
static struct qcom_icc_bcm bcm_sn4 = {
1210
+
.name = "SN4",
1211
+
.num_nodes = 1,
1212
+
.nodes = { &qxs_pimem },
1213
+
};
1214
+
1215
+
static struct qcom_icc_bcm bcm_sn5 = {
1216
+
.name = "SN5",
1217
+
.num_nodes = 1,
1218
+
.nodes = { &xs_qdss_stm },
1219
+
};
1220
+
1221
+
static struct qcom_icc_bcm bcm_sn8 = {
1222
+
.name = "SN8",
1223
+
.num_nodes = 2,
1224
+
.nodes = { &qnm_gemnoc_pcie, &xs_pcie },
1225
+
};
1226
+
1227
+
static struct qcom_icc_bcm bcm_sn9 = {
1228
+
.name = "SN9",
1229
+
.num_nodes = 1,
1230
+
.nodes = { &qnm_aggre1_noc },
1231
+
};
1232
+
1233
+
static struct qcom_icc_bcm bcm_sn12 = {
1234
+
.name = "SN12",
1235
+
.num_nodes = 2,
1236
+
.nodes = { &qxm_pimem, &xm_gic },
1237
+
};
1238
+
1239
+
static struct qcom_icc_bcm bcm_sn13 = {
1240
+
.name = "SN13",
1241
+
.num_nodes = 1,
1242
+
.nodes = { &qnm_lpass_anoc },
1243
+
};
1244
+
1245
+
static struct qcom_icc_bcm bcm_sn14 = {
1246
+
.name = "SN14",
1247
+
.num_nodes = 1,
1248
+
.nodes = { &qns_pcie_snoc },
1249
+
};
1250
+
1251
+
static struct qcom_icc_bcm bcm_sn15 = {
1252
+
.name = "SN15",
1253
+
.num_nodes = 1,
1254
+
.nodes = { &qnm_gemnoc },
1255
+
};
1256
+
1257
+
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1258
+
&bcm_ce0,
1259
+
&bcm_cn1,
1260
+
&bcm_qup0,
1261
+
&bcm_sn3,
1262
+
&bcm_sn14,
1263
+
&bcm_ip0,
1264
+
};
1265
+
1266
+
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1267
+
[MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
1268
+
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
1269
+
[MASTER_QSPI] = &qhm_qspi,
1270
+
[MASTER_QUP_0] = &qhm_qup0,
1271
+
[MASTER_BLSP_1] = &qhm_qup1,
1272
+
[MASTER_CNOC_A2NOC] = &qnm_cnoc,
1273
+
[MASTER_CRYPTO] = &qxm_crypto,
1274
+
[MASTER_IPA] = &qxm_ipa,
1275
+
[MASTER_EMAC_EVB] = &xm_emac_avb,
1276
+
[MASTER_PCIE] = &xm_pcie,
1277
+
[MASTER_QDSS_ETR] = &xm_qdss_etr,
1278
+
[MASTER_SDCC_1] = &xm_sdc1,
1279
+
[MASTER_SDCC_2] = &xm_sdc2,
1280
+
[MASTER_UFS_MEM] = &xm_ufs_mem,
1281
+
[MASTER_USB2] = &xm_usb2,
1282
+
[MASTER_USB3_0] = &xm_usb3_0,
1283
+
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1284
+
[SLAVE_LPASS_SNOC] = &qns_lpass_snoc,
1285
+
[SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc,
1286
+
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1287
+
};
1288
+
1289
+
static const struct qcom_icc_desc qcs615_aggre1_noc = {
1290
+
.nodes = aggre1_noc_nodes,
1291
+
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1292
+
.bcms = aggre1_noc_bcms,
1293
+
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1294
+
};
1295
+
1296
+
static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
1297
+
&bcm_mm1,
1298
+
};
1299
+
1300
+
static struct qcom_icc_node * const camnoc_virt_nodes[] = {
1301
+
[MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
1302
+
[MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
1303
+
[MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
1304
+
[SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
1305
+
};
1306
+
1307
+
static const struct qcom_icc_desc qcs615_camnoc_virt = {
1308
+
.nodes = camnoc_virt_nodes,
1309
+
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
1310
+
.bcms = camnoc_virt_bcms,
1311
+
.num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
1312
+
};
1313
+
1314
+
static struct qcom_icc_bcm * const config_noc_bcms[] = {
1315
+
&bcm_cn0,
1316
+
&bcm_cn1,
1317
+
};
1318
+
1319
+
static struct qcom_icc_node * const config_noc_nodes[] = {
1320
+
[MASTER_SPDM] = &qhm_spdm,
1321
+
[MASTER_SNOC_CNOC] = &qnm_snoc,
1322
+
[MASTER_QDSS_DAP] = &xm_qdss_dap,
1323
+
[SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
1324
+
[SLAVE_AHB2PHY_EAST] = &qhs_ahb2phy_east,
1325
+
[SLAVE_AHB2PHY_WEST] = &qhs_ahb2phy_west,
1326
+
[SLAVE_AOP] = &qhs_aop,
1327
+
[SLAVE_AOSS] = &qhs_aoss,
1328
+
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1329
+
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1330
+
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1331
+
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1332
+
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1333
+
[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
1334
+
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1335
+
[SLAVE_EMAC_AVB_CFG] = &qhs_emac_avb_cfg,
1336
+
[SLAVE_GLM] = &qhs_glm,
1337
+
[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1338
+
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1339
+
[SLAVE_IPA_CFG] = &qhs_ipa,
1340
+
[SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
1341
+
[SLAVE_PCIE_CFG] = &qhs_pcie_config,
1342
+
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1343
+
[SLAVE_PRNG] = &qhs_prng,
1344
+
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1345
+
[SLAVE_QSPI] = &qhs_qspi,
1346
+
[SLAVE_QUP_0] = &qhs_qup0,
1347
+
[SLAVE_QUP_1] = &qhs_qup1,
1348
+
[SLAVE_SDCC_1] = &qhs_sdc1,
1349
+
[SLAVE_SDCC_2] = &qhs_sdc2,
1350
+
[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
1351
+
[SLAVE_SPDM_WRAPPER] = &qhs_spdm,
1352
+
[SLAVE_TCSR] = &qhs_tcsr,
1353
+
[SLAVE_TLMM_EAST] = &qhs_tlmm_east,
1354
+
[SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
1355
+
[SLAVE_TLMM_WEST] = &qhs_tlmm_west,
1356
+
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1357
+
[SLAVE_USB2] = &qhs_usb2,
1358
+
[SLAVE_USB3] = &qhs_usb3,
1359
+
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1360
+
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1361
+
[SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1362
+
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1363
+
};
1364
+
1365
+
static const struct qcom_icc_desc qcs615_config_noc = {
1366
+
.nodes = config_noc_nodes,
1367
+
.num_nodes = ARRAY_SIZE(config_noc_nodes),
1368
+
.bcms = config_noc_bcms,
1369
+
.num_bcms = ARRAY_SIZE(config_noc_bcms),
1370
+
};
1371
+
1372
+
static struct qcom_icc_node * const dc_noc_nodes[] = {
1373
+
[MASTER_CNOC_DC_NOC] = &qhm_cnoc,
1374
+
[SLAVE_DC_NOC_GEMNOC] = &qhs_dc_noc_gemnoc,
1375
+
[SLAVE_LLCC_CFG] = &qhs_llcc,
1376
+
};
1377
+
1378
+
static const struct qcom_icc_desc qcs615_dc_noc = {
1379
+
.nodes = dc_noc_nodes,
1380
+
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
1381
+
};
1382
+
1383
+
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1384
+
&bcm_sh0,
1385
+
&bcm_sh2,
1386
+
&bcm_sh3,
1387
+
&bcm_mm1,
1388
+
};
1389
+
1390
+
static struct qcom_icc_node * const gem_noc_nodes[] = {
1391
+
[MASTER_APPSS_PROC] = &acm_apps,
1392
+
[MASTER_GPU_TCU] = &acm_gpu_tcu,
1393
+
[MASTER_SYS_TCU] = &acm_sys_tcu,
1394
+
[MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
1395
+
[MASTER_GFX3D] = &qnm_gpu,
1396
+
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1397
+
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1398
+
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1399
+
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1400
+
[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1401
+
[SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
1402
+
[SLAVE_LLCC] = &qns_llcc,
1403
+
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
1404
+
[SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
1405
+
};
1406
+
1407
+
static const struct qcom_icc_desc qcs615_gem_noc = {
1408
+
.nodes = gem_noc_nodes,
1409
+
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1410
+
.bcms = gem_noc_bcms,
1411
+
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1412
+
};
1413
+
1414
+
static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
1415
+
&bcm_ip0,
1416
+
};
1417
+
1418
+
static struct qcom_icc_node * const ipa_virt_nodes[] = {
1419
+
[MASTER_IPA_CORE] = &ipa_core_master,
1420
+
[SLAVE_IPA_CORE] = &ipa_core_slave,
1421
+
};
1422
+
1423
+
static const struct qcom_icc_desc qcs615_ipa_virt = {
1424
+
.nodes = ipa_virt_nodes,
1425
+
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
1426
+
.bcms = ipa_virt_bcms,
1427
+
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
1428
+
};
1429
+
1430
+
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1431
+
&bcm_acv,
1432
+
&bcm_mc0,
1433
+
};
1434
+
1435
+
static struct qcom_icc_node * const mc_virt_nodes[] = {
1436
+
[MASTER_LLCC] = &llcc_mc,
1437
+
[SLAVE_EBI1] = &ebi,
1438
+
};
1439
+
1440
+
static const struct qcom_icc_desc qcs615_mc_virt = {
1441
+
.nodes = mc_virt_nodes,
1442
+
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1443
+
.bcms = mc_virt_bcms,
1444
+
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
1445
+
};
1446
+
1447
+
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1448
+
&bcm_mm0,
1449
+
&bcm_mm1,
1450
+
&bcm_mm2,
1451
+
&bcm_mm3,
1452
+
};
1453
+
1454
+
static struct qcom_icc_node * const mmss_noc_nodes[] = {
1455
+
[MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
1456
+
[MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
1457
+
[MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
1458
+
[MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1459
+
[MASTER_MDP0] = &qxm_mdp0,
1460
+
[MASTER_ROTATOR] = &qxm_rot,
1461
+
[MASTER_VIDEO_P0] = &qxm_venus0,
1462
+
[MASTER_VIDEO_PROC] = &qxm_venus_arm9,
1463
+
[SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
1464
+
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1465
+
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1466
+
};
1467
+
1468
+
static const struct qcom_icc_desc qcs615_mmss_noc = {
1469
+
.nodes = mmss_noc_nodes,
1470
+
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1471
+
.bcms = mmss_noc_bcms,
1472
+
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1473
+
};
1474
+
1475
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
1476
+
&bcm_sn0,
1477
+
&bcm_sn1,
1478
+
&bcm_sn2,
1479
+
&bcm_sn3,
1480
+
&bcm_sn4,
1481
+
&bcm_sn5,
1482
+
&bcm_sn8,
1483
+
&bcm_sn9,
1484
+
&bcm_sn12,
1485
+
&bcm_sn13,
1486
+
&bcm_sn15,
1487
+
};
1488
+
1489
+
static struct qcom_icc_node * const system_noc_nodes[] = {
1490
+
[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1491
+
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1492
+
[MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
1493
+
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1494
+
[MASTER_LPASS_ANOC] = &qnm_lpass_anoc,
1495
+
[MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc,
1496
+
[MASTER_PIMEM] = &qxm_pimem,
1497
+
[MASTER_GIC] = &xm_gic,
1498
+
[SLAVE_APPSS] = &qhs_apss,
1499
+
[SLAVE_SNOC_CNOC] = &qns_cnoc,
1500
+
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1501
+
[SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc,
1502
+
[SLAVE_IMEM] = &qxs_imem,
1503
+
[SLAVE_PIMEM] = &qxs_pimem,
1504
+
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
1505
+
[SLAVE_PCIE_0] = &xs_pcie,
1506
+
[SLAVE_QDSS_STM] = &xs_qdss_stm,
1507
+
[SLAVE_TCU] = &xs_sys_tcu_cfg,
1508
+
};
1509
+
1510
+
static const struct qcom_icc_desc qcs615_system_noc = {
1511
+
.nodes = system_noc_nodes,
1512
+
.num_nodes = ARRAY_SIZE(system_noc_nodes),
1513
+
.bcms = system_noc_bcms,
1514
+
.num_bcms = ARRAY_SIZE(system_noc_bcms),
1515
+
};
1516
+
1517
+
static const struct of_device_id qnoc_of_match[] = {
1518
+
{ .compatible = "qcom,qcs615-aggre1-noc",
1519
+
.data = &qcs615_aggre1_noc},
1520
+
{ .compatible = "qcom,qcs615-camnoc-virt",
1521
+
.data = &qcs615_camnoc_virt},
1522
+
{ .compatible = "qcom,qcs615-config-noc",
1523
+
.data = &qcs615_config_noc},
1524
+
{ .compatible = "qcom,qcs615-dc-noc",
1525
+
.data = &qcs615_dc_noc},
1526
+
{ .compatible = "qcom,qcs615-gem-noc",
1527
+
.data = &qcs615_gem_noc},
1528
+
{ .compatible = "qcom,qcs615-ipa-virt",
1529
+
.data = &qcs615_ipa_virt},
1530
+
{ .compatible = "qcom,qcs615-mc-virt",
1531
+
.data = &qcs615_mc_virt},
1532
+
{ .compatible = "qcom,qcs615-mmss-noc",
1533
+
.data = &qcs615_mmss_noc},
1534
+
{ .compatible = "qcom,qcs615-system-noc",
1535
+
.data = &qcs615_system_noc},
1536
+
{ }
1537
+
};
1538
+
MODULE_DEVICE_TABLE(of, qnoc_of_match);
1539
+
1540
+
static struct platform_driver qnoc_driver = {
1541
+
.probe = qcom_icc_rpmh_probe,
1542
+
.remove = qcom_icc_rpmh_remove,
1543
+
.driver = {
1544
+
.name = "qnoc-qcs615",
1545
+
.of_match_table = qnoc_of_match,
1546
+
.sync_state = icc_sync_state,
1547
+
},
1548
+
};
1549
+
1550
+
static int __init qnoc_driver_init(void)
1551
+
{
1552
+
return platform_driver_register(&qnoc_driver);
1553
+
}
1554
+
core_initcall(qnoc_driver_init);
1555
+
1556
+
static void __exit qnoc_driver_exit(void)
1557
+
{
1558
+
platform_driver_unregister(&qnoc_driver);
1559
+
}
1560
+
module_exit(qnoc_driver_exit);
1561
+
1562
+
MODULE_DESCRIPTION("qcs615 NoC driver");
1563
+
MODULE_LICENSE("GPL");
+128
drivers/interconnect/qcom/qcs615.h
+128
drivers/interconnect/qcom/qcs615.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS615_H
7
+
#define __DRIVERS_INTERCONNECT_QCOM_QCS615_H
8
+
9
+
#define QCS615_MASTER_A1NOC_CFG 1
10
+
#define QCS615_MASTER_A1NOC_SNOC 2
11
+
#define QCS615_MASTER_ANOC_PCIE_SNOC 3
12
+
#define QCS615_MASTER_APPSS_PROC 4
13
+
#define QCS615_MASTER_BLSP_1 5
14
+
#define QCS615_MASTER_CAMNOC_HF0 6
15
+
#define QCS615_MASTER_CAMNOC_HF0_UNCOMP 7
16
+
#define QCS615_MASTER_CAMNOC_HF1 8
17
+
#define QCS615_MASTER_CAMNOC_HF1_UNCOMP 9
18
+
#define QCS615_MASTER_CAMNOC_SF 10
19
+
#define QCS615_MASTER_CAMNOC_SF_UNCOMP 11
20
+
#define QCS615_MASTER_CNOC_A2NOC 12
21
+
#define QCS615_MASTER_CNOC_DC_NOC 13
22
+
#define QCS615_MASTER_CNOC_MNOC_CFG 14
23
+
#define QCS615_MASTER_CRYPTO 15
24
+
#define QCS615_MASTER_EMAC_EVB 16
25
+
#define QCS615_MASTER_GEM_NOC_CFG 17
26
+
#define QCS615_MASTER_GEM_NOC_PCIE_SNOC 18
27
+
#define QCS615_MASTER_GEM_NOC_SNOC 19
28
+
#define QCS615_MASTER_GFX3D 20
29
+
#define QCS615_MASTER_GIC 21
30
+
#define QCS615_MASTER_GPU_TCU 22
31
+
#define QCS615_MASTER_IPA 23
32
+
#define QCS615_MASTER_IPA_CORE 24
33
+
#define QCS615_MASTER_LLCC 25
34
+
#define QCS615_MASTER_LPASS_ANOC 26
35
+
#define QCS615_MASTER_MDP0 27
36
+
#define QCS615_MASTER_MNOC_HF_MEM_NOC 28
37
+
#define QCS615_MASTER_MNOC_SF_MEM_NOC 29
38
+
#define QCS615_MASTER_PCIE 30
39
+
#define QCS615_MASTER_PIMEM 31
40
+
#define QCS615_MASTER_QDSS_BAM 32
41
+
#define QCS615_MASTER_QDSS_DAP 33
42
+
#define QCS615_MASTER_QDSS_ETR 34
43
+
#define QCS615_MASTER_QSPI 35
44
+
#define QCS615_MASTER_QUP_0 36
45
+
#define QCS615_MASTER_ROTATOR 37
46
+
#define QCS615_MASTER_SDCC_1 38
47
+
#define QCS615_MASTER_SDCC_2 39
48
+
#define QCS615_MASTER_SNOC_CFG 40
49
+
#define QCS615_MASTER_SNOC_CNOC 41
50
+
#define QCS615_MASTER_SNOC_GC_MEM_NOC 42
51
+
#define QCS615_MASTER_SNOC_SF_MEM_NOC 43
52
+
#define QCS615_MASTER_SPDM 44
53
+
#define QCS615_MASTER_SYS_TCU 45
54
+
#define QCS615_MASTER_UFS_MEM 46
55
+
#define QCS615_MASTER_USB2 47
56
+
#define QCS615_MASTER_USB3_0 48
57
+
#define QCS615_MASTER_VIDEO_P0 49
58
+
#define QCS615_MASTER_VIDEO_PROC 50
59
+
#define QCS615_SLAVE_A1NOC_CFG 51
60
+
#define QCS615_SLAVE_A1NOC_SNOC 52
61
+
#define QCS615_SLAVE_AHB2PHY_EAST 53
62
+
#define QCS615_SLAVE_AHB2PHY_WEST 54
63
+
#define QCS615_SLAVE_ANOC_PCIE_SNOC 55
64
+
#define QCS615_SLAVE_AOP 56
65
+
#define QCS615_SLAVE_AOSS 57
66
+
#define QCS615_SLAVE_APPSS 58
67
+
#define QCS615_SLAVE_CAMERA_CFG 59
68
+
#define QCS615_SLAVE_CAMNOC_UNCOMP 60
69
+
#define QCS615_SLAVE_CLK_CTL 61
70
+
#define QCS615_SLAVE_CNOC_A2NOC 62
71
+
#define QCS615_SLAVE_CNOC_DDRSS 63
72
+
#define QCS615_SLAVE_CNOC_MNOC_CFG 64
73
+
#define QCS615_SLAVE_CRYPTO_0_CFG 65
74
+
#define QCS615_SLAVE_DC_NOC_GEMNOC 66
75
+
#define QCS615_SLAVE_DISPLAY_CFG 67
76
+
#define QCS615_SLAVE_EBI1 68
77
+
#define QCS615_SLAVE_EMAC_AVB_CFG 69
78
+
#define QCS615_SLAVE_GEM_NOC_SNOC 70
79
+
#define QCS615_SLAVE_GFX3D_CFG 71
80
+
#define QCS615_SLAVE_GLM 72
81
+
#define QCS615_SLAVE_IMEM 73
82
+
#define QCS615_SLAVE_IMEM_CFG 74
83
+
#define QCS615_SLAVE_IPA_CFG 75
84
+
#define QCS615_SLAVE_IPA_CORE 76
85
+
#define QCS615_SLAVE_LLCC 77
86
+
#define QCS615_SLAVE_LLCC_CFG 78
87
+
#define QCS615_SLAVE_LPASS_SNOC 79
88
+
#define QCS615_SLAVE_MEM_NOC_PCIE_SNOC 80
89
+
#define QCS615_SLAVE_MNOC_HF_MEM_NOC 81
90
+
#define QCS615_SLAVE_MNOC_SF_MEM_NOC 82
91
+
#define QCS615_SLAVE_MSS_PROC_MS_MPU_CFG 83
92
+
#define QCS615_SLAVE_PCIE_0 84
93
+
#define QCS615_SLAVE_PCIE_CFG 85
94
+
#define QCS615_SLAVE_PIMEM 86
95
+
#define QCS615_SLAVE_PIMEM_CFG 87
96
+
#define QCS615_SLAVE_PRNG 88
97
+
#define QCS615_SLAVE_QDSS_CFG 89
98
+
#define QCS615_SLAVE_QDSS_STM 90
99
+
#define QCS615_SLAVE_QSPI 91
100
+
#define QCS615_SLAVE_QUP_0 92
101
+
#define QCS615_SLAVE_QUP_1 93
102
+
#define QCS615_SLAVE_RBCPR_CX_CFG 94
103
+
#define QCS615_SLAVE_RBCPR_MX_CFG 95
104
+
#define QCS615_SLAVE_SDCC_1 96
105
+
#define QCS615_SLAVE_SDCC_2 97
106
+
#define QCS615_SLAVE_SERVICE_A2NOC 98
107
+
#define QCS615_SLAVE_SERVICE_CNOC 99
108
+
#define QCS615_SLAVE_SERVICE_GEM_NOC 100
109
+
#define QCS615_SLAVE_SERVICE_MNOC 101
110
+
#define QCS615_SLAVE_SERVICE_SNOC 102
111
+
#define QCS615_SLAVE_SNOC_CFG 103
112
+
#define QCS615_SLAVE_SNOC_CNOC 104
113
+
#define QCS615_SLAVE_SNOC_GEM_NOC_SF 105
114
+
#define QCS615_SLAVE_SNOC_MEM_NOC_GC 106
115
+
#define QCS615_SLAVE_SPDM_WRAPPER 107
116
+
#define QCS615_SLAVE_TCSR 108
117
+
#define QCS615_SLAVE_TCU 109
118
+
#define QCS615_SLAVE_TLMM_EAST 110
119
+
#define QCS615_SLAVE_TLMM_SOUTH 111
120
+
#define QCS615_SLAVE_TLMM_WEST 112
121
+
#define QCS615_SLAVE_UFS_MEM_CFG 113
122
+
#define QCS615_SLAVE_USB2 114
123
+
#define QCS615_SLAVE_USB3 115
124
+
#define QCS615_SLAVE_VENUS_CFG 116
125
+
#define QCS615_SLAVE_VSENSE_CTRL_CFG 117
126
+
127
+
#endif
128
+
+2088
drivers/interconnect/qcom/qcs8300.c
+2088
drivers/interconnect/qcom/qcs8300.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*
5
+
*/
6
+
7
+
#include <linux/device.h>
8
+
#include <linux/interconnect.h>
9
+
#include <linux/interconnect-provider.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of_platform.h>
12
+
#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
13
+
14
+
#include "bcm-voter.h"
15
+
#include "icc-rpmh.h"
16
+
#include "qcs8300.h"
17
+
18
+
static struct qcom_icc_node qxm_qup3 = {
19
+
.name = "qxm_qup3",
20
+
.id = QCS8300_MASTER_QUP_3,
21
+
.channels = 1,
22
+
.buswidth = 8,
23
+
.num_links = 1,
24
+
.links = { QCS8300_SLAVE_A1NOC_SNOC },
25
+
};
26
+
27
+
static struct qcom_icc_node xm_emac_0 = {
28
+
.name = "xm_emac_0",
29
+
.id = QCS8300_MASTER_EMAC,
30
+
.channels = 1,
31
+
.buswidth = 8,
32
+
.num_links = 1,
33
+
.links = { QCS8300_SLAVE_A1NOC_SNOC },
34
+
};
35
+
36
+
static struct qcom_icc_node xm_sdc1 = {
37
+
.name = "xm_sdc1",
38
+
.id = QCS8300_MASTER_SDC,
39
+
.channels = 1,
40
+
.buswidth = 8,
41
+
.num_links = 1,
42
+
.links = { QCS8300_SLAVE_A1NOC_SNOC },
43
+
};
44
+
45
+
static struct qcom_icc_node xm_ufs_mem = {
46
+
.name = "xm_ufs_mem",
47
+
.id = QCS8300_MASTER_UFS_MEM,
48
+
.channels = 1,
49
+
.buswidth = 8,
50
+
.num_links = 1,
51
+
.links = { QCS8300_SLAVE_A1NOC_SNOC },
52
+
};
53
+
54
+
static struct qcom_icc_node xm_usb2_2 = {
55
+
.name = "xm_usb2_2",
56
+
.id = QCS8300_MASTER_USB2,
57
+
.channels = 1,
58
+
.buswidth = 8,
59
+
.num_links = 1,
60
+
.links = { QCS8300_SLAVE_A1NOC_SNOC },
61
+
};
62
+
63
+
static struct qcom_icc_node xm_usb3_0 = {
64
+
.name = "xm_usb3_0",
65
+
.id = QCS8300_MASTER_USB3_0,
66
+
.channels = 1,
67
+
.buswidth = 8,
68
+
.num_links = 1,
69
+
.links = { QCS8300_SLAVE_A1NOC_SNOC },
70
+
};
71
+
72
+
static struct qcom_icc_node qhm_qdss_bam = {
73
+
.name = "qhm_qdss_bam",
74
+
.id = QCS8300_MASTER_QDSS_BAM,
75
+
.channels = 1,
76
+
.buswidth = 4,
77
+
.num_links = 1,
78
+
.links = { QCS8300_SLAVE_A2NOC_SNOC },
79
+
};
80
+
81
+
static struct qcom_icc_node qhm_qup0 = {
82
+
.name = "qhm_qup0",
83
+
.id = QCS8300_MASTER_QUP_0,
84
+
.channels = 1,
85
+
.buswidth = 4,
86
+
.num_links = 1,
87
+
.links = { QCS8300_SLAVE_A2NOC_SNOC },
88
+
};
89
+
90
+
static struct qcom_icc_node qhm_qup1 = {
91
+
.name = "qhm_qup1",
92
+
.id = QCS8300_MASTER_QUP_1,
93
+
.channels = 1,
94
+
.buswidth = 4,
95
+
.num_links = 1,
96
+
.links = { QCS8300_SLAVE_A2NOC_SNOC },
97
+
};
98
+
99
+
static struct qcom_icc_node qnm_cnoc_datapath = {
100
+
.name = "qnm_cnoc_datapath",
101
+
.id = QCS8300_MASTER_CNOC_A2NOC,
102
+
.channels = 1,
103
+
.buswidth = 8,
104
+
.num_links = 1,
105
+
.links = { QCS8300_SLAVE_A2NOC_SNOC },
106
+
};
107
+
108
+
static struct qcom_icc_node qxm_crypto_0 = {
109
+
.name = "qxm_crypto_0",
110
+
.id = QCS8300_MASTER_CRYPTO_CORE0,
111
+
.channels = 1,
112
+
.buswidth = 8,
113
+
.num_links = 1,
114
+
.links = { QCS8300_SLAVE_A2NOC_SNOC },
115
+
};
116
+
117
+
static struct qcom_icc_node qxm_crypto_1 = {
118
+
.name = "qxm_crypto_1",
119
+
.id = QCS8300_MASTER_CRYPTO_CORE1,
120
+
.channels = 1,
121
+
.buswidth = 8,
122
+
.num_links = 1,
123
+
.links = { QCS8300_SLAVE_A2NOC_SNOC },
124
+
};
125
+
126
+
static struct qcom_icc_node qxm_ipa = {
127
+
.name = "qxm_ipa",
128
+
.id = QCS8300_MASTER_IPA,
129
+
.channels = 1,
130
+
.buswidth = 8,
131
+
.num_links = 1,
132
+
.links = { QCS8300_SLAVE_A2NOC_SNOC },
133
+
};
134
+
135
+
static struct qcom_icc_node xm_qdss_etr_0 = {
136
+
.name = "xm_qdss_etr_0",
137
+
.id = QCS8300_MASTER_QDSS_ETR_0,
138
+
.channels = 1,
139
+
.buswidth = 8,
140
+
.num_links = 1,
141
+
.links = { QCS8300_SLAVE_A2NOC_SNOC },
142
+
};
143
+
144
+
static struct qcom_icc_node xm_qdss_etr_1 = {
145
+
.name = "xm_qdss_etr_1",
146
+
.id = QCS8300_MASTER_QDSS_ETR_1,
147
+
.channels = 1,
148
+
.buswidth = 8,
149
+
.num_links = 1,
150
+
.links = { QCS8300_SLAVE_A2NOC_SNOC },
151
+
};
152
+
153
+
static struct qcom_icc_node qup0_core_master = {
154
+
.name = "qup0_core_master",
155
+
.id = QCS8300_MASTER_QUP_CORE_0,
156
+
.channels = 1,
157
+
.buswidth = 4,
158
+
.num_links = 1,
159
+
.links = { QCS8300_SLAVE_QUP_CORE_0 },
160
+
};
161
+
162
+
static struct qcom_icc_node qup1_core_master = {
163
+
.name = "qup1_core_master",
164
+
.id = QCS8300_MASTER_QUP_CORE_1,
165
+
.channels = 1,
166
+
.buswidth = 4,
167
+
.num_links = 1,
168
+
.links = { QCS8300_SLAVE_QUP_CORE_1 },
169
+
};
170
+
171
+
static struct qcom_icc_node qup3_core_master = {
172
+
.name = "qup3_core_master",
173
+
.id = QCS8300_MASTER_QUP_CORE_3,
174
+
.channels = 1,
175
+
.buswidth = 4,
176
+
.num_links = 1,
177
+
.links = { QCS8300_SLAVE_QUP_CORE_3 },
178
+
};
179
+
180
+
static struct qcom_icc_node qnm_gemnoc_cnoc = {
181
+
.name = "qnm_gemnoc_cnoc",
182
+
.id = QCS8300_MASTER_GEM_NOC_CNOC,
183
+
.channels = 1,
184
+
.buswidth = 16,
185
+
.num_links = 71,
186
+
.links = { QCS8300_SLAVE_AHB2PHY_2, QCS8300_SLAVE_AHB2PHY_3,
187
+
QCS8300_SLAVE_ANOC_THROTTLE_CFG, QCS8300_SLAVE_AOSS,
188
+
QCS8300_SLAVE_APPSS, QCS8300_SLAVE_BOOT_ROM,
189
+
QCS8300_SLAVE_CAMERA_CFG, QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG,
190
+
QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG, QCS8300_SLAVE_CLK_CTL,
191
+
QCS8300_SLAVE_CDSP_CFG, QCS8300_SLAVE_RBCPR_CX_CFG,
192
+
QCS8300_SLAVE_RBCPR_MMCX_CFG, QCS8300_SLAVE_RBCPR_MX_CFG,
193
+
QCS8300_SLAVE_CPR_NSPCX, QCS8300_SLAVE_CPR_NSPHMX,
194
+
QCS8300_SLAVE_CRYPTO_0_CFG, QCS8300_SLAVE_CX_RDPM,
195
+
QCS8300_SLAVE_DISPLAY_CFG, QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG,
196
+
QCS8300_SLAVE_EMAC_CFG, QCS8300_SLAVE_GP_DSP0_CFG,
197
+
QCS8300_SLAVE_GPDSP0_THROTTLE_CFG, QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG,
198
+
QCS8300_SLAVE_GFX3D_CFG, QCS8300_SLAVE_HWKM,
199
+
QCS8300_SLAVE_IMEM_CFG, QCS8300_SLAVE_IPA_CFG,
200
+
QCS8300_SLAVE_IPC_ROUTER_CFG, QCS8300_SLAVE_LPASS,
201
+
QCS8300_SLAVE_LPASS_THROTTLE_CFG, QCS8300_SLAVE_MX_RDPM,
202
+
QCS8300_SLAVE_MXC_RDPM, QCS8300_SLAVE_PCIE_0_CFG,
203
+
QCS8300_SLAVE_PCIE_1_CFG, QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG,
204
+
QCS8300_SLAVE_PCIE_THROTTLE_CFG, QCS8300_SLAVE_PDM,
205
+
QCS8300_SLAVE_PIMEM_CFG, QCS8300_SLAVE_PKA_WRAPPER_CFG,
206
+
QCS8300_SLAVE_QDSS_CFG, QCS8300_SLAVE_QM_CFG,
207
+
QCS8300_SLAVE_QM_MPU_CFG, QCS8300_SLAVE_QUP_0,
208
+
QCS8300_SLAVE_QUP_1, QCS8300_SLAVE_QUP_3,
209
+
QCS8300_SLAVE_SAIL_THROTTLE_CFG, QCS8300_SLAVE_SDC1,
210
+
QCS8300_SLAVE_SECURITY, QCS8300_SLAVE_SNOC_THROTTLE_CFG,
211
+
QCS8300_SLAVE_TCSR, QCS8300_SLAVE_TLMM,
212
+
QCS8300_SLAVE_TSC_CFG, QCS8300_SLAVE_UFS_MEM_CFG,
213
+
QCS8300_SLAVE_USB2, QCS8300_SLAVE_USB3_0,
214
+
QCS8300_SLAVE_VENUS_CFG, QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG,
215
+
QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
216
+
QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
217
+
QCS8300_SLAVE_DDRSS_CFG, QCS8300_SLAVE_GPDSP_NOC_CFG,
218
+
QCS8300_SLAVE_CNOC_MNOC_HF_CFG, QCS8300_SLAVE_CNOC_MNOC_SF_CFG,
219
+
QCS8300_SLAVE_PCIE_ANOC_CFG, QCS8300_SLAVE_SNOC_CFG,
220
+
QCS8300_SLAVE_BOOT_IMEM, QCS8300_SLAVE_IMEM,
221
+
QCS8300_SLAVE_PIMEM, QCS8300_SLAVE_QDSS_STM,
222
+
QCS8300_SLAVE_TCU },
223
+
};
224
+
225
+
static struct qcom_icc_node qnm_gemnoc_pcie = {
226
+
.name = "qnm_gemnoc_pcie",
227
+
.id = QCS8300_MASTER_GEM_NOC_PCIE_SNOC,
228
+
.channels = 1,
229
+
.buswidth = 16,
230
+
.num_links = 2,
231
+
.links = { QCS8300_SLAVE_PCIE_0, QCS8300_SLAVE_PCIE_1 },
232
+
};
233
+
234
+
static struct qcom_icc_node qnm_cnoc_dc_noc = {
235
+
.name = "qnm_cnoc_dc_noc",
236
+
.id = QCS8300_MASTER_CNOC_DC_NOC,
237
+
.channels = 1,
238
+
.buswidth = 4,
239
+
.num_links = 2,
240
+
.links = { QCS8300_SLAVE_LLCC_CFG, QCS8300_SLAVE_GEM_NOC_CFG },
241
+
};
242
+
243
+
static struct qcom_icc_node alm_gpu_tcu = {
244
+
.name = "alm_gpu_tcu",
245
+
.id = QCS8300_MASTER_GPU_TCU,
246
+
.channels = 1,
247
+
.buswidth = 8,
248
+
.num_links = 2,
249
+
.links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
250
+
};
251
+
252
+
static struct qcom_icc_node alm_pcie_tcu = {
253
+
.name = "alm_pcie_tcu",
254
+
.id = QCS8300_MASTER_PCIE_TCU,
255
+
.channels = 1,
256
+
.buswidth = 8,
257
+
.num_links = 2,
258
+
.links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
259
+
};
260
+
261
+
static struct qcom_icc_node alm_sys_tcu = {
262
+
.name = "alm_sys_tcu",
263
+
.id = QCS8300_MASTER_SYS_TCU,
264
+
.channels = 1,
265
+
.buswidth = 8,
266
+
.num_links = 2,
267
+
.links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
268
+
};
269
+
270
+
static struct qcom_icc_node chm_apps = {
271
+
.name = "chm_apps",
272
+
.id = QCS8300_MASTER_APPSS_PROC,
273
+
.channels = 4,
274
+
.buswidth = 32,
275
+
.num_links = 3,
276
+
.links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC,
277
+
QCS8300_SLAVE_GEM_NOC_PCIE_CNOC },
278
+
};
279
+
280
+
static struct qcom_icc_node qnm_cmpnoc0 = {
281
+
.name = "qnm_cmpnoc0",
282
+
.id = QCS8300_MASTER_COMPUTE_NOC,
283
+
.channels = 2,
284
+
.buswidth = 32,
285
+
.num_links = 2,
286
+
.links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
287
+
};
288
+
289
+
static struct qcom_icc_node qnm_gemnoc_cfg = {
290
+
.name = "qnm_gemnoc_cfg",
291
+
.id = QCS8300_MASTER_GEM_NOC_CFG,
292
+
.channels = 1,
293
+
.buswidth = 4,
294
+
.num_links = 4,
295
+
.links = { QCS8300_SLAVE_SERVICE_GEM_NOC_1, QCS8300_SLAVE_SERVICE_GEM_NOC_2,
296
+
QCS8300_SLAVE_SERVICE_GEM_NOC, QCS8300_SLAVE_SERVICE_GEM_NOC2 },
297
+
};
298
+
299
+
static struct qcom_icc_node qnm_gpdsp_sail = {
300
+
.name = "qnm_gpdsp_sail",
301
+
.id = QCS8300_MASTER_GPDSP_SAIL,
302
+
.channels = 1,
303
+
.buswidth = 16,
304
+
.num_links = 2,
305
+
.links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
306
+
};
307
+
308
+
static struct qcom_icc_node qnm_gpu = {
309
+
.name = "qnm_gpu",
310
+
.id = QCS8300_MASTER_GFX3D,
311
+
.channels = 2,
312
+
.buswidth = 32,
313
+
.num_links = 2,
314
+
.links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
315
+
};
316
+
317
+
static struct qcom_icc_node qnm_mnoc_hf = {
318
+
.name = "qnm_mnoc_hf",
319
+
.id = QCS8300_MASTER_MNOC_HF_MEM_NOC,
320
+
.channels = 2,
321
+
.buswidth = 32,
322
+
.num_links = 2,
323
+
.links = { QCS8300_SLAVE_LLCC, QCS8300_SLAVE_GEM_NOC_PCIE_CNOC },
324
+
};
325
+
326
+
static struct qcom_icc_node qnm_mnoc_sf = {
327
+
.name = "qnm_mnoc_sf",
328
+
.id = QCS8300_MASTER_MNOC_SF_MEM_NOC,
329
+
.channels = 2,
330
+
.buswidth = 32,
331
+
.num_links = 3,
332
+
.links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC,
333
+
QCS8300_SLAVE_GEM_NOC_PCIE_CNOC },
334
+
};
335
+
336
+
static struct qcom_icc_node qnm_pcie = {
337
+
.name = "qnm_pcie",
338
+
.id = QCS8300_MASTER_ANOC_PCIE_GEM_NOC,
339
+
.channels = 1,
340
+
.buswidth = 32,
341
+
.num_links = 2,
342
+
.links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC },
343
+
};
344
+
345
+
static struct qcom_icc_node qnm_snoc_gc = {
346
+
.name = "qnm_snoc_gc",
347
+
.id = QCS8300_MASTER_SNOC_GC_MEM_NOC,
348
+
.channels = 1,
349
+
.buswidth = 8,
350
+
.num_links = 1,
351
+
.links = { QCS8300_SLAVE_LLCC },
352
+
};
353
+
354
+
static struct qcom_icc_node qnm_snoc_sf = {
355
+
.name = "qnm_snoc_sf",
356
+
.id = QCS8300_MASTER_SNOC_SF_MEM_NOC,
357
+
.channels = 1,
358
+
.buswidth = 16,
359
+
.num_links = 3,
360
+
.links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC,
361
+
QCS8300_SLAVE_GEM_NOC_PCIE_CNOC },
362
+
};
363
+
364
+
static struct qcom_icc_node qnm_sailss_md0 = {
365
+
.name = "qnm_sailss_md0",
366
+
.id = QCS8300_MASTER_SAILSS_MD0,
367
+
.channels = 1,
368
+
.buswidth = 16,
369
+
.num_links = 1,
370
+
.links = { QCS8300_SLAVE_GP_DSP_SAIL_NOC },
371
+
};
372
+
373
+
static struct qcom_icc_node qxm_dsp0 = {
374
+
.name = "qxm_dsp0",
375
+
.id = QCS8300_MASTER_DSP0,
376
+
.channels = 1,
377
+
.buswidth = 16,
378
+
.num_links = 1,
379
+
.links = { QCS8300_SLAVE_GP_DSP_SAIL_NOC },
380
+
};
381
+
382
+
static struct qcom_icc_node qhm_config_noc = {
383
+
.name = "qhm_config_noc",
384
+
.id = QCS8300_MASTER_CNOC_LPASS_AG_NOC,
385
+
.channels = 1,
386
+
.buswidth = 4,
387
+
.num_links = 6,
388
+
.links = { QCS8300_SLAVE_LPASS_CORE_CFG, QCS8300_SLAVE_LPASS_LPI_CFG,
389
+
QCS8300_SLAVE_LPASS_MPU_CFG, QCS8300_SLAVE_LPASS_TOP_CFG,
390
+
QCS8300_SLAVE_SERVICES_LPASS_AML_NOC, QCS8300_SLAVE_SERVICE_LPASS_AG_NOC },
391
+
};
392
+
393
+
static struct qcom_icc_node qxm_lpass_dsp = {
394
+
.name = "qxm_lpass_dsp",
395
+
.id = QCS8300_MASTER_LPASS_PROC,
396
+
.channels = 1,
397
+
.buswidth = 8,
398
+
.num_links = 4,
399
+
.links = { QCS8300_SLAVE_LPASS_TOP_CFG, QCS8300_SLAVE_LPASS_SNOC,
400
+
QCS8300_SLAVE_SERVICES_LPASS_AML_NOC, QCS8300_SLAVE_SERVICE_LPASS_AG_NOC },
401
+
};
402
+
403
+
static struct qcom_icc_node llcc_mc = {
404
+
.name = "llcc_mc",
405
+
.id = QCS8300_MASTER_LLCC,
406
+
.channels = 8,
407
+
.buswidth = 4,
408
+
.num_links = 1,
409
+
.links = { QCS8300_SLAVE_EBI1 },
410
+
};
411
+
412
+
static struct qcom_icc_node qnm_camnoc_hf = {
413
+
.name = "qnm_camnoc_hf",
414
+
.id = QCS8300_MASTER_CAMNOC_HF,
415
+
.channels = 1,
416
+
.buswidth = 32,
417
+
.num_links = 1,
418
+
.links = { QCS8300_SLAVE_MNOC_HF_MEM_NOC },
419
+
};
420
+
421
+
static struct qcom_icc_node qnm_camnoc_icp = {
422
+
.name = "qnm_camnoc_icp",
423
+
.id = QCS8300_MASTER_CAMNOC_ICP,
424
+
.channels = 1,
425
+
.buswidth = 8,
426
+
.num_links = 1,
427
+
.links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
428
+
};
429
+
430
+
static struct qcom_icc_node qnm_camnoc_sf = {
431
+
.name = "qnm_camnoc_sf",
432
+
.id = QCS8300_MASTER_CAMNOC_SF,
433
+
.channels = 1,
434
+
.buswidth = 32,
435
+
.num_links = 1,
436
+
.links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
437
+
};
438
+
439
+
static struct qcom_icc_node qnm_mdp0_0 = {
440
+
.name = "qnm_mdp0_0",
441
+
.id = QCS8300_MASTER_MDP0,
442
+
.channels = 1,
443
+
.buswidth = 32,
444
+
.num_links = 1,
445
+
.links = { QCS8300_SLAVE_MNOC_HF_MEM_NOC },
446
+
};
447
+
448
+
static struct qcom_icc_node qnm_mdp0_1 = {
449
+
.name = "qnm_mdp0_1",
450
+
.id = QCS8300_MASTER_MDP1,
451
+
.channels = 1,
452
+
.buswidth = 32,
453
+
.num_links = 1,
454
+
.links = { QCS8300_SLAVE_MNOC_HF_MEM_NOC },
455
+
};
456
+
457
+
static struct qcom_icc_node qnm_mnoc_hf_cfg = {
458
+
.name = "qnm_mnoc_hf_cfg",
459
+
.id = QCS8300_MASTER_CNOC_MNOC_HF_CFG,
460
+
.channels = 1,
461
+
.buswidth = 4,
462
+
.num_links = 1,
463
+
.links = { QCS8300_SLAVE_SERVICE_MNOC_HF },
464
+
};
465
+
466
+
static struct qcom_icc_node qnm_mnoc_sf_cfg = {
467
+
.name = "qnm_mnoc_sf_cfg",
468
+
.id = QCS8300_MASTER_CNOC_MNOC_SF_CFG,
469
+
.channels = 1,
470
+
.buswidth = 4,
471
+
.num_links = 1,
472
+
.links = { QCS8300_SLAVE_SERVICE_MNOC_SF },
473
+
};
474
+
475
+
static struct qcom_icc_node qnm_video0 = {
476
+
.name = "qnm_video0",
477
+
.id = QCS8300_MASTER_VIDEO_P0,
478
+
.channels = 1,
479
+
.buswidth = 32,
480
+
.num_links = 1,
481
+
.links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
482
+
};
483
+
484
+
static struct qcom_icc_node qnm_video_cvp = {
485
+
.name = "qnm_video_cvp",
486
+
.id = QCS8300_MASTER_VIDEO_PROC,
487
+
.channels = 1,
488
+
.buswidth = 32,
489
+
.num_links = 1,
490
+
.links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
491
+
};
492
+
493
+
static struct qcom_icc_node qnm_video_v_cpu = {
494
+
.name = "qnm_video_v_cpu",
495
+
.id = QCS8300_MASTER_VIDEO_V_PROC,
496
+
.channels = 1,
497
+
.buswidth = 8,
498
+
.num_links = 1,
499
+
.links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC },
500
+
};
501
+
502
+
static struct qcom_icc_node qhm_nsp_noc_config = {
503
+
.name = "qhm_nsp_noc_config",
504
+
.id = QCS8300_MASTER_CDSP_NOC_CFG,
505
+
.channels = 1,
506
+
.buswidth = 4,
507
+
.num_links = 1,
508
+
.links = { QCS8300_SLAVE_SERVICE_NSP_NOC },
509
+
};
510
+
511
+
static struct qcom_icc_node qxm_nsp = {
512
+
.name = "qxm_nsp",
513
+
.id = QCS8300_MASTER_CDSP_PROC,
514
+
.channels = 2,
515
+
.buswidth = 32,
516
+
.num_links = 2,
517
+
.links = { QCS8300_SLAVE_HCP_A, QCS8300_SLAVE_CDSP_MEM_NOC },
518
+
};
519
+
520
+
static struct qcom_icc_node xm_pcie3_0 = {
521
+
.name = "xm_pcie3_0",
522
+
.id = QCS8300_MASTER_PCIE_0,
523
+
.channels = 1,
524
+
.buswidth = 16,
525
+
.num_links = 1,
526
+
.links = { QCS8300_SLAVE_ANOC_PCIE_GEM_NOC },
527
+
};
528
+
529
+
static struct qcom_icc_node xm_pcie3_1 = {
530
+
.name = "xm_pcie3_1",
531
+
.id = QCS8300_MASTER_PCIE_1,
532
+
.channels = 1,
533
+
.buswidth = 32,
534
+
.num_links = 1,
535
+
.links = { QCS8300_SLAVE_ANOC_PCIE_GEM_NOC },
536
+
};
537
+
538
+
static struct qcom_icc_node qhm_gic = {
539
+
.name = "qhm_gic",
540
+
.id = QCS8300_MASTER_GIC_AHB,
541
+
.channels = 1,
542
+
.buswidth = 4,
543
+
.num_links = 1,
544
+
.links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
545
+
};
546
+
547
+
static struct qcom_icc_node qnm_aggre1_noc = {
548
+
.name = "qnm_aggre1_noc",
549
+
.id = QCS8300_MASTER_A1NOC_SNOC,
550
+
.channels = 1,
551
+
.buswidth = 32,
552
+
.num_links = 1,
553
+
.links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
554
+
};
555
+
556
+
static struct qcom_icc_node qnm_aggre2_noc = {
557
+
.name = "qnm_aggre2_noc",
558
+
.id = QCS8300_MASTER_A2NOC_SNOC,
559
+
.channels = 1,
560
+
.buswidth = 16,
561
+
.num_links = 1,
562
+
.links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
563
+
};
564
+
565
+
static struct qcom_icc_node qnm_lpass_noc = {
566
+
.name = "qnm_lpass_noc",
567
+
.id = QCS8300_MASTER_LPASS_ANOC,
568
+
.channels = 1,
569
+
.buswidth = 16,
570
+
.num_links = 1,
571
+
.links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
572
+
};
573
+
574
+
static struct qcom_icc_node qnm_snoc_cfg = {
575
+
.name = "qnm_snoc_cfg",
576
+
.id = QCS8300_MASTER_SNOC_CFG,
577
+
.channels = 1,
578
+
.buswidth = 4,
579
+
.num_links = 1,
580
+
.links = { QCS8300_SLAVE_SERVICE_SNOC },
581
+
};
582
+
583
+
static struct qcom_icc_node qxm_pimem = {
584
+
.name = "qxm_pimem",
585
+
.id = QCS8300_MASTER_PIMEM,
586
+
.channels = 1,
587
+
.buswidth = 8,
588
+
.num_links = 1,
589
+
.links = { QCS8300_SLAVE_SNOC_GEM_NOC_GC },
590
+
};
591
+
592
+
static struct qcom_icc_node xm_gic = {
593
+
.name = "xm_gic",
594
+
.id = QCS8300_MASTER_GIC,
595
+
.channels = 1,
596
+
.buswidth = 8,
597
+
.num_links = 1,
598
+
.links = { QCS8300_SLAVE_SNOC_GEM_NOC_GC },
599
+
};
600
+
601
+
static struct qcom_icc_node qns_a1noc_snoc = {
602
+
.name = "qns_a1noc_snoc",
603
+
.id = QCS8300_SLAVE_A1NOC_SNOC,
604
+
.channels = 1,
605
+
.buswidth = 32,
606
+
.num_links = 1,
607
+
.links = { QCS8300_MASTER_A1NOC_SNOC },
608
+
};
609
+
610
+
static struct qcom_icc_node qns_a2noc_snoc = {
611
+
.name = "qns_a2noc_snoc",
612
+
.id = QCS8300_SLAVE_A2NOC_SNOC,
613
+
.channels = 1,
614
+
.buswidth = 16,
615
+
.num_links = 1,
616
+
.links = { QCS8300_MASTER_A2NOC_SNOC },
617
+
};
618
+
619
+
static struct qcom_icc_node qup0_core_slave = {
620
+
.name = "qup0_core_slave",
621
+
.id = QCS8300_SLAVE_QUP_CORE_0,
622
+
.channels = 1,
623
+
.buswidth = 4,
624
+
.num_links = 0,
625
+
};
626
+
627
+
static struct qcom_icc_node qup1_core_slave = {
628
+
.name = "qup1_core_slave",
629
+
.id = QCS8300_SLAVE_QUP_CORE_1,
630
+
.channels = 1,
631
+
.buswidth = 4,
632
+
.num_links = 0,
633
+
};
634
+
635
+
static struct qcom_icc_node qup3_core_slave = {
636
+
.name = "qup3_core_slave",
637
+
.id = QCS8300_SLAVE_QUP_CORE_3,
638
+
.channels = 1,
639
+
.buswidth = 4,
640
+
.num_links = 0,
641
+
};
642
+
643
+
static struct qcom_icc_node qhs_ahb2phy2 = {
644
+
.name = "qhs_ahb2phy2",
645
+
.id = QCS8300_SLAVE_AHB2PHY_2,
646
+
.channels = 1,
647
+
.buswidth = 4,
648
+
.num_links = 0,
649
+
};
650
+
651
+
static struct qcom_icc_node qhs_ahb2phy3 = {
652
+
.name = "qhs_ahb2phy3",
653
+
.id = QCS8300_SLAVE_AHB2PHY_3,
654
+
.channels = 1,
655
+
.buswidth = 4,
656
+
.num_links = 0,
657
+
};
658
+
659
+
static struct qcom_icc_node qhs_anoc_throttle_cfg = {
660
+
.name = "qhs_anoc_throttle_cfg",
661
+
.id = QCS8300_SLAVE_ANOC_THROTTLE_CFG,
662
+
.channels = 1,
663
+
.buswidth = 4,
664
+
.num_links = 0,
665
+
};
666
+
667
+
static struct qcom_icc_node qhs_aoss = {
668
+
.name = "qhs_aoss",
669
+
.id = QCS8300_SLAVE_AOSS,
670
+
.channels = 1,
671
+
.buswidth = 4,
672
+
.num_links = 0,
673
+
};
674
+
675
+
static struct qcom_icc_node qhs_apss = {
676
+
.name = "qhs_apss",
677
+
.id = QCS8300_SLAVE_APPSS,
678
+
.channels = 1,
679
+
.buswidth = 8,
680
+
.num_links = 0,
681
+
};
682
+
683
+
static struct qcom_icc_node qhs_boot_rom = {
684
+
.name = "qhs_boot_rom",
685
+
.id = QCS8300_SLAVE_BOOT_ROM,
686
+
.channels = 1,
687
+
.buswidth = 4,
688
+
.num_links = 0,
689
+
};
690
+
691
+
static struct qcom_icc_node qhs_camera_cfg = {
692
+
.name = "qhs_camera_cfg",
693
+
.id = QCS8300_SLAVE_CAMERA_CFG,
694
+
.channels = 1,
695
+
.buswidth = 4,
696
+
.num_links = 0,
697
+
};
698
+
699
+
static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
700
+
.name = "qhs_camera_nrt_throttle_cfg",
701
+
.id = QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG,
702
+
.channels = 1,
703
+
.buswidth = 4,
704
+
.num_links = 0,
705
+
};
706
+
707
+
static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
708
+
.name = "qhs_camera_rt_throttle_cfg",
709
+
.id = QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG,
710
+
.channels = 1,
711
+
.buswidth = 4,
712
+
.num_links = 0,
713
+
};
714
+
715
+
static struct qcom_icc_node qhs_clk_ctl = {
716
+
.name = "qhs_clk_ctl",
717
+
.id = QCS8300_SLAVE_CLK_CTL,
718
+
.channels = 1,
719
+
.buswidth = 4,
720
+
.num_links = 0,
721
+
};
722
+
723
+
static struct qcom_icc_node qhs_compute0_cfg = {
724
+
.name = "qhs_compute0_cfg",
725
+
.id = QCS8300_SLAVE_CDSP_CFG,
726
+
.channels = 1,
727
+
.buswidth = 4,
728
+
.num_links = 1,
729
+
.links = { QCS8300_MASTER_CDSP_NOC_CFG },
730
+
};
731
+
732
+
static struct qcom_icc_node qhs_cpr_cx = {
733
+
.name = "qhs_cpr_cx",
734
+
.id = QCS8300_SLAVE_RBCPR_CX_CFG,
735
+
.channels = 1,
736
+
.buswidth = 4,
737
+
.num_links = 0,
738
+
};
739
+
740
+
static struct qcom_icc_node qhs_cpr_mmcx = {
741
+
.name = "qhs_cpr_mmcx",
742
+
.id = QCS8300_SLAVE_RBCPR_MMCX_CFG,
743
+
.channels = 1,
744
+
.buswidth = 4,
745
+
.num_links = 0,
746
+
};
747
+
748
+
static struct qcom_icc_node qhs_cpr_mx = {
749
+
.name = "qhs_cpr_mx",
750
+
.id = QCS8300_SLAVE_RBCPR_MX_CFG,
751
+
.channels = 1,
752
+
.buswidth = 4,
753
+
.num_links = 0,
754
+
};
755
+
756
+
static struct qcom_icc_node qhs_cpr_nspcx = {
757
+
.name = "qhs_cpr_nspcx",
758
+
.id = QCS8300_SLAVE_CPR_NSPCX,
759
+
.channels = 1,
760
+
.buswidth = 4,
761
+
.num_links = 0,
762
+
};
763
+
764
+
static struct qcom_icc_node qhs_cpr_nsphmx = {
765
+
.name = "qhs_cpr_nsphmx",
766
+
.id = QCS8300_SLAVE_CPR_NSPHMX,
767
+
.channels = 1,
768
+
.buswidth = 4,
769
+
.num_links = 0,
770
+
};
771
+
772
+
static struct qcom_icc_node qhs_crypto0_cfg = {
773
+
.name = "qhs_crypto0_cfg",
774
+
.id = QCS8300_SLAVE_CRYPTO_0_CFG,
775
+
.channels = 1,
776
+
.buswidth = 4,
777
+
.num_links = 0,
778
+
};
779
+
780
+
static struct qcom_icc_node qhs_cx_rdpm = {
781
+
.name = "qhs_cx_rdpm",
782
+
.id = QCS8300_SLAVE_CX_RDPM,
783
+
.channels = 1,
784
+
.buswidth = 4,
785
+
.num_links = 0,
786
+
};
787
+
788
+
static struct qcom_icc_node qhs_display0_cfg = {
789
+
.name = "qhs_display0_cfg",
790
+
.id = QCS8300_SLAVE_DISPLAY_CFG,
791
+
.channels = 1,
792
+
.buswidth = 4,
793
+
.num_links = 0,
794
+
};
795
+
796
+
static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
797
+
.name = "qhs_display0_rt_throttle_cfg",
798
+
.id = QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG,
799
+
.channels = 1,
800
+
.buswidth = 4,
801
+
.num_links = 0,
802
+
};
803
+
804
+
static struct qcom_icc_node qhs_emac0_cfg = {
805
+
.name = "qhs_emac0_cfg",
806
+
.id = QCS8300_SLAVE_EMAC_CFG,
807
+
.channels = 1,
808
+
.buswidth = 4,
809
+
.num_links = 0,
810
+
};
811
+
812
+
static struct qcom_icc_node qhs_gp_dsp0_cfg = {
813
+
.name = "qhs_gp_dsp0_cfg",
814
+
.id = QCS8300_SLAVE_GP_DSP0_CFG,
815
+
.channels = 1,
816
+
.buswidth = 4,
817
+
.num_links = 0,
818
+
};
819
+
820
+
static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
821
+
.name = "qhs_gpdsp0_throttle_cfg",
822
+
.id = QCS8300_SLAVE_GPDSP0_THROTTLE_CFG,
823
+
.channels = 1,
824
+
.buswidth = 4,
825
+
.num_links = 0,
826
+
};
827
+
828
+
static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
829
+
.name = "qhs_gpu_tcu_throttle_cfg",
830
+
.id = QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG,
831
+
.channels = 1,
832
+
.buswidth = 4,
833
+
.num_links = 0,
834
+
};
835
+
836
+
static struct qcom_icc_node qhs_gpuss_cfg = {
837
+
.name = "qhs_gpuss_cfg",
838
+
.id = QCS8300_SLAVE_GFX3D_CFG,
839
+
.channels = 1,
840
+
.buswidth = 8,
841
+
.num_links = 0,
842
+
};
843
+
844
+
static struct qcom_icc_node qhs_hwkm = {
845
+
.name = "qhs_hwkm",
846
+
.id = QCS8300_SLAVE_HWKM,
847
+
.channels = 1,
848
+
.buswidth = 4,
849
+
.num_links = 0,
850
+
};
851
+
852
+
static struct qcom_icc_node qhs_imem_cfg = {
853
+
.name = "qhs_imem_cfg",
854
+
.id = QCS8300_SLAVE_IMEM_CFG,
855
+
.channels = 1,
856
+
.buswidth = 4,
857
+
.num_links = 0,
858
+
};
859
+
860
+
static struct qcom_icc_node qhs_ipa = {
861
+
.name = "qhs_ipa",
862
+
.id = QCS8300_SLAVE_IPA_CFG,
863
+
.channels = 1,
864
+
.buswidth = 4,
865
+
.num_links = 0,
866
+
};
867
+
868
+
static struct qcom_icc_node qhs_ipc_router = {
869
+
.name = "qhs_ipc_router",
870
+
.id = QCS8300_SLAVE_IPC_ROUTER_CFG,
871
+
.channels = 1,
872
+
.buswidth = 4,
873
+
.num_links = 0,
874
+
};
875
+
876
+
static struct qcom_icc_node qhs_lpass_cfg = {
877
+
.name = "qhs_lpass_cfg",
878
+
.id = QCS8300_SLAVE_LPASS,
879
+
.channels = 1,
880
+
.buswidth = 4,
881
+
.num_links = 1,
882
+
.links = { QCS8300_MASTER_CNOC_LPASS_AG_NOC },
883
+
};
884
+
885
+
static struct qcom_icc_node qhs_lpass_throttle_cfg = {
886
+
.name = "qhs_lpass_throttle_cfg",
887
+
.id = QCS8300_SLAVE_LPASS_THROTTLE_CFG,
888
+
.channels = 1,
889
+
.buswidth = 4,
890
+
.num_links = 0,
891
+
};
892
+
893
+
static struct qcom_icc_node qhs_mx_rdpm = {
894
+
.name = "qhs_mx_rdpm",
895
+
.id = QCS8300_SLAVE_MX_RDPM,
896
+
.channels = 1,
897
+
.buswidth = 4,
898
+
.num_links = 0,
899
+
};
900
+
901
+
static struct qcom_icc_node qhs_mxc_rdpm = {
902
+
.name = "qhs_mxc_rdpm",
903
+
.id = QCS8300_SLAVE_MXC_RDPM,
904
+
.channels = 1,
905
+
.buswidth = 4,
906
+
.num_links = 0,
907
+
};
908
+
909
+
static struct qcom_icc_node qhs_pcie0_cfg = {
910
+
.name = "qhs_pcie0_cfg",
911
+
.id = QCS8300_SLAVE_PCIE_0_CFG,
912
+
.channels = 1,
913
+
.buswidth = 4,
914
+
.num_links = 0,
915
+
};
916
+
917
+
static struct qcom_icc_node qhs_pcie1_cfg = {
918
+
.name = "qhs_pcie1_cfg",
919
+
.id = QCS8300_SLAVE_PCIE_1_CFG,
920
+
.channels = 1,
921
+
.buswidth = 4,
922
+
.num_links = 0,
923
+
};
924
+
925
+
static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
926
+
.name = "qhs_pcie_tcu_throttle_cfg",
927
+
.id = QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG,
928
+
.channels = 1,
929
+
.buswidth = 4,
930
+
.num_links = 0,
931
+
};
932
+
933
+
static struct qcom_icc_node qhs_pcie_throttle_cfg = {
934
+
.name = "qhs_pcie_throttle_cfg",
935
+
.id = QCS8300_SLAVE_PCIE_THROTTLE_CFG,
936
+
.channels = 1,
937
+
.buswidth = 4,
938
+
.num_links = 0,
939
+
};
940
+
941
+
static struct qcom_icc_node qhs_pdm = {
942
+
.name = "qhs_pdm",
943
+
.id = QCS8300_SLAVE_PDM,
944
+
.channels = 1,
945
+
.buswidth = 4,
946
+
.num_links = 0,
947
+
};
948
+
949
+
static struct qcom_icc_node qhs_pimem_cfg = {
950
+
.name = "qhs_pimem_cfg",
951
+
.id = QCS8300_SLAVE_PIMEM_CFG,
952
+
.channels = 1,
953
+
.buswidth = 4,
954
+
.num_links = 0,
955
+
};
956
+
957
+
static struct qcom_icc_node qhs_pke_wrapper_cfg = {
958
+
.name = "qhs_pke_wrapper_cfg",
959
+
.id = QCS8300_SLAVE_PKA_WRAPPER_CFG,
960
+
.channels = 1,
961
+
.buswidth = 4,
962
+
.num_links = 0,
963
+
};
964
+
965
+
static struct qcom_icc_node qhs_qdss_cfg = {
966
+
.name = "qhs_qdss_cfg",
967
+
.id = QCS8300_SLAVE_QDSS_CFG,
968
+
.channels = 1,
969
+
.buswidth = 4,
970
+
.num_links = 0,
971
+
};
972
+
973
+
static struct qcom_icc_node qhs_qm_cfg = {
974
+
.name = "qhs_qm_cfg",
975
+
.id = QCS8300_SLAVE_QM_CFG,
976
+
.channels = 1,
977
+
.buswidth = 4,
978
+
.num_links = 0,
979
+
};
980
+
981
+
static struct qcom_icc_node qhs_qm_mpu_cfg = {
982
+
.name = "qhs_qm_mpu_cfg",
983
+
.id = QCS8300_SLAVE_QM_MPU_CFG,
984
+
.channels = 1,
985
+
.buswidth = 4,
986
+
.num_links = 0,
987
+
};
988
+
989
+
static struct qcom_icc_node qhs_qup0 = {
990
+
.name = "qhs_qup0",
991
+
.id = QCS8300_SLAVE_QUP_0,
992
+
.channels = 1,
993
+
.buswidth = 4,
994
+
.num_links = 0,
995
+
};
996
+
997
+
static struct qcom_icc_node qhs_qup1 = {
998
+
.name = "qhs_qup1",
999
+
.id = QCS8300_SLAVE_QUP_1,
1000
+
.channels = 1,
1001
+
.buswidth = 4,
1002
+
.num_links = 0,
1003
+
};
1004
+
1005
+
static struct qcom_icc_node qhs_qup3 = {
1006
+
.name = "qhs_qup3",
1007
+
.id = QCS8300_SLAVE_QUP_3,
1008
+
.channels = 1,
1009
+
.buswidth = 4,
1010
+
.num_links = 0,
1011
+
};
1012
+
1013
+
static struct qcom_icc_node qhs_sail_throttle_cfg = {
1014
+
.name = "qhs_sail_throttle_cfg",
1015
+
.id = QCS8300_SLAVE_SAIL_THROTTLE_CFG,
1016
+
.channels = 1,
1017
+
.buswidth = 4,
1018
+
.num_links = 0,
1019
+
};
1020
+
1021
+
static struct qcom_icc_node qhs_sdc1 = {
1022
+
.name = "qhs_sdc1",
1023
+
.id = QCS8300_SLAVE_SDC1,
1024
+
.channels = 1,
1025
+
.buswidth = 4,
1026
+
.num_links = 0,
1027
+
};
1028
+
1029
+
static struct qcom_icc_node qhs_security = {
1030
+
.name = "qhs_security",
1031
+
.id = QCS8300_SLAVE_SECURITY,
1032
+
.channels = 1,
1033
+
.buswidth = 4,
1034
+
.num_links = 0,
1035
+
};
1036
+
1037
+
static struct qcom_icc_node qhs_snoc_throttle_cfg = {
1038
+
.name = "qhs_snoc_throttle_cfg",
1039
+
.id = QCS8300_SLAVE_SNOC_THROTTLE_CFG,
1040
+
.channels = 1,
1041
+
.buswidth = 4,
1042
+
.num_links = 0,
1043
+
};
1044
+
1045
+
static struct qcom_icc_node qhs_tcsr = {
1046
+
.name = "qhs_tcsr",
1047
+
.id = QCS8300_SLAVE_TCSR,
1048
+
.channels = 1,
1049
+
.buswidth = 4,
1050
+
.num_links = 0,
1051
+
};
1052
+
1053
+
static struct qcom_icc_node qhs_tlmm = {
1054
+
.name = "qhs_tlmm",
1055
+
.id = QCS8300_SLAVE_TLMM,
1056
+
.channels = 1,
1057
+
.buswidth = 4,
1058
+
.num_links = 0,
1059
+
};
1060
+
1061
+
static struct qcom_icc_node qhs_tsc_cfg = {
1062
+
.name = "qhs_tsc_cfg",
1063
+
.id = QCS8300_SLAVE_TSC_CFG,
1064
+
.channels = 1,
1065
+
.buswidth = 4,
1066
+
.num_links = 0,
1067
+
};
1068
+
1069
+
static struct qcom_icc_node qhs_ufs_mem_cfg = {
1070
+
.name = "qhs_ufs_mem_cfg",
1071
+
.id = QCS8300_SLAVE_UFS_MEM_CFG,
1072
+
.channels = 1,
1073
+
.buswidth = 4,
1074
+
.num_links = 0,
1075
+
};
1076
+
1077
+
static struct qcom_icc_node qhs_usb2_0 = {
1078
+
.name = "qhs_usb2_0",
1079
+
.id = QCS8300_SLAVE_USB2,
1080
+
.channels = 1,
1081
+
.buswidth = 4,
1082
+
.num_links = 0,
1083
+
};
1084
+
1085
+
static struct qcom_icc_node qhs_usb3_0 = {
1086
+
.name = "qhs_usb3_0",
1087
+
.id = QCS8300_SLAVE_USB3_0,
1088
+
.channels = 1,
1089
+
.buswidth = 4,
1090
+
.num_links = 0,
1091
+
};
1092
+
1093
+
static struct qcom_icc_node qhs_venus_cfg = {
1094
+
.name = "qhs_venus_cfg",
1095
+
.id = QCS8300_SLAVE_VENUS_CFG,
1096
+
.channels = 1,
1097
+
.buswidth = 4,
1098
+
.num_links = 0,
1099
+
};
1100
+
1101
+
static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
1102
+
.name = "qhs_venus_cvp_throttle_cfg",
1103
+
.id = QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG,
1104
+
.channels = 1,
1105
+
.buswidth = 4,
1106
+
.num_links = 0,
1107
+
};
1108
+
1109
+
static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
1110
+
.name = "qhs_venus_v_cpu_throttle_cfg",
1111
+
.id = QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
1112
+
.channels = 1,
1113
+
.buswidth = 4,
1114
+
.num_links = 0,
1115
+
};
1116
+
1117
+
static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
1118
+
.name = "qhs_venus_vcodec_throttle_cfg",
1119
+
.id = QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
1120
+
.channels = 1,
1121
+
.buswidth = 4,
1122
+
.num_links = 0,
1123
+
};
1124
+
1125
+
static struct qcom_icc_node qns_ddrss_cfg = {
1126
+
.name = "qns_ddrss_cfg",
1127
+
.id = QCS8300_SLAVE_DDRSS_CFG,
1128
+
.channels = 1,
1129
+
.buswidth = 4,
1130
+
.num_links = 1,
1131
+
.links = { QCS8300_MASTER_CNOC_DC_NOC },
1132
+
};
1133
+
1134
+
static struct qcom_icc_node qns_gpdsp_noc_cfg = {
1135
+
.name = "qns_gpdsp_noc_cfg",
1136
+
.id = QCS8300_SLAVE_GPDSP_NOC_CFG,
1137
+
.channels = 1,
1138
+
.buswidth = 4,
1139
+
.num_links = 0,
1140
+
};
1141
+
1142
+
static struct qcom_icc_node qns_mnoc_hf_cfg = {
1143
+
.name = "qns_mnoc_hf_cfg",
1144
+
.id = QCS8300_SLAVE_CNOC_MNOC_HF_CFG,
1145
+
.channels = 1,
1146
+
.buswidth = 4,
1147
+
.num_links = 1,
1148
+
.links = { QCS8300_MASTER_CNOC_MNOC_HF_CFG },
1149
+
};
1150
+
1151
+
static struct qcom_icc_node qns_mnoc_sf_cfg = {
1152
+
.name = "qns_mnoc_sf_cfg",
1153
+
.id = QCS8300_SLAVE_CNOC_MNOC_SF_CFG,
1154
+
.channels = 1,
1155
+
.buswidth = 4,
1156
+
.num_links = 1,
1157
+
.links = { QCS8300_MASTER_CNOC_MNOC_SF_CFG },
1158
+
};
1159
+
1160
+
static struct qcom_icc_node qns_pcie_anoc_cfg = {
1161
+
.name = "qns_pcie_anoc_cfg",
1162
+
.id = QCS8300_SLAVE_PCIE_ANOC_CFG,
1163
+
.channels = 1,
1164
+
.buswidth = 4,
1165
+
.num_links = 0,
1166
+
};
1167
+
1168
+
static struct qcom_icc_node qns_snoc_cfg = {
1169
+
.name = "qns_snoc_cfg",
1170
+
.id = QCS8300_SLAVE_SNOC_CFG,
1171
+
.channels = 1,
1172
+
.buswidth = 4,
1173
+
.num_links = 1,
1174
+
.links = { QCS8300_MASTER_SNOC_CFG },
1175
+
};
1176
+
1177
+
static struct qcom_icc_node qxs_boot_imem = {
1178
+
.name = "qxs_boot_imem",
1179
+
.id = QCS8300_SLAVE_BOOT_IMEM,
1180
+
.channels = 1,
1181
+
.buswidth = 16,
1182
+
.num_links = 0,
1183
+
};
1184
+
1185
+
static struct qcom_icc_node qxs_imem = {
1186
+
.name = "qxs_imem",
1187
+
.id = QCS8300_SLAVE_IMEM,
1188
+
.channels = 1,
1189
+
.buswidth = 8,
1190
+
.num_links = 0,
1191
+
};
1192
+
1193
+
static struct qcom_icc_node qxs_pimem = {
1194
+
.name = "qxs_pimem",
1195
+
.id = QCS8300_SLAVE_PIMEM,
1196
+
.channels = 1,
1197
+
.buswidth = 8,
1198
+
.num_links = 0,
1199
+
};
1200
+
1201
+
static struct qcom_icc_node xs_pcie_0 = {
1202
+
.name = "xs_pcie_0",
1203
+
.id = QCS8300_SLAVE_PCIE_0,
1204
+
.channels = 1,
1205
+
.buswidth = 16,
1206
+
.num_links = 0,
1207
+
};
1208
+
1209
+
static struct qcom_icc_node xs_pcie_1 = {
1210
+
.name = "xs_pcie_1",
1211
+
.id = QCS8300_SLAVE_PCIE_1,
1212
+
.channels = 1,
1213
+
.buswidth = 32,
1214
+
.num_links = 0,
1215
+
};
1216
+
1217
+
static struct qcom_icc_node xs_qdss_stm = {
1218
+
.name = "xs_qdss_stm",
1219
+
.id = QCS8300_SLAVE_QDSS_STM,
1220
+
.channels = 1,
1221
+
.buswidth = 4,
1222
+
.num_links = 0,
1223
+
};
1224
+
1225
+
static struct qcom_icc_node xs_sys_tcu_cfg = {
1226
+
.name = "xs_sys_tcu_cfg",
1227
+
.id = QCS8300_SLAVE_TCU,
1228
+
.channels = 1,
1229
+
.buswidth = 8,
1230
+
.num_links = 0,
1231
+
};
1232
+
1233
+
static struct qcom_icc_node qhs_llcc = {
1234
+
.name = "qhs_llcc",
1235
+
.id = QCS8300_SLAVE_LLCC_CFG,
1236
+
.channels = 1,
1237
+
.buswidth = 4,
1238
+
.num_links = 0,
1239
+
};
1240
+
1241
+
static struct qcom_icc_node qns_gemnoc = {
1242
+
.name = "qns_gemnoc",
1243
+
.id = QCS8300_SLAVE_GEM_NOC_CFG,
1244
+
.channels = 1,
1245
+
.buswidth = 4,
1246
+
.num_links = 1,
1247
+
.links = { QCS8300_MASTER_GEM_NOC_CFG },
1248
+
};
1249
+
1250
+
static struct qcom_icc_node qns_gem_noc_cnoc = {
1251
+
.name = "qns_gem_noc_cnoc",
1252
+
.id = QCS8300_SLAVE_GEM_NOC_CNOC,
1253
+
.channels = 1,
1254
+
.buswidth = 16,
1255
+
.num_links = 1,
1256
+
.links = { QCS8300_MASTER_GEM_NOC_CNOC },
1257
+
};
1258
+
1259
+
static struct qcom_icc_node qns_llcc = {
1260
+
.name = "qns_llcc",
1261
+
.id = QCS8300_SLAVE_LLCC,
1262
+
.channels = 4,
1263
+
.buswidth = 16,
1264
+
.num_links = 1,
1265
+
.links = { QCS8300_MASTER_LLCC },
1266
+
};
1267
+
1268
+
static struct qcom_icc_node qns_pcie = {
1269
+
.name = "qns_pcie",
1270
+
.id = QCS8300_SLAVE_GEM_NOC_PCIE_CNOC,
1271
+
.channels = 1,
1272
+
.buswidth = 16,
1273
+
.num_links = 1,
1274
+
.links = { QCS8300_MASTER_GEM_NOC_PCIE_SNOC },
1275
+
};
1276
+
1277
+
static struct qcom_icc_node srvc_even_gemnoc = {
1278
+
.name = "srvc_even_gemnoc",
1279
+
.id = QCS8300_SLAVE_SERVICE_GEM_NOC_1,
1280
+
.channels = 1,
1281
+
.buswidth = 4,
1282
+
.num_links = 0,
1283
+
};
1284
+
1285
+
static struct qcom_icc_node srvc_odd_gemnoc = {
1286
+
.name = "srvc_odd_gemnoc",
1287
+
.id = QCS8300_SLAVE_SERVICE_GEM_NOC_2,
1288
+
.channels = 1,
1289
+
.buswidth = 4,
1290
+
.num_links = 0,
1291
+
};
1292
+
1293
+
static struct qcom_icc_node srvc_sys_gemnoc = {
1294
+
.name = "srvc_sys_gemnoc",
1295
+
.id = QCS8300_SLAVE_SERVICE_GEM_NOC,
1296
+
.channels = 1,
1297
+
.buswidth = 4,
1298
+
.num_links = 0,
1299
+
};
1300
+
1301
+
static struct qcom_icc_node srvc_sys_gemnoc_2 = {
1302
+
.name = "srvc_sys_gemnoc_2",
1303
+
.id = QCS8300_SLAVE_SERVICE_GEM_NOC2,
1304
+
.channels = 1,
1305
+
.buswidth = 4,
1306
+
.num_links = 0,
1307
+
};
1308
+
1309
+
static struct qcom_icc_node qns_gp_dsp_sail_noc = {
1310
+
.name = "qns_gp_dsp_sail_noc",
1311
+
.id = QCS8300_SLAVE_GP_DSP_SAIL_NOC,
1312
+
.channels = 1,
1313
+
.buswidth = 16,
1314
+
.num_links = 1,
1315
+
.links = { QCS8300_MASTER_GPDSP_SAIL },
1316
+
};
1317
+
1318
+
static struct qcom_icc_node qhs_lpass_core = {
1319
+
.name = "qhs_lpass_core",
1320
+
.id = QCS8300_SLAVE_LPASS_CORE_CFG,
1321
+
.channels = 1,
1322
+
.buswidth = 4,
1323
+
.num_links = 0,
1324
+
};
1325
+
1326
+
static struct qcom_icc_node qhs_lpass_lpi = {
1327
+
.name = "qhs_lpass_lpi",
1328
+
.id = QCS8300_SLAVE_LPASS_LPI_CFG,
1329
+
.channels = 1,
1330
+
.buswidth = 4,
1331
+
.num_links = 0,
1332
+
};
1333
+
1334
+
static struct qcom_icc_node qhs_lpass_mpu = {
1335
+
.name = "qhs_lpass_mpu",
1336
+
.id = QCS8300_SLAVE_LPASS_MPU_CFG,
1337
+
.channels = 1,
1338
+
.buswidth = 4,
1339
+
.num_links = 0,
1340
+
};
1341
+
1342
+
static struct qcom_icc_node qhs_lpass_top = {
1343
+
.name = "qhs_lpass_top",
1344
+
.id = QCS8300_SLAVE_LPASS_TOP_CFG,
1345
+
.channels = 1,
1346
+
.buswidth = 4,
1347
+
.num_links = 0,
1348
+
};
1349
+
1350
+
static struct qcom_icc_node qns_sysnoc = {
1351
+
.name = "qns_sysnoc",
1352
+
.id = QCS8300_SLAVE_LPASS_SNOC,
1353
+
.channels = 1,
1354
+
.buswidth = 16,
1355
+
.num_links = 1,
1356
+
.links = { QCS8300_MASTER_LPASS_ANOC },
1357
+
};
1358
+
1359
+
static struct qcom_icc_node srvc_niu_aml_noc = {
1360
+
.name = "srvc_niu_aml_noc",
1361
+
.id = QCS8300_SLAVE_SERVICES_LPASS_AML_NOC,
1362
+
.channels = 1,
1363
+
.buswidth = 4,
1364
+
.num_links = 0,
1365
+
};
1366
+
1367
+
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1368
+
.name = "srvc_niu_lpass_agnoc",
1369
+
.id = QCS8300_SLAVE_SERVICE_LPASS_AG_NOC,
1370
+
.channels = 1,
1371
+
.buswidth = 4,
1372
+
.num_links = 0,
1373
+
};
1374
+
1375
+
static struct qcom_icc_node ebi = {
1376
+
.name = "ebi",
1377
+
.id = QCS8300_SLAVE_EBI1,
1378
+
.channels = 8,
1379
+
.buswidth = 4,
1380
+
.num_links = 0,
1381
+
};
1382
+
1383
+
static struct qcom_icc_node qns_mem_noc_hf = {
1384
+
.name = "qns_mem_noc_hf",
1385
+
.id = QCS8300_SLAVE_MNOC_HF_MEM_NOC,
1386
+
.channels = 2,
1387
+
.buswidth = 32,
1388
+
.num_links = 1,
1389
+
.links = { QCS8300_MASTER_MNOC_HF_MEM_NOC },
1390
+
};
1391
+
1392
+
static struct qcom_icc_node qns_mem_noc_sf = {
1393
+
.name = "qns_mem_noc_sf",
1394
+
.id = QCS8300_SLAVE_MNOC_SF_MEM_NOC,
1395
+
.channels = 2,
1396
+
.buswidth = 32,
1397
+
.num_links = 1,
1398
+
.links = { QCS8300_MASTER_MNOC_SF_MEM_NOC },
1399
+
};
1400
+
1401
+
static struct qcom_icc_node srvc_mnoc_hf = {
1402
+
.name = "srvc_mnoc_hf",
1403
+
.id = QCS8300_SLAVE_SERVICE_MNOC_HF,
1404
+
.channels = 1,
1405
+
.buswidth = 4,
1406
+
.num_links = 0,
1407
+
};
1408
+
1409
+
static struct qcom_icc_node srvc_mnoc_sf = {
1410
+
.name = "srvc_mnoc_sf",
1411
+
.id = QCS8300_SLAVE_SERVICE_MNOC_SF,
1412
+
.channels = 1,
1413
+
.buswidth = 4,
1414
+
.num_links = 0,
1415
+
};
1416
+
1417
+
static struct qcom_icc_node qns_hcp = {
1418
+
.name = "qns_hcp",
1419
+
.id = QCS8300_SLAVE_HCP_A,
1420
+
.channels = 2,
1421
+
.buswidth = 32,
1422
+
.num_links = 0,
1423
+
};
1424
+
1425
+
static struct qcom_icc_node qns_nsp_gemnoc = {
1426
+
.name = "qns_nsp_gemnoc",
1427
+
.id = QCS8300_SLAVE_CDSP_MEM_NOC,
1428
+
.channels = 2,
1429
+
.buswidth = 32,
1430
+
.num_links = 1,
1431
+
.links = { QCS8300_MASTER_COMPUTE_NOC },
1432
+
};
1433
+
1434
+
static struct qcom_icc_node service_nsp_noc = {
1435
+
.name = "service_nsp_noc",
1436
+
.id = QCS8300_SLAVE_SERVICE_NSP_NOC,
1437
+
.channels = 1,
1438
+
.buswidth = 4,
1439
+
.num_links = 0,
1440
+
};
1441
+
1442
+
static struct qcom_icc_node qns_pcie_mem_noc = {
1443
+
.name = "qns_pcie_mem_noc",
1444
+
.id = QCS8300_SLAVE_ANOC_PCIE_GEM_NOC,
1445
+
.channels = 1,
1446
+
.buswidth = 32,
1447
+
.num_links = 1,
1448
+
.links = { QCS8300_MASTER_ANOC_PCIE_GEM_NOC },
1449
+
};
1450
+
1451
+
static struct qcom_icc_node qns_gemnoc_gc = {
1452
+
.name = "qns_gemnoc_gc",
1453
+
.id = QCS8300_SLAVE_SNOC_GEM_NOC_GC,
1454
+
.channels = 1,
1455
+
.buswidth = 8,
1456
+
.num_links = 1,
1457
+
.links = { QCS8300_MASTER_SNOC_GC_MEM_NOC },
1458
+
};
1459
+
1460
+
static struct qcom_icc_node qns_gemnoc_sf = {
1461
+
.name = "qns_gemnoc_sf",
1462
+
.id = QCS8300_SLAVE_SNOC_GEM_NOC_SF,
1463
+
.channels = 1,
1464
+
.buswidth = 16,
1465
+
.num_links = 1,
1466
+
.links = { QCS8300_MASTER_SNOC_SF_MEM_NOC },
1467
+
};
1468
+
1469
+
static struct qcom_icc_node srvc_snoc = {
1470
+
.name = "srvc_snoc",
1471
+
.id = QCS8300_SLAVE_SERVICE_SNOC,
1472
+
.channels = 1,
1473
+
.buswidth = 4,
1474
+
.num_links = 0,
1475
+
};
1476
+
1477
+
static struct qcom_icc_bcm bcm_acv = {
1478
+
.name = "ACV",
1479
+
.enable_mask = BIT(3),
1480
+
.num_nodes = 1,
1481
+
.nodes = { &ebi },
1482
+
};
1483
+
1484
+
static struct qcom_icc_bcm bcm_ce0 = {
1485
+
.name = "CE0",
1486
+
.num_nodes = 2,
1487
+
.nodes = { &qxm_crypto_0, &qxm_crypto_1 },
1488
+
};
1489
+
1490
+
static struct qcom_icc_bcm bcm_cn0 = {
1491
+
.name = "CN0",
1492
+
.keepalive = true,
1493
+
.num_nodes = 2,
1494
+
.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1495
+
};
1496
+
1497
+
static struct qcom_icc_bcm bcm_cn1 = {
1498
+
.name = "CN1",
1499
+
.num_nodes = 66,
1500
+
.nodes = { &qhs_ahb2phy2, &qhs_ahb2phy3,
1501
+
&qhs_anoc_throttle_cfg, &qhs_aoss,
1502
+
&qhs_apss, &qhs_boot_rom,
1503
+
&qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
1504
+
&qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
1505
+
&qhs_compute0_cfg, &qhs_cpr_cx,
1506
+
&qhs_cpr_mmcx, &qhs_cpr_mx,
1507
+
&qhs_cpr_nspcx, &qhs_cpr_nsphmx,
1508
+
&qhs_crypto0_cfg, &qhs_cx_rdpm,
1509
+
&qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
1510
+
&qhs_emac0_cfg, &qhs_gp_dsp0_cfg,
1511
+
&qhs_gpdsp0_throttle_cfg, &qhs_gpu_tcu_throttle_cfg,
1512
+
&qhs_gpuss_cfg, &qhs_hwkm,
1513
+
&qhs_imem_cfg, &qhs_ipa,
1514
+
&qhs_ipc_router, &qhs_lpass_cfg,
1515
+
&qhs_lpass_throttle_cfg, &qhs_mx_rdpm,
1516
+
&qhs_mxc_rdpm, &qhs_pcie0_cfg,
1517
+
&qhs_pcie1_cfg, &qhs_pcie_tcu_throttle_cfg,
1518
+
&qhs_pcie_throttle_cfg, &qhs_pdm,
1519
+
&qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
1520
+
&qhs_qdss_cfg, &qhs_qm_cfg,
1521
+
&qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg,
1522
+
&qhs_sdc1, &qhs_security,
1523
+
&qhs_snoc_throttle_cfg, &qhs_tcsr,
1524
+
&qhs_tlmm, &qhs_tsc_cfg,
1525
+
&qhs_ufs_mem_cfg, &qhs_usb2_0,
1526
+
&qhs_usb3_0, &qhs_venus_cfg,
1527
+
&qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
1528
+
&qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
1529
+
&qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
1530
+
&qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
1531
+
&qns_snoc_cfg, &qxs_boot_imem,
1532
+
&qxs_imem, &xs_sys_tcu_cfg },
1533
+
};
1534
+
1535
+
static struct qcom_icc_bcm bcm_cn2 = {
1536
+
.name = "CN2",
1537
+
.num_nodes = 3,
1538
+
.nodes = { &qhs_qup0, &qhs_qup1,
1539
+
&qhs_qup3 },
1540
+
};
1541
+
1542
+
static struct qcom_icc_bcm bcm_cn3 = {
1543
+
.name = "CN3",
1544
+
.num_nodes = 2,
1545
+
.nodes = { &xs_pcie_0, &xs_pcie_1 },
1546
+
};
1547
+
1548
+
static struct qcom_icc_bcm bcm_gna0 = {
1549
+
.name = "GNA0",
1550
+
.num_nodes = 1,
1551
+
.nodes = { &qxm_dsp0 },
1552
+
};
1553
+
1554
+
static struct qcom_icc_bcm bcm_mc0 = {
1555
+
.name = "MC0",
1556
+
.keepalive = true,
1557
+
.num_nodes = 1,
1558
+
.nodes = { &ebi },
1559
+
};
1560
+
1561
+
static struct qcom_icc_bcm bcm_mm0 = {
1562
+
.name = "MM0",
1563
+
.keepalive = true,
1564
+
.num_nodes = 4,
1565
+
.nodes = { &qnm_camnoc_hf, &qnm_mdp0_0,
1566
+
&qnm_mdp0_1, &qns_mem_noc_hf },
1567
+
};
1568
+
1569
+
static struct qcom_icc_bcm bcm_mm1 = {
1570
+
.name = "MM1",
1571
+
.num_nodes = 6,
1572
+
.nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf,
1573
+
&qnm_video0, &qnm_video_cvp,
1574
+
&qnm_video_v_cpu, &qns_mem_noc_sf },
1575
+
};
1576
+
1577
+
static struct qcom_icc_bcm bcm_nsa0 = {
1578
+
.name = "NSA0",
1579
+
.num_nodes = 2,
1580
+
.nodes = { &qns_hcp, &qns_nsp_gemnoc },
1581
+
};
1582
+
1583
+
static struct qcom_icc_bcm bcm_nsa1 = {
1584
+
.name = "NSA1",
1585
+
.num_nodes = 1,
1586
+
.nodes = { &qxm_nsp },
1587
+
};
1588
+
1589
+
static struct qcom_icc_bcm bcm_pci0 = {
1590
+
.name = "PCI0",
1591
+
.num_nodes = 1,
1592
+
.nodes = { &qns_pcie_mem_noc },
1593
+
};
1594
+
1595
+
static struct qcom_icc_bcm bcm_qup0 = {
1596
+
.name = "QUP0",
1597
+
.vote_scale = 1,
1598
+
.keepalive = true,
1599
+
.num_nodes = 1,
1600
+
.nodes = { &qup0_core_slave },
1601
+
};
1602
+
1603
+
static struct qcom_icc_bcm bcm_qup1 = {
1604
+
.name = "QUP1",
1605
+
.vote_scale = 1,
1606
+
.keepalive = true,
1607
+
.num_nodes = 1,
1608
+
.nodes = { &qup1_core_slave },
1609
+
};
1610
+
1611
+
static struct qcom_icc_bcm bcm_qup2 = {
1612
+
.name = "QUP2",
1613
+
.vote_scale = 1,
1614
+
.keepalive = true,
1615
+
.num_nodes = 1,
1616
+
.nodes = { &qup3_core_slave },
1617
+
};
1618
+
1619
+
static struct qcom_icc_bcm bcm_sh0 = {
1620
+
.name = "SH0",
1621
+
.keepalive = true,
1622
+
.num_nodes = 1,
1623
+
.nodes = { &qns_llcc },
1624
+
};
1625
+
1626
+
static struct qcom_icc_bcm bcm_sh2 = {
1627
+
.name = "SH2",
1628
+
.num_nodes = 1,
1629
+
.nodes = { &chm_apps },
1630
+
};
1631
+
1632
+
static struct qcom_icc_bcm bcm_sn0 = {
1633
+
.name = "SN0",
1634
+
.keepalive = true,
1635
+
.num_nodes = 1,
1636
+
.nodes = { &qns_gemnoc_sf },
1637
+
};
1638
+
1639
+
static struct qcom_icc_bcm bcm_sn1 = {
1640
+
.name = "SN1",
1641
+
.num_nodes = 1,
1642
+
.nodes = { &qns_gemnoc_gc },
1643
+
};
1644
+
1645
+
static struct qcom_icc_bcm bcm_sn2 = {
1646
+
.name = "SN2",
1647
+
.num_nodes = 1,
1648
+
.nodes = { &qxs_pimem },
1649
+
};
1650
+
1651
+
static struct qcom_icc_bcm bcm_sn3 = {
1652
+
.name = "SN3",
1653
+
.num_nodes = 2,
1654
+
.nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
1655
+
};
1656
+
1657
+
static struct qcom_icc_bcm bcm_sn4 = {
1658
+
.name = "SN4",
1659
+
.num_nodes = 2,
1660
+
.nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc },
1661
+
};
1662
+
1663
+
static struct qcom_icc_bcm bcm_sn9 = {
1664
+
.name = "SN9",
1665
+
.num_nodes = 2,
1666
+
.nodes = { &qns_sysnoc, &qnm_lpass_noc },
1667
+
};
1668
+
1669
+
static struct qcom_icc_bcm bcm_sn10 = {
1670
+
.name = "SN10",
1671
+
.num_nodes = 1,
1672
+
.nodes = { &xs_qdss_stm },
1673
+
};
1674
+
1675
+
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1676
+
&bcm_sn3,
1677
+
};
1678
+
1679
+
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1680
+
[MASTER_QUP_3] = &qxm_qup3,
1681
+
[MASTER_EMAC] = &xm_emac_0,
1682
+
[MASTER_SDC] = &xm_sdc1,
1683
+
[MASTER_UFS_MEM] = &xm_ufs_mem,
1684
+
[MASTER_USB2] = &xm_usb2_2,
1685
+
[MASTER_USB3_0] = &xm_usb3_0,
1686
+
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1687
+
};
1688
+
1689
+
static const struct qcom_icc_desc qcs8300_aggre1_noc = {
1690
+
.nodes = aggre1_noc_nodes,
1691
+
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1692
+
.bcms = aggre1_noc_bcms,
1693
+
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1694
+
};
1695
+
1696
+
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1697
+
&bcm_ce0,
1698
+
&bcm_sn4,
1699
+
};
1700
+
1701
+
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1702
+
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
1703
+
[MASTER_QUP_0] = &qhm_qup0,
1704
+
[MASTER_QUP_1] = &qhm_qup1,
1705
+
[MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
1706
+
[MASTER_CRYPTO_CORE0] = &qxm_crypto_0,
1707
+
[MASTER_CRYPTO_CORE1] = &qxm_crypto_1,
1708
+
[MASTER_IPA] = &qxm_ipa,
1709
+
[MASTER_QDSS_ETR_0] = &xm_qdss_etr_0,
1710
+
[MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1711
+
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1712
+
};
1713
+
1714
+
static const struct qcom_icc_desc qcs8300_aggre2_noc = {
1715
+
.nodes = aggre2_noc_nodes,
1716
+
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1717
+
.bcms = aggre2_noc_bcms,
1718
+
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1719
+
};
1720
+
1721
+
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1722
+
&bcm_qup0,
1723
+
&bcm_qup1,
1724
+
&bcm_qup2,
1725
+
};
1726
+
1727
+
static struct qcom_icc_node * const clk_virt_nodes[] = {
1728
+
[MASTER_QUP_CORE_0] = &qup0_core_master,
1729
+
[MASTER_QUP_CORE_1] = &qup1_core_master,
1730
+
[MASTER_QUP_CORE_3] = &qup3_core_master,
1731
+
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
1732
+
[SLAVE_QUP_CORE_1] = &qup1_core_slave,
1733
+
[SLAVE_QUP_CORE_3] = &qup3_core_slave,
1734
+
};
1735
+
1736
+
static const struct qcom_icc_desc qcs8300_clk_virt = {
1737
+
.nodes = clk_virt_nodes,
1738
+
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
1739
+
.bcms = clk_virt_bcms,
1740
+
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
1741
+
};
1742
+
1743
+
static struct qcom_icc_bcm * const config_noc_bcms[] = {
1744
+
&bcm_cn0,
1745
+
&bcm_cn1,
1746
+
&bcm_cn2,
1747
+
&bcm_cn3,
1748
+
&bcm_sn2,
1749
+
&bcm_sn10,
1750
+
};
1751
+
1752
+
static struct qcom_icc_node * const config_noc_nodes[] = {
1753
+
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1754
+
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1755
+
[SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
1756
+
[SLAVE_AHB2PHY_3] = &qhs_ahb2phy3,
1757
+
[SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg,
1758
+
[SLAVE_AOSS] = &qhs_aoss,
1759
+
[SLAVE_APPSS] = &qhs_apss,
1760
+
[SLAVE_BOOT_ROM] = &qhs_boot_rom,
1761
+
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1762
+
[SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
1763
+
[SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
1764
+
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1765
+
[SLAVE_CDSP_CFG] = &qhs_compute0_cfg,
1766
+
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1767
+
[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1768
+
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1769
+
[SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
1770
+
[SLAVE_CPR_NSPHMX] = &qhs_cpr_nsphmx,
1771
+
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1772
+
[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1773
+
[SLAVE_DISPLAY_CFG] = &qhs_display0_cfg,
1774
+
[SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg,
1775
+
[SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
1776
+
[SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg,
1777
+
[SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg,
1778
+
[SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg,
1779
+
[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1780
+
[SLAVE_HWKM] = &qhs_hwkm,
1781
+
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1782
+
[SLAVE_IPA_CFG] = &qhs_ipa,
1783
+
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1784
+
[SLAVE_LPASS] = &qhs_lpass_cfg,
1785
+
[SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg,
1786
+
[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1787
+
[SLAVE_MXC_RDPM] = &qhs_mxc_rdpm,
1788
+
[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1789
+
[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1790
+
[SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg,
1791
+
[SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg,
1792
+
[SLAVE_PDM] = &qhs_pdm,
1793
+
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1794
+
[SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg,
1795
+
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1796
+
[SLAVE_QM_CFG] = &qhs_qm_cfg,
1797
+
[SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
1798
+
[SLAVE_QUP_0] = &qhs_qup0,
1799
+
[SLAVE_QUP_1] = &qhs_qup1,
1800
+
[SLAVE_QUP_3] = &qhs_qup3,
1801
+
[SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg,
1802
+
[SLAVE_SDC1] = &qhs_sdc1,
1803
+
[SLAVE_SECURITY] = &qhs_security,
1804
+
[SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg,
1805
+
[SLAVE_TCSR] = &qhs_tcsr,
1806
+
[SLAVE_TLMM] = &qhs_tlmm,
1807
+
[SLAVE_TSC_CFG] = &qhs_tsc_cfg,
1808
+
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1809
+
[SLAVE_USB2] = &qhs_usb2_0,
1810
+
[SLAVE_USB3_0] = &qhs_usb3_0,
1811
+
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1812
+
[SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg,
1813
+
[SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg,
1814
+
[SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg,
1815
+
[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1816
+
[SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg,
1817
+
[SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg,
1818
+
[SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg,
1819
+
[SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
1820
+
[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1821
+
[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1822
+
[SLAVE_IMEM] = &qxs_imem,
1823
+
[SLAVE_PIMEM] = &qxs_pimem,
1824
+
[SLAVE_PCIE_0] = &xs_pcie_0,
1825
+
[SLAVE_PCIE_1] = &xs_pcie_1,
1826
+
[SLAVE_QDSS_STM] = &xs_qdss_stm,
1827
+
[SLAVE_TCU] = &xs_sys_tcu_cfg,
1828
+
};
1829
+
1830
+
static const struct qcom_icc_desc qcs8300_config_noc = {
1831
+
.nodes = config_noc_nodes,
1832
+
.num_nodes = ARRAY_SIZE(config_noc_nodes),
1833
+
.bcms = config_noc_bcms,
1834
+
.num_bcms = ARRAY_SIZE(config_noc_bcms),
1835
+
};
1836
+
1837
+
static struct qcom_icc_node * const dc_noc_nodes[] = {
1838
+
[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
1839
+
[SLAVE_LLCC_CFG] = &qhs_llcc,
1840
+
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
1841
+
};
1842
+
1843
+
static const struct qcom_icc_desc qcs8300_dc_noc = {
1844
+
.nodes = dc_noc_nodes,
1845
+
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
1846
+
};
1847
+
1848
+
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1849
+
&bcm_sh0,
1850
+
&bcm_sh2,
1851
+
};
1852
+
1853
+
static struct qcom_icc_node * const gem_noc_nodes[] = {
1854
+
[MASTER_GPU_TCU] = &alm_gpu_tcu,
1855
+
[MASTER_PCIE_TCU] = &alm_pcie_tcu,
1856
+
[MASTER_SYS_TCU] = &alm_sys_tcu,
1857
+
[MASTER_APPSS_PROC] = &chm_apps,
1858
+
[MASTER_COMPUTE_NOC] = &qnm_cmpnoc0,
1859
+
[MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
1860
+
[MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail,
1861
+
[MASTER_GFX3D] = &qnm_gpu,
1862
+
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1863
+
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1864
+
[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1865
+
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1866
+
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1867
+
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1868
+
[SLAVE_LLCC] = &qns_llcc,
1869
+
[SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie,
1870
+
[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
1871
+
[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
1872
+
[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
1873
+
[SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
1874
+
};
1875
+
1876
+
static const struct qcom_icc_desc qcs8300_gem_noc = {
1877
+
.nodes = gem_noc_nodes,
1878
+
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1879
+
.bcms = gem_noc_bcms,
1880
+
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1881
+
};
1882
+
1883
+
static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
1884
+
&bcm_gna0,
1885
+
};
1886
+
1887
+
static struct qcom_icc_node * const gpdsp_anoc_nodes[] = {
1888
+
[MASTER_SAILSS_MD0] = &qnm_sailss_md0,
1889
+
[MASTER_DSP0] = &qxm_dsp0,
1890
+
[SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
1891
+
};
1892
+
1893
+
static const struct qcom_icc_desc qcs8300_gpdsp_anoc = {
1894
+
.nodes = gpdsp_anoc_nodes,
1895
+
.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
1896
+
.bcms = gpdsp_anoc_bcms,
1897
+
.num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
1898
+
};
1899
+
1900
+
static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1901
+
&bcm_sn9,
1902
+
};
1903
+
1904
+
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1905
+
[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1906
+
[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
1907
+
[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1908
+
[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1909
+
[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1910
+
[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1911
+
[SLAVE_LPASS_SNOC] = &qns_sysnoc,
1912
+
[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1913
+
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1914
+
};
1915
+
1916
+
static const struct qcom_icc_desc qcs8300_lpass_ag_noc = {
1917
+
.nodes = lpass_ag_noc_nodes,
1918
+
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1919
+
.bcms = lpass_ag_noc_bcms,
1920
+
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1921
+
};
1922
+
1923
+
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1924
+
&bcm_acv,
1925
+
&bcm_mc0,
1926
+
};
1927
+
1928
+
static struct qcom_icc_node * const mc_virt_nodes[] = {
1929
+
[MASTER_LLCC] = &llcc_mc,
1930
+
[SLAVE_EBI1] = &ebi,
1931
+
};
1932
+
1933
+
static const struct qcom_icc_desc qcs8300_mc_virt = {
1934
+
.nodes = mc_virt_nodes,
1935
+
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1936
+
.bcms = mc_virt_bcms,
1937
+
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
1938
+
};
1939
+
1940
+
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1941
+
&bcm_mm0,
1942
+
&bcm_mm1,
1943
+
};
1944
+
1945
+
static struct qcom_icc_node * const mmss_noc_nodes[] = {
1946
+
[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1947
+
[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1948
+
[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1949
+
[MASTER_MDP0] = &qnm_mdp0_0,
1950
+
[MASTER_MDP1] = &qnm_mdp0_1,
1951
+
[MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg,
1952
+
[MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg,
1953
+
[MASTER_VIDEO_P0] = &qnm_video0,
1954
+
[MASTER_VIDEO_PROC] = &qnm_video_cvp,
1955
+
[MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1956
+
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1957
+
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1958
+
[SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf,
1959
+
[SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
1960
+
};
1961
+
1962
+
static const struct qcom_icc_desc qcs8300_mmss_noc = {
1963
+
.nodes = mmss_noc_nodes,
1964
+
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1965
+
.bcms = mmss_noc_bcms,
1966
+
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1967
+
};
1968
+
1969
+
static struct qcom_icc_bcm * const nspa_noc_bcms[] = {
1970
+
&bcm_nsa0,
1971
+
&bcm_nsa1,
1972
+
};
1973
+
1974
+
static struct qcom_icc_node * const nspa_noc_nodes[] = {
1975
+
[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
1976
+
[MASTER_CDSP_PROC] = &qxm_nsp,
1977
+
[SLAVE_HCP_A] = &qns_hcp,
1978
+
[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1979
+
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
1980
+
};
1981
+
1982
+
static const struct qcom_icc_desc qcs8300_nspa_noc = {
1983
+
.nodes = nspa_noc_nodes,
1984
+
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
1985
+
.bcms = nspa_noc_bcms,
1986
+
.num_bcms = ARRAY_SIZE(nspa_noc_bcms),
1987
+
};
1988
+
1989
+
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1990
+
&bcm_pci0,
1991
+
};
1992
+
1993
+
static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1994
+
[MASTER_PCIE_0] = &xm_pcie3_0,
1995
+
[MASTER_PCIE_1] = &xm_pcie3_1,
1996
+
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1997
+
};
1998
+
1999
+
static const struct qcom_icc_desc qcs8300_pcie_anoc = {
2000
+
.nodes = pcie_anoc_nodes,
2001
+
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
2002
+
.bcms = pcie_anoc_bcms,
2003
+
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
2004
+
};
2005
+
2006
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
2007
+
&bcm_sn0,
2008
+
&bcm_sn1,
2009
+
&bcm_sn3,
2010
+
&bcm_sn4,
2011
+
&bcm_sn9,
2012
+
};
2013
+
2014
+
static struct qcom_icc_node * const system_noc_nodes[] = {
2015
+
[MASTER_GIC_AHB] = &qhm_gic,
2016
+
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2017
+
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2018
+
[MASTER_LPASS_ANOC] = &qnm_lpass_noc,
2019
+
[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
2020
+
[MASTER_PIMEM] = &qxm_pimem,
2021
+
[MASTER_GIC] = &xm_gic,
2022
+
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
2023
+
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2024
+
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
2025
+
};
2026
+
2027
+
static const struct qcom_icc_desc qcs8300_system_noc = {
2028
+
.nodes = system_noc_nodes,
2029
+
.num_nodes = ARRAY_SIZE(system_noc_nodes),
2030
+
.bcms = system_noc_bcms,
2031
+
.num_bcms = ARRAY_SIZE(system_noc_bcms),
2032
+
};
2033
+
2034
+
static const struct of_device_id qnoc_of_match[] = {
2035
+
{ .compatible = "qcom,qcs8300-aggre1-noc",
2036
+
.data = &qcs8300_aggre1_noc},
2037
+
{ .compatible = "qcom,qcs8300-aggre2-noc",
2038
+
.data = &qcs8300_aggre2_noc},
2039
+
{ .compatible = "qcom,qcs8300-clk-virt",
2040
+
.data = &qcs8300_clk_virt},
2041
+
{ .compatible = "qcom,qcs8300-config-noc",
2042
+
.data = &qcs8300_config_noc},
2043
+
{ .compatible = "qcom,qcs8300-dc-noc",
2044
+
.data = &qcs8300_dc_noc},
2045
+
{ .compatible = "qcom,qcs8300-gem-noc",
2046
+
.data = &qcs8300_gem_noc},
2047
+
{ .compatible = "qcom,qcs8300-gpdsp-anoc",
2048
+
.data = &qcs8300_gpdsp_anoc},
2049
+
{ .compatible = "qcom,qcs8300-lpass-ag-noc",
2050
+
.data = &qcs8300_lpass_ag_noc},
2051
+
{ .compatible = "qcom,qcs8300-mc-virt",
2052
+
.data = &qcs8300_mc_virt},
2053
+
{ .compatible = "qcom,qcs8300-mmss-noc",
2054
+
.data = &qcs8300_mmss_noc},
2055
+
{ .compatible = "qcom,qcs8300-nspa-noc",
2056
+
.data = &qcs8300_nspa_noc},
2057
+
{ .compatible = "qcom,qcs8300-pcie-anoc",
2058
+
.data = &qcs8300_pcie_anoc},
2059
+
{ .compatible = "qcom,qcs8300-system-noc",
2060
+
.data = &qcs8300_system_noc},
2061
+
{ }
2062
+
};
2063
+
MODULE_DEVICE_TABLE(of, qnoc_of_match);
2064
+
2065
+
static struct platform_driver qnoc_driver = {
2066
+
.probe = qcom_icc_rpmh_probe,
2067
+
.remove = qcom_icc_rpmh_remove,
2068
+
.driver = {
2069
+
.name = "qnoc-qcs8300",
2070
+
.of_match_table = qnoc_of_match,
2071
+
.sync_state = icc_sync_state,
2072
+
},
2073
+
};
2074
+
2075
+
static int __init qnoc_driver_init(void)
2076
+
{
2077
+
return platform_driver_register(&qnoc_driver);
2078
+
}
2079
+
core_initcall(qnoc_driver_init);
2080
+
2081
+
static void __exit qnoc_driver_exit(void)
2082
+
{
2083
+
platform_driver_unregister(&qnoc_driver);
2084
+
}
2085
+
module_exit(qnoc_driver_exit);
2086
+
2087
+
MODULE_DESCRIPTION("QCS8300 NoC driver");
2088
+
MODULE_LICENSE("GPL");
+177
drivers/interconnect/qcom/qcs8300.h
+177
drivers/interconnect/qcom/qcs8300.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS8300_H
7
+
#define __DRIVERS_INTERCONNECT_QCOM_QCS8300_H
8
+
9
+
#define QCS8300_MASTER_GPU_TCU 0
10
+
#define QCS8300_MASTER_PCIE_TCU 1
11
+
#define QCS8300_MASTER_SYS_TCU 2
12
+
#define QCS8300_MASTER_APPSS_PROC 3
13
+
#define QCS8300_MASTER_LLCC 4
14
+
#define QCS8300_MASTER_CNOC_LPASS_AG_NOC 5
15
+
#define QCS8300_MASTER_GIC_AHB 6
16
+
#define QCS8300_MASTER_CDSP_NOC_CFG 7
17
+
#define QCS8300_MASTER_QDSS_BAM 8
18
+
#define QCS8300_MASTER_QUP_0 9
19
+
#define QCS8300_MASTER_QUP_1 10
20
+
#define QCS8300_MASTER_A1NOC_SNOC 11
21
+
#define QCS8300_MASTER_A2NOC_SNOC 12
22
+
#define QCS8300_MASTER_CAMNOC_HF 13
23
+
#define QCS8300_MASTER_CAMNOC_ICP 14
24
+
#define QCS8300_MASTER_CAMNOC_SF 15
25
+
#define QCS8300_MASTER_COMPUTE_NOC 16
26
+
#define QCS8300_MASTER_CNOC_A2NOC 17
27
+
#define QCS8300_MASTER_CNOC_DC_NOC 18
28
+
#define QCS8300_MASTER_GEM_NOC_CFG 19
29
+
#define QCS8300_MASTER_GEM_NOC_CNOC 20
30
+
#define QCS8300_MASTER_GEM_NOC_PCIE_SNOC 21
31
+
#define QCS8300_MASTER_GPDSP_SAIL 22
32
+
#define QCS8300_MASTER_GFX3D 23
33
+
#define QCS8300_MASTER_LPASS_ANOC 24
34
+
#define QCS8300_MASTER_MDP0 25
35
+
#define QCS8300_MASTER_MDP1 26
36
+
#define QCS8300_MASTER_MNOC_HF_MEM_NOC 27
37
+
#define QCS8300_MASTER_CNOC_MNOC_HF_CFG 28
38
+
#define QCS8300_MASTER_MNOC_SF_MEM_NOC 29
39
+
#define QCS8300_MASTER_CNOC_MNOC_SF_CFG 30
40
+
#define QCS8300_MASTER_ANOC_PCIE_GEM_NOC 31
41
+
#define QCS8300_MASTER_SAILSS_MD0 32
42
+
#define QCS8300_MASTER_SNOC_CFG 33
43
+
#define QCS8300_MASTER_SNOC_GC_MEM_NOC 34
44
+
#define QCS8300_MASTER_SNOC_SF_MEM_NOC 35
45
+
#define QCS8300_MASTER_VIDEO_P0 36
46
+
#define QCS8300_MASTER_VIDEO_PROC 37
47
+
#define QCS8300_MASTER_VIDEO_V_PROC 38
48
+
#define QCS8300_MASTER_QUP_CORE_0 39
49
+
#define QCS8300_MASTER_QUP_CORE_1 40
50
+
#define QCS8300_MASTER_QUP_CORE_3 41
51
+
#define QCS8300_MASTER_CRYPTO_CORE0 42
52
+
#define QCS8300_MASTER_CRYPTO_CORE1 43
53
+
#define QCS8300_MASTER_DSP0 44
54
+
#define QCS8300_MASTER_IPA 45
55
+
#define QCS8300_MASTER_LPASS_PROC 46
56
+
#define QCS8300_MASTER_CDSP_PROC 47
57
+
#define QCS8300_MASTER_PIMEM 48
58
+
#define QCS8300_MASTER_QUP_3 49
59
+
#define QCS8300_MASTER_EMAC 50
60
+
#define QCS8300_MASTER_GIC 51
61
+
#define QCS8300_MASTER_PCIE_0 52
62
+
#define QCS8300_MASTER_PCIE_1 53
63
+
#define QCS8300_MASTER_QDSS_ETR_0 54
64
+
#define QCS8300_MASTER_QDSS_ETR_1 55
65
+
#define QCS8300_MASTER_SDC 56
66
+
#define QCS8300_MASTER_UFS_MEM 57
67
+
#define QCS8300_MASTER_USB2 58
68
+
#define QCS8300_MASTER_USB3_0 59
69
+
#define QCS8300_SLAVE_EBI1 60
70
+
#define QCS8300_SLAVE_AHB2PHY_2 61
71
+
#define QCS8300_SLAVE_AHB2PHY_3 62
72
+
#define QCS8300_SLAVE_ANOC_THROTTLE_CFG 63
73
+
#define QCS8300_SLAVE_AOSS 64
74
+
#define QCS8300_SLAVE_APPSS 65
75
+
#define QCS8300_SLAVE_BOOT_ROM 66
76
+
#define QCS8300_SLAVE_CAMERA_CFG 67
77
+
#define QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG 68
78
+
#define QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG 69
79
+
#define QCS8300_SLAVE_CLK_CTL 70
80
+
#define QCS8300_SLAVE_CDSP_CFG 71
81
+
#define QCS8300_SLAVE_RBCPR_CX_CFG 72
82
+
#define QCS8300_SLAVE_RBCPR_MMCX_CFG 73
83
+
#define QCS8300_SLAVE_RBCPR_MX_CFG 74
84
+
#define QCS8300_SLAVE_CPR_NSPCX 75
85
+
#define QCS8300_SLAVE_CPR_NSPHMX 76
86
+
#define QCS8300_SLAVE_CRYPTO_0_CFG 77
87
+
#define QCS8300_SLAVE_CX_RDPM 78
88
+
#define QCS8300_SLAVE_DISPLAY_CFG 79
89
+
#define QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG 80
90
+
#define QCS8300_SLAVE_EMAC_CFG 81
91
+
#define QCS8300_SLAVE_GP_DSP0_CFG 82
92
+
#define QCS8300_SLAVE_GPDSP0_THROTTLE_CFG 83
93
+
#define QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG 84
94
+
#define QCS8300_SLAVE_GFX3D_CFG 85
95
+
#define QCS8300_SLAVE_HWKM 86
96
+
#define QCS8300_SLAVE_IMEM_CFG 87
97
+
#define QCS8300_SLAVE_IPA_CFG 88
98
+
#define QCS8300_SLAVE_IPC_ROUTER_CFG 89
99
+
#define QCS8300_SLAVE_LLCC_CFG 90
100
+
#define QCS8300_SLAVE_LPASS 91
101
+
#define QCS8300_SLAVE_LPASS_CORE_CFG 92
102
+
#define QCS8300_SLAVE_LPASS_LPI_CFG 93
103
+
#define QCS8300_SLAVE_LPASS_MPU_CFG 94
104
+
#define QCS8300_SLAVE_LPASS_THROTTLE_CFG 95
105
+
#define QCS8300_SLAVE_LPASS_TOP_CFG 96
106
+
#define QCS8300_SLAVE_MX_RDPM 97
107
+
#define QCS8300_SLAVE_MXC_RDPM 98
108
+
#define QCS8300_SLAVE_PCIE_0_CFG 99
109
+
#define QCS8300_SLAVE_PCIE_1_CFG 100
110
+
#define QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG 101
111
+
#define QCS8300_SLAVE_PCIE_THROTTLE_CFG 102
112
+
#define QCS8300_SLAVE_PDM 103
113
+
#define QCS8300_SLAVE_PIMEM_CFG 104
114
+
#define QCS8300_SLAVE_PKA_WRAPPER_CFG 105
115
+
#define QCS8300_SLAVE_QDSS_CFG 106
116
+
#define QCS8300_SLAVE_QM_CFG 107
117
+
#define QCS8300_SLAVE_QM_MPU_CFG 108
118
+
#define QCS8300_SLAVE_QUP_0 109
119
+
#define QCS8300_SLAVE_QUP_1 110
120
+
#define QCS8300_SLAVE_QUP_3 111
121
+
#define QCS8300_SLAVE_SAIL_THROTTLE_CFG 112
122
+
#define QCS8300_SLAVE_SDC1 113
123
+
#define QCS8300_SLAVE_SECURITY 114
124
+
#define QCS8300_SLAVE_SNOC_THROTTLE_CFG 115
125
+
#define QCS8300_SLAVE_TCSR 116
126
+
#define QCS8300_SLAVE_TLMM 117
127
+
#define QCS8300_SLAVE_TSC_CFG 118
128
+
#define QCS8300_SLAVE_UFS_MEM_CFG 119
129
+
#define QCS8300_SLAVE_USB2 120
130
+
#define QCS8300_SLAVE_USB3_0 121
131
+
#define QCS8300_SLAVE_VENUS_CFG 122
132
+
#define QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG 123
133
+
#define QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG 124
134
+
#define QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG 125
135
+
#define QCS8300_SLAVE_A1NOC_SNOC 126
136
+
#define QCS8300_SLAVE_A2NOC_SNOC 127
137
+
#define QCS8300_SLAVE_DDRSS_CFG 128
138
+
#define QCS8300_SLAVE_GEM_NOC_CNOC 129
139
+
#define QCS8300_SLAVE_GEM_NOC_CFG 130
140
+
#define QCS8300_SLAVE_SNOC_GEM_NOC_GC 131
141
+
#define QCS8300_SLAVE_SNOC_GEM_NOC_SF 132
142
+
#define QCS8300_SLAVE_GP_DSP_SAIL_NOC 133
143
+
#define QCS8300_SLAVE_GPDSP_NOC_CFG 134
144
+
#define QCS8300_SLAVE_HCP_A 135
145
+
#define QCS8300_SLAVE_LLCC 136
146
+
#define QCS8300_SLAVE_MNOC_HF_MEM_NOC 137
147
+
#define QCS8300_SLAVE_MNOC_SF_MEM_NOC 138
148
+
#define QCS8300_SLAVE_CNOC_MNOC_HF_CFG 139
149
+
#define QCS8300_SLAVE_CNOC_MNOC_SF_CFG 140
150
+
#define QCS8300_SLAVE_CDSP_MEM_NOC 141
151
+
#define QCS8300_SLAVE_GEM_NOC_PCIE_CNOC 142
152
+
#define QCS8300_SLAVE_PCIE_ANOC_CFG 143
153
+
#define QCS8300_SLAVE_ANOC_PCIE_GEM_NOC 144
154
+
#define QCS8300_SLAVE_SNOC_CFG 145
155
+
#define QCS8300_SLAVE_LPASS_SNOC 146
156
+
#define QCS8300_SLAVE_QUP_CORE_0 147
157
+
#define QCS8300_SLAVE_QUP_CORE_1 148
158
+
#define QCS8300_SLAVE_QUP_CORE_3 149
159
+
#define QCS8300_SLAVE_BOOT_IMEM 150
160
+
#define QCS8300_SLAVE_IMEM 151
161
+
#define QCS8300_SLAVE_PIMEM 152
162
+
#define QCS8300_SLAVE_SERVICE_NSP_NOC 153
163
+
#define QCS8300_SLAVE_SERVICE_GEM_NOC_1 154
164
+
#define QCS8300_SLAVE_SERVICE_MNOC_HF 155
165
+
#define QCS8300_SLAVE_SERVICE_MNOC_SF 156
166
+
#define QCS8300_SLAVE_SERVICES_LPASS_AML_NOC 157
167
+
#define QCS8300_SLAVE_SERVICE_LPASS_AG_NOC 158
168
+
#define QCS8300_SLAVE_SERVICE_GEM_NOC_2 159
169
+
#define QCS8300_SLAVE_SERVICE_SNOC 160
170
+
#define QCS8300_SLAVE_SERVICE_GEM_NOC 161
171
+
#define QCS8300_SLAVE_SERVICE_GEM_NOC2 162
172
+
#define QCS8300_SLAVE_PCIE_0 163
173
+
#define QCS8300_SLAVE_PCIE_1 164
174
+
#define QCS8300_SLAVE_QDSS_STM 165
175
+
#define QCS8300_SLAVE_TCU 166
176
+
177
+
#endif
+1
-1
drivers/interconnect/qcom/qdu1000.c
+1
-1
drivers/interconnect/qcom/qdu1000.c
+1
-1
drivers/interconnect/qcom/sa8775p.c
+1
-1
drivers/interconnect/qcom/sa8775p.c
+1930
drivers/interconnect/qcom/sar2130p.c
+1930
drivers/interconnect/qcom/sar2130p.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
5
+
* Copyright (c) 2024, Linaro Ltd.
6
+
*/
7
+
8
+
#include <linux/device.h>
9
+
#include <linux/interconnect.h>
10
+
#include <linux/interconnect-provider.h>
11
+
#include <linux/io.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of_device.h>
14
+
#include <linux/of_platform.h>
15
+
#include <linux/platform_device.h>
16
+
#include <linux/sort.h>
17
+
#include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h>
18
+
19
+
#include "bcm-voter.h"
20
+
#include "icc-common.h"
21
+
#include "icc-rpmh.h"
22
+
23
+
enum {
24
+
SAR2130P_MASTER_QUP_CORE_0,
25
+
SAR2130P_MASTER_QUP_CORE_1,
26
+
SAR2130P_MASTER_GEM_NOC_CNOC,
27
+
SAR2130P_MASTER_GEM_NOC_PCIE_SNOC,
28
+
SAR2130P_MASTER_QDSS_DAP,
29
+
SAR2130P_MASTER_GPU_TCU,
30
+
SAR2130P_MASTER_SYS_TCU,
31
+
SAR2130P_MASTER_APPSS_PROC,
32
+
SAR2130P_MASTER_GFX3D,
33
+
SAR2130P_MASTER_MNOC_HF_MEM_NOC,
34
+
SAR2130P_MASTER_MNOC_SF_MEM_NOC,
35
+
SAR2130P_MASTER_COMPUTE_NOC,
36
+
SAR2130P_MASTER_ANOC_PCIE_GEM_NOC,
37
+
SAR2130P_MASTER_SNOC_GC_MEM_NOC,
38
+
SAR2130P_MASTER_SNOC_SF_MEM_NOC,
39
+
SAR2130P_MASTER_WLAN_Q6,
40
+
SAR2130P_MASTER_CNOC_LPASS_AG_NOC,
41
+
SAR2130P_MASTER_LPASS_PROC,
42
+
SAR2130P_MASTER_LLCC,
43
+
SAR2130P_MASTER_CAMNOC_HF,
44
+
SAR2130P_MASTER_CAMNOC_ICP,
45
+
SAR2130P_MASTER_CAMNOC_SF,
46
+
SAR2130P_MASTER_LSR,
47
+
SAR2130P_MASTER_MDP,
48
+
SAR2130P_MASTER_CNOC_MNOC_CFG,
49
+
SAR2130P_MASTER_VIDEO,
50
+
SAR2130P_MASTER_VIDEO_CV_PROC,
51
+
SAR2130P_MASTER_VIDEO_PROC,
52
+
SAR2130P_MASTER_VIDEO_V_PROC,
53
+
SAR2130P_MASTER_CDSP_NOC_CFG,
54
+
SAR2130P_MASTER_CDSP_PROC,
55
+
SAR2130P_MASTER_PCIE_0,
56
+
SAR2130P_MASTER_PCIE_1,
57
+
SAR2130P_MASTER_GIC_AHB,
58
+
SAR2130P_MASTER_QDSS_BAM,
59
+
SAR2130P_MASTER_QSPI_0,
60
+
SAR2130P_MASTER_QUP_0,
61
+
SAR2130P_MASTER_QUP_1,
62
+
SAR2130P_MASTER_A2NOC_SNOC,
63
+
SAR2130P_MASTER_CNOC_DATAPATH,
64
+
SAR2130P_MASTER_LPASS_ANOC,
65
+
SAR2130P_MASTER_SNOC_CFG,
66
+
SAR2130P_MASTER_CRYPTO,
67
+
SAR2130P_MASTER_PIMEM,
68
+
SAR2130P_MASTER_GIC,
69
+
SAR2130P_MASTER_QDSS_ETR,
70
+
SAR2130P_MASTER_QDSS_ETR_1,
71
+
SAR2130P_MASTER_SDCC_1,
72
+
SAR2130P_MASTER_USB3_0,
73
+
SAR2130P_SLAVE_QUP_CORE_0,
74
+
SAR2130P_SLAVE_QUP_CORE_1,
75
+
SAR2130P_SLAVE_AHB2PHY_SOUTH,
76
+
SAR2130P_SLAVE_AOSS,
77
+
SAR2130P_SLAVE_CAMERA_CFG,
78
+
SAR2130P_SLAVE_CLK_CTL,
79
+
SAR2130P_SLAVE_CDSP_CFG,
80
+
SAR2130P_SLAVE_RBCPR_CX_CFG,
81
+
SAR2130P_SLAVE_RBCPR_MMCX_CFG,
82
+
SAR2130P_SLAVE_RBCPR_MXA_CFG,
83
+
SAR2130P_SLAVE_RBCPR_MXC_CFG,
84
+
SAR2130P_SLAVE_CPR_NSPCX,
85
+
SAR2130P_SLAVE_CRYPTO_0_CFG,
86
+
SAR2130P_SLAVE_CX_RDPM,
87
+
SAR2130P_SLAVE_DISPLAY_CFG,
88
+
SAR2130P_SLAVE_GFX3D_CFG,
89
+
SAR2130P_SLAVE_IMEM_CFG,
90
+
SAR2130P_SLAVE_IPC_ROUTER_CFG,
91
+
SAR2130P_SLAVE_LPASS,
92
+
SAR2130P_SLAVE_MX_RDPM,
93
+
SAR2130P_SLAVE_PCIE_0_CFG,
94
+
SAR2130P_SLAVE_PCIE_1_CFG,
95
+
SAR2130P_SLAVE_PDM,
96
+
SAR2130P_SLAVE_PIMEM_CFG,
97
+
SAR2130P_SLAVE_PRNG,
98
+
SAR2130P_SLAVE_QDSS_CFG,
99
+
SAR2130P_SLAVE_QSPI_0,
100
+
SAR2130P_SLAVE_QUP_0,
101
+
SAR2130P_SLAVE_QUP_1,
102
+
SAR2130P_SLAVE_SDCC_1,
103
+
SAR2130P_SLAVE_TCSR,
104
+
SAR2130P_SLAVE_TLMM,
105
+
SAR2130P_SLAVE_TME_CFG,
106
+
SAR2130P_SLAVE_USB3_0,
107
+
SAR2130P_SLAVE_VENUS_CFG,
108
+
SAR2130P_SLAVE_VSENSE_CTRL_CFG,
109
+
SAR2130P_SLAVE_WLAN_Q6_CFG,
110
+
SAR2130P_SLAVE_DDRSS_CFG,
111
+
SAR2130P_SLAVE_CNOC_MNOC_CFG,
112
+
SAR2130P_SLAVE_SNOC_CFG,
113
+
SAR2130P_SLAVE_IMEM,
114
+
SAR2130P_SLAVE_PIMEM,
115
+
SAR2130P_SLAVE_SERVICE_CNOC,
116
+
SAR2130P_SLAVE_PCIE_0,
117
+
SAR2130P_SLAVE_PCIE_1,
118
+
SAR2130P_SLAVE_QDSS_STM,
119
+
SAR2130P_SLAVE_TCU,
120
+
SAR2130P_SLAVE_GEM_NOC_CNOC,
121
+
SAR2130P_SLAVE_LLCC,
122
+
SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC,
123
+
SAR2130P_SLAVE_LPASS_CORE_CFG,
124
+
SAR2130P_SLAVE_LPASS_LPI_CFG,
125
+
SAR2130P_SLAVE_LPASS_MPU_CFG,
126
+
SAR2130P_SLAVE_LPASS_TOP_CFG,
127
+
SAR2130P_SLAVE_LPASS_SNOC,
128
+
SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC,
129
+
SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC,
130
+
SAR2130P_SLAVE_EBI1,
131
+
SAR2130P_SLAVE_MNOC_HF_MEM_NOC,
132
+
SAR2130P_SLAVE_MNOC_SF_MEM_NOC,
133
+
SAR2130P_SLAVE_SERVICE_MNOC,
134
+
SAR2130P_SLAVE_CDSP_MEM_NOC,
135
+
SAR2130P_SLAVE_SERVICE_NSP_NOC,
136
+
SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC,
137
+
SAR2130P_SLAVE_A2NOC_SNOC,
138
+
SAR2130P_SLAVE_SNOC_GEM_NOC_GC,
139
+
SAR2130P_SLAVE_SNOC_GEM_NOC_SF,
140
+
SAR2130P_SLAVE_SERVICE_SNOC,
141
+
};
142
+
143
+
static const struct regmap_config icc_regmap_config = {
144
+
.reg_bits = 32,
145
+
.reg_stride = 4,
146
+
.val_bits = 32,
147
+
.fast_io = true,
148
+
};
149
+
150
+
static struct qcom_icc_node qup0_core_master = {
151
+
.name = "qup0_core_master",
152
+
.id = SAR2130P_MASTER_QUP_CORE_0,
153
+
.channels = 1,
154
+
.buswidth = 4,
155
+
.num_links = 1,
156
+
.links = { SAR2130P_SLAVE_QUP_CORE_0 },
157
+
};
158
+
159
+
static struct qcom_icc_node qup1_core_master = {
160
+
.name = "qup1_core_master",
161
+
.id = SAR2130P_MASTER_QUP_CORE_1,
162
+
.channels = 1,
163
+
.buswidth = 4,
164
+
.num_links = 1,
165
+
.links = { SAR2130P_SLAVE_QUP_CORE_1 },
166
+
};
167
+
168
+
static struct qcom_icc_node qnm_gemnoc_cnoc = {
169
+
.name = "qnm_gemnoc_cnoc",
170
+
.id = SAR2130P_MASTER_GEM_NOC_CNOC,
171
+
.channels = 1,
172
+
.buswidth = 16,
173
+
.num_links = 43,
174
+
.links = { SAR2130P_SLAVE_AHB2PHY_SOUTH, SAR2130P_SLAVE_AOSS,
175
+
SAR2130P_SLAVE_CAMERA_CFG, SAR2130P_SLAVE_CLK_CTL,
176
+
SAR2130P_SLAVE_CDSP_CFG, SAR2130P_SLAVE_RBCPR_CX_CFG,
177
+
SAR2130P_SLAVE_RBCPR_MMCX_CFG, SAR2130P_SLAVE_RBCPR_MXA_CFG,
178
+
SAR2130P_SLAVE_RBCPR_MXC_CFG, SAR2130P_SLAVE_CPR_NSPCX,
179
+
SAR2130P_SLAVE_CRYPTO_0_CFG, SAR2130P_SLAVE_CX_RDPM,
180
+
SAR2130P_SLAVE_DISPLAY_CFG, SAR2130P_SLAVE_GFX3D_CFG,
181
+
SAR2130P_SLAVE_IMEM_CFG, SAR2130P_SLAVE_IPC_ROUTER_CFG,
182
+
SAR2130P_SLAVE_LPASS, SAR2130P_SLAVE_MX_RDPM,
183
+
SAR2130P_SLAVE_PCIE_0_CFG, SAR2130P_SLAVE_PCIE_1_CFG,
184
+
SAR2130P_SLAVE_PDM, SAR2130P_SLAVE_PIMEM_CFG,
185
+
SAR2130P_SLAVE_PRNG, SAR2130P_SLAVE_QDSS_CFG,
186
+
SAR2130P_SLAVE_QSPI_0, SAR2130P_SLAVE_QUP_0,
187
+
SAR2130P_SLAVE_QUP_1, SAR2130P_SLAVE_SDCC_1,
188
+
SAR2130P_SLAVE_TCSR, SAR2130P_SLAVE_TLMM,
189
+
SAR2130P_SLAVE_TME_CFG, SAR2130P_SLAVE_USB3_0,
190
+
SAR2130P_SLAVE_VENUS_CFG, SAR2130P_SLAVE_VSENSE_CTRL_CFG,
191
+
SAR2130P_SLAVE_WLAN_Q6_CFG, SAR2130P_SLAVE_DDRSS_CFG,
192
+
SAR2130P_SLAVE_CNOC_MNOC_CFG, SAR2130P_SLAVE_SNOC_CFG,
193
+
SAR2130P_SLAVE_IMEM, SAR2130P_SLAVE_PIMEM,
194
+
SAR2130P_SLAVE_SERVICE_CNOC, SAR2130P_SLAVE_QDSS_STM,
195
+
SAR2130P_SLAVE_TCU },
196
+
};
197
+
198
+
static struct qcom_icc_node qnm_gemnoc_pcie = {
199
+
.name = "qnm_gemnoc_pcie",
200
+
.id = SAR2130P_MASTER_GEM_NOC_PCIE_SNOC,
201
+
.channels = 1,
202
+
.buswidth = 8,
203
+
.num_links = 2,
204
+
.links = { SAR2130P_SLAVE_PCIE_0, SAR2130P_SLAVE_PCIE_1 },
205
+
};
206
+
207
+
static struct qcom_icc_node xm_qdss_dap = {
208
+
.name = "xm_qdss_dap",
209
+
.id = SAR2130P_MASTER_QDSS_DAP,
210
+
.channels = 1,
211
+
.buswidth = 8,
212
+
.num_links = 43,
213
+
.links = { SAR2130P_SLAVE_AHB2PHY_SOUTH, SAR2130P_SLAVE_AOSS,
214
+
SAR2130P_SLAVE_CAMERA_CFG, SAR2130P_SLAVE_CLK_CTL,
215
+
SAR2130P_SLAVE_CDSP_CFG, SAR2130P_SLAVE_RBCPR_CX_CFG,
216
+
SAR2130P_SLAVE_RBCPR_MMCX_CFG, SAR2130P_SLAVE_RBCPR_MXA_CFG,
217
+
SAR2130P_SLAVE_RBCPR_MXC_CFG, SAR2130P_SLAVE_CPR_NSPCX,
218
+
SAR2130P_SLAVE_CRYPTO_0_CFG, SAR2130P_SLAVE_CX_RDPM,
219
+
SAR2130P_SLAVE_DISPLAY_CFG, SAR2130P_SLAVE_GFX3D_CFG,
220
+
SAR2130P_SLAVE_IMEM_CFG, SAR2130P_SLAVE_IPC_ROUTER_CFG,
221
+
SAR2130P_SLAVE_LPASS, SAR2130P_SLAVE_MX_RDPM,
222
+
SAR2130P_SLAVE_PCIE_0_CFG, SAR2130P_SLAVE_PCIE_1_CFG,
223
+
SAR2130P_SLAVE_PDM, SAR2130P_SLAVE_PIMEM_CFG,
224
+
SAR2130P_SLAVE_PRNG, SAR2130P_SLAVE_QDSS_CFG,
225
+
SAR2130P_SLAVE_QSPI_0, SAR2130P_SLAVE_QUP_0,
226
+
SAR2130P_SLAVE_QUP_1, SAR2130P_SLAVE_SDCC_1,
227
+
SAR2130P_SLAVE_TCSR, SAR2130P_SLAVE_TLMM,
228
+
SAR2130P_SLAVE_TME_CFG, SAR2130P_SLAVE_USB3_0,
229
+
SAR2130P_SLAVE_VENUS_CFG, SAR2130P_SLAVE_VSENSE_CTRL_CFG,
230
+
SAR2130P_SLAVE_WLAN_Q6_CFG, SAR2130P_SLAVE_DDRSS_CFG,
231
+
SAR2130P_SLAVE_CNOC_MNOC_CFG, SAR2130P_SLAVE_SNOC_CFG,
232
+
SAR2130P_SLAVE_IMEM, SAR2130P_SLAVE_PIMEM,
233
+
SAR2130P_SLAVE_SERVICE_CNOC, SAR2130P_SLAVE_QDSS_STM,
234
+
SAR2130P_SLAVE_TCU },
235
+
};
236
+
237
+
static const struct qcom_icc_qosbox alm_gpu_tcu_qos = {
238
+
.num_ports = 1,
239
+
.port_offsets = { 0x9e000 },
240
+
.prio = 1,
241
+
.urg_fwd = 0,
242
+
.prio_fwd_disable = 1,
243
+
};
244
+
245
+
static struct qcom_icc_node alm_gpu_tcu = {
246
+
.name = "alm_gpu_tcu",
247
+
.id = SAR2130P_MASTER_GPU_TCU,
248
+
.channels = 1,
249
+
.buswidth = 8,
250
+
.qosbox = &alm_gpu_tcu_qos,
251
+
.num_links = 2,
252
+
.links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
253
+
};
254
+
255
+
static const struct qcom_icc_qosbox alm_sys_tcu_qos = {
256
+
.num_ports = 1,
257
+
.port_offsets = { 0x9f000 },
258
+
.prio = 6,
259
+
.urg_fwd = 0,
260
+
.prio_fwd_disable = 1,
261
+
};
262
+
263
+
static struct qcom_icc_node alm_sys_tcu = {
264
+
.name = "alm_sys_tcu",
265
+
.id = SAR2130P_MASTER_SYS_TCU,
266
+
.channels = 1,
267
+
.buswidth = 8,
268
+
.qosbox = &alm_sys_tcu_qos,
269
+
.num_links = 2,
270
+
.links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
271
+
};
272
+
273
+
static struct qcom_icc_node chm_apps = {
274
+
.name = "chm_apps",
275
+
.id = SAR2130P_MASTER_APPSS_PROC,
276
+
.channels = 1,
277
+
.buswidth = 32,
278
+
.num_links = 3,
279
+
.links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC,
280
+
SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC },
281
+
};
282
+
283
+
static const struct qcom_icc_qosbox qnm_gpu_qos = {
284
+
.num_ports = 2,
285
+
.port_offsets = { 0xe000, 0x4e000 },
286
+
.prio = 0,
287
+
.urg_fwd = 0,
288
+
.prio_fwd_disable = 1,
289
+
};
290
+
291
+
static struct qcom_icc_node qnm_gpu = {
292
+
.name = "qnm_gpu",
293
+
.id = SAR2130P_MASTER_GFX3D,
294
+
.channels = 2,
295
+
.buswidth = 32,
296
+
.qosbox = &qnm_gpu_qos,
297
+
.num_links = 2,
298
+
.links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
299
+
};
300
+
301
+
static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
302
+
.num_ports = 2,
303
+
.port_offsets = { 0xf000, 0x4f000 },
304
+
.prio = 0,
305
+
.urg_fwd = 1,
306
+
};
307
+
308
+
static struct qcom_icc_node qnm_mnoc_hf = {
309
+
.name = "qnm_mnoc_hf",
310
+
.id = SAR2130P_MASTER_MNOC_HF_MEM_NOC,
311
+
.channels = 2,
312
+
.buswidth = 32,
313
+
.qosbox = &qnm_mnoc_hf_qos,
314
+
.num_links = 2,
315
+
.links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
316
+
};
317
+
318
+
static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
319
+
.num_ports = 1,
320
+
.port_offsets = { 0x9d000 },
321
+
.prio = 0,
322
+
.urg_fwd = 1,
323
+
};
324
+
325
+
static struct qcom_icc_node qnm_mnoc_sf = {
326
+
.name = "qnm_mnoc_sf",
327
+
.id = SAR2130P_MASTER_MNOC_SF_MEM_NOC,
328
+
.channels = 1,
329
+
.buswidth = 32,
330
+
.qosbox = &qnm_mnoc_sf_qos,
331
+
.num_links = 2,
332
+
.links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
333
+
};
334
+
335
+
static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
336
+
.num_ports = 2,
337
+
.port_offsets = { 0x10000, 0x50000 },
338
+
.prio = 0,
339
+
.urg_fwd = 0,
340
+
.prio_fwd_disable = 1,
341
+
};
342
+
343
+
static struct qcom_icc_node qnm_nsp_gemnoc = {
344
+
.name = "qnm_nsp_gemnoc",
345
+
.id = SAR2130P_MASTER_COMPUTE_NOC,
346
+
.channels = 2,
347
+
.buswidth = 32,
348
+
.qosbox = &qnm_nsp_gemnoc_qos,
349
+
.num_links = 2,
350
+
.links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
351
+
};
352
+
353
+
static const struct qcom_icc_qosbox qnm_pcie_qos = {
354
+
.num_ports = 1,
355
+
.port_offsets = { 0xa2000 },
356
+
.prio = 2,
357
+
.urg_fwd = 1,
358
+
};
359
+
360
+
static struct qcom_icc_node qnm_pcie = {
361
+
.name = "qnm_pcie",
362
+
.id = SAR2130P_MASTER_ANOC_PCIE_GEM_NOC,
363
+
.channels = 1,
364
+
.buswidth = 16,
365
+
.qosbox = &qnm_pcie_qos,
366
+
.num_links = 2,
367
+
.links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC },
368
+
};
369
+
370
+
static const struct qcom_icc_qosbox qnm_snoc_gc_qos = {
371
+
.num_ports = 1,
372
+
.port_offsets = { 0xa0000 },
373
+
.prio = 0,
374
+
.urg_fwd = 1,
375
+
};
376
+
377
+
static struct qcom_icc_node qnm_snoc_gc = {
378
+
.name = "qnm_snoc_gc",
379
+
.id = SAR2130P_MASTER_SNOC_GC_MEM_NOC,
380
+
.channels = 1,
381
+
.buswidth = 8,
382
+
.qosbox = &qnm_snoc_gc_qos,
383
+
.num_links = 1,
384
+
.links = { SAR2130P_SLAVE_LLCC },
385
+
};
386
+
387
+
static const struct qcom_icc_qosbox qnm_snoc_sf_qos = {
388
+
.num_ports = 1,
389
+
.port_offsets = { 0xa1000 },
390
+
.prio = 0,
391
+
.urg_fwd = 1,
392
+
};
393
+
394
+
static struct qcom_icc_node qnm_snoc_sf = {
395
+
.name = "qnm_snoc_sf",
396
+
.id = SAR2130P_MASTER_SNOC_SF_MEM_NOC,
397
+
.channels = 1,
398
+
.buswidth = 16,
399
+
.qosbox = &qnm_snoc_sf_qos,
400
+
.num_links = 3,
401
+
.links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC,
402
+
SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC },
403
+
};
404
+
405
+
static struct qcom_icc_node qxm_wlan_q6 = {
406
+
.name = "qxm_wlan_q6",
407
+
.id = SAR2130P_MASTER_WLAN_Q6,
408
+
.channels = 1,
409
+
.buswidth = 8,
410
+
.num_links = 3,
411
+
.links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC,
412
+
SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC },
413
+
};
414
+
415
+
static struct qcom_icc_node qhm_config_noc = {
416
+
.name = "qhm_config_noc",
417
+
.id = SAR2130P_MASTER_CNOC_LPASS_AG_NOC,
418
+
.channels = 1,
419
+
.buswidth = 4,
420
+
.num_links = 6,
421
+
.links = { SAR2130P_SLAVE_LPASS_CORE_CFG, SAR2130P_SLAVE_LPASS_LPI_CFG,
422
+
SAR2130P_SLAVE_LPASS_MPU_CFG, SAR2130P_SLAVE_LPASS_TOP_CFG,
423
+
SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC },
424
+
};
425
+
426
+
static struct qcom_icc_node qxm_lpass_dsp = {
427
+
.name = "qxm_lpass_dsp",
428
+
.id = SAR2130P_MASTER_LPASS_PROC,
429
+
.channels = 1,
430
+
.buswidth = 8,
431
+
.num_links = 4,
432
+
.links = { SAR2130P_SLAVE_LPASS_TOP_CFG, SAR2130P_SLAVE_LPASS_SNOC,
433
+
SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC },
434
+
};
435
+
436
+
static struct qcom_icc_node llcc_mc = {
437
+
.name = "llcc_mc",
438
+
.id = SAR2130P_MASTER_LLCC,
439
+
.channels = 1,
440
+
.buswidth = 4,
441
+
.num_links = 1,
442
+
.links = { SAR2130P_SLAVE_EBI1 },
443
+
};
444
+
445
+
static const struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
446
+
.num_ports = 1,
447
+
.port_offsets = { 0x1c000 },
448
+
.prio = 0,
449
+
.urg_fwd = 1,
450
+
};
451
+
452
+
static struct qcom_icc_node qnm_camnoc_hf = {
453
+
.name = "qnm_camnoc_hf",
454
+
.id = SAR2130P_MASTER_CAMNOC_HF,
455
+
.channels = 1,
456
+
.buswidth = 32,
457
+
.qosbox = &qnm_camnoc_hf_qos,
458
+
.num_links = 1,
459
+
.links = { SAR2130P_SLAVE_MNOC_HF_MEM_NOC },
460
+
};
461
+
462
+
static const struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
463
+
.num_ports = 1,
464
+
.port_offsets = { 0x1c080 },
465
+
.prio = 4,
466
+
.urg_fwd = 1,
467
+
};
468
+
469
+
static struct qcom_icc_node qnm_camnoc_icp = {
470
+
.name = "qnm_camnoc_icp",
471
+
.id = SAR2130P_MASTER_CAMNOC_ICP,
472
+
.channels = 1,
473
+
.buswidth = 8,
474
+
.qosbox = &qnm_camnoc_icp_qos,
475
+
.num_links = 1,
476
+
.links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC },
477
+
};
478
+
479
+
static const struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
480
+
.num_ports = 1,
481
+
.port_offsets = { 0x1c100 },
482
+
.prio = 0,
483
+
.urg_fwd = 1,
484
+
};
485
+
486
+
static struct qcom_icc_node qnm_camnoc_sf = {
487
+
.name = "qnm_camnoc_sf",
488
+
.id = SAR2130P_MASTER_CAMNOC_SF,
489
+
.channels = 1,
490
+
.buswidth = 32,
491
+
.qosbox = &qnm_camnoc_sf_qos,
492
+
.num_links = 1,
493
+
.links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC },
494
+
};
495
+
496
+
static const struct qcom_icc_qosbox qnm_lsr_qos = {
497
+
.num_ports = 2,
498
+
.port_offsets = { 0x1f000, 0x1f080 },
499
+
.prio = 3,
500
+
.urg_fwd = 1,
501
+
};
502
+
503
+
static struct qcom_icc_node qnm_lsr = {
504
+
.name = "qnm_lsr",
505
+
.id = SAR2130P_MASTER_LSR,
506
+
.channels = 2,
507
+
.buswidth = 32,
508
+
.qosbox = &qnm_lsr_qos,
509
+
.num_links = 1,
510
+
.links = { SAR2130P_SLAVE_MNOC_HF_MEM_NOC },
511
+
};
512
+
513
+
static const struct qcom_icc_qosbox qnm_mdp_qos = {
514
+
.num_ports = 2,
515
+
.port_offsets = { 0x1d000, 0x1d080 },
516
+
.prio = 0,
517
+
.urg_fwd = 1,
518
+
};
519
+
520
+
static struct qcom_icc_node qnm_mdp = {
521
+
.name = "qnm_mdp",
522
+
.id = SAR2130P_MASTER_MDP,
523
+
.channels = 2,
524
+
.buswidth = 32,
525
+
.qosbox = &qnm_mdp_qos,
526
+
.num_links = 1,
527
+
.links = { SAR2130P_SLAVE_MNOC_HF_MEM_NOC },
528
+
};
529
+
530
+
static struct qcom_icc_node qnm_mnoc_cfg = {
531
+
.name = "qnm_mnoc_cfg",
532
+
.id = SAR2130P_MASTER_CNOC_MNOC_CFG,
533
+
.channels = 1,
534
+
.buswidth = 4,
535
+
.num_links = 1,
536
+
.links = { SAR2130P_SLAVE_SERVICE_MNOC },
537
+
};
538
+
539
+
static const struct qcom_icc_qosbox qnm_video_qos = {
540
+
.num_ports = 2,
541
+
.port_offsets = { 0x1e000, 0x1e080 },
542
+
.prio = 0,
543
+
.urg_fwd = 1,
544
+
};
545
+
546
+
static struct qcom_icc_node qnm_video = {
547
+
.name = "qnm_video",
548
+
.id = SAR2130P_MASTER_VIDEO,
549
+
.channels = 2,
550
+
.buswidth = 32,
551
+
.qosbox = &qnm_video_qos,
552
+
.num_links = 1,
553
+
.links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC },
554
+
};
555
+
556
+
static const struct qcom_icc_qosbox qnm_video_cv_cpu_qos = {
557
+
.num_ports = 1,
558
+
.port_offsets = { 0x1e100 },
559
+
.prio = 4,
560
+
.urg_fwd = 1,
561
+
};
562
+
563
+
static struct qcom_icc_node qnm_video_cv_cpu = {
564
+
.name = "qnm_video_cv_cpu",
565
+
.id = SAR2130P_MASTER_VIDEO_CV_PROC,
566
+
.channels = 1,
567
+
.buswidth = 8,
568
+
.qosbox = &qnm_video_cv_cpu_qos,
569
+
.num_links = 1,
570
+
.links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC },
571
+
};
572
+
573
+
static const struct qcom_icc_qosbox qnm_video_cvp_qos = {
574
+
.num_ports = 1,
575
+
.port_offsets = { 0x1e180 },
576
+
.prio = 0,
577
+
.urg_fwd = 1,
578
+
};
579
+
580
+
static struct qcom_icc_node qnm_video_cvp = {
581
+
.name = "qnm_video_cvp",
582
+
.id = SAR2130P_MASTER_VIDEO_PROC,
583
+
.channels = 1,
584
+
.buswidth = 32,
585
+
.qosbox = &qnm_video_cvp_qos,
586
+
.num_links = 1,
587
+
.links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC },
588
+
};
589
+
590
+
static const struct qcom_icc_qosbox qnm_video_v_cpu_qos = {
591
+
.num_ports = 1,
592
+
.port_offsets = { 0x1e200 },
593
+
.prio = 4,
594
+
.urg_fwd = 1,
595
+
};
596
+
597
+
static struct qcom_icc_node qnm_video_v_cpu = {
598
+
.name = "qnm_video_v_cpu",
599
+
.id = SAR2130P_MASTER_VIDEO_V_PROC,
600
+
.channels = 1,
601
+
.buswidth = 8,
602
+
.qosbox = &qnm_video_v_cpu_qos,
603
+
.num_links = 1,
604
+
.links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC },
605
+
};
606
+
607
+
static struct qcom_icc_node qhm_nsp_noc_config = {
608
+
.name = "qhm_nsp_noc_config",
609
+
.id = SAR2130P_MASTER_CDSP_NOC_CFG,
610
+
.channels = 1,
611
+
.buswidth = 4,
612
+
.num_links = 1,
613
+
.links = { SAR2130P_SLAVE_SERVICE_NSP_NOC },
614
+
};
615
+
616
+
static struct qcom_icc_node qxm_nsp = {
617
+
.name = "qxm_nsp",
618
+
.id = SAR2130P_MASTER_CDSP_PROC,
619
+
.channels = 2,
620
+
.buswidth = 32,
621
+
.num_links = 1,
622
+
.links = { SAR2130P_SLAVE_CDSP_MEM_NOC },
623
+
};
624
+
625
+
static const struct qcom_icc_qosbox xm_pcie3_0_qos = {
626
+
.num_ports = 1,
627
+
.port_offsets = { 0x9000 },
628
+
.prio = 3,
629
+
.urg_fwd = 0,
630
+
.prio_fwd_disable = 1,
631
+
};
632
+
633
+
static struct qcom_icc_node xm_pcie3_0 = {
634
+
.name = "xm_pcie3_0",
635
+
.id = SAR2130P_MASTER_PCIE_0,
636
+
.channels = 1,
637
+
.buswidth = 8,
638
+
.qosbox = &xm_pcie3_0_qos,
639
+
.num_links = 1,
640
+
.links = { SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC },
641
+
};
642
+
643
+
static const struct qcom_icc_qosbox xm_pcie3_1_qos = {
644
+
.num_ports = 1,
645
+
.port_offsets = { 0xa000 },
646
+
.prio = 2,
647
+
.urg_fwd = 0,
648
+
.prio_fwd_disable = 1,
649
+
};
650
+
651
+
static struct qcom_icc_node xm_pcie3_1 = {
652
+
.name = "xm_pcie3_1",
653
+
.id = SAR2130P_MASTER_PCIE_1,
654
+
.channels = 1,
655
+
.buswidth = 8,
656
+
.qosbox = &xm_pcie3_1_qos,
657
+
.num_links = 1,
658
+
.links = { SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC },
659
+
};
660
+
661
+
static const struct qcom_icc_qosbox qhm_gic_qos = {
662
+
.num_ports = 1,
663
+
.port_offsets = { 0x1d000 },
664
+
.prio = 2,
665
+
.urg_fwd = 0,
666
+
.prio_fwd_disable = 1,
667
+
};
668
+
669
+
static struct qcom_icc_node qhm_gic = {
670
+
.name = "qhm_gic",
671
+
.id = SAR2130P_MASTER_GIC_AHB,
672
+
.channels = 1,
673
+
.buswidth = 4,
674
+
.qosbox = &qhm_gic_qos,
675
+
.num_links = 1,
676
+
.links = { SAR2130P_SLAVE_SNOC_GEM_NOC_SF },
677
+
};
678
+
679
+
static const struct qcom_icc_qosbox qhm_qdss_bam_qos = {
680
+
.num_ports = 1,
681
+
.port_offsets = { 0x22000 },
682
+
.prio = 2,
683
+
.urg_fwd = 0,
684
+
.prio_fwd_disable = 1,
685
+
};
686
+
687
+
static struct qcom_icc_node qhm_qdss_bam = {
688
+
.name = "qhm_qdss_bam",
689
+
.id = SAR2130P_MASTER_QDSS_BAM,
690
+
.channels = 1,
691
+
.buswidth = 4,
692
+
.qosbox = &qhm_qdss_bam_qos,
693
+
.num_links = 1,
694
+
.links = { SAR2130P_SLAVE_A2NOC_SNOC },
695
+
};
696
+
697
+
static const struct qcom_icc_qosbox qhm_qspi_qos = {
698
+
.num_ports = 1,
699
+
.port_offsets = { 0x23000 },
700
+
.prio = 2,
701
+
.urg_fwd = 0,
702
+
.prio_fwd_disable = 1,
703
+
};
704
+
705
+
static struct qcom_icc_node qhm_qspi = {
706
+
.name = "qhm_qspi",
707
+
.id = SAR2130P_MASTER_QSPI_0,
708
+
.channels = 1,
709
+
.buswidth = 4,
710
+
.qosbox = &qhm_qspi_qos,
711
+
.num_links = 1,
712
+
.links = { SAR2130P_SLAVE_A2NOC_SNOC },
713
+
};
714
+
715
+
static const struct qcom_icc_qosbox qhm_qup0_qos = {
716
+
.num_ports = 1,
717
+
.port_offsets = { 0x24000 },
718
+
.prio = 2,
719
+
.urg_fwd = 0,
720
+
.prio_fwd_disable = 1,
721
+
};
722
+
723
+
static struct qcom_icc_node qhm_qup0 = {
724
+
.name = "qhm_qup0",
725
+
.id = SAR2130P_MASTER_QUP_0,
726
+
.channels = 1,
727
+
.buswidth = 4,
728
+
.qosbox = &qhm_qup0_qos,
729
+
.num_links = 1,
730
+
.links = { SAR2130P_SLAVE_A2NOC_SNOC },
731
+
};
732
+
733
+
static const struct qcom_icc_qosbox qhm_qup1_qos = {
734
+
.num_ports = 1,
735
+
.port_offsets = { 0x25000 },
736
+
.prio = 2,
737
+
.urg_fwd = 0,
738
+
.prio_fwd_disable = 1,
739
+
};
740
+
741
+
static struct qcom_icc_node qhm_qup1 = {
742
+
.name = "qhm_qup1",
743
+
.id = SAR2130P_MASTER_QUP_1,
744
+
.channels = 1,
745
+
.buswidth = 4,
746
+
.qosbox = &qhm_qup1_qos,
747
+
.num_links = 1,
748
+
.links = { SAR2130P_SLAVE_A2NOC_SNOC },
749
+
};
750
+
751
+
static struct qcom_icc_node qnm_aggre2_noc = {
752
+
.name = "qnm_aggre2_noc",
753
+
.id = SAR2130P_MASTER_A2NOC_SNOC,
754
+
.channels = 1,
755
+
.buswidth = 16,
756
+
.num_links = 1,
757
+
.links = { SAR2130P_SLAVE_SNOC_GEM_NOC_SF },
758
+
};
759
+
760
+
static const struct qcom_icc_qosbox qnm_cnoc_datapath_qos = {
761
+
.num_ports = 1,
762
+
.port_offsets = { 0x26000 },
763
+
.prio = 2,
764
+
.urg_fwd = 0,
765
+
.prio_fwd_disable = 1,
766
+
};
767
+
768
+
static struct qcom_icc_node qnm_cnoc_datapath = {
769
+
.name = "qnm_cnoc_datapath",
770
+
.id = SAR2130P_MASTER_CNOC_DATAPATH,
771
+
.channels = 1,
772
+
.buswidth = 8,
773
+
.qosbox = &qnm_cnoc_datapath_qos,
774
+
.num_links = 1,
775
+
.links = { SAR2130P_SLAVE_A2NOC_SNOC },
776
+
};
777
+
778
+
static const struct qcom_icc_qosbox qnm_lpass_noc_qos = {
779
+
.num_ports = 1,
780
+
.port_offsets = { 0x1e000 },
781
+
.prio = 0,
782
+
.urg_fwd = 0,
783
+
.prio_fwd_disable = 1,
784
+
};
785
+
786
+
static struct qcom_icc_node qnm_lpass_noc = {
787
+
.name = "qnm_lpass_noc",
788
+
.id = SAR2130P_MASTER_LPASS_ANOC,
789
+
.channels = 1,
790
+
.buswidth = 16,
791
+
.qosbox = &qnm_lpass_noc_qos,
792
+
.num_links = 1,
793
+
.links = { SAR2130P_SLAVE_SNOC_GEM_NOC_SF },
794
+
};
795
+
796
+
static struct qcom_icc_node qnm_snoc_cfg = {
797
+
.name = "qnm_snoc_cfg",
798
+
.id = SAR2130P_MASTER_SNOC_CFG,
799
+
.channels = 1,
800
+
.buswidth = 4,
801
+
.num_links = 1,
802
+
.links = { SAR2130P_SLAVE_SERVICE_SNOC },
803
+
};
804
+
805
+
static const struct qcom_icc_qosbox qxm_crypto_qos = {
806
+
.num_ports = 1,
807
+
.port_offsets = { 0x27000 },
808
+
.prio = 2,
809
+
.urg_fwd = 0,
810
+
.prio_fwd_disable = 1,
811
+
};
812
+
813
+
static struct qcom_icc_node qxm_crypto = {
814
+
.name = "qxm_crypto",
815
+
.id = SAR2130P_MASTER_CRYPTO,
816
+
.channels = 1,
817
+
.buswidth = 8,
818
+
.qosbox = &qxm_crypto_qos,
819
+
.num_links = 1,
820
+
.links = { SAR2130P_SLAVE_A2NOC_SNOC },
821
+
};
822
+
823
+
static const struct qcom_icc_qosbox qxm_pimem_qos = {
824
+
.num_ports = 1,
825
+
.port_offsets = { 0x1f000 },
826
+
.prio = 2,
827
+
.urg_fwd = 0,
828
+
.prio_fwd_disable = 1,
829
+
};
830
+
831
+
static struct qcom_icc_node qxm_pimem = {
832
+
.name = "qxm_pimem",
833
+
.id = SAR2130P_MASTER_PIMEM,
834
+
.channels = 1,
835
+
.buswidth = 8,
836
+
.qosbox = &qxm_pimem_qos,
837
+
.num_links = 1,
838
+
.links = { SAR2130P_SLAVE_SNOC_GEM_NOC_GC },
839
+
};
840
+
841
+
static const struct qcom_icc_qosbox xm_gic_qos = {
842
+
.num_ports = 1,
843
+
.port_offsets = { 0x21000 },
844
+
.prio = 2,
845
+
.urg_fwd = 0,
846
+
.prio_fwd_disable = 1,
847
+
};
848
+
849
+
static struct qcom_icc_node xm_gic = {
850
+
.name = "xm_gic",
851
+
.id = SAR2130P_MASTER_GIC,
852
+
.channels = 1,
853
+
.buswidth = 8,
854
+
.qosbox = &xm_gic_qos,
855
+
.num_links = 1,
856
+
.links = { SAR2130P_SLAVE_SNOC_GEM_NOC_GC },
857
+
};
858
+
859
+
static const struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
860
+
.num_ports = 1,
861
+
.port_offsets = { 0x1b000 },
862
+
.prio = 2,
863
+
.urg_fwd = 0,
864
+
.prio_fwd_disable = 1,
865
+
};
866
+
867
+
static struct qcom_icc_node xm_qdss_etr_0 = {
868
+
.name = "xm_qdss_etr_0",
869
+
.id = SAR2130P_MASTER_QDSS_ETR,
870
+
.channels = 1,
871
+
.buswidth = 8,
872
+
.qosbox = &xm_qdss_etr_0_qos,
873
+
.num_links = 1,
874
+
.links = { SAR2130P_SLAVE_A2NOC_SNOC },
875
+
};
876
+
877
+
static const struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
878
+
.num_ports = 1,
879
+
.port_offsets = { 0x1c000 },
880
+
.prio = 2,
881
+
.urg_fwd = 0,
882
+
.prio_fwd_disable = 1,
883
+
};
884
+
885
+
static struct qcom_icc_node xm_qdss_etr_1 = {
886
+
.name = "xm_qdss_etr_1",
887
+
.id = SAR2130P_MASTER_QDSS_ETR_1,
888
+
.channels = 1,
889
+
.buswidth = 8,
890
+
.qosbox = &xm_qdss_etr_1_qos,
891
+
.num_links = 1,
892
+
.links = { SAR2130P_SLAVE_A2NOC_SNOC },
893
+
};
894
+
895
+
static const struct qcom_icc_qosbox xm_sdc1_qos = {
896
+
.num_ports = 1,
897
+
.port_offsets = { 0x29000 },
898
+
.prio = 2,
899
+
.urg_fwd = 0,
900
+
.prio_fwd_disable = 1,
901
+
};
902
+
903
+
static struct qcom_icc_node xm_sdc1 = {
904
+
.name = "xm_sdc1",
905
+
.id = SAR2130P_MASTER_SDCC_1,
906
+
.channels = 1,
907
+
.buswidth = 8,
908
+
.qosbox = &xm_sdc1_qos,
909
+
.num_links = 1,
910
+
.links = { SAR2130P_SLAVE_A2NOC_SNOC },
911
+
};
912
+
913
+
static const struct qcom_icc_qosbox xm_usb3_0_qos = {
914
+
.num_ports = 1,
915
+
.port_offsets = { 0x28000 },
916
+
.prio = 2,
917
+
.urg_fwd = 0,
918
+
.prio_fwd_disable = 1,
919
+
};
920
+
921
+
static struct qcom_icc_node xm_usb3_0 = {
922
+
.name = "xm_usb3_0",
923
+
.id = SAR2130P_MASTER_USB3_0,
924
+
.channels = 1,
925
+
.buswidth = 8,
926
+
.qosbox = &xm_usb3_0_qos,
927
+
.num_links = 1,
928
+
.links = { SAR2130P_SLAVE_A2NOC_SNOC },
929
+
};
930
+
931
+
static struct qcom_icc_node qup0_core_slave = {
932
+
.name = "qup0_core_slave",
933
+
.id = SAR2130P_SLAVE_QUP_CORE_0,
934
+
.channels = 1,
935
+
.buswidth = 4,
936
+
.num_links = 0,
937
+
};
938
+
939
+
static struct qcom_icc_node qup1_core_slave = {
940
+
.name = "qup1_core_slave",
941
+
.id = SAR2130P_SLAVE_QUP_CORE_1,
942
+
.channels = 1,
943
+
.buswidth = 4,
944
+
.num_links = 0,
945
+
};
946
+
947
+
static struct qcom_icc_node qhs_ahb2phy0 = {
948
+
.name = "qhs_ahb2phy0",
949
+
.id = SAR2130P_SLAVE_AHB2PHY_SOUTH,
950
+
.channels = 1,
951
+
.buswidth = 4,
952
+
.num_links = 0,
953
+
};
954
+
955
+
static struct qcom_icc_node qhs_aoss = {
956
+
.name = "qhs_aoss",
957
+
.id = SAR2130P_SLAVE_AOSS,
958
+
.channels = 1,
959
+
.buswidth = 4,
960
+
.num_links = 0,
961
+
};
962
+
963
+
static struct qcom_icc_node qhs_camera_cfg = {
964
+
.name = "qhs_camera_cfg",
965
+
.id = SAR2130P_SLAVE_CAMERA_CFG,
966
+
.channels = 1,
967
+
.buswidth = 4,
968
+
.num_links = 0,
969
+
};
970
+
971
+
static struct qcom_icc_node qhs_clk_ctl = {
972
+
.name = "qhs_clk_ctl",
973
+
.id = SAR2130P_SLAVE_CLK_CTL,
974
+
.channels = 1,
975
+
.buswidth = 4,
976
+
.num_links = 0,
977
+
};
978
+
979
+
static struct qcom_icc_node qhs_compute_cfg = {
980
+
.name = "qhs_compute_cfg",
981
+
.id = SAR2130P_SLAVE_CDSP_CFG,
982
+
.channels = 1,
983
+
.buswidth = 4,
984
+
.num_links = 1,
985
+
.links = { SAR2130P_MASTER_CDSP_NOC_CFG },
986
+
};
987
+
988
+
static struct qcom_icc_node qhs_cpr_cx = {
989
+
.name = "qhs_cpr_cx",
990
+
.id = SAR2130P_SLAVE_RBCPR_CX_CFG,
991
+
.channels = 1,
992
+
.buswidth = 4,
993
+
.num_links = 0,
994
+
};
995
+
996
+
static struct qcom_icc_node qhs_cpr_mmcx = {
997
+
.name = "qhs_cpr_mmcx",
998
+
.id = SAR2130P_SLAVE_RBCPR_MMCX_CFG,
999
+
.channels = 1,
1000
+
.buswidth = 4,
1001
+
.num_links = 0,
1002
+
};
1003
+
1004
+
static struct qcom_icc_node qhs_cpr_mxa = {
1005
+
.name = "qhs_cpr_mxa",
1006
+
.id = SAR2130P_SLAVE_RBCPR_MXA_CFG,
1007
+
.channels = 1,
1008
+
.buswidth = 4,
1009
+
.num_links = 0,
1010
+
};
1011
+
1012
+
static struct qcom_icc_node qhs_cpr_mxc = {
1013
+
.name = "qhs_cpr_mxc",
1014
+
.id = SAR2130P_SLAVE_RBCPR_MXC_CFG,
1015
+
.channels = 1,
1016
+
.buswidth = 4,
1017
+
.num_links = 0,
1018
+
};
1019
+
1020
+
static struct qcom_icc_node qhs_cpr_nspcx = {
1021
+
.name = "qhs_cpr_nspcx",
1022
+
.id = SAR2130P_SLAVE_CPR_NSPCX,
1023
+
.channels = 1,
1024
+
.buswidth = 4,
1025
+
.num_links = 0,
1026
+
};
1027
+
1028
+
static struct qcom_icc_node qhs_crypto0_cfg = {
1029
+
.name = "qhs_crypto0_cfg",
1030
+
.id = SAR2130P_SLAVE_CRYPTO_0_CFG,
1031
+
.channels = 1,
1032
+
.buswidth = 4,
1033
+
.num_links = 0,
1034
+
};
1035
+
1036
+
static struct qcom_icc_node qhs_cx_rdpm = {
1037
+
.name = "qhs_cx_rdpm",
1038
+
.id = SAR2130P_SLAVE_CX_RDPM,
1039
+
.channels = 1,
1040
+
.buswidth = 4,
1041
+
.num_links = 0,
1042
+
};
1043
+
1044
+
static struct qcom_icc_node qhs_display_cfg = {
1045
+
.name = "qhs_display_cfg",
1046
+
.id = SAR2130P_SLAVE_DISPLAY_CFG,
1047
+
.channels = 1,
1048
+
.buswidth = 4,
1049
+
.num_links = 0,
1050
+
};
1051
+
1052
+
static struct qcom_icc_node qhs_gpuss_cfg = {
1053
+
.name = "qhs_gpuss_cfg",
1054
+
.id = SAR2130P_SLAVE_GFX3D_CFG,
1055
+
.channels = 1,
1056
+
.buswidth = 8,
1057
+
.num_links = 0,
1058
+
};
1059
+
1060
+
static struct qcom_icc_node qhs_imem_cfg = {
1061
+
.name = "qhs_imem_cfg",
1062
+
.id = SAR2130P_SLAVE_IMEM_CFG,
1063
+
.channels = 1,
1064
+
.buswidth = 4,
1065
+
.num_links = 0,
1066
+
};
1067
+
1068
+
static struct qcom_icc_node qhs_ipc_router = {
1069
+
.name = "qhs_ipc_router",
1070
+
.id = SAR2130P_SLAVE_IPC_ROUTER_CFG,
1071
+
.channels = 1,
1072
+
.buswidth = 4,
1073
+
.num_links = 0,
1074
+
};
1075
+
1076
+
static struct qcom_icc_node qhs_lpass_cfg = {
1077
+
.name = "qhs_lpass_cfg",
1078
+
.id = SAR2130P_SLAVE_LPASS,
1079
+
.channels = 1,
1080
+
.buswidth = 4,
1081
+
.num_links = 1,
1082
+
.links = { SAR2130P_MASTER_CNOC_LPASS_AG_NOC },
1083
+
};
1084
+
1085
+
static struct qcom_icc_node qhs_mx_rdpm = {
1086
+
.name = "qhs_mx_rdpm",
1087
+
.id = SAR2130P_SLAVE_MX_RDPM,
1088
+
.channels = 1,
1089
+
.buswidth = 4,
1090
+
.num_links = 0,
1091
+
};
1092
+
1093
+
static struct qcom_icc_node qhs_pcie0_cfg = {
1094
+
.name = "qhs_pcie0_cfg",
1095
+
.id = SAR2130P_SLAVE_PCIE_0_CFG,
1096
+
.channels = 1,
1097
+
.buswidth = 4,
1098
+
.num_links = 0,
1099
+
};
1100
+
1101
+
static struct qcom_icc_node qhs_pcie1_cfg = {
1102
+
.name = "qhs_pcie1_cfg",
1103
+
.id = SAR2130P_SLAVE_PCIE_1_CFG,
1104
+
.channels = 1,
1105
+
.buswidth = 4,
1106
+
.num_links = 0,
1107
+
};
1108
+
1109
+
static struct qcom_icc_node qhs_pdm = {
1110
+
.name = "qhs_pdm",
1111
+
.id = SAR2130P_SLAVE_PDM,
1112
+
.channels = 1,
1113
+
.buswidth = 4,
1114
+
.num_links = 0,
1115
+
};
1116
+
1117
+
static struct qcom_icc_node qhs_pimem_cfg = {
1118
+
.name = "qhs_pimem_cfg",
1119
+
.id = SAR2130P_SLAVE_PIMEM_CFG,
1120
+
.channels = 1,
1121
+
.buswidth = 4,
1122
+
.num_links = 0,
1123
+
};
1124
+
1125
+
static struct qcom_icc_node qhs_prng = {
1126
+
.name = "qhs_prng",
1127
+
.id = SAR2130P_SLAVE_PRNG,
1128
+
.channels = 1,
1129
+
.buswidth = 4,
1130
+
.num_links = 0,
1131
+
};
1132
+
1133
+
static struct qcom_icc_node qhs_qdss_cfg = {
1134
+
.name = "qhs_qdss_cfg",
1135
+
.id = SAR2130P_SLAVE_QDSS_CFG,
1136
+
.channels = 1,
1137
+
.buswidth = 4,
1138
+
.num_links = 0,
1139
+
};
1140
+
1141
+
static struct qcom_icc_node qhs_qspi = {
1142
+
.name = "qhs_qspi",
1143
+
.id = SAR2130P_SLAVE_QSPI_0,
1144
+
.channels = 1,
1145
+
.buswidth = 4,
1146
+
.num_links = 0,
1147
+
};
1148
+
1149
+
static struct qcom_icc_node qhs_qup0 = {
1150
+
.name = "qhs_qup0",
1151
+
.id = SAR2130P_SLAVE_QUP_0,
1152
+
.channels = 1,
1153
+
.buswidth = 4,
1154
+
.num_links = 0,
1155
+
};
1156
+
1157
+
static struct qcom_icc_node qhs_qup1 = {
1158
+
.name = "qhs_qup1",
1159
+
.id = SAR2130P_SLAVE_QUP_1,
1160
+
.channels = 1,
1161
+
.buswidth = 4,
1162
+
.num_links = 0,
1163
+
};
1164
+
1165
+
static struct qcom_icc_node qhs_sdc1 = {
1166
+
.name = "qhs_sdc1",
1167
+
.id = SAR2130P_SLAVE_SDCC_1,
1168
+
.channels = 1,
1169
+
.buswidth = 4,
1170
+
.num_links = 0,
1171
+
};
1172
+
1173
+
static struct qcom_icc_node qhs_tcsr = {
1174
+
.name = "qhs_tcsr",
1175
+
.id = SAR2130P_SLAVE_TCSR,
1176
+
.channels = 1,
1177
+
.buswidth = 4,
1178
+
.num_links = 0,
1179
+
};
1180
+
1181
+
static struct qcom_icc_node qhs_tlmm = {
1182
+
.name = "qhs_tlmm",
1183
+
.id = SAR2130P_SLAVE_TLMM,
1184
+
.channels = 1,
1185
+
.buswidth = 4,
1186
+
.num_links = 0,
1187
+
};
1188
+
1189
+
static struct qcom_icc_node qhs_tme_cfg = {
1190
+
.name = "qhs_tme_cfg",
1191
+
.id = SAR2130P_SLAVE_TME_CFG,
1192
+
.channels = 1,
1193
+
.buswidth = 4,
1194
+
.num_links = 0,
1195
+
};
1196
+
1197
+
static struct qcom_icc_node qhs_usb3_0 = {
1198
+
.name = "qhs_usb3_0",
1199
+
.id = SAR2130P_SLAVE_USB3_0,
1200
+
.channels = 1,
1201
+
.buswidth = 4,
1202
+
.num_links = 0,
1203
+
};
1204
+
1205
+
static struct qcom_icc_node qhs_venus_cfg = {
1206
+
.name = "qhs_venus_cfg",
1207
+
.id = SAR2130P_SLAVE_VENUS_CFG,
1208
+
.channels = 1,
1209
+
.buswidth = 4,
1210
+
.num_links = 0,
1211
+
};
1212
+
1213
+
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1214
+
.name = "qhs_vsense_ctrl_cfg",
1215
+
.id = SAR2130P_SLAVE_VSENSE_CTRL_CFG,
1216
+
.channels = 1,
1217
+
.buswidth = 4,
1218
+
.num_links = 0,
1219
+
};
1220
+
1221
+
static struct qcom_icc_node qhs_wlan_q6 = {
1222
+
.name = "qhs_wlan_q6",
1223
+
.id = SAR2130P_SLAVE_WLAN_Q6_CFG,
1224
+
.channels = 1,
1225
+
.buswidth = 4,
1226
+
.num_links = 0,
1227
+
};
1228
+
1229
+
static struct qcom_icc_node qns_ddrss_cfg = {
1230
+
.name = "qns_ddrss_cfg",
1231
+
.id = SAR2130P_SLAVE_DDRSS_CFG,
1232
+
.channels = 1,
1233
+
.buswidth = 4,
1234
+
.num_links = 0,
1235
+
};
1236
+
1237
+
static struct qcom_icc_node qns_mnoc_cfg = {
1238
+
.name = "qns_mnoc_cfg",
1239
+
.id = SAR2130P_SLAVE_CNOC_MNOC_CFG,
1240
+
.channels = 1,
1241
+
.buswidth = 4,
1242
+
.num_links = 1,
1243
+
.links = { SAR2130P_MASTER_CNOC_MNOC_CFG },
1244
+
};
1245
+
1246
+
static struct qcom_icc_node qns_snoc_cfg = {
1247
+
.name = "qns_snoc_cfg",
1248
+
.id = SAR2130P_SLAVE_SNOC_CFG,
1249
+
.channels = 1,
1250
+
.buswidth = 4,
1251
+
.num_links = 1,
1252
+
.links = { SAR2130P_MASTER_SNOC_CFG },
1253
+
};
1254
+
1255
+
static struct qcom_icc_node qxs_imem = {
1256
+
.name = "qxs_imem",
1257
+
.id = SAR2130P_SLAVE_IMEM,
1258
+
.channels = 1,
1259
+
.buswidth = 8,
1260
+
.num_links = 0,
1261
+
};
1262
+
1263
+
static struct qcom_icc_node qxs_pimem = {
1264
+
.name = "qxs_pimem",
1265
+
.id = SAR2130P_SLAVE_PIMEM,
1266
+
.channels = 1,
1267
+
.buswidth = 8,
1268
+
.num_links = 0,
1269
+
};
1270
+
1271
+
static struct qcom_icc_node srvc_cnoc = {
1272
+
.name = "srvc_cnoc",
1273
+
.id = SAR2130P_SLAVE_SERVICE_CNOC,
1274
+
.channels = 1,
1275
+
.buswidth = 4,
1276
+
.num_links = 0,
1277
+
};
1278
+
1279
+
static struct qcom_icc_node xs_pcie_0 = {
1280
+
.name = "xs_pcie_0",
1281
+
.id = SAR2130P_SLAVE_PCIE_0,
1282
+
.channels = 1,
1283
+
.buswidth = 8,
1284
+
.num_links = 0,
1285
+
};
1286
+
1287
+
static struct qcom_icc_node xs_pcie_1 = {
1288
+
.name = "xs_pcie_1",
1289
+
.id = SAR2130P_SLAVE_PCIE_1,
1290
+
.channels = 1,
1291
+
.buswidth = 8,
1292
+
.num_links = 0,
1293
+
};
1294
+
1295
+
static struct qcom_icc_node xs_qdss_stm = {
1296
+
.name = "xs_qdss_stm",
1297
+
.id = SAR2130P_SLAVE_QDSS_STM,
1298
+
.channels = 1,
1299
+
.buswidth = 4,
1300
+
.num_links = 0,
1301
+
};
1302
+
1303
+
static struct qcom_icc_node xs_sys_tcu_cfg = {
1304
+
.name = "xs_sys_tcu_cfg",
1305
+
.id = SAR2130P_SLAVE_TCU,
1306
+
.channels = 1,
1307
+
.buswidth = 8,
1308
+
.num_links = 0,
1309
+
};
1310
+
1311
+
static struct qcom_icc_node qns_gem_noc_cnoc = {
1312
+
.name = "qns_gem_noc_cnoc",
1313
+
.id = SAR2130P_SLAVE_GEM_NOC_CNOC,
1314
+
.channels = 1,
1315
+
.buswidth = 16,
1316
+
.num_links = 1,
1317
+
.links = { SAR2130P_MASTER_GEM_NOC_CNOC },
1318
+
};
1319
+
1320
+
static struct qcom_icc_node qns_llcc = {
1321
+
.name = "qns_llcc",
1322
+
.id = SAR2130P_SLAVE_LLCC,
1323
+
.channels = 2,
1324
+
.buswidth = 16,
1325
+
.num_links = 1,
1326
+
.links = { SAR2130P_MASTER_LLCC },
1327
+
};
1328
+
1329
+
static struct qcom_icc_node qns_pcie = {
1330
+
.name = "qns_pcie",
1331
+
.id = SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC,
1332
+
.channels = 1,
1333
+
.buswidth = 8,
1334
+
.num_links = 1,
1335
+
.links = { SAR2130P_MASTER_GEM_NOC_PCIE_SNOC },
1336
+
};
1337
+
1338
+
static struct qcom_icc_node qhs_lpass_core = {
1339
+
.name = "qhs_lpass_core",
1340
+
.id = SAR2130P_SLAVE_LPASS_CORE_CFG,
1341
+
.channels = 1,
1342
+
.buswidth = 4,
1343
+
.num_links = 0,
1344
+
};
1345
+
1346
+
static struct qcom_icc_node qhs_lpass_lpi = {
1347
+
.name = "qhs_lpass_lpi",
1348
+
.id = SAR2130P_SLAVE_LPASS_LPI_CFG,
1349
+
.channels = 1,
1350
+
.buswidth = 4,
1351
+
.num_links = 0,
1352
+
};
1353
+
1354
+
static struct qcom_icc_node qhs_lpass_mpu = {
1355
+
.name = "qhs_lpass_mpu",
1356
+
.id = SAR2130P_SLAVE_LPASS_MPU_CFG,
1357
+
.channels = 1,
1358
+
.buswidth = 4,
1359
+
.num_links = 0,
1360
+
};
1361
+
1362
+
static struct qcom_icc_node qhs_lpass_top = {
1363
+
.name = "qhs_lpass_top",
1364
+
.id = SAR2130P_SLAVE_LPASS_TOP_CFG,
1365
+
.channels = 1,
1366
+
.buswidth = 4,
1367
+
.num_links = 0,
1368
+
};
1369
+
1370
+
static struct qcom_icc_node qns_sysnoc = {
1371
+
.name = "qns_sysnoc",
1372
+
.id = SAR2130P_SLAVE_LPASS_SNOC,
1373
+
.channels = 1,
1374
+
.buswidth = 16,
1375
+
.num_links = 1,
1376
+
.links = { SAR2130P_MASTER_LPASS_ANOC },
1377
+
};
1378
+
1379
+
static struct qcom_icc_node srvc_niu_aml_noc = {
1380
+
.name = "srvc_niu_aml_noc",
1381
+
.id = SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC,
1382
+
.channels = 1,
1383
+
.buswidth = 4,
1384
+
.num_links = 0,
1385
+
};
1386
+
1387
+
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1388
+
.name = "srvc_niu_lpass_agnoc",
1389
+
.id = SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC,
1390
+
.channels = 1,
1391
+
.buswidth = 4,
1392
+
.num_links = 0,
1393
+
};
1394
+
1395
+
static struct qcom_icc_node ebi = {
1396
+
.name = "ebi",
1397
+
.id = SAR2130P_SLAVE_EBI1,
1398
+
.channels = 1,
1399
+
.buswidth = 4,
1400
+
.num_links = 0,
1401
+
};
1402
+
1403
+
static struct qcom_icc_node qns_mem_noc_hf = {
1404
+
.name = "qns_mem_noc_hf",
1405
+
.id = SAR2130P_SLAVE_MNOC_HF_MEM_NOC,
1406
+
.channels = 2,
1407
+
.buswidth = 32,
1408
+
.num_links = 1,
1409
+
.links = { SAR2130P_MASTER_MNOC_HF_MEM_NOC },
1410
+
};
1411
+
1412
+
static struct qcom_icc_node qns_mem_noc_sf = {
1413
+
.name = "qns_mem_noc_sf",
1414
+
.id = SAR2130P_SLAVE_MNOC_SF_MEM_NOC,
1415
+
.channels = 1,
1416
+
.buswidth = 32,
1417
+
.num_links = 1,
1418
+
.links = { SAR2130P_MASTER_MNOC_SF_MEM_NOC },
1419
+
};
1420
+
1421
+
static struct qcom_icc_node srvc_mnoc = {
1422
+
.name = "srvc_mnoc",
1423
+
.id = SAR2130P_SLAVE_SERVICE_MNOC,
1424
+
.channels = 1,
1425
+
.buswidth = 4,
1426
+
.num_links = 0,
1427
+
};
1428
+
1429
+
static struct qcom_icc_node qns_nsp_gemnoc = {
1430
+
.name = "qns_nsp_gemnoc",
1431
+
.id = SAR2130P_SLAVE_CDSP_MEM_NOC,
1432
+
.channels = 2,
1433
+
.buswidth = 32,
1434
+
.num_links = 1,
1435
+
.links = { SAR2130P_MASTER_COMPUTE_NOC },
1436
+
};
1437
+
1438
+
static struct qcom_icc_node service_nsp_noc = {
1439
+
.name = "service_nsp_noc",
1440
+
.id = SAR2130P_SLAVE_SERVICE_NSP_NOC,
1441
+
.channels = 1,
1442
+
.buswidth = 4,
1443
+
.num_links = 0,
1444
+
};
1445
+
1446
+
static struct qcom_icc_node qns_pcie_mem_noc = {
1447
+
.name = "qns_pcie_mem_noc",
1448
+
.id = SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC,
1449
+
.channels = 1,
1450
+
.buswidth = 16,
1451
+
.num_links = 1,
1452
+
.links = { SAR2130P_MASTER_ANOC_PCIE_GEM_NOC },
1453
+
};
1454
+
1455
+
static struct qcom_icc_node qns_a2noc_snoc = {
1456
+
.name = "qns_a2noc_snoc",
1457
+
.id = SAR2130P_SLAVE_A2NOC_SNOC,
1458
+
.channels = 1,
1459
+
.buswidth = 16,
1460
+
.num_links = 1,
1461
+
.links = { SAR2130P_MASTER_A2NOC_SNOC },
1462
+
};
1463
+
1464
+
static struct qcom_icc_node qns_gemnoc_gc = {
1465
+
.name = "qns_gemnoc_gc",
1466
+
.id = SAR2130P_SLAVE_SNOC_GEM_NOC_GC,
1467
+
.channels = 1,
1468
+
.buswidth = 8,
1469
+
.num_links = 1,
1470
+
.links = { SAR2130P_MASTER_SNOC_GC_MEM_NOC },
1471
+
};
1472
+
1473
+
static struct qcom_icc_node qns_gemnoc_sf = {
1474
+
.name = "qns_gemnoc_sf",
1475
+
.id = SAR2130P_SLAVE_SNOC_GEM_NOC_SF,
1476
+
.channels = 1,
1477
+
.buswidth = 16,
1478
+
.num_links = 1,
1479
+
.links = { SAR2130P_MASTER_SNOC_SF_MEM_NOC },
1480
+
};
1481
+
1482
+
static struct qcom_icc_node srvc_snoc = {
1483
+
.name = "srvc_snoc",
1484
+
.id = SAR2130P_SLAVE_SERVICE_SNOC,
1485
+
.channels = 1,
1486
+
.buswidth = 4,
1487
+
.num_links = 0,
1488
+
};
1489
+
1490
+
static struct qcom_icc_bcm bcm_acv = {
1491
+
.name = "ACV",
1492
+
.enable_mask = BIT(3),
1493
+
.num_nodes = 1,
1494
+
.nodes = { &ebi },
1495
+
};
1496
+
1497
+
static struct qcom_icc_bcm bcm_ce0 = {
1498
+
.name = "CE0",
1499
+
.num_nodes = 1,
1500
+
.nodes = { &qxm_crypto },
1501
+
};
1502
+
1503
+
static struct qcom_icc_bcm bcm_cn0 = {
1504
+
.name = "CN0",
1505
+
.enable_mask = BIT(0),
1506
+
.keepalive = true,
1507
+
.num_nodes = 48,
1508
+
.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1509
+
&xm_qdss_dap, &qhs_ahb2phy0,
1510
+
&qhs_aoss, &qhs_camera_cfg,
1511
+
&qhs_clk_ctl, &qhs_compute_cfg,
1512
+
&qhs_cpr_cx, &qhs_cpr_mmcx,
1513
+
&qhs_cpr_mxa, &qhs_cpr_mxc,
1514
+
&qhs_cpr_nspcx, &qhs_crypto0_cfg,
1515
+
&qhs_cx_rdpm, &qhs_display_cfg,
1516
+
&qhs_gpuss_cfg, &qhs_imem_cfg,
1517
+
&qhs_ipc_router, &qhs_lpass_cfg,
1518
+
&qhs_mx_rdpm, &qhs_pcie0_cfg,
1519
+
&qhs_pcie1_cfg, &qhs_pdm,
1520
+
&qhs_pimem_cfg, &qhs_prng,
1521
+
&qhs_qdss_cfg, &qhs_qspi,
1522
+
&qhs_qup0, &qhs_qup1,
1523
+
&qhs_sdc1, &qhs_tcsr,
1524
+
&qhs_tlmm, &qhs_tme_cfg,
1525
+
&qhs_usb3_0, &qhs_venus_cfg,
1526
+
&qhs_vsense_ctrl_cfg, &qhs_wlan_q6,
1527
+
&qns_ddrss_cfg, &qns_mnoc_cfg,
1528
+
&qns_snoc_cfg, &qxs_imem,
1529
+
&qxs_pimem, &srvc_cnoc,
1530
+
&xs_pcie_0, &xs_pcie_1,
1531
+
&xs_qdss_stm, &xs_sys_tcu_cfg },
1532
+
};
1533
+
1534
+
static struct qcom_icc_bcm bcm_co0 = {
1535
+
.name = "CO0",
1536
+
.enable_mask = BIT(0),
1537
+
.num_nodes = 2,
1538
+
.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1539
+
};
1540
+
1541
+
static struct qcom_icc_bcm bcm_mc0 = {
1542
+
.name = "MC0",
1543
+
.keepalive = true,
1544
+
.num_nodes = 1,
1545
+
.nodes = { &ebi },
1546
+
};
1547
+
1548
+
static struct qcom_icc_bcm bcm_mm0 = {
1549
+
.name = "MM0",
1550
+
.keepalive = true,
1551
+
.num_nodes = 1,
1552
+
.nodes = { &qns_mem_noc_hf },
1553
+
};
1554
+
1555
+
static struct qcom_icc_bcm bcm_mm1 = {
1556
+
.name = "MM1",
1557
+
.enable_mask = BIT(0),
1558
+
.num_nodes = 11,
1559
+
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1560
+
&qnm_camnoc_sf, &qnm_lsr,
1561
+
&qnm_mdp, &qnm_mnoc_cfg,
1562
+
&qnm_video, &qnm_video_cv_cpu,
1563
+
&qnm_video_cvp, &qnm_video_v_cpu,
1564
+
&qns_mem_noc_sf },
1565
+
};
1566
+
1567
+
static struct qcom_icc_bcm bcm_qup0 = {
1568
+
.name = "QUP0",
1569
+
.keepalive = true,
1570
+
.vote_scale = 1,
1571
+
.num_nodes = 1,
1572
+
.nodes = { &qup0_core_slave },
1573
+
};
1574
+
1575
+
static struct qcom_icc_bcm bcm_qup1 = {
1576
+
.name = "QUP1",
1577
+
.keepalive = true,
1578
+
.vote_scale = 1,
1579
+
.num_nodes = 1,
1580
+
.nodes = { &qup1_core_slave },
1581
+
};
1582
+
1583
+
static struct qcom_icc_bcm bcm_sh0 = {
1584
+
.name = "SH0",
1585
+
.keepalive = true,
1586
+
.num_nodes = 1,
1587
+
.nodes = { &qns_llcc },
1588
+
};
1589
+
1590
+
static struct qcom_icc_bcm bcm_sh1 = {
1591
+
.name = "SH1",
1592
+
.enable_mask = BIT(0),
1593
+
.num_nodes = 13,
1594
+
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1595
+
&chm_apps, &qnm_gpu,
1596
+
&qnm_mnoc_hf, &qnm_mnoc_sf,
1597
+
&qnm_nsp_gemnoc, &qnm_pcie,
1598
+
&qnm_snoc_gc, &qnm_snoc_sf,
1599
+
&qxm_wlan_q6, &qns_gem_noc_cnoc,
1600
+
&qns_pcie },
1601
+
};
1602
+
1603
+
static struct qcom_icc_bcm bcm_sn0 = {
1604
+
.name = "SN0",
1605
+
.keepalive = true,
1606
+
.num_nodes = 1,
1607
+
.nodes = { &qns_gemnoc_sf },
1608
+
};
1609
+
1610
+
static struct qcom_icc_bcm bcm_sn1 = {
1611
+
.name = "SN1",
1612
+
.enable_mask = BIT(0),
1613
+
.num_nodes = 4,
1614
+
.nodes = { &qhm_gic, &qxm_pimem,
1615
+
&xm_gic, &qns_gemnoc_gc },
1616
+
};
1617
+
1618
+
static struct qcom_icc_bcm bcm_sn3 = {
1619
+
.name = "SN3",
1620
+
.num_nodes = 1,
1621
+
.nodes = { &qnm_aggre2_noc },
1622
+
};
1623
+
1624
+
static struct qcom_icc_bcm bcm_sn4 = {
1625
+
.name = "SN4",
1626
+
.num_nodes = 1,
1627
+
.nodes = { &qnm_lpass_noc },
1628
+
};
1629
+
1630
+
static struct qcom_icc_bcm bcm_sn7 = {
1631
+
.name = "SN7",
1632
+
.num_nodes = 1,
1633
+
.nodes = { &qns_pcie_mem_noc },
1634
+
};
1635
+
1636
+
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1637
+
&bcm_qup0,
1638
+
&bcm_qup1,
1639
+
};
1640
+
1641
+
static struct qcom_icc_node * const clk_virt_nodes[] = {
1642
+
[MASTER_QUP_CORE_0] = &qup0_core_master,
1643
+
[MASTER_QUP_CORE_1] = &qup1_core_master,
1644
+
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
1645
+
[SLAVE_QUP_CORE_1] = &qup1_core_slave,
1646
+
};
1647
+
1648
+
static const struct qcom_icc_desc sar2130p_clk_virt = {
1649
+
.nodes = clk_virt_nodes,
1650
+
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
1651
+
.bcms = clk_virt_bcms,
1652
+
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
1653
+
};
1654
+
1655
+
static struct qcom_icc_bcm * const config_noc_bcms[] = {
1656
+
&bcm_cn0,
1657
+
};
1658
+
1659
+
static struct qcom_icc_node * const config_noc_nodes[] = {
1660
+
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1661
+
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1662
+
[MASTER_QDSS_DAP] = &xm_qdss_dap,
1663
+
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1664
+
[SLAVE_AOSS] = &qhs_aoss,
1665
+
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1666
+
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1667
+
[SLAVE_CDSP_CFG] = &qhs_compute_cfg,
1668
+
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1669
+
[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1670
+
[SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
1671
+
[SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc,
1672
+
[SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
1673
+
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1674
+
[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1675
+
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1676
+
[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1677
+
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1678
+
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1679
+
[SLAVE_LPASS] = &qhs_lpass_cfg,
1680
+
[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1681
+
[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1682
+
[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1683
+
[SLAVE_PDM] = &qhs_pdm,
1684
+
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1685
+
[SLAVE_PRNG] = &qhs_prng,
1686
+
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1687
+
[SLAVE_QSPI_0] = &qhs_qspi,
1688
+
[SLAVE_QUP_0] = &qhs_qup0,
1689
+
[SLAVE_QUP_1] = &qhs_qup1,
1690
+
[SLAVE_SDCC_1] = &qhs_sdc1,
1691
+
[SLAVE_TCSR] = &qhs_tcsr,
1692
+
[SLAVE_TLMM] = &qhs_tlmm,
1693
+
[SLAVE_TME_CFG] = &qhs_tme_cfg,
1694
+
[SLAVE_USB3_0] = &qhs_usb3_0,
1695
+
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1696
+
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1697
+
[SLAVE_WLAN_Q6_CFG] = &qhs_wlan_q6,
1698
+
[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1699
+
[SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
1700
+
[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1701
+
[SLAVE_IMEM] = &qxs_imem,
1702
+
[SLAVE_PIMEM] = &qxs_pimem,
1703
+
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1704
+
[SLAVE_PCIE_0] = &xs_pcie_0,
1705
+
[SLAVE_PCIE_1] = &xs_pcie_1,
1706
+
[SLAVE_QDSS_STM] = &xs_qdss_stm,
1707
+
[SLAVE_TCU] = &xs_sys_tcu_cfg,
1708
+
};
1709
+
1710
+
static const struct qcom_icc_desc sar2130p_config_noc = {
1711
+
.config = &icc_regmap_config,
1712
+
.nodes = config_noc_nodes,
1713
+
.num_nodes = ARRAY_SIZE(config_noc_nodes),
1714
+
.bcms = config_noc_bcms,
1715
+
.num_bcms = ARRAY_SIZE(config_noc_bcms),
1716
+
};
1717
+
1718
+
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1719
+
&bcm_sh0,
1720
+
&bcm_sh1,
1721
+
};
1722
+
1723
+
static struct qcom_icc_node * const gem_noc_nodes[] = {
1724
+
[MASTER_GPU_TCU] = &alm_gpu_tcu,
1725
+
[MASTER_SYS_TCU] = &alm_sys_tcu,
1726
+
[MASTER_APPSS_PROC] = &chm_apps,
1727
+
[MASTER_GFX3D] = &qnm_gpu,
1728
+
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1729
+
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1730
+
[MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1731
+
[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1732
+
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1733
+
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1734
+
[MASTER_WLAN_Q6] = &qxm_wlan_q6,
1735
+
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1736
+
[SLAVE_LLCC] = &qns_llcc,
1737
+
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1738
+
};
1739
+
1740
+
static const struct qcom_icc_desc sar2130p_gem_noc = {
1741
+
.config = &icc_regmap_config,
1742
+
.nodes = gem_noc_nodes,
1743
+
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1744
+
.bcms = gem_noc_bcms,
1745
+
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1746
+
};
1747
+
1748
+
static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1749
+
};
1750
+
1751
+
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1752
+
[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1753
+
[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
1754
+
[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1755
+
[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1756
+
[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1757
+
[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1758
+
[SLAVE_LPASS_SNOC] = &qns_sysnoc,
1759
+
[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1760
+
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1761
+
};
1762
+
1763
+
static const struct qcom_icc_desc sar2130p_lpass_ag_noc = {
1764
+
.config = &icc_regmap_config,
1765
+
.nodes = lpass_ag_noc_nodes,
1766
+
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1767
+
.bcms = lpass_ag_noc_bcms,
1768
+
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1769
+
};
1770
+
1771
+
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1772
+
&bcm_acv,
1773
+
&bcm_mc0,
1774
+
};
1775
+
1776
+
static struct qcom_icc_node * const mc_virt_nodes[] = {
1777
+
[MASTER_LLCC] = &llcc_mc,
1778
+
[SLAVE_EBI1] = &ebi,
1779
+
};
1780
+
1781
+
static const struct qcom_icc_desc sar2130p_mc_virt = {
1782
+
.nodes = mc_virt_nodes,
1783
+
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1784
+
.bcms = mc_virt_bcms,
1785
+
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
1786
+
};
1787
+
1788
+
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1789
+
&bcm_mm0,
1790
+
&bcm_mm1,
1791
+
};
1792
+
1793
+
static struct qcom_icc_node * const mmss_noc_nodes[] = {
1794
+
[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1795
+
[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1796
+
[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1797
+
[MASTER_LSR] = &qnm_lsr,
1798
+
[MASTER_MDP] = &qnm_mdp,
1799
+
[MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
1800
+
[MASTER_VIDEO] = &qnm_video,
1801
+
[MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1802
+
[MASTER_VIDEO_PROC] = &qnm_video_cvp,
1803
+
[MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1804
+
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1805
+
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1806
+
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1807
+
};
1808
+
1809
+
static const struct qcom_icc_desc sar2130p_mmss_noc = {
1810
+
.config = &icc_regmap_config,
1811
+
.nodes = mmss_noc_nodes,
1812
+
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1813
+
.bcms = mmss_noc_bcms,
1814
+
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1815
+
};
1816
+
1817
+
static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1818
+
&bcm_co0,
1819
+
};
1820
+
1821
+
static struct qcom_icc_node * const nsp_noc_nodes[] = {
1822
+
[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
1823
+
[MASTER_CDSP_PROC] = &qxm_nsp,
1824
+
[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1825
+
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
1826
+
};
1827
+
1828
+
static const struct qcom_icc_desc sar2130p_nsp_noc = {
1829
+
.config = &icc_regmap_config,
1830
+
.nodes = nsp_noc_nodes,
1831
+
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1832
+
.bcms = nsp_noc_bcms,
1833
+
.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1834
+
};
1835
+
1836
+
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1837
+
&bcm_sn7,
1838
+
};
1839
+
1840
+
static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1841
+
[MASTER_PCIE_0] = &xm_pcie3_0,
1842
+
[MASTER_PCIE_1] = &xm_pcie3_1,
1843
+
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1844
+
};
1845
+
1846
+
static const struct qcom_icc_desc sar2130p_pcie_anoc = {
1847
+
.config = &icc_regmap_config,
1848
+
.nodes = pcie_anoc_nodes,
1849
+
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1850
+
.bcms = pcie_anoc_bcms,
1851
+
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1852
+
};
1853
+
1854
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
1855
+
&bcm_ce0,
1856
+
&bcm_sn0,
1857
+
&bcm_sn1,
1858
+
&bcm_sn3,
1859
+
&bcm_sn4,
1860
+
};
1861
+
1862
+
static struct qcom_icc_node * const system_noc_nodes[] = {
1863
+
[MASTER_GIC_AHB] = &qhm_gic,
1864
+
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
1865
+
[MASTER_QSPI_0] = &qhm_qspi,
1866
+
[MASTER_QUP_0] = &qhm_qup0,
1867
+
[MASTER_QUP_1] = &qhm_qup1,
1868
+
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1869
+
[MASTER_CNOC_DATAPATH] = &qnm_cnoc_datapath,
1870
+
[MASTER_LPASS_ANOC] = &qnm_lpass_noc,
1871
+
[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
1872
+
[MASTER_CRYPTO] = &qxm_crypto,
1873
+
[MASTER_PIMEM] = &qxm_pimem,
1874
+
[MASTER_GIC] = &xm_gic,
1875
+
[MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1876
+
[MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1877
+
[MASTER_SDCC_1] = &xm_sdc1,
1878
+
[MASTER_USB3_0] = &xm_usb3_0,
1879
+
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1880
+
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1881
+
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1882
+
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
1883
+
};
1884
+
1885
+
static const struct qcom_icc_desc sar2130p_system_noc = {
1886
+
.config = &icc_regmap_config,
1887
+
.nodes = system_noc_nodes,
1888
+
.num_nodes = ARRAY_SIZE(system_noc_nodes),
1889
+
.bcms = system_noc_bcms,
1890
+
.num_bcms = ARRAY_SIZE(system_noc_bcms),
1891
+
};
1892
+
1893
+
static const struct of_device_id qnoc_of_match[] = {
1894
+
{ .compatible = "qcom,sar2130p-clk-virt", .data = &sar2130p_clk_virt},
1895
+
{ .compatible = "qcom,sar2130p-config-noc", .data = &sar2130p_config_noc},
1896
+
{ .compatible = "qcom,sar2130p-gem-noc", .data = &sar2130p_gem_noc},
1897
+
{ .compatible = "qcom,sar2130p-lpass-ag-noc", .data = &sar2130p_lpass_ag_noc},
1898
+
{ .compatible = "qcom,sar2130p-mc-virt", .data = &sar2130p_mc_virt},
1899
+
{ .compatible = "qcom,sar2130p-mmss-noc", .data = &sar2130p_mmss_noc},
1900
+
{ .compatible = "qcom,sar2130p-nsp-noc", .data = &sar2130p_nsp_noc},
1901
+
{ .compatible = "qcom,sar2130p-pcie-anoc", .data = &sar2130p_pcie_anoc},
1902
+
{ .compatible = "qcom,sar2130p-system-noc", .data = &sar2130p_system_noc},
1903
+
{ }
1904
+
};
1905
+
MODULE_DEVICE_TABLE(of, qnoc_of_match);
1906
+
1907
+
static struct platform_driver qnoc_driver = {
1908
+
.probe = qcom_icc_rpmh_probe,
1909
+
.remove = qcom_icc_rpmh_remove,
1910
+
.driver = {
1911
+
.name = "qnoc-sar2130p",
1912
+
.of_match_table = qnoc_of_match,
1913
+
.sync_state = icc_sync_state,
1914
+
},
1915
+
};
1916
+
1917
+
static int __init qnoc_driver_init(void)
1918
+
{
1919
+
return platform_driver_register(&qnoc_driver);
1920
+
}
1921
+
core_initcall(qnoc_driver_init);
1922
+
1923
+
static void __exit qnoc_driver_exit(void)
1924
+
{
1925
+
platform_driver_unregister(&qnoc_driver);
1926
+
}
1927
+
1928
+
module_exit(qnoc_driver_exit);
1929
+
MODULE_DESCRIPTION("Qualcomm SAR2130P NoC driver");
1930
+
MODULE_LICENSE("GPL");
+1
-1
drivers/interconnect/qcom/sc7180.c
+1
-1
drivers/interconnect/qcom/sc7180.c
+3
-3
drivers/interconnect/qcom/sc7280.c
+3
-3
drivers/interconnect/qcom/sc7280.c
···
1691
1691
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1692
1692
.bcms = aggre1_noc_bcms,
1693
1693
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1694
-
.qos_clks_required = true,
1694
+
.qos_requires_clocks = true,
1695
1695
};
1696
1696
1697
1697
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
···
1723
1723
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1724
1724
.bcms = aggre2_noc_bcms,
1725
1725
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1726
-
.qos_clks_required = true,
1726
+
.qos_requires_clocks = true,
1727
1727
};
1728
1728
1729
1729
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
···
2111
2111
2112
2112
static struct platform_driver qnoc_driver = {
2113
2113
.probe = qcom_icc_rpmh_probe,
2114
-
.remove_new = qcom_icc_rpmh_remove,
2114
+
.remove = qcom_icc_rpmh_remove,
2115
2115
.driver = {
2116
2116
.name = "qnoc-sc7280",
2117
2117
.of_match_table = qnoc_of_match,
+1
-1
drivers/interconnect/qcom/sc8180x.c
+1
-1
drivers/interconnect/qcom/sc8180x.c
+1
-1
drivers/interconnect/qcom/sc8280xp.c
+1
-1
drivers/interconnect/qcom/sc8280xp.c
+1
-1
drivers/interconnect/qcom/sdm660.c
+1
-1
drivers/interconnect/qcom/sdm660.c
+1
-1
drivers/interconnect/qcom/sdm670.c
+1
-1
drivers/interconnect/qcom/sdm670.c
+1
-1
drivers/interconnect/qcom/sdm845.c
+1
-1
drivers/interconnect/qcom/sdm845.c
+1
-1
drivers/interconnect/qcom/sdx55.c
+1
-1
drivers/interconnect/qcom/sdx55.c
+1
-1
drivers/interconnect/qcom/sdx65.c
+1
-1
drivers/interconnect/qcom/sdx65.c
+1
-1
drivers/interconnect/qcom/sdx75.c
+1
-1
drivers/interconnect/qcom/sdx75.c
+1
-1
drivers/interconnect/qcom/sm6115.c
+1
-1
drivers/interconnect/qcom/sm6115.c
+1
-1
drivers/interconnect/qcom/sm6350.c
+1
-1
drivers/interconnect/qcom/sm6350.c
+1
-1
drivers/interconnect/qcom/sm7150.c
+1
-1
drivers/interconnect/qcom/sm7150.c
+1
-1
drivers/interconnect/qcom/sm8150.c
+1
-1
drivers/interconnect/qcom/sm8150.c
+1
-1
drivers/interconnect/qcom/sm8250.c
+1
-1
drivers/interconnect/qcom/sm8250.c
+1
-1
drivers/interconnect/qcom/sm8350.c
+1
-1
drivers/interconnect/qcom/sm8350.c
+1
-1
drivers/interconnect/qcom/sm8450.c
+1
-1
drivers/interconnect/qcom/sm8450.c
+1
-1
drivers/interconnect/qcom/sm8550.c
+1
-1
drivers/interconnect/qcom/sm8550.c
+1
-1
drivers/interconnect/qcom/sm8650.c
+1
-1
drivers/interconnect/qcom/sm8650.c
+1
-1
drivers/interconnect/qcom/smd-rpm.c
+1
-1
drivers/interconnect/qcom/smd-rpm.c
···
85
85
.name = "icc_smd_rpm",
86
86
},
87
87
.probe = qcom_icc_rpm_smd_probe,
88
-
.remove_new = qcom_icc_rpm_smd_remove,
88
+
.remove = qcom_icc_rpm_smd_remove,
89
89
};
90
90
module_platform_driver(qcom_interconnect_rpm_smd_driver);
91
91
MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");
+1
-1
drivers/interconnect/qcom/x1e80100.c
+1
-1
drivers/interconnect/qcom/x1e80100.c
+1
-1
drivers/interconnect/samsung/exynos.c
+1
-1
drivers/interconnect/samsung/exynos.c
+136
include/dt-bindings/interconnect/qcom,qcs615-rpmh.h
+136
include/dt-bindings/interconnect/qcom,qcs615-rpmh.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS615_H
7
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS615_H
8
+
9
+
#define MASTER_A1NOC_CFG 1
10
+
#define MASTER_QDSS_BAM 2
11
+
#define MASTER_QSPI 3
12
+
#define MASTER_QUP_0 4
13
+
#define MASTER_BLSP_1 5
14
+
#define MASTER_CNOC_A2NOC 6
15
+
#define MASTER_CRYPTO 7
16
+
#define MASTER_IPA 8
17
+
#define MASTER_EMAC_EVB 9
18
+
#define MASTER_PCIE 10
19
+
#define MASTER_QDSS_ETR 11
20
+
#define MASTER_SDCC_1 12
21
+
#define MASTER_SDCC_2 13
22
+
#define MASTER_UFS_MEM 14
23
+
#define MASTER_USB2 15
24
+
#define MASTER_USB3_0 16
25
+
#define SLAVE_A1NOC_SNOC 17
26
+
#define SLAVE_LPASS_SNOC 18
27
+
#define SLAVE_ANOC_PCIE_SNOC 19
28
+
#define SLAVE_SERVICE_A2NOC 20
29
+
30
+
#define MASTER_CAMNOC_HF0_UNCOMP 1
31
+
#define MASTER_CAMNOC_HF1_UNCOMP 2
32
+
#define MASTER_CAMNOC_SF_UNCOMP 3
33
+
#define SLAVE_CAMNOC_UNCOMP 4
34
+
35
+
#define MASTER_SPDM 1
36
+
#define MASTER_SNOC_CNOC 2
37
+
#define MASTER_QDSS_DAP 3
38
+
#define SLAVE_A1NOC_CFG 4
39
+
#define SLAVE_AHB2PHY_EAST 5
40
+
#define SLAVE_AHB2PHY_WEST 6
41
+
#define SLAVE_AOP 7
42
+
#define SLAVE_AOSS 8
43
+
#define SLAVE_CAMERA_CFG 9
44
+
#define SLAVE_CLK_CTL 10
45
+
#define SLAVE_RBCPR_CX_CFG 11
46
+
#define SLAVE_RBCPR_MX_CFG 12
47
+
#define SLAVE_CRYPTO_0_CFG 13
48
+
#define SLAVE_CNOC_DDRSS 14
49
+
#define SLAVE_DISPLAY_CFG 15
50
+
#define SLAVE_EMAC_AVB_CFG 16
51
+
#define SLAVE_GLM 17
52
+
#define SLAVE_GFX3D_CFG 18
53
+
#define SLAVE_IMEM_CFG 19
54
+
#define SLAVE_IPA_CFG 20
55
+
#define SLAVE_CNOC_MNOC_CFG 21
56
+
#define SLAVE_PCIE_CFG 22
57
+
#define SLAVE_PIMEM_CFG 23
58
+
#define SLAVE_PRNG 24
59
+
#define SLAVE_QDSS_CFG 25
60
+
#define SLAVE_QSPI 26
61
+
#define SLAVE_QUP_0 27
62
+
#define SLAVE_QUP_1 28
63
+
#define SLAVE_SDCC_1 29
64
+
#define SLAVE_SDCC_2 30
65
+
#define SLAVE_SNOC_CFG 31
66
+
#define SLAVE_SPDM_WRAPPER 32
67
+
#define SLAVE_TCSR 33
68
+
#define SLAVE_TLMM_EAST 34
69
+
#define SLAVE_TLMM_SOUTH 35
70
+
#define SLAVE_TLMM_WEST 36
71
+
#define SLAVE_UFS_MEM_CFG 37
72
+
#define SLAVE_USB2 38
73
+
#define SLAVE_USB3 39
74
+
#define SLAVE_VENUS_CFG 40
75
+
#define SLAVE_VSENSE_CTRL_CFG 41
76
+
#define SLAVE_CNOC_A2NOC 42
77
+
#define SLAVE_SERVICE_CNOC 43
78
+
79
+
#define MASTER_CNOC_DC_NOC 1
80
+
#define SLAVE_DC_NOC_GEMNOC 2
81
+
#define SLAVE_LLCC_CFG 3
82
+
83
+
#define MASTER_APPSS_PROC 1
84
+
#define MASTER_GPU_TCU 2
85
+
#define MASTER_SYS_TCU 3
86
+
#define MASTER_GEM_NOC_CFG 4
87
+
#define MASTER_GFX3D 5
88
+
#define MASTER_MNOC_HF_MEM_NOC 6
89
+
#define MASTER_MNOC_SF_MEM_NOC 7
90
+
#define MASTER_SNOC_GC_MEM_NOC 8
91
+
#define MASTER_SNOC_SF_MEM_NOC 9
92
+
#define SLAVE_MSS_PROC_MS_MPU_CFG 10
93
+
#define SLAVE_GEM_NOC_SNOC 11
94
+
#define SLAVE_LLCC 12
95
+
#define SLAVE_MEM_NOC_PCIE_SNOC 13
96
+
#define SLAVE_SERVICE_GEM_NOC 14
97
+
98
+
#define MASTER_IPA_CORE 1
99
+
#define SLAVE_IPA_CORE 2
100
+
101
+
#define MASTER_LLCC 1
102
+
#define SLAVE_EBI1 2
103
+
104
+
#define MASTER_CNOC_MNOC_CFG 1
105
+
#define MASTER_CAMNOC_HF0 2
106
+
#define MASTER_CAMNOC_HF1 3
107
+
#define MASTER_CAMNOC_SF 4
108
+
#define MASTER_MDP0 5
109
+
#define MASTER_ROTATOR 6
110
+
#define MASTER_VIDEO_P0 7
111
+
#define MASTER_VIDEO_PROC 8
112
+
#define SLAVE_MNOC_SF_MEM_NOC 9
113
+
#define SLAVE_MNOC_HF_MEM_NOC 10
114
+
#define SLAVE_SERVICE_MNOC 11
115
+
116
+
#define MASTER_SNOC_CFG 1
117
+
#define MASTER_A1NOC_SNOC 2
118
+
#define MASTER_GEM_NOC_SNOC 3
119
+
#define MASTER_GEM_NOC_PCIE_SNOC 4
120
+
#define MASTER_LPASS_ANOC 5
121
+
#define MASTER_ANOC_PCIE_SNOC 6
122
+
#define MASTER_PIMEM 7
123
+
#define MASTER_GIC 8
124
+
#define SLAVE_APPSS 9
125
+
#define SLAVE_SNOC_CNOC 10
126
+
#define SLAVE_SNOC_GEM_NOC_SF 11
127
+
#define SLAVE_SNOC_MEM_NOC_GC 12
128
+
#define SLAVE_IMEM 13
129
+
#define SLAVE_PIMEM 14
130
+
#define SLAVE_SERVICE_SNOC 15
131
+
#define SLAVE_PCIE_0 16
132
+
#define SLAVE_QDSS_STM 17
133
+
#define SLAVE_TCU 18
134
+
135
+
#endif
136
+
+189
include/dt-bindings/interconnect/qcom,qcs8300-rpmh.h
+189
include/dt-bindings/interconnect/qcom,qcs8300-rpmh.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS8300_H
7
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS8300_H
8
+
9
+
#define MASTER_QUP_3 0
10
+
#define MASTER_EMAC 1
11
+
#define MASTER_SDC 2
12
+
#define MASTER_UFS_MEM 3
13
+
#define MASTER_USB2 4
14
+
#define MASTER_USB3_0 5
15
+
#define SLAVE_A1NOC_SNOC 6
16
+
17
+
#define MASTER_QDSS_BAM 0
18
+
#define MASTER_QUP_0 1
19
+
#define MASTER_QUP_1 2
20
+
#define MASTER_CNOC_A2NOC 3
21
+
#define MASTER_CRYPTO_CORE0 4
22
+
#define MASTER_CRYPTO_CORE1 5
23
+
#define MASTER_IPA 6
24
+
#define MASTER_QDSS_ETR_0 7
25
+
#define MASTER_QDSS_ETR_1 8
26
+
#define SLAVE_A2NOC_SNOC 9
27
+
28
+
#define MASTER_QUP_CORE_0 0
29
+
#define MASTER_QUP_CORE_1 1
30
+
#define MASTER_QUP_CORE_3 2
31
+
#define SLAVE_QUP_CORE_0 3
32
+
#define SLAVE_QUP_CORE_1 4
33
+
#define SLAVE_QUP_CORE_3 5
34
+
35
+
#define MASTER_GEM_NOC_CNOC 0
36
+
#define MASTER_GEM_NOC_PCIE_SNOC 1
37
+
#define SLAVE_AHB2PHY_2 2
38
+
#define SLAVE_AHB2PHY_3 3
39
+
#define SLAVE_ANOC_THROTTLE_CFG 4
40
+
#define SLAVE_AOSS 5
41
+
#define SLAVE_APPSS 6
42
+
#define SLAVE_BOOT_ROM 7
43
+
#define SLAVE_CAMERA_CFG 8
44
+
#define SLAVE_CAMERA_NRT_THROTTLE_CFG 9
45
+
#define SLAVE_CAMERA_RT_THROTTLE_CFG 10
46
+
#define SLAVE_CLK_CTL 11
47
+
#define SLAVE_CDSP_CFG 12
48
+
#define SLAVE_RBCPR_CX_CFG 13
49
+
#define SLAVE_RBCPR_MMCX_CFG 14
50
+
#define SLAVE_RBCPR_MX_CFG 15
51
+
#define SLAVE_CPR_NSPCX 16
52
+
#define SLAVE_CPR_NSPHMX 17
53
+
#define SLAVE_CRYPTO_0_CFG 18
54
+
#define SLAVE_CX_RDPM 19
55
+
#define SLAVE_DISPLAY_CFG 20
56
+
#define SLAVE_DISPLAY_RT_THROTTLE_CFG 21
57
+
#define SLAVE_EMAC_CFG 22
58
+
#define SLAVE_GP_DSP0_CFG 23
59
+
#define SLAVE_GPDSP0_THROTTLE_CFG 24
60
+
#define SLAVE_GPU_TCU_THROTTLE_CFG 25
61
+
#define SLAVE_GFX3D_CFG 26
62
+
#define SLAVE_HWKM 27
63
+
#define SLAVE_IMEM_CFG 28
64
+
#define SLAVE_IPA_CFG 29
65
+
#define SLAVE_IPC_ROUTER_CFG 30
66
+
#define SLAVE_LPASS 31
67
+
#define SLAVE_LPASS_THROTTLE_CFG 32
68
+
#define SLAVE_MX_RDPM 33
69
+
#define SLAVE_MXC_RDPM 34
70
+
#define SLAVE_PCIE_0_CFG 35
71
+
#define SLAVE_PCIE_1_CFG 36
72
+
#define SLAVE_PCIE_TCU_THROTTLE_CFG 37
73
+
#define SLAVE_PCIE_THROTTLE_CFG 38
74
+
#define SLAVE_PDM 39
75
+
#define SLAVE_PIMEM_CFG 40
76
+
#define SLAVE_PKA_WRAPPER_CFG 41
77
+
#define SLAVE_QDSS_CFG 42
78
+
#define SLAVE_QM_CFG 43
79
+
#define SLAVE_QM_MPU_CFG 44
80
+
#define SLAVE_QUP_0 45
81
+
#define SLAVE_QUP_1 46
82
+
#define SLAVE_QUP_3 47
83
+
#define SLAVE_SAIL_THROTTLE_CFG 48
84
+
#define SLAVE_SDC1 49
85
+
#define SLAVE_SECURITY 50
86
+
#define SLAVE_SNOC_THROTTLE_CFG 51
87
+
#define SLAVE_TCSR 52
88
+
#define SLAVE_TLMM 53
89
+
#define SLAVE_TSC_CFG 54
90
+
#define SLAVE_UFS_MEM_CFG 55
91
+
#define SLAVE_USB2 56
92
+
#define SLAVE_USB3_0 57
93
+
#define SLAVE_VENUS_CFG 58
94
+
#define SLAVE_VENUS_CVP_THROTTLE_CFG 59
95
+
#define SLAVE_VENUS_V_CPU_THROTTLE_CFG 60
96
+
#define SLAVE_VENUS_VCODEC_THROTTLE_CFG 61
97
+
#define SLAVE_DDRSS_CFG 62
98
+
#define SLAVE_GPDSP_NOC_CFG 63
99
+
#define SLAVE_CNOC_MNOC_HF_CFG 64
100
+
#define SLAVE_CNOC_MNOC_SF_CFG 65
101
+
#define SLAVE_PCIE_ANOC_CFG 66
102
+
#define SLAVE_SNOC_CFG 67
103
+
#define SLAVE_BOOT_IMEM 68
104
+
#define SLAVE_IMEM 69
105
+
#define SLAVE_PIMEM 70
106
+
#define SLAVE_PCIE_0 71
107
+
#define SLAVE_PCIE_1 72
108
+
#define SLAVE_QDSS_STM 73
109
+
#define SLAVE_TCU 74
110
+
111
+
#define MASTER_CNOC_DC_NOC 0
112
+
#define SLAVE_LLCC_CFG 1
113
+
#define SLAVE_GEM_NOC_CFG 2
114
+
115
+
#define MASTER_GPU_TCU 0
116
+
#define MASTER_PCIE_TCU 1
117
+
#define MASTER_SYS_TCU 2
118
+
#define MASTER_APPSS_PROC 3
119
+
#define MASTER_COMPUTE_NOC 4
120
+
#define MASTER_GEM_NOC_CFG 5
121
+
#define MASTER_GPDSP_SAIL 6
122
+
#define MASTER_GFX3D 7
123
+
#define MASTER_MNOC_HF_MEM_NOC 8
124
+
#define MASTER_MNOC_SF_MEM_NOC 9
125
+
#define MASTER_ANOC_PCIE_GEM_NOC 10
126
+
#define MASTER_SNOC_GC_MEM_NOC 11
127
+
#define MASTER_SNOC_SF_MEM_NOC 12
128
+
#define SLAVE_GEM_NOC_CNOC 13
129
+
#define SLAVE_LLCC 14
130
+
#define SLAVE_GEM_NOC_PCIE_CNOC 15
131
+
#define SLAVE_SERVICE_GEM_NOC_1 16
132
+
#define SLAVE_SERVICE_GEM_NOC_2 17
133
+
#define SLAVE_SERVICE_GEM_NOC 18
134
+
#define SLAVE_SERVICE_GEM_NOC2 19
135
+
136
+
#define MASTER_SAILSS_MD0 0
137
+
#define MASTER_DSP0 1
138
+
#define SLAVE_GP_DSP_SAIL_NOC 2
139
+
140
+
#define MASTER_CNOC_LPASS_AG_NOC 0
141
+
#define MASTER_LPASS_PROC 1
142
+
#define SLAVE_LPASS_CORE_CFG 2
143
+
#define SLAVE_LPASS_LPI_CFG 3
144
+
#define SLAVE_LPASS_MPU_CFG 4
145
+
#define SLAVE_LPASS_TOP_CFG 5
146
+
#define SLAVE_LPASS_SNOC 6
147
+
#define SLAVE_SERVICES_LPASS_AML_NOC 7
148
+
#define SLAVE_SERVICE_LPASS_AG_NOC 8
149
+
150
+
#define MASTER_LLCC 0
151
+
#define SLAVE_EBI1 1
152
+
153
+
#define MASTER_CAMNOC_HF 0
154
+
#define MASTER_CAMNOC_ICP 1
155
+
#define MASTER_CAMNOC_SF 2
156
+
#define MASTER_MDP0 3
157
+
#define MASTER_MDP1 4
158
+
#define MASTER_CNOC_MNOC_HF_CFG 5
159
+
#define MASTER_CNOC_MNOC_SF_CFG 6
160
+
#define MASTER_VIDEO_P0 7
161
+
#define MASTER_VIDEO_PROC 8
162
+
#define MASTER_VIDEO_V_PROC 9
163
+
#define SLAVE_MNOC_HF_MEM_NOC 10
164
+
#define SLAVE_MNOC_SF_MEM_NOC 11
165
+
#define SLAVE_SERVICE_MNOC_HF 12
166
+
#define SLAVE_SERVICE_MNOC_SF 13
167
+
168
+
#define MASTER_CDSP_NOC_CFG 0
169
+
#define MASTER_CDSP_PROC 1
170
+
#define SLAVE_HCP_A 2
171
+
#define SLAVE_CDSP_MEM_NOC 3
172
+
#define SLAVE_SERVICE_NSP_NOC 4
173
+
174
+
#define MASTER_PCIE_0 0
175
+
#define MASTER_PCIE_1 1
176
+
#define SLAVE_ANOC_PCIE_GEM_NOC 2
177
+
178
+
#define MASTER_GIC_AHB 0
179
+
#define MASTER_A1NOC_SNOC 1
180
+
#define MASTER_A2NOC_SNOC 2
181
+
#define MASTER_LPASS_ANOC 3
182
+
#define MASTER_SNOC_CFG 4
183
+
#define MASTER_PIMEM 5
184
+
#define MASTER_GIC 6
185
+
#define SLAVE_SNOC_GEM_NOC_GC 7
186
+
#define SLAVE_SNOC_GEM_NOC_SF 8
187
+
#define SLAVE_SERVICE_SNOC 9
188
+
189
+
#endif
+137
include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h
+137
include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
5
+
* Copyright (c) 2024, Linaro Ltd.
6
+
*/
7
+
8
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SAR2130P_H
9
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_SAR2130P_H
10
+
11
+
#define MASTER_QUP_CORE_0 0
12
+
#define MASTER_QUP_CORE_1 1
13
+
#define SLAVE_QUP_CORE_0 2
14
+
#define SLAVE_QUP_CORE_1 3
15
+
16
+
#define MASTER_GEM_NOC_CNOC 0
17
+
#define MASTER_GEM_NOC_PCIE_SNOC 1
18
+
#define MASTER_QDSS_DAP 2
19
+
#define SLAVE_AHB2PHY_SOUTH 3
20
+
#define SLAVE_AOSS 4
21
+
#define SLAVE_CAMERA_CFG 5
22
+
#define SLAVE_CLK_CTL 6
23
+
#define SLAVE_CDSP_CFG 7
24
+
#define SLAVE_RBCPR_CX_CFG 8
25
+
#define SLAVE_RBCPR_MMCX_CFG 9
26
+
#define SLAVE_RBCPR_MXA_CFG 10
27
+
#define SLAVE_RBCPR_MXC_CFG 11
28
+
#define SLAVE_CPR_NSPCX 12
29
+
#define SLAVE_CRYPTO_0_CFG 13
30
+
#define SLAVE_CX_RDPM 14
31
+
#define SLAVE_DISPLAY_CFG 15
32
+
#define SLAVE_GFX3D_CFG 16
33
+
#define SLAVE_IMEM_CFG 17
34
+
#define SLAVE_IPC_ROUTER_CFG 18
35
+
#define SLAVE_LPASS 19
36
+
#define SLAVE_MX_RDPM 20
37
+
#define SLAVE_PCIE_0_CFG 21
38
+
#define SLAVE_PCIE_1_CFG 22
39
+
#define SLAVE_PDM 23
40
+
#define SLAVE_PIMEM_CFG 24
41
+
#define SLAVE_PRNG 25
42
+
#define SLAVE_QDSS_CFG 26
43
+
#define SLAVE_QSPI_0 27
44
+
#define SLAVE_QUP_0 28
45
+
#define SLAVE_QUP_1 29
46
+
#define SLAVE_SDCC_1 30
47
+
#define SLAVE_TCSR 31
48
+
#define SLAVE_TLMM 32
49
+
#define SLAVE_TME_CFG 33
50
+
#define SLAVE_USB3_0 34
51
+
#define SLAVE_VENUS_CFG 35
52
+
#define SLAVE_VSENSE_CTRL_CFG 36
53
+
#define SLAVE_WLAN_Q6_CFG 37
54
+
#define SLAVE_DDRSS_CFG 38
55
+
#define SLAVE_CNOC_MNOC_CFG 39
56
+
#define SLAVE_SNOC_CFG 40
57
+
#define SLAVE_IMEM 41
58
+
#define SLAVE_PIMEM 42
59
+
#define SLAVE_SERVICE_CNOC 43
60
+
#define SLAVE_PCIE_0 44
61
+
#define SLAVE_PCIE_1 45
62
+
#define SLAVE_QDSS_STM 46
63
+
#define SLAVE_TCU 47
64
+
65
+
#define MASTER_GPU_TCU 0
66
+
#define MASTER_SYS_TCU 1
67
+
#define MASTER_APPSS_PROC 2
68
+
#define MASTER_GFX3D 3
69
+
#define MASTER_MNOC_HF_MEM_NOC 4
70
+
#define MASTER_MNOC_SF_MEM_NOC 5
71
+
#define MASTER_COMPUTE_NOC 6
72
+
#define MASTER_ANOC_PCIE_GEM_NOC 7
73
+
#define MASTER_SNOC_GC_MEM_NOC 8
74
+
#define MASTER_SNOC_SF_MEM_NOC 9
75
+
#define MASTER_WLAN_Q6 10
76
+
#define SLAVE_GEM_NOC_CNOC 11
77
+
#define SLAVE_LLCC 12
78
+
#define SLAVE_MEM_NOC_PCIE_SNOC 13
79
+
80
+
#define MASTER_CNOC_LPASS_AG_NOC 0
81
+
#define MASTER_LPASS_PROC 1
82
+
#define SLAVE_LPASS_CORE_CFG 2
83
+
#define SLAVE_LPASS_LPI_CFG 3
84
+
#define SLAVE_LPASS_MPU_CFG 4
85
+
#define SLAVE_LPASS_TOP_CFG 5
86
+
#define SLAVE_LPASS_SNOC 6
87
+
#define SLAVE_SERVICES_LPASS_AML_NOC 7
88
+
#define SLAVE_SERVICE_LPASS_AG_NOC 8
89
+
90
+
#define MASTER_LLCC 0
91
+
#define SLAVE_EBI1 1
92
+
93
+
#define MASTER_CAMNOC_HF 0
94
+
#define MASTER_CAMNOC_ICP 1
95
+
#define MASTER_CAMNOC_SF 2
96
+
#define MASTER_LSR 3
97
+
#define MASTER_MDP 4
98
+
#define MASTER_CNOC_MNOC_CFG 5
99
+
#define MASTER_VIDEO 6
100
+
#define MASTER_VIDEO_CV_PROC 7
101
+
#define MASTER_VIDEO_PROC 8
102
+
#define MASTER_VIDEO_V_PROC 9
103
+
#define SLAVE_MNOC_HF_MEM_NOC 10
104
+
#define SLAVE_MNOC_SF_MEM_NOC 11
105
+
#define SLAVE_SERVICE_MNOC 12
106
+
107
+
#define MASTER_CDSP_NOC_CFG 0
108
+
#define MASTER_CDSP_PROC 1
109
+
#define SLAVE_CDSP_MEM_NOC 2
110
+
#define SLAVE_SERVICE_NSP_NOC 3
111
+
112
+
#define MASTER_PCIE_0 0
113
+
#define MASTER_PCIE_1 1
114
+
#define SLAVE_ANOC_PCIE_GEM_NOC 2
115
+
116
+
#define MASTER_GIC_AHB 0
117
+
#define MASTER_QDSS_BAM 1
118
+
#define MASTER_QSPI_0 2
119
+
#define MASTER_QUP_0 3
120
+
#define MASTER_QUP_1 4
121
+
#define MASTER_A2NOC_SNOC 5
122
+
#define MASTER_CNOC_DATAPATH 6
123
+
#define MASTER_LPASS_ANOC 7
124
+
#define MASTER_SNOC_CFG 8
125
+
#define MASTER_CRYPTO 9
126
+
#define MASTER_PIMEM 10
127
+
#define MASTER_GIC 11
128
+
#define MASTER_QDSS_ETR 12
129
+
#define MASTER_QDSS_ETR_1 13
130
+
#define MASTER_SDCC_1 14
131
+
#define MASTER_USB3_0 15
132
+
#define SLAVE_A2NOC_SNOC 16
133
+
#define SLAVE_SNOC_GEM_NOC_GC 17
134
+
#define SLAVE_SNOC_GEM_NOC_SF 18
135
+
#define SLAVE_SERVICE_SNOC 19
136
+
137
+
#endif