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clk: qcom: gcc-msm8916: use ARRAY_SIZE instead of specifying num_parents

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

This conversion fixes an issue present since the first version of this
driver. For the gp1_clk_src, gp2_clk_src and gp3_clk_src it was
impossible to select sleep_clk as a prent of the clock, since
num_parents was limited to 3 rather than 4. Switching to use num_parents
automatically makes sleep_clk available for selection.

Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support")
Cc: Georgi Djakov <djakov@kernel.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Georgi Djakov <djakov@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220704172453.838303-4-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson 5a6d3067 bdeb3cf0

+54 -54
+54 -54
drivers/clk/qcom/gcc-msm8916.c
··· 371 371 .clkr.hw.init = &(struct clk_init_data){ 372 372 .name = "pcnoc_bfdcd_clk_src", 373 373 .parent_names = gcc_xo_gpll0_bimc, 374 - .num_parents = 3, 374 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), 375 375 .ops = &clk_rcg2_ops, 376 376 }, 377 377 }; ··· 383 383 .clkr.hw.init = &(struct clk_init_data){ 384 384 .name = "system_noc_bfdcd_clk_src", 385 385 .parent_names = gcc_xo_gpll0_bimc, 386 - .num_parents = 3, 386 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), 387 387 .ops = &clk_rcg2_ops, 388 388 }, 389 389 }; ··· 403 403 .clkr.hw.init = &(struct clk_init_data){ 404 404 .name = "camss_ahb_clk_src", 405 405 .parent_names = gcc_xo_gpll0, 406 - .num_parents = 2, 406 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 407 407 .ops = &clk_rcg2_ops, 408 408 }, 409 409 }; ··· 424 424 .clkr.hw.init = &(struct clk_init_data){ 425 425 .name = "apss_ahb_clk_src", 426 426 .parent_names = gcc_xo_gpll0, 427 - .num_parents = 2, 427 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 428 428 .ops = &clk_rcg2_ops, 429 429 }, 430 430 }; ··· 443 443 .clkr.hw.init = &(struct clk_init_data){ 444 444 .name = "csi0_clk_src", 445 445 .parent_names = gcc_xo_gpll0, 446 - .num_parents = 2, 446 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 447 447 .ops = &clk_rcg2_ops, 448 448 }, 449 449 }; ··· 456 456 .clkr.hw.init = &(struct clk_init_data){ 457 457 .name = "csi1_clk_src", 458 458 .parent_names = gcc_xo_gpll0, 459 - .num_parents = 2, 459 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 460 460 .ops = &clk_rcg2_ops, 461 461 }, 462 462 }; ··· 484 484 .clkr.hw.init = &(struct clk_init_data){ 485 485 .name = "gfx3d_clk_src", 486 486 .parent_names = gcc_xo_gpll0a_gpll1_gpll2a, 487 - .num_parents = 4, 487 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2a), 488 488 .ops = &clk_rcg2_ops, 489 489 }, 490 490 }; ··· 511 511 .clkr.hw.init = &(struct clk_init_data){ 512 512 .name = "vfe0_clk_src", 513 513 .parent_names = gcc_xo_gpll0_gpll2, 514 - .num_parents = 3, 514 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), 515 515 .ops = &clk_rcg2_ops, 516 516 }, 517 517 }; ··· 530 530 .clkr.hw.init = &(struct clk_init_data){ 531 531 .name = "blsp1_qup1_i2c_apps_clk_src", 532 532 .parent_names = gcc_xo_gpll0, 533 - .num_parents = 2, 533 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 534 534 .ops = &clk_rcg2_ops, 535 535 }, 536 536 }; ··· 559 559 .clkr.hw.init = &(struct clk_init_data){ 560 560 .name = "blsp1_qup1_spi_apps_clk_src", 561 561 .parent_names = gcc_xo_gpll0, 562 - .num_parents = 2, 562 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 563 563 .ops = &clk_rcg2_ops, 564 564 }, 565 565 }; ··· 572 572 .clkr.hw.init = &(struct clk_init_data){ 573 573 .name = "blsp1_qup2_i2c_apps_clk_src", 574 574 .parent_names = gcc_xo_gpll0, 575 - .num_parents = 2, 575 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 576 576 .ops = &clk_rcg2_ops, 577 577 }, 578 578 }; ··· 586 586 .clkr.hw.init = &(struct clk_init_data){ 587 587 .name = "blsp1_qup2_spi_apps_clk_src", 588 588 .parent_names = gcc_xo_gpll0, 589 - .num_parents = 2, 589 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 590 590 .ops = &clk_rcg2_ops, 591 591 }, 592 592 }; ··· 599 599 .clkr.hw.init = &(struct clk_init_data){ 600 600 .name = "blsp1_qup3_i2c_apps_clk_src", 601 601 .parent_names = gcc_xo_gpll0, 602 - .num_parents = 2, 602 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 603 603 .ops = &clk_rcg2_ops, 604 604 }, 605 605 }; ··· 613 613 .clkr.hw.init = &(struct clk_init_data){ 614 614 .name = "blsp1_qup3_spi_apps_clk_src", 615 615 .parent_names = gcc_xo_gpll0, 616 - .num_parents = 2, 616 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 617 617 .ops = &clk_rcg2_ops, 618 618 }, 619 619 }; ··· 626 626 .clkr.hw.init = &(struct clk_init_data){ 627 627 .name = "blsp1_qup4_i2c_apps_clk_src", 628 628 .parent_names = gcc_xo_gpll0, 629 - .num_parents = 2, 629 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 630 630 .ops = &clk_rcg2_ops, 631 631 }, 632 632 }; ··· 640 640 .clkr.hw.init = &(struct clk_init_data){ 641 641 .name = "blsp1_qup4_spi_apps_clk_src", 642 642 .parent_names = gcc_xo_gpll0, 643 - .num_parents = 2, 643 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 644 644 .ops = &clk_rcg2_ops, 645 645 }, 646 646 }; ··· 653 653 .clkr.hw.init = &(struct clk_init_data){ 654 654 .name = "blsp1_qup5_i2c_apps_clk_src", 655 655 .parent_names = gcc_xo_gpll0, 656 - .num_parents = 2, 656 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 657 657 .ops = &clk_rcg2_ops, 658 658 }, 659 659 }; ··· 667 667 .clkr.hw.init = &(struct clk_init_data){ 668 668 .name = "blsp1_qup5_spi_apps_clk_src", 669 669 .parent_names = gcc_xo_gpll0, 670 - .num_parents = 2, 670 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 671 671 .ops = &clk_rcg2_ops, 672 672 }, 673 673 }; ··· 680 680 .clkr.hw.init = &(struct clk_init_data){ 681 681 .name = "blsp1_qup6_i2c_apps_clk_src", 682 682 .parent_names = gcc_xo_gpll0, 683 - .num_parents = 2, 683 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 684 684 .ops = &clk_rcg2_ops, 685 685 }, 686 686 }; ··· 694 694 .clkr.hw.init = &(struct clk_init_data){ 695 695 .name = "blsp1_qup6_spi_apps_clk_src", 696 696 .parent_names = gcc_xo_gpll0, 697 - .num_parents = 2, 697 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 698 698 .ops = &clk_rcg2_ops, 699 699 }, 700 700 }; ··· 727 727 .clkr.hw.init = &(struct clk_init_data){ 728 728 .name = "blsp1_uart1_apps_clk_src", 729 729 .parent_names = gcc_xo_gpll0, 730 - .num_parents = 2, 730 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 731 731 .ops = &clk_rcg2_ops, 732 732 }, 733 733 }; ··· 741 741 .clkr.hw.init = &(struct clk_init_data){ 742 742 .name = "blsp1_uart2_apps_clk_src", 743 743 .parent_names = gcc_xo_gpll0, 744 - .num_parents = 2, 744 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 745 745 .ops = &clk_rcg2_ops, 746 746 }, 747 747 }; ··· 760 760 .clkr.hw.init = &(struct clk_init_data){ 761 761 .name = "cci_clk_src", 762 762 .parent_names = gcc_xo_gpll0a, 763 - .num_parents = 2, 763 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a), 764 764 .ops = &clk_rcg2_ops, 765 765 }, 766 766 }; ··· 793 793 .clkr.hw.init = &(struct clk_init_data){ 794 794 .name = "camss_gp0_clk_src", 795 795 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 796 - .num_parents = 4, 796 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 797 797 .ops = &clk_rcg2_ops, 798 798 }, 799 799 }; ··· 807 807 .clkr.hw.init = &(struct clk_init_data){ 808 808 .name = "camss_gp1_clk_src", 809 809 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 810 - .num_parents = 4, 810 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 811 811 .ops = &clk_rcg2_ops, 812 812 }, 813 813 }; ··· 827 827 .clkr.hw.init = &(struct clk_init_data){ 828 828 .name = "jpeg0_clk_src", 829 829 .parent_names = gcc_xo_gpll0, 830 - .num_parents = 2, 830 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 831 831 .ops = &clk_rcg2_ops, 832 832 }, 833 833 }; ··· 848 848 .clkr.hw.init = &(struct clk_init_data){ 849 849 .name = "mclk0_clk_src", 850 850 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 851 - .num_parents = 4, 851 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 852 852 .ops = &clk_rcg2_ops, 853 853 }, 854 854 }; ··· 862 862 .clkr.hw.init = &(struct clk_init_data){ 863 863 .name = "mclk1_clk_src", 864 864 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 865 - .num_parents = 4, 865 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 866 866 .ops = &clk_rcg2_ops, 867 867 }, 868 868 }; ··· 881 881 .clkr.hw.init = &(struct clk_init_data){ 882 882 .name = "csi0phytimer_clk_src", 883 883 .parent_names = gcc_xo_gpll0_gpll1a, 884 - .num_parents = 3, 884 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a), 885 885 .ops = &clk_rcg2_ops, 886 886 }, 887 887 }; ··· 894 894 .clkr.hw.init = &(struct clk_init_data){ 895 895 .name = "csi1phytimer_clk_src", 896 896 .parent_names = gcc_xo_gpll0_gpll1a, 897 - .num_parents = 3, 897 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a), 898 898 .ops = &clk_rcg2_ops, 899 899 }, 900 900 }; ··· 914 914 .clkr.hw.init = &(struct clk_init_data){ 915 915 .name = "cpp_clk_src", 916 916 .parent_names = gcc_xo_gpll0_gpll2, 917 - .num_parents = 3, 917 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), 918 918 .ops = &clk_rcg2_ops, 919 919 }, 920 920 }; ··· 935 935 .clkr.hw.init = &(struct clk_init_data){ 936 936 .name = "crypto_clk_src", 937 937 .parent_names = gcc_xo_gpll0, 938 - .num_parents = 2, 938 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 939 939 .ops = &clk_rcg2_ops, 940 940 }, 941 941 }; ··· 976 976 .clkr.hw.init = &(struct clk_init_data){ 977 977 .name = "gp1_clk_src", 978 978 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 979 - .num_parents = 3, 979 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 980 980 .ops = &clk_rcg2_ops, 981 981 }, 982 982 }; ··· 990 990 .clkr.hw.init = &(struct clk_init_data){ 991 991 .name = "gp2_clk_src", 992 992 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 993 - .num_parents = 3, 993 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 994 994 .ops = &clk_rcg2_ops, 995 995 }, 996 996 }; ··· 1004 1004 .clkr.hw.init = &(struct clk_init_data){ 1005 1005 .name = "gp3_clk_src", 1006 1006 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 1007 - .num_parents = 3, 1007 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 1008 1008 .ops = &clk_rcg2_ops, 1009 1009 }, 1010 1010 }; ··· 1016 1016 .clkr.hw.init = &(struct clk_init_data){ 1017 1017 .name = "byte0_clk_src", 1018 1018 .parent_names = gcc_xo_gpll0a_dsibyte, 1019 - .num_parents = 3, 1019 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte), 1020 1020 .ops = &clk_byte2_ops, 1021 1021 .flags = CLK_SET_RATE_PARENT, 1022 1022 }, ··· 1035 1035 .clkr.hw.init = &(struct clk_init_data){ 1036 1036 .name = "esc0_clk_src", 1037 1037 .parent_names = gcc_xo_dsibyte, 1038 - .num_parents = 2, 1038 + .num_parents = ARRAY_SIZE(gcc_xo_dsibyte), 1039 1039 .ops = &clk_rcg2_ops, 1040 1040 }, 1041 1041 }; ··· 1060 1060 .clkr.hw.init = &(struct clk_init_data){ 1061 1061 .name = "mdp_clk_src", 1062 1062 .parent_names = gcc_xo_gpll0_dsiphy, 1063 - .num_parents = 3, 1063 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_dsiphy), 1064 1064 .ops = &clk_rcg2_ops, 1065 1065 }, 1066 1066 }; ··· 1073 1073 .clkr.hw.init = &(struct clk_init_data){ 1074 1074 .name = "pclk0_clk_src", 1075 1075 .parent_names = gcc_xo_gpll0a_dsiphy, 1076 - .num_parents = 3, 1076 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy), 1077 1077 .ops = &clk_pixel_ops, 1078 1078 .flags = CLK_SET_RATE_PARENT, 1079 1079 }, ··· 1092 1092 .clkr.hw.init = &(struct clk_init_data){ 1093 1093 .name = "vsync_clk_src", 1094 1094 .parent_names = gcc_xo_gpll0a, 1095 - .num_parents = 2, 1095 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a), 1096 1096 .ops = &clk_rcg2_ops, 1097 1097 }, 1098 1098 }; ··· 1110 1110 .clkr.hw.init = &(struct clk_init_data){ 1111 1111 .name = "pdm2_clk_src", 1112 1112 .parent_names = gcc_xo_gpll0, 1113 - .num_parents = 2, 1113 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1114 1114 .ops = &clk_rcg2_ops, 1115 1115 }, 1116 1116 }; ··· 1135 1135 .clkr.hw.init = &(struct clk_init_data){ 1136 1136 .name = "sdcc1_apps_clk_src", 1137 1137 .parent_names = gcc_xo_gpll0, 1138 - .num_parents = 2, 1138 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1139 1139 .ops = &clk_rcg2_floor_ops, 1140 1140 }, 1141 1141 }; ··· 1160 1160 .clkr.hw.init = &(struct clk_init_data){ 1161 1161 .name = "sdcc2_apps_clk_src", 1162 1162 .parent_names = gcc_xo_gpll0, 1163 - .num_parents = 2, 1163 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1164 1164 .ops = &clk_rcg2_floor_ops, 1165 1165 }, 1166 1166 }; ··· 1180 1180 .clkr.hw.init = &(struct clk_init_data){ 1181 1181 .name = "apss_tcu_clk_src", 1182 1182 .parent_names = gcc_xo_gpll0a_gpll1_gpll2, 1183 - .num_parents = 4, 1183 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2), 1184 1184 .ops = &clk_rcg2_ops, 1185 1185 }, 1186 1186 }; ··· 1203 1203 .clkr.hw.init = &(struct clk_init_data){ 1204 1204 .name = "bimc_gpu_clk_src", 1205 1205 .parent_names = gcc_xo_gpll0_bimc, 1206 - .num_parents = 3, 1206 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), 1207 1207 .flags = CLK_GET_RATE_NOCACHE, 1208 1208 .ops = &clk_rcg2_ops, 1209 1209 }, ··· 1222 1222 .clkr.hw.init = &(struct clk_init_data){ 1223 1223 .name = "usb_hs_system_clk_src", 1224 1224 .parent_names = gcc_xo_gpll0, 1225 - .num_parents = 2, 1225 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1226 1226 .ops = &clk_rcg2_ops, 1227 1227 }, 1228 1228 }; ··· 1248 1248 .clkr.hw.init = &(struct clk_init_data){ 1249 1249 .name = "ultaudio_ahbfabric_clk_src", 1250 1250 .parent_names = gcc_xo_gpll0_gpll1_sleep, 1251 - .num_parents = 4, 1251 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep), 1252 1252 .ops = &clk_rcg2_ops, 1253 1253 }, 1254 1254 }; ··· 1327 1327 .clkr.hw.init = &(struct clk_init_data){ 1328 1328 .name = "ultaudio_lpaif_pri_i2s_clk_src", 1329 1329 .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep, 1330 - .num_parents = 5, 1330 + .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep), 1331 1331 .ops = &clk_rcg2_ops, 1332 1332 }, 1333 1333 }; ··· 1358 1358 .clkr.hw.init = &(struct clk_init_data){ 1359 1359 .name = "ultaudio_lpaif_sec_i2s_clk_src", 1360 1360 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1361 - .num_parents = 5, 1361 + .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep), 1362 1362 .ops = &clk_rcg2_ops, 1363 1363 }, 1364 1364 }; ··· 1389 1389 .clkr.hw.init = &(struct clk_init_data){ 1390 1390 .name = "ultaudio_lpaif_aux_i2s_clk_src", 1391 1391 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1392 - .num_parents = 5, 1392 + .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep), 1393 1393 .ops = &clk_rcg2_ops, 1394 1394 }, 1395 1395 }; ··· 1424 1424 .clkr.hw.init = &(struct clk_init_data){ 1425 1425 .name = "ultaudio_xo_clk_src", 1426 1426 .parent_names = gcc_xo_sleep, 1427 - .num_parents = 2, 1427 + .num_parents = ARRAY_SIZE(gcc_xo_sleep), 1428 1428 .ops = &clk_rcg2_ops, 1429 1429 }, 1430 1430 }; ··· 1480 1480 .clkr.hw.init = &(struct clk_init_data){ 1481 1481 .name = "codec_digcodec_clk_src", 1482 1482 .parent_names = gcc_xo_gpll1_emclk_sleep, 1483 - .num_parents = 4, 1483 + .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep), 1484 1484 .ops = &clk_rcg2_ops, 1485 1485 }, 1486 1486 }; ··· 1550 1550 .clkr.hw.init = &(struct clk_init_data){ 1551 1551 .name = "vcodec0_clk_src", 1552 1552 .parent_names = gcc_xo_gpll0, 1553 - .num_parents = 2, 1553 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1554 1554 .ops = &clk_rcg2_ops, 1555 1555 }, 1556 1556 }; ··· 2806 2806 .clkr.hw.init = &(struct clk_init_data){ 2807 2807 .name = "bimc_ddr_clk_src", 2808 2808 .parent_names = gcc_xo_gpll0_bimc, 2809 - .num_parents = 3, 2809 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), 2810 2810 .ops = &clk_rcg2_ops, 2811 2811 .flags = CLK_GET_RATE_NOCACHE, 2812 2812 },